Quanta FM9 Schematic

1

2

3

4

5

6

7

8

FM9 XXXX Intel Discrete GFX

VER : 1A
PWA:

A A

FAN & THERMAL

SMSC1422

POWER

AC/BATT
CONNECTOR

PG 53

B B

DDR3-SODIMM1

PG 13

DDR3-SODIMM2

PG 14

E-SATA Combo

C C

with USB CONN

SYSTEM
RESET CIRCUIT

BATT
CHARGER

RUN POWER SW

+3.3V_SUS/+5V_SUS
+5V/+3.3V/+1.8V

Dual Channel DDR3
800/1067/1333 1.5V

SATA-ODD

SATA-HDD
& Fall Sensor

PI2EQX3211BHE

PG 35

PG 35

PG 33PG 33

PG 42

PG 45

PG 52

SATA

SATA

SATA

IHDA
USB2.0

Auburndale/
Clarksfield

( rPGA 989 )

PG 3,4,5,6

PCH

CLOCK

SLG8SP585VTR
(QFN-32)

PCIEx16

DDR3 x 4
(512M 64bits)

PG 20

DMI X 4FDI

USB2.0 x 3
PCIEx1
PCIEx1

USB2.0

PCIEx2
USB2.0

PG 38

PG 15

ATI M92-XT

PCI EXPRESS GFX

PG 16,17,18,19,21,22

POWER

+1.5V_SUS/+0.75V_DDR_VTT
+1.05V
+1.1V_DDR_VTT

LVDS

HDMI

VGA

USB conn x 3

PG 33, 34

AUDIO/AMP

92HD73C

PG 39

Audio
SPK conn

Audio
Jacks x3

PG 39 PG 40

D D

1

Camera + D-MIC

PG 40

USER
INTERFACE

PG 37

2

KBC

ITE8502

SPI PS/2

FLASH
2Mbyts

PG 30

LPC

3

PG 29

Touchpad

PG 36

PG 7,8,9,10,11,12

17X8

Keyboard

4

PG 36

USB2.0

5

6

PWB:

PG 47
PG 48
PG 49

Panel Connector

HDMI CONN.

CRT CONN.

DC/DC

+3.3V_ALW/+5V_ALW/
+15V_ALW

VGA Core

PG 24

PG 24

PG 25

LAN
RTL8111DL\RJ45\Transformer

EXPRESS/Card Reader CONN.

MINI-CARD

CPU VRREGULATOR

WLAN

MINI-CARD

WWAN

Bluetooth BTB Conn

Title

Title

Title

Schematic Block Diagram1

Schematic Block Diagram1

Schematic Block Diagram1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

FM9 1A

FM9 1A

FM9 1A

Date: Sheet of

Date: Sheet of

Date: Sheet of

PG 32

PG 31

PG 32

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

7

PG 51

PG 46

PG 50

PG 41

PG 28

1 64Thursday, February 26, 2009

1 64Thursday, February 26, 2009

1 64Thursday, February 26, 2009

8

1

2

3

4

5

6

7

8

Table of Contents Power States

PAGE DESCRIPTION

1

Schematic Block Diagram

2

Front Page

3-6

Clarksfield/Auburndale

7-12

PCH

13-14

A A

B B

C C

DDRIII SO-DIMM(204P)

15

Clock Generator

16-22

M92-S2-XT

23

BLANK PAGE

24

LCD CONN / HDMI CONN

25

CRT CONN

26

OZ888GS0L3N
BLANK PAGE

27
28

Express/CRard/1394

29

SIO (ITE8512)

30

FLASH / RTC

31

MINI-Card (WWAN)

32

MINI-Card (WLAN\WPAN)
Left PUSB/ESATA

33
34

Right USB
SATA (HDD & CD_ROM)

35

TP / KEYBOARD

36

SWITCH / /LED

37
38

FAN / THERMAL
Azelia CODEC

39
40

AUDIO CONN

41

LAN(RTL8111DL/RJ-45)

42

System Reset Circuit

43

Blank Page

44451.8V_RUN(RT9018/RT9024)
Charger (ISL88731)

46

3V/5V (TPS51427A)

1.5_DDR/0.75(TPS51116)

47

1.05V_PCH(TPS51218)

48

1.1_VTT(TPS51218)

49
50

VGA_M92-XT(MAX8792)

51

V_CORE(ISL62882)

52

Run Power Switch

53

DCin & Batt

54

PAD & SCREW

55

EMI CAP

56

SMBUS BLOCK

57

THERMAL MAP

58

Power Block Diagram

59

XDP

POWER PLANE

+PWR_SRC
+RTC_CELL
+3.3V_ALW
+5V_ALW2
+3.3V_LAN
+5V_SUS
+3.3V_SUS
+1.5V_SUS
+0.75V_DDR_VTT
+5V_RUN
+3.3V_RUN
+1.8V_RUN
+1.5V_RUN
+1.8V_RUN_GFX
+VCC_GFX_CORE
+1.05V_PCH
+VCC_CORE
+LCDVCC
+5V_MOD
+5V_HDD
+1.1V_VTT 03,05,10,11,49,59+1.1V
+1.1V_GFX_PCIE

10V~+19V

+3.0V~+3.3V

+3.3V
+5V
+3.3V
+5V
+3.3V
+1.8V
+0.9V
+5V
+3.3V
+1.8V
+1.5V
+1.25V

+0.9V~+1.2V RUN_ON

+1.05V 08,09,11,15,48

+0.7V~+1.77V

+3.3V
+5V
+5V

+1.1V 18,50

GND PLANE PAGE

GND_CHG
GND_1.05V
GND_VGA
GND_SIGNAL
AGND_DC/DC

GND

46
47
50
51
52
ALL

24,30,45,46,47,48,49,50,51
08,11,29,30
08,29,30,35,36,37,42,44,45,46,47,52,53
37,46,53
41
11,33,34,35,37,51,52

7,09,10,11,13,14,19,24,26,28,29,37,41,42,44
,48,49,50,51,52

03,05,13,14,47,50,52
13,14,47,52
11,18,24,25,35,36,38,39,40,52

3,7,8,9,10,11,13,14,15,17,24,25,26,28,29,30
,31,32,33,35,37,38,39,40,41,42,46,51,52,59

05,11,26,44,52
11,18,19,20,28,31,32,52
17,18,21,22,44,52
18,21,50

05,51
26
36
36

DESCRIPTION

DESCRIPTION

MAIN POWER
RTC
8051 POWER
LARGE POWER
LAN POWER
SLP_S5# CTRLD POWER
SLP_S5# CTRLD POWER
SODIMM POWER
SODIMM POWER
SLP_S3# CTRLD POWER
SLP_S3# CTRLD POWER
SDVO POWER
CALISTOGA/ICH9 POWER
VGA POWER
VGA POWER
CPU/CALISTOGA/ICH8 POWER
CPU CORE POWER
LCD Power
Module Power
HDD Power

CONTROL
SIGNAL

ALWON
RUN_ON
AUX_ON
SUS_ON
SUS_ON
SUS_ON
RUN_ON
RUN_ON
RUN_ON
RUN_ON
RUN_ON
RUN_ON

1.05V_RUN_ON
IMVP_VR_ON

LCDVCC_TST_EN
& ENVDD

MODC_EN
HDDC_EN

ACTIVE INVOLTAGE PAGE

S0~S5
S0~S5
S0~S5
S0~S5

D D

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

1

2

3

4

5

6

Date: Sheet of

COMPUTER

Index & Power Status

Index & Power Status

Index & Power Status

FM9 1A

FM9 1A

FM9 1A

7

2 64Thursday, February 26, 2009

2 64Thursday, February 26, 2009

2 64Thursday, February 26, 2009

8

5

4

3

2

1

AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)

SC(V1.0),P11: Should be shorted at the pins
and then routed to one end of the 49.9-Ω ±1%
resistor, pulled-down to GND on the board.

U3031A

U3031A

R7621KR762
1K

A24
C23
B22
A21

B24
D23
B23
A22

D24
G24
F23
H23

D25
F24
E23
G23

E22
D21
D19
D18
G21
E19
F21
G18

D22
C21
D20
C18
G22
E20
F20
G19

F17
E17

C17
F18

D17

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]

FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]

FDI_FSYNC[0]
FDI_FSYNC[1]

FDI_INT
FDI_LSYNC[0]

FDI_LSYNC[1]

DMI_TXN07

D D

C C

DMI_TXN17
DMI_TXN27
DMI_TXN37

DMI_TXP07
DMI_TXP17
DMI_TXP27
DMI_TXP37

DMI_RXN07
DMI_RXN17
DMI_RXN27
DMI_RXN37

DMI_RXP07
DMI_RXP17
DMI_RXP27
DMI_RXP37

0214

DG(V1.0),P79: should be tied to GND
(through 1K ±5% resistors),
if these signals are left floating,
there are nofunctional impacts
but a small amount of power (~15 mW)
maybe wasted.
DG(V1.1) P83:
FDI_FSYNC[0], FDI_FSYNC[1],
FDI_LSYNC[0],FDI_LSYNC[1]

B B

can be ganged together
with one resistor.

PCIE_MTX_GRX_C_N0
PCIE_MTX_GRX_C_N1
PCIE_MTX_GRX_C_N2
PCIE_MTX_GRX_C_N3
PCIE_MTX_GRX_C_N4
PCIE_MTX_GRX_C_N5
PCIE_MTX_GRX_C_N6
PCIE_MTX_GRX_C_N7
PCIE_MTX_GRX_C_N8
PCIE_MTX_GRX_C_N9
PCIE_MTX_GRX_C_N10
PCIE_MTX_GRX_C_N11
PCIE_MTX_GRX_C_N12
PCIE_MTX_GRX_C_N13
PCIE_MTX_GRX_C_N14
PCIE_MTX_GRX_C_N15

Processor
Pullups

A A

H_CATERR#
H_PROCHOT#_D
H_CPURST#

R793

R793

49.9/F

49.9/F

C1175 0.1U10 C1175 0.1U10
C1177 0.1U10 C1177 0.1U10
C1179 0.1U10 C1179 0.1U10
C1181 0.1U10 C1181 0.1U10
C1183 0.1U10 C1183 0.1U10
C1185 0.1U10 C1185 0.1U10
C1187 0.1U10 C1187 0.1U10
C1189 0.1U10 C1189 0.1U10
C1191 0.1U10 C1191 0.1U10
C1193 0.1U10 C1193 0.1U10
C1195 0.1U10 C1195 0.1U10
C1197 0.1U10 C1197 0.1U10
C1199 0.1U10 C1199 0.1U10
C1201 0.1U10 C1201 0.1U10
C1203 0.1U10 C1203 0.1U10
C1205 0.1U10 C1205 0.1U10

+1.1V_VTT

R794

R794

49.9/F

49.9/F

5

Clarksfield/Auburndale

Clarksfield/Auburndale

PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15

SC(1.0V),P17:
H_PROCHOT#D
use: pull to 68 ohm

R795

R795

if it isn'tt used: pull to 50 ohm

*68_NC

*68_NC

SC(1.0V),P17:
H_CATERR#

49.9-Ω ±1% Pull-Up to the VTT rail
(+V1.1S_VTT)

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS
PEG_RX#[0]

PEG_RX#[1]
PEG_RX#[2]

DMI Intel(R) FDI

DMI Intel(R) FDI

PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]

PCI EXPRESS -- GRAPHICS

PCI EXPRESS -- GRAPHICS

PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

PCIE_MTX_GRX_N[0..15] 16 PCIE_MTX_GRX_P[0..15] 16

PEG_ICOMPI

B26
A26
B27
A25

K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31

J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30

L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26

L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25

R742 49.9/FR742 49.9/F

R744 750/FR744 750/F

PCIE_MRX_GTX_N15
PCIE_MRX_GTX_N14
PCIE_MRX_GTX_N13
PCIE_MRX_GTX_N12
PCIE_MRX_GTX_N11
PCIE_MRX_GTX_N10
PCIE_MRX_GTX_N9
PCIE_MRX_GTX_N8
PCIE_MRX_GTX_N7
PCIE_MRX_GTX_N6
PCIE_MRX_GTX_N5
PCIE_MRX_GTX_N4
PCIE_MRX_GTX_N3
PCIE_MRX_GTX_N2
PCIE_MRX_GTX_N1
PCIE_MRX_GTX_N0

PCIE_MRX_GTX_P15
PCIE_MRX_GTX_P14
PCIE_MRX_GTX_P13
PCIE_MRX_GTX_P12
PCIE_MRX_GTX_P11
PCIE_MRX_GTX_P10
PCIE_MRX_GTX_P9
PCIE_MRX_GTX_P8
PCIE_MRX_GTX_P7
PCIE_MRX_GTX_P6
PCIE_MRX_GTX_P5
PCIE_MRX_GTX_P4
PCIE_MRX_GTX_P3
PCIE_MRX_GTX_P2
PCIE_MRX_GTX_P1
PCIE_MRX_GTX_P0

PCIE_MTX_GRX_C_N15
PCIE_MTX_GRX_C_N14
PCIE_MTX_GRX_C_N13
PCIE_MTX_GRX_C_N12
PCIE_MTX_GRX_C_N11
PCIE_MTX_GRX_C_N10

PCIE_MTX_GRX_C_N9
PCIE_MTX_GRX_C_N8
PCIE_MTX_GRX_C_N7
PCIE_MTX_GRX_C_N6
PCIE_MTX_GRX_C_N5
PCIE_MTX_GRX_C_N4
PCIE_MTX_GRX_C_N3
PCIE_MTX_GRX_C_N2
PCIE_MTX_GRX_C_N1
PCIE_MTX_GRX_C_N0

PCIE_MTX_GRX_C_P15
PCIE_MTX_GRX_C_P14
PCIE_MTX_GRX_C_P13
PCIE_MTX_GRX_C_P12
PCIE_MTX_GRX_C_P11
PCIE_MTX_GRX_C_P10

PCIE_MTX_GRX_C_P9
PCIE_MTX_GRX_C_P8
PCIE_MTX_GRX_C_P7
PCIE_MTX_GRX_C_P6
PCIE_MTX_GRX_C_P5
PCIE_MTX_GRX_C_P4
PCIE_MTX_GRX_C_P3
PCIE_MTX_GRX_C_P2
PCIE_MTX_GRX_C_P1
PCIE_MTX_GRX_C_P0

PCIE_MTX_GRX_C_P0
PCIE_MTX_GRX_C_P1
PCIE_MTX_GRX_C_P2
PCIE_MTX_GRX_C_P3
PCIE_MTX_GRX_C_P4
PCIE_MTX_GRX_C_P5
PCIE_MTX_GRX_C_P6
PCIE_MTX_GRX_C_P7
PCIE_MTX_GRX_C_P8
PCIE_MTX_GRX_C_P9
PCIE_MTX_GRX_C_P10
PCIE_MTX_GRX_C_P11
PCIE_MTX_GRX_C_P12
PCIE_MTX_GRX_C_P13
PCIE_MTX_GRX_C_P14
PCIE_MTX_GRX_C_P15

PCIE_MRX_GTX_N[0..15] 16

PCIE_MRX_GTX_P[0..15] 16

SC(V1.0),P17,35:
This signal should be connected to
the processor's VCCPWRGOOD_1
and VCCPWRGOOD_0 input to
indicate when the
processor power is valid.

VTTPWRGOOD
SC(V1.0)P18:
VTT_1.1 VR power good signal
to processor. Signal voltage level
is 1.1 V.

1

+1.5V_SUS

R778

R778

4.75K/F

4.75K/F

R779

R779
12K/F

12K/F

C1176 0.1U10 C1176 0.1U10
C1178 0.1U10 C1178 0.1U10
C1180 0.1U10 C1180 0.1U10
C1182 0.1U10 C1182 0.1U10
C1184 0.1U10 C1184 0.1U10
C1186 0.1U10 C1186 0.1U10
C1188 0.1U10 C1188 0.1U10
C1190 0.1U10 C1190 0.1U10
C1192 0.1U10 C1192 0.1U10
C1194 0.1U10 C1194 0.1U10
C1196 0.1U10 C1196 0.1U10
C1198 0.1U10 C1198 0.1U10
C1200 0.1U10 C1200 0.1U10
C1202 0.1U10 C1202 0.1U10
C1204 0.1U10 C1204 0.1U10
C1206 0.1U10 C1206 0.1U10

Processor Compensation Signals

R796

R796

R797

R797

49.9/F

49.9/F

49.9/F

49.9/F

DG(V1.0),P17:
COMP[0.1] 49.9-Ω ±1% pull-down to GND
COMP[2.3] 20-Ω ±1% pull-down to GND

4

R798

R798
20/F

20/F

PM_DRAM_PWRGD

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P15

H_COMP0
H_COMP1
H_COMP2
H_COMP3

R799

R799
20/F

20/F

U3031B

SC(V1.0),P17:
SKTOCC#
Can be left No Connect
or tied to GND

T182T182

H_PECI10

H_THERM10

H_CPURST#60

PM_SYNC7

H_PWRGOOD10,60

PM_DRAM_PWRGD7

H_VTTPWRGD42

H_PWRGD_XDP60

PLTRST#9,16,26,28,29,31,32,41

RSTIN#:
DG(V1.11)(Doc.# 414044),P10:
Need a voltage divider
network to scale down from

3.3V (PCH driven) to 1.05V/1.1V (Clarksfield/Auburndale)

SM_DRAMPWROK:
DG(V1.0) P311&SC(V1.0) P18:recommend 4.75-kΩ
pull-up to DDR3 Power Rail (VDDQ) of +V1.5U
and a 12-kΩ pull-down to ground to convert
to processor’s VTT level.
CRB(V1.0) P11:CRB uses a 3.3V (always ON) rail
with 2K and 1K combination. CRB Implementation
is different for the Calpella Platform Design Guide.
Customers to
follow the latest Calpella Platform Design
Guide for DRAMPWROK Implementation.

R751 0R751 0

R755 0R755 0

R776 1.5K/FR776 1.5K/F

SM_DRAMPWROK:(Intell Feedback)
Either way works.

H_COMP3
H_COMP2
H_COMP1
H_COMP0

TP_SKT0CC#

H_CATERR#

H_PECI_ISO

H_PROCHOT#_D

H_CPURST#

PM_DRAM_PWRGD

R777

R777
750/F

750/F

U3031B

AT23
AT24

G16

AT26

AH24

AK14

AT15

AN26

AK15

AP26

AL15

AN14

AN27

AK13

AM15

AM26

AL14

Clarksfield/Auburndale

Clarksfield/Auburndale

0214

CRB(V1.0) P11:
is it necessery?

DDR3 Compensation Signals

R800

R800
130/F

130/F

3

COMP3
COMP2
COMP1
COMP0

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

RESET_OBS#

PM_SYNC

VCCPWRGOOD_1

VCCPWRGOOD_0

SM_DRAMPWROK

VTTPWRGOOD

TAPPWRGOOD

RSTIN#

H_THERM

MMST3904-7-F

MMST3904-7-F

T188T188

T187T187

R801

R801

R802

R802

24.9/F

24.9/F

100/F

100/F

DG(V1.0),P83:
SM_RCOMP[0] 100-Ω ±1% pull-down to GND
SM_RCOMP[1] 24.9-Ω ±1% pull-down to GND
SM_RCOMP[2] 130-Ω ±1% pull-down to GND

MISC THERMAL

MISC THERMAL

PWR MANAGEMENT

PWR MANAGEMENT

+3.3V_RUN

R28

R28
10M

10M

2

Q7

Q7

1 3

XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TCLK

SM_RCOMP_2
SM_RCOMP_1
SM_RCOMP_0

Layout Note: Place
these resistors
near Processor

12

R787 *51_NCR787 *51_NC
R788 *51_NCR788 *51_NC
R789 *51_NCR789 *51_NC
R790 *51_NCR790 *51_NC

CLOCKS

CLOCKS

DDR3

DDR3

JTAG & BPM

JTAG & BPM

2

C24

C24

0.1U

0.1U

10

10

MISC

MISC

31

2

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PM_EXT_TS#[0]
PM_EXT_TS#[1]

PRDY#

PREQ#

TRST#

TDI_M

TDO_M

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

PM_THRMTRIP# 46

Q6

Q6
2N7002W-7-F

2N7002W-7-F

+1.1V_VTT

A16
B16

AR30
AT30

E16
D16

A18
A17

F6

SM_RCOMP_0

AL1

SM_RCOMP_1

AM1

SM_RCOMP_2

AN1
AN15

AP15

AT28

XDP_PREQ#

AP27

XDP_TCLK

AN28

TCK

XDP_TMS

AP28

TMS

XDP_TRST#

AT27

XDP_TDI_R

AT29

TDI

XDP_TDO_R

AR27

TDO

XDP_TDI_M

AR29

XDP_TDO_M

AP29

H_DBR#_R

AN25

XDP_OBS0_R

AJ22

XDP_OBS1_R

AK22

XDP_OBS2_R

AK24

XDP_OBS3_R

AJ24

XDP_OBS4_R

AJ25

XDP_OBS5_R

AH22

XDP_OBS6_R

AK23

XDP_OBS7_R

AH23

DBR#:
SC(V1.0) P22:Connected to the DBR# pin of the Processor.50-Ω to 5-kΩ pull-up to 3.3VS
CRB(V1.0) P11,P71:CRB uses a 1-kΩ pull-up to 3.3VS.
On the CRB this signal is ANDed with Master Reset to generate SYS_RESET.

DBR#:(Intell fe edback)
Nothing wrong w / CRB design. I f you want to
connect it to PCH directly, make sure pull high
to 3.3V (S0) ma in power.

CLK_CPU_BCLK 10
CLK_CPU_BCLK# 10

BCLK_ITP 60
BCLK_ITP# 60

CLK_PCIE_3GPLL 9
CLK_PCIE_3GPLL# 9

DPLL_REF_SSCLK and DPLL_REF_SSCLK# can be connected to GND
on Auburndale d irectly if moth erboard
only supports d iscrete graphic s.

DDR3_DRAMRST# 13,14

R1065

R1065

*12.4K/F_NC

*12.4K/F_NC

+1.1V_VTT

PM_EXTTS#0 13
PM_EXTTS#1 14

XDP_DBRESET# 7,60
XDP_OBS[0:7] 60

R759 0R759 0

R758 0R758 0
R760 0R760 0
R761 0R761 0
R763 0R763 0
R764 0R764 0
R766 0R766 0
R767 0R767 0
R769 0R769 0

R752 10K/FR752 10K/F
R753 10K/FR753 10K/F
R754 0R754 0
R756 0R756 0

XDP_PRDY# 60
XDP_PREQ# 60

XDP_TCLK 60
XDP_TMS 60
XDP_TRST# 60

T186T186
T168T168
T169T169

XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7

JTAG MAPPING

XDP_TDI_R
XDP_TDO_M

XDP_TDI_M
XDP_TDO_R

Scan Chain
(Default)

CPU Only

GMCH Only

DG(v1.0) table 27

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

R780 0R780 0

R781 *0_NCR781 *0_NC
R7830R783
0

R785 *0_NCR785 *0_NC

R786 0R786 0

STUFF -> R780, R783, R786
NO STUFF -> R781, R785

STUFF -> R780, R781
NO STUFF -> R783, R785, R786

STUFF -> R785, R786
NO STUFF -> R780, R781, R783

TRST#
SC(V1.0)P22:
should be route d as a single
daisy chain to all loads and
terminated at the end of the trace.
51 Ω ± 5% pull down resistor.
CRB()V1.0)P11

QUANTA

QUANTA

QUANTA

COMPUTER

COMPUTER

COMPUTER

AUBURNDA 1/4

AUBURNDA 1/4

AUBURNDA 1/4

FM9 1A

FM9 1A

FM9 1A

1

CRB(v0.71) P.11

2

XDP_TDI 60
XDP_TDO 60

XDP_TRST#

R78451R784
51

3 64Thursday, February 26, 2009

3 64Thursday, February 26, 2009

3 64Thursday, February 26, 2009

5

4

3

2

1

AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3)

U3031D

AF3
AG1

AJ3
AK1
AG4
AG3

AJ4
AH4
AK3
AK4

AM6
AN2

AK5
AK2

AM4
AM3

AP3

AN5

AT4

AN6
AN4
AN3

AT5
AT6

AN7

AP6
AP8
AT9
AT7
AP9

AR10
AT10

AB1

AC5
AC6

B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2

G1
G5

K2
M1

K5
K4
M4
N5

W5

R7

Y7

J6
J3

J2
J1
J5

L3

U3031D

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

W8

SB_CK[0]

W9

SB_CK#[0]

M3

SB_CKE[0]

V7

SB_CK[1]

V6

SB_CK#[1]

M2

SB_CKE[1]

AB8

SB_CS#[0]

AD6

SB_CS#[1]

AC7

SB_ODT[0]

AD1

SB_ODT[1]

M_B_DM0

D4

SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

DDR SYSTEM MEMORY - B

DDR SYSTEM MEMORY - B

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

E1
H3
K1
AH1
AL2
AR4
AT8

D5
F4
J4
L4
AH2
AL4
AR5
AR8

C5
E3
H4
M5
AG2
AL5
AP5
AR7

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_CLK0 14
M_B_CLK0# 14
M_B_CKE0 14

M_B_CLK1 14
M_B_CLK1# 14
M_B_CKE1 14

M_B_CS0# 14
M_B_CS1# 14

M_B_ODT0 14
M_B_ODT1 14

M_B_DM[7:0] 14

M_B_DQS#[7:0] 14

M_B_DQS[7:0] 14

M_B_A[15:0] 14

U3031C

U3031C

AA6

SA_CK[0]

D D

M_A_DQ[63:0]13

C C

B B

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

M_A_BS013
M_A_BS113
M_A_BS213

M_A_CAS#13
M_A_RAS#13
M_A_WE#13

C10

D10

H10

G10

AH5
AF5
AK6
AK7
AF6
AG5

AJ10
AL10

AK12

AK8

AK11

AN8
AM10
AR11

AL11

AM9

AN9

AT11

AP12
AM12
AN12
AM13

AT14

AT12

AL13
AR14

AP14

AC3
AB2

AE1
AB3
AE9

A10

B10
E10

F10

J10

AJ7
AJ6

AJ9

AL7
AL8

C7

A7

A8

D8

E6
F7
E9
B7
E7

C6
G8

K7

J8

G7

J7

L7
M6
M8

L9

L6

K8
N8

P9

U7

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_CK#[0]

SA_CKE[0]

SA_CK[1]

SA_CK#[1]

SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AA7
P7

Y6
Y5
P6

AE2
AE8

AD8
AF9

B9
D7
H7
M7
AG6
AM7
AN10
AN13

C9
F8
J9
N9
AH7
AK9
AP11
AT13

C8
F9
H9
M9
AH8
AK10
AN11
AR13

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_CLK0 13
M_A_CLK0# 13
M_A_CKE0 13

M_A_CLK1 13
M_A_CLK1# 13
M_A_CKE1 13

M_A_CS0# 13
M_A_CS1# 13

M_A_ODT0 13
M_A_ODT1 13

M_A_DM[7:0] 13

M_A_DQS#[7:0] 13

M_A_DQS[7:0] 13

M_A_A[15:0] 13

M_B_DQ[63:0]14

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60M_A_A0
M_B_DQ61
M_B_DQ62
M_B_DQ63

M_B_BS014
M_B_BS114
M_B_BS214

M_B_CAS#14
M_B_RAS#14
M_B_WE#14

Clarksfield/Auburndale

Clarksfield/Auburndale

A A

5

Channel A DQ[15,32,48,54], DM[5]
Requires minimum 12mils spacing
with all other signals, including data signals.

4

Channel B DQ[16,18,36,42,56,57,60,61,62]
Requires minimum 12mils spacing
with all other signals, including data signals.

3

Clarksfield/Auburndale

Clarksfield/Auburndale

2

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

COMPUTER

AUBURNDA 2/4

AUBURNDA 2/4

AUBURNDA 2/4

FM9 1A

FM9 1A

FM9 1A

4 64Thursday, February 26, 2009

4 64Thursday, February 26, 2009

4 64Thursday, February 26, 2009

1

5

U3031F

CPU Core Power

+VCC_CORE

D D

C C

B B

A A

U3031F

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

Clarksfield/Auburndale

Clarksfield/Auburndale

AH14

VTT0_1

AH12

VTT0_2

AH11

VTT0_3

AH10

VTT0_4

J14

VTT0_5

J13

VTT0_6

H14

VTT0_7

H12

VTT0_8

G14

VTT0_9

G13

VTT0_10

G12

VTT0_11

G11

VTT0_12

F14

VTT0_13

F13

VTT0_14

F12

VTT0_15

F11

VTT0_16

E14

VTT0_17

E12

VTT0_18

D14

VTT0_19

D13

VTT0_20

D12

VTT0_21

D11

VTT0_22

C14

VTT0_23

C13

VTT0_24

C12

VTT0_25

C11

VTT0_26

B14

VTT0_27

B12

VTT0_28

A14

VTT0_29

A13

VTT0_30

A12

VTT0_31
VTT0_32

VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VTT_SELECT

ISENSE

VCC_SENSE
VSS_SENSE

VTT_SENSE

A11

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11

+VTT_43

J16

+VTT_44

J15

VTT0_43,VTT0_44:
CRB(V1.0)P13
Why add 0ohm?? Is it trace width control??

VTT0_43,VTT0_44:(Intel feedback)
They are connected to hidden page for
intel validation purpose.

AN33

PSI#

VID0

AK35

VID1

AK33

VID2

AK34

VID3

AL35

VID4

AL33

VID5

AM33

VID6

AM35

DPRSLPVR

AM34

G15

AN35

AJ34
AJ35

B15

TP_VSS_SENSE_VTT

A15

VSS_SENSE_VTT:
SC(V1.0)P20
Connect VSS_SENSE_VTT to GND
or can be left floating.
Note: CRB has the VSS_SENSE_VTT floating.

1.1V RAIL POWER

1.1V RAIL POWER

CPU CORE SUPPLY

CPU CORE SUPPLY

POWER

POWER

PROC_DPRSLPVR

CPU VIDS

CPU VIDS

VSS_SENSE_VTT

SENSE LINES

SENSE LINES

AUBURNDALE/CLARKSFIELD PROCESSOR (POWER)

5

C1207

C1207
10U

10U

C1234

C1234
22U

22U

4

C1208

C1208
10U

10U

C1235

C1235
22U

22U

H_PSI# 51

VID0 51
VID1 51
VID2 51
VID3 51
VID4 51
VID5 51
VID6 51
DPRSLPVR 51

H_VTTVID1 49

I_MON 51

VTT_SENSE 49

T196T196

4

+1.1V_VTT

C1212

C1209

C1209
10U

10U

C1210

C1210
10U

10U

+1.1V_VTT

C1211

C1211
10U

10U

C1212
10U

10U

+1.1V_VTT

C1213

C1213
10U

10U

C1217

C1217
22U

22U

C1214

C1214
*10U_NC

*10U_NC

+1.1V_VTT

C1222

C1222
22U

22U

3

C1237

C1237
22U

22U

C1269

C1270

C1270

22U

22U

22U

22U

VTT_SELECT:
High level 1.05V for Auburndale
Low level 1.1V for Clarksfield

+VCC_CORE

VCC_SENSE & VSS_SENSE:
SC(V1.0)P19

R807

R807

100- ±1% pull-down to GND near processor

100/F

100/F

VCCSENSE 51
VSSSENSE 51

R819

R819
100/F

100/F

PROC_DPRSLPVR:
SC(V1.0)P19:
It is important to have the resistor stuffing options
in the design f or the Turbo fu nctionality.
The stuffing an d no-stuffing o f the resistors
will depend on the POC configu ration of AUB
and CFD
CRB(V1.0)P67:
uses 1K pull-up and pull-down resistors
CRB default set ting is "1"

C1273

C1273
22U

22U

C1215

C1215
*10U_NC

*10U_NC

C1223

C1223
22U

22U

C1238

C1238
22U

22U

3

AUBURNDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER)

U3031G

U3031G

AT21

VAXG1

AT19

VAXG2

AT18

VAXG3

AT16

VAXG4

AR21

VAXG5

AR19

VAXG6

AR18

VAXG7

AR16

VAXG8

AP21

VAXG9

AP19

VAXG10

AP18

VAXG11

AP16

VAXG12

AN21

VAXG13

AN19

VAXG14

AN18

VAXG15

AN16

VAXG16

AM21

VAXG17

AM19

VAXG18

AM18

VAXG19

AM16

VAXG20

AL21

VAXG21

AL19

VAXG22

AL18

VAXG23

AL16

VAXG24

AK21

VAXG25

AK19

VAXG26

AK18

VAXG27

AK16

VAXG28

AJ21

VAXG29

AJ19

VAXG30

AJ18

VAXG31

AJ16

VAXG32

AH21

VAXG33

AH19

VAXG34

AH18

VAXG35

AH16

VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

K26

VTT1_48

J27

VTT1_49

J26

C1274

C1274
22U

22U

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

Clarksfield/Auburndale

Clarksfield/Auburndale

Note:
For Validating IMVP VR R814 should be STUFF
and R827 NO_STUFF

3

2

GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

GFX_VR_EN

GFX_IMON

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18

VTT0_59
VTT0_60
VTT0_61
VTT0_62

VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68

VCCPLL1
VCCPLL2
VCCPLL3

R8101KR810
1K

R820

R820
*1K_NC

*1K_NC

R8111KR811
1K

R821

R821
*1K_NC

*1K_NC

AR22
AT22

AM22
AP22
AN22
AP23
AM23
AP24
AN24

AR25
AT25

R803 *1K/F_NCR803 *1K/F_NC

AM24

AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1

P10
N10
L10
K10

J22
J20
J18
H21
H20
H19

L26
L27
M26

R8121KR812
1K

R822

R822
*1K_NC

*1K_NC

+1.1V_VTT

R813

R813
*1K_NC

*1K_NC

R8231KR823
1K

4

GFX_VID[0..6],GFX_VR_EN,GFX_DPRSLPVR,GFX_IMON:
Could this be left unconnected when not in use?

GFX_VID[0..6],GFX_VR_EN,GFX_DPRSLPVR,GFX_IMON:(Intel feedback)
Yes, see DG rev1.5

+1.5V_SUS

C1248

C1248
10U

10U

C1272

C1272
22U

22U

C12191UC1219
1U

C1277

C1277

2.2U

2.2U

R816

R816
*1K_NC

*1K_NC

R8261KR826
1K

+

+

+

+

C1258

C1258
*330U_NC

*330U_NC

7343

7343

2.5

2.5

C12201UC1220
1U

C1224

C1224
330U

330U

7343

7343

2.5

2.5

+1.1V_VTT

+1.8V_RUN

C1278

C1278

4.7U

4.7U

R8171KR817
1K

R827

R827
*1K_NC

*1K_NC

C12211UC1221
1U

C1225

C1225
22U

22U

C1279

C1279
22U

22U

R818

R818
*1K_NC

*1K_NC

R8281KR828
1K

+VCC_CORE

C1226

C1226
22U

22U

C1227

C1227
22U

22U

C1239

C1239
22U

22U

C1250

C1250

C1249

C1249

10U

10U

10U

10U

C1262

C1262

C1261

C1261

10U

10U

10U

10U

+

+

+

+

C1507

C1507
*470U_NC

*470U_NC

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

COMPUTER

AUBURNDA 3/4

AUBURNDA 3/4

AUBURNDA 3/4

FM9 1A

FM9 1A

FM9 1A

C12161UC1216
1U

C12751UC1275
1U

R814

R814
*1K_NC

*1K_NC

R8241KR824
1K

C1247

C1247
10U

10U

C1271

C1271
22U

22UC1269

2

C12181UC1218
1U

C12761UC1276
1U

R8151KR815
1K

R825

R825
*1K_NC

*1K_NC

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

GRAPHICS

GRAPHICS

GFX_DPRSLPVR

GRAPHICS VIDs

GRAPHICS VIDs

FDI PEG & DMI

FDI PEG & DMI

POWER

POWER

DDR3 - 1.5V RAILS

DDR3 - 1.5V RAILS

1.1V1.8V

1.1V1.8V

VID0
VID1
VID2
VID3
VID4
VID5
VID6
DPRSLPVR
H_PSI#

C1228

C1228
22U

22U

C1240

C1240
22U

22U

C1251

C1251
10U

10U

C1263

C1263
10U

10U

C1508

C1508
*470U_NC

*470U_NC

C1229

C1229
22U

22U

C1241

C1241
22U

22U

C1252

C1252
10U

10U

C1264

C1264
10U

10U

1

C1231

C1231

C1232

C1230

C1230
22U

22U

C1242

C1242
22U

22U

C1254

C1254

C1253

C1253

10U

10U

10U

10U

C1265

C1265

C1266

C1266

10U

10U

10U

10U

1

C1232

22U

22U

22U

22U

C1243

C1243

C1244

C1244

22U

22U

22U

22U

C1256

C1256

C1255

C1255

10U

10U

10U

10U

C1267

C1267

C1268

C1268

10U

10U

10U

10U

5 64Thursday, February 26, 2009

5 64Thursday, February 26, 2009

5 64Thursday, February 26, 2009

5

4

3

2

1

AUBURNDALE/CLARKSFIELD PROCESSOR (GND) AUBURNDALE/CLARKSFIELD PROCESSOR( RESERVED, CFG)

U3031H

U3031H

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

AR23

VSS7

AR20

VSS8

AR17

D D

C C

B B

VSS9

AR15

VSS10

AR12

VSS11

AR9

VSS12

AR6

VSS13

AR3

VSS14

AP20

VSS15

AP17

VSS16

AP13

VSS17

AP10

VSS18

AP7

VSS19

AP4

VSS20

AP2

VSS21

AN34

VSS22

AN31

VSS23

AN23

VSS24

AN20

VSS25

AN17

VSS26

AM29

VSS27

AM27

VSS28

AM25

VSS29

AM20

VSS30

AM17

VSS31

AM14

VSS32

AM11

VSS33

AM8

VSS34

AM5

VSS35

AM2

VSS36

AL34

VSS37

AL31

VSS38

AL23

VSS39

AL20

VSS40

AL17

VSS41

AL12

VSS42

AL9

VSS43

AL6

VSS44

AL3

VSS45

AK29

VSS46

AK27

VSS47

AK25

VSS48

AK20

VSS49

AK17

VSS50

AJ31

VSS51

AJ23

VSS52

AJ20

VSS53

AJ17

VSS54

AJ14

VSS55

AJ11

VSS56

AJ8

VSS57

AJ5

VSS58

AJ2

VSS59

AH35

VSS60

AH34

VSS61

AH33

VSS62

AH32

VSS63

AH31

VSS64

AH30

VSS65

AH29

VSS66

AH28

VSS67

AH27

VSS68

AH26

VSS69

AH20

VSS70

AH17

VSS71

AH13

VSS72

AH9

VSS73

AH6

VSS74

AH3

VSS75

AG10

VSS76

AF8

VSS77

AF4

VSS78

AF2

VSS79

AE35

VSS80

Clarksfield/Auburndale

Clarksfield/Auburndale

VSS

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

U3031I

U3031I

K27

VSS161

K9

VSS162

K6

VSS163

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

H8

VSS179

H5

VSS180

H2

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

G9

VSS185

G6

VSS186

G3

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

E8

VSS202

E5

VSS203

E2

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

D9

VSS208

D6

VSS209

D3

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

B8

VSS227

B6

VSS228

B4

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

A9

VSS233

Clarksfield/Auburndale

Clarksfield/Auburndale

VSS

VSS

NCTF

NCTF

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7

AT35
AT1
AR34
B34
B2
B1
A35

+M_VREF_DQ_DIMM0
+M_VREF_DQ_DIMM1

R833 0R833 0
R834 0R834 0

CFG0

CFG3
CFG4

CFG7

TP_RSVD17_R
TP_RSVD18_R

U3031E

U3031E

AP25

RSVD1

AL25

RSVD2

AL24

RSVD3

AL22

RSVD4

AJ33

RSVD5

AG9

RSVD6

M27

RSVD7

L28

RSVD8

J17

SA_DIMM_VREF

H17

SB_DIMM_VREF

G25

RSVD11

G17

RSVD12

E31

RSVD13

E30

RSVD14

AM30

CFG[0]

AM28

CFG[1]

AP31

CFG[2]

AL32

CFG[3]

AL30

CFG[4]

AM31

CFG[5]

AN29

CFG[6]

AM32

CFG[7]

AK32

CFG[8]

AK31

CFG[9]

AK28

CFG[10]

AJ28

CFG[11]

AN30

CFG[12]

AN32

CFG[13]

AJ32

CFG[14]

AJ29

CFG[15]

AJ30

CFG[16]

AK30

CFG[17]

H16

RSVD_TP_86

B19

RSVD15

A19

RSVD16

A20

RSVD17

B20

RSVD18

U9

RSVD19

T9

RSVD20

AC9

RSVD21

AB9

RSVD22

C1

RSVD_NCTF_23

A3

RSVD_NCTF_24

J29

RSVD26

J28

RSVD27

A34

RSVD_NCTF_28

A33

RSVD_NCTF_29

C35

RSVD_NCTF_30

B35

RSVD_NCTF_31

Clarksfield/Auburndale

Clarksfield/Auburndale

RESERVED

RESERVED

RSVD32
RSVD33

RSVD34
RSVD35

RSVD36

RSVD_NCTF_37

RSVD38
RSVD39

RSVD_NCTF_40
RSVD_NCTF_41

RSVD_NCTF_42
RSVD_NCTF_43

RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52

RSVD53
RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57

RSVD58

RSVD_TP_59
RSVD_TP_60

KEY
RSVD62
RSVD63
RSVD64
RSVD65

RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75

RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85

VSS

AJ13
AJ12

AH25
AK26

AL26
AR2

AJ26
AJ27

AP1
AT2

AT3
AR1

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32

E15
F15
A2
D15
C15
AJ15
AH15

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3

V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

AP34

RSVD64_R
RSVD65_R

Can be left NC is Intel CRM

R8390R839

implementation; ESD/DG

0

recommendation to GND

R831 0R831 0
R832 0R832 0

1 0

CFG4

A A

The Clarkfield processor's PCI Express interface may
not meet PCI Express 2.0 jitter specifications. Intel
recommends placing a 3.01K +/- 5% pull down resistor to
VSS on CFG[7] pin for both rPGA and BGA components.
This pull down resistor should be removed when this
issue is fixed.

CFG4
CFG0
CFG3
CFG7

R835 *3.01K/F_NCR835 *3.01K/F_NC
R836 *3.01K/F_NCR836 *3.01K/F_NC
R837 3.01K/FR837 3.01K/F
R838 *3.01K/F_NCR838 *3.01K/F_NC

PCIE LANE is Lane Numbers Reversed

5

4

(Display Port
Presence)

CFG0
(PCI-Epress
Configuration Select)

CFG3
(PCI-Epress Static
Lane Reversal)

Disabled; No Physical Display Port
attached to Embedded Diplay Port

Single PEG

Normal Operation Lane Numbers Reversed

3

Enabled; An external Display port
device is connected to the Embedded
Display port

Bifurcation enabled

2

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

COMPUTER

AUBURNDA 4/4

AUBURNDA 4/4

AUBURNDA 4/4

FM9 1A

FM9 1A

FM9 1A

1

6 64Thursday, February 26, 2009

6 64Thursday, February 26, 2009

6 64Thursday, February 26, 2009

5

4

3

2

1

IBEX PEAK-M (DMI,FDI,GPIO)

U3035C

U3035C

DMI_RXN03

D D

CS(V1.0) P32
PWROK and SYS_PWROK should be tied
together on the platform.MEPWROK can be connected

C C

to PCH_PWROK pin on PCH when Intel AMT
is not enabled.

B B

MEPWROK
SC(V1.0)P32:
It can be connected to PCH_PWROK pin
on PCH when Intel AMT is not enabled.

A A

DMI_RXN13
DMI_RXN23
DMI_RXN33

DMI_RXP03
DMI_RXP13
DMI_RXP23
DMI_RXP33

DMI_TXN03
DMI_TXN13
DMI_TXN23
DMI_TXN33

DMI_TXP03
DMI_TXP13
DMI_TXP23
DMI_TXP33

+1.05V_VCCIO

XDP_DBRESET#3,60

PCH_PWRGD29

PM_DRAM_PW RGD3

ICH_RSMRST#29

SUS_PWR_ACK29

SIO_PWRBTN#29

AC_PRESENT29

CLKRUN#

PCH_PWRGD
ICH_RSMRST#
LAN_RST#

LAN_RST#
DG(V1.0) P311
If integrated LAN is not used, recommend
to connect LAN_RST# to GND via an 8.2-kΩ
to 10-kΩ pull-down resistor.
EDS(V1.0)P64
must be grounded if Intel LAN is disabled.

R842 49.9/FR842 49.9/F

R1062 0R1062 0

R1063 0R1063 0

R846 0R846 0

+3.3V_RUN

R580 10K/FR580 10K/F

R1075 10K/FR1075 10K/F
R861 10K/FR861 10K/F
R1013 10K/FR1013 10K/F

5

DMI_ZCOMP

SYS_PWROK

PWROK

MEPWROK

LAN_RST#

ICH_RSMRST#

PM_BATLOW#

PM_RI#

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK / GPIO30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

F14

RI#

IbexPeak-M_R1P0

IbexPeak-M_R1P0

PM_RI#
PCIE_WAKE#

PWROK
SC(V1.0)P32:

8.2 kΩ to 10 kΩ pull-down resistor to GND.
PWROK and SYS_PWROK should be tied together on the platform.

R858 10K/FR858 10K/F
R860 1KR860 1K

System Power Management

System Power Management

+3.3V_SUS

4

DMI

FDI

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_LAN# / GPIO29

FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

BA18

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

PM_BATLOW#

PM_BATLOW#:
EDS(V1.0)P95: 15K~40K (+3.3V_SUS)
CRB(V1.0)P25: 8.2K (+3.3V_ALW)

PM_BATLOW#:(Intel feedback)
15K ~ 40K is a simulation result,
the expected value should be 20K
internal pull high in PCH.

8.2K is external pull high.

DG(V1.0)P185:

BH17
BD16

If the LVDS interface is not implemented,

BJ16

all signals associated with the interface can

BA16

be left as No Connects. The supply pins

BE14

VccTX_LVDS and VCCA_LVD can be

BA14

connected to ground.

BC12

DG(V1.1) P83:FDI_FSYNC[0], FDI_FSYNC[1],

BB18

FDI_LSYNC[0], FDI_LSYNC[1], and FDI_INT

BF17

signals on PCH side can be left as

BC16

no connect without any power

BG16

or functional impact.

AW16
BD14
BB14
BD12

BJ14
BF13
BH13
BJ12
BG14

J12

CLKRUN#

Y1

RSV_LPCPD#

P8

ICH_SUSCLK

F3

SLP_S5#_R

E4

SLP_S4#_R

H7

SLP_S3#_R

P12

SLP_M#_R

K8

N2

BJ10

PM_SLP_LAN#_R

F6

R859 8.2K/FR859 8.2K/F

T221T221

T222T222

R1073 0R1073 0

R1074 0R1074 0

T223T223

T224T224

T225T225

+3.3V_SUS

PCIE_WAKE# 28,31,32,41

CLKRUN# 29

SIO_SLP_S5# 29

SIO_SLP_S4# 13

SIO_SLP_S3# 29

PM_SYNC 3

5

3

DG(V1.0)P189:
If the CRT interface is not implemented,
all signals associated with the interface can
be left as No Connects. The pins
CRT_IRTN Connect this signals to GND
and DAC_IREF Connect to GND
via a 1.0 k ±0.5% pull-down resistor

R8561KR856
1K

IBEX PEAK-M (LVDS,DDI)

U3035D

U3035D

Y48

AB48

Y45

AB46

V48

AP39
AP41

AT43
AT42

AV53
AV51

BB47
BA52
AY48
AV47

BB48
BA50
AY49
AV48

AP48
AP47

AY53
AT49
AU52
AT53

AY51
AT48
AU50
AT51

AA52
AB53
AD53

V51
V53

Y53
Y51

AD48
AB51

T48
T47

L_BKLTEN
L_VDD_EN

L_BKLTCTL
L_DDC_CLK

L_DDC_DATA
L_CTRL_CLK

L_CTRL_DATA
LVD_IBG

LVD_VBG
LVD_VREFH

LVD_VREFL

LVDSA_CLK#
LVDSA_CLK

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

IbexPeak-M_R1P0

IbexPeak-M_R1P0

SDVO_TVCLKINN

SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN

DDPB_AUXP

LVDS

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

Digital Display Interface

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN
DDPD_AUXP

CRT

CRT

2

BJ46
BG46

BJ48
BG48

BF45

SDVO_INTN

BH45

SDVO_INTP

T51
T53

BG44
BJ44
AU38

DDPB_HPD

BD42

DDPB_0N

BC42

DDPB_0P

BJ42

DDPB_1N

BG42

DDPB_1P

BB40

DDPB_2N

BA40

DDPB_2P

AW38

DDPB_3N

BA38

DDPB_3P

Y49
AB49

BE44
BD44
AV40

DDPC_HPD

BE40

DDPC_0N

BD40

DDPC_0P

BF41

DDPC_1N

BH41

DDPC_1P

BD38

DDPC_2N

BC38

DDPC_2P

BB36

DDPC_3N

BA36

DDPC_3P

U50
U52

BC46
BD46
AT38

DDPD_HPD

BJ40

DDPD_0N

BG40

DDPD_0P

BJ38

DDPD_1N

BG38

DDPD_1P

BF37

DDPD_2N

BH37

DDPD_2P

BE36

DDPD_3N

BD36

DDPD_3P

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

SDVO

Display port BDisplay port CDisplay port D

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

IBEX PEAK-M 2/6

IBEX PEAK-M 2/6

IBEX PEAK-M 2/6

FM9 1A

FM9 1A

FM9 1A

7 64Thursday, February 26, 2009

7 64Thursday, February 26, 2009

7 64Thursday, February 26, 2009

1

5

4

3

2

1

C1284

C1284
*27P_NC

*27P_NC

50

50

+RTC_CELL

ACZ_BIT_CLK

ACZ_SYNC
ACZ_RST#
ACZ_SDOUT

R8671MR867
1M

R864 20K/FR864 20K/F

C12821UC1282

1U

R865 20K/FR865 20K/F

C12811UC1281

1U

INTVRMEN(Internal Voltage Regulator Enable) :
This signal enables the internal 1.05 V regulators.
This signal must be always pulled-up to VccRTC.

Flash Descriptor Security Override

Low = Enabled

GPIO33

High = Disabled

R503 *10K/F_NCR503 *10K/F_NC

1 2

GPIO33

(Internal 20K/F pull high to +3.3V_RUN)

Note : GPIO33 is a signal used for Flash
Descriptor Security Override/ME Debug
Mode.This signal should be only asserted
lowthrough an external pull-down in
manufacturing or debug environments
ONLY.

No Reboot strap.

Low = Default.

SPKR

+3.3V_RUN

1 2

R221 *1K_NCR221 *1K_NC

High = No Reboot.

SPKR

C1280

C1280

18PF

18PF

Y5

32.768KHZY532.768KHZ

C1283

C1283

18PF

18PF

Cap values depend on Xtal

+RTC_CELL

R868 330KR868 330K

SPKR39

ICH_AZ_CODEC_SDIN039

KB_LED_DET36

T183T183
T180T180
T178T178
T174T174
T175T175

23

SPI_CLK30
SPI_CS0#30

SPI_SI30

4 1

T185T185

SPI_SO30

R866

R866
10M

10M

RTC_X1
RTC_X2

RTC_RST#
SRTC_RST#
SM_INTRUDER#
PCH_INVRMEN

ACZ_BIT_CLK
ACZ_SYNC
SPKR
ACZ_RST#

ACZ_SDOUT

GPIO33

PCH_JTAG_TCK_BUF
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_RST#

IBEX PEAK-M (HDA,JTAG,SATA)

U3035A

U3035A

SPI_CLK
SPI_CS0#
SPI_CS1#

SPI_SI
SPI_SO

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN# / GPIO33

J30

HDA_DOCK_RST# / GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

TRST#

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IbexPeak-M_R1P0

IbexPeak-M_R1P0

RTCIHDA

RTCIHDA

SPI JTAG

SPI JTAG

FWH4 / LFRAME#

LDRQ1# / GPIO23

LPC

LPC

SATA

SATA

SATA0GP / GPIO21
SATA1GP / GPIO19

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

LDRQ0#

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

D33
B33
C32
A32

C34
A34

F34
AB9

AK7
AK6
AK11
AK9

AH6
AH5
AH9
AH8

AF11
AF9
AF7
AF6

AH3
AH1
AF3
AF1

AD9
AD8
AD6
AD5

AD3
AD1
AB3
AB1

AF16
AF15

T3

Y9
V1

SATA port 2/3 are not support in HM55 .
They are only in PM 55

SATA_COMP

SATA_ACT#

R881 10K/FR881 10K/F

1 2

R882 10K/FR882 10K/F

1 2

R877 37.4/FR877 37.4/F

R51 100KR51 100K

+3.3V_RUN

+1.05V_PCH

+3.3V_RUN

LPC_LAD0 29,32
LPC_LAD1 29,32
LPC_LAD2 29,32
LPC_LAD3 29,32

LPC_LFRAME# 29,32

IRQ_SERIRQ 29

SATA_RX0- 35
SATA_RX0+ 35
SATA_TX0- 35
SATA_TX0+ 35

SATA_RX1- 35
SATA_RX1+ 35
SATA_TX1- 35
SATA_TX1+ 35

SATA_RX4- 33
SATA_RX4+ 33
SATA_TX4- 33
SATA_TX4+ 33

SATA_ACT# 29

SATA HDD

SATA ODD

Distance between the PCH and
cap on the "P" signal should be
identical distace between the
PCH and cap on the "N" signal
for the same pair.

E-SATA

D D

C C

ICH_AZ_CODEC_BITCLK39

ICH_AZ_CODEC_SYNC39
ICH_AZ_CODEC_RST #29,39
ICH_AZ_CODEC_SDOUT39

Place all series terms close to PCH except for SDIN input
lines,which should be close to source.Placement of R773, R775,
R776 & R777 should equal distance to the T split trace point.
Basically, keep the same distance from T for all series
termination resistors.

B B

R869 33R869 33

R871 33R871 33
R872 33R872 33
R873 33R873 33

JTAG
Test Pads are need to put on

A A

5

the same side of mother board.

4

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

COMPUTER

IBEX PEAK-M 1/6

IBEX PEAK-M 1/6

IBEX PEAK-M 1/6

FM9 1A

FM9 1A

FM9 1A

1

8 64Thursday, February 26, 2009

8 64Thursday, February 26, 2009

8 64Thursday, February 26, 2009

5

4

3

2

1

IBEX PEAK-M (PCI,USB,NVRAM)

Place TX DC blocking caps close PCH.

U3035E

U3035E

H40

AD0

N34

AD1

C44

AD2

A38

AD3

C36

AD4

J34

AD5

A40

AD6

D45

D D

PCI_PIRQA#

T172T172

PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

T173T173

C C

USB_MCARD1_DET#32

GNT3#10

PCH_IRQH_GPIO535

PCIRST#:
DG(V1.0) P277
Can be left unconnected.

PAR:
SC(V1.0) P36
Can be left unconnected
if not using PCI.

PME:
DG(V1.0) P277
Can be left unconnected.

CLK_LPC_DEBUG32

B B

CLK_PCI_851229

CLKOUT_PCI[0..4]:
22 ohm series resistor is recommend
(single & double load) on PDG v1.1

Reserve capacitor pads for
improving WWAN.

CLK_LPC_DEBUG
CLK_PCI_8512

0214

R892 22/FR892 22/F
R896 22/FR896 22/F

CLK_PCI_FB CLK_PCI_FB_C

R898 22/FR898 22/F

50

50

C1287 *27P_NC

C1287 *27P_NC

50

50

C1289 *27P_NC

C1289 *27P_NC

Non-iAMT

A A

C1290 0.047U

C1290 0.047U

PCI_PLTRST#

10

10

PCI_REQ0#
REQ1#

T234T234

SB_WWAN_PCIE_RST#

T239T239

USB_MCARD1_DET#
PCI_GNT0#

GNT#1

T235T235

GNT#2

T236T236

SB_WPAN_PCIE_RST#

T240T240

SB_WLAN_PCIE_RST#

T241T241

PIRQG#

T243T243

PCH_IRQH_GPIO5
PCI_RST#

T237T237

PCI_SERR#
PCI_PERR#

PCI_IRDY#
PCI_DEVSEL#

PCI_FRAME#
PCI_PLOCK#
PCI_STOP#

PCI_TRDY#
PME#

T238T238

PCI_PLTRST#

CLK_LPC_DEBUG_C
CLK_PCI_8512_C

RSV_SMBALERT#
RSV_ICH_CL_RST1#
ICH_SMBCLK
ICH_SMBDATA
SMB_CLK_ME0
SMB_DATA_ME0
SMB_CLK_ME1
SMB_DATA_ME1
LPD_SPI_INTR#

PEG_CLKREQ#

Add Buffers as needed for
Loading and fanout concerns.

+3.3V_SUS

5

U56

U56

2
1

5

4

TC7SZ32FU(T5L,F,T)

TC7SZ32FU(T5L,F,T)

AD7

E36

AD8

H48

AD9

E40

AD10

C40

AD11

M48

AD12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1# / GPIO50

B45

REQ2# / GPIO52

M53

REQ3# / GPIO54

F48

GNT0#

K45

GNT1# / GPIO51

F36

GNT2# / GPIO53

H53

GNT3# / GPIO55

B41

PIRQE# / GPIO2

K53

PIRQF# / GPIO3

A36

PIRQG# / GPIO4

A48

PIRQH# / GPIO5

K6

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

M7

PME#

D5

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

IbexPeak-M_R1P0

IbexPeak-M_R1P0

+3.3V_SUS

R90010K/F R90010K/F
R90210K/F R90210K/F
R9032.2K/F R9032.2K/F
R9052.2K/F R9052.2K/F
R9072.2K/F R9072.2K/F
R9102.2K/F R9102.2K/F
R9112.2K/F R9112.2K/F

R91310K/F R91310K/F
R91610K/F R91610K/F

PLTRST# 3,16,26,28,29,31,32,41

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8

NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11

NVRAM

NVRAM

NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

PCI

PCI

USB

USB

PIRQG#
SB_WPAN_PCIE_RST#
SB_WWAN_PCIE_RST#
SB_WLAN_PCIE_RST#

OC7#
OC5#
OC4#
OC3#

+3.3V_SUS

PCH_IRQH_GPIO5
PCI_REQ0#
PCI_PIRQB#

USB_MCARD1_DET#

+3.3V_RUN

PCI_STOP#
PCI_PIRQA#
PCI_PIRQC#
PCI_IRDY#

+3.3V_RUN

NV_WR#0_RE#
NV_WR#1_RE#

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC6# / GPIO10
OC7# / GPIO14

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

NV_DQS0
NV_DQS1

NV_ALE

NV_CLE

NV_RCOMP

NV_RB#

NV_WE#_CK0
NV_WE#_CK1

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC5# / GPIO9

RP45

RP45

6

7

8

9
10

10P8R-8.2K

10P8R-8.2K

RP46

RP46

6

7

8

9
10

10P8R-8.2K

10P8R-8.2K

RP47

RP47

6

7

8

9
10

10P8R-8.2K

10P8R-8.2K

4

AY9
BD1
AP15
BD8

AV9
BG8

AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

BD3
AY6

AU2
AV7
AY8

AY5
AV11

BF5

H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24

B25
D25

N16
J16
F16
L16
E14
G16
F12
T15

R901 8.2K/FR901 8.2K/F
R1117 8.2K/FR1117 8.2K/F
R1118 8.2K/FR1118 8.2K/FR9122.2K/F R9122.2K/F
R1119 8.2K/FR1119 8.2K/F

NV_ALE 10
NV_CLE 10

ICH_USBP0- 33
ICH_USBP0+ 33
ICH_USBP1- 33
ICH_USBP1+ 33
ICH_USBP2- 34
ICH_USBP2+ 34

ICH_USBP4- 32
ICH_USBP4+ 32
ICH_USBP5- 31
ICH_USBP5+ 31

USB port 6/7 are not support in HM55 .
They are only in PM 55

ICH_USBP8- 32
ICH_USBP8+ 32
ICH_USBP9- 28
ICH_USBP9+ 28

ICH_USBP11- 40 MINI1CLK_REQ#32
ICH_USBP11+ 40
ICH_USBP12- 37
ICH_USBP12+ 37

USB_BIAS

R887 22.6/FR887 22.6/F

OC0#
OC1#
OC2#
OC3#
OC4#
OC5#
OC6#
OC7#

OC0#~OC7#:
DG(V1.0)P214
Pin Default Port Mapping
OC0# Port0,Port1
OC1# Port2,Port3

OC2#
OC6#
OC1#
OC0#

PCI_TRDY#
PCI_FRAME#
REQ1#
PCI_PIRQD#

PCI_SERR#
PCI_PERR#
PCI_PLOCK#
PCI_DEVSEL#

+3.3V_SUS

+3.3V_RUN

+3.3V_RUN

5
4
3
2
1

5
4
3
2
1

5
4
3
2
1

Left Side pair Top
Left Side pair bottom

Right Side pair top (Cable)

Mini Card (WLAN)
Mini Card (WWAN)

Mini Card (WPAN)
Express Card

Camera
Touch Screen Module

Note : place these
resistors near to PCIe
Slots

OC0# 33
OC1# 34

MiniWWAN

MiniWLAN

Express Card

Card Reader

Giga Bit LOM

MiniWWAN

MiniWLAN

Express Card

Card Reader

Giga Bit LOM

+3.3V_SUS

+3.3V_RUN

Boot BIOS Strap

PCI_GNT0# GNT#1

0 0
0
1
1 1

1
0

PCIE_RX6-/GLAN_RX-41
PCIE_RX6+/GLAN_RX+41

PCIE_TX6-/GLAN_TX-41
PCIE_TX6+/GLAN_TX+41

CLK_PCIE_CARD_READER#26
CLK_PCIE_CARD_READER26

R904 10KR904 10K
R906 10KR906 10K
R908 10KR908 10K
R909 10KR909 10K
R1014 10KR1014 10K

R914 10KR914 10K
R915 10KR915 10K

R917 1KR917 1K
R918 1KR918 1K

Boot BIOS Location
LPC
Reserved (NAND)
PCI
SPI

3

PCIE_RX1-31
PCIE_RX1+31
PCIE_TX1-31
PCIE_TX1+31

PCIE_RX2-32
PCIE_RX2+32
PCIE_TX2-32
PCIE_TX2+32

PCIE_RX4-28
PCIE_RX4+28
PCIE_TX4-28
PCIE_TX4+28

PCIE_RX5-26
PCIE_RX5+26
PCIE_TX5-26
PCIE_TX5+26

PCI-E port 7/8 are not support in HM55 .
They are only in PM 55

CLK_PCIE_MINI2#31
CLK_PCIE_MINI231

CLK_PCIE_REQ1#31

CLK_PCIE_MINI1#32
CLK_PCIE_MINI132

CLK_PCIE_EXPCARD#28
CLK_PCIE_EXPCARD28

CARD_CLK_REQ#28

CLK_PCIE_REQ5#26

CLK_PCIE_LOM#41
CLK_PCIE_LOM41

LOM_CLK_REQ#41

MINI1CLK_REQ#
CARD_CLK_REQ#
CLK_PCIE_REQ5#
CLK_PEG0_REQ#
LOM_CLK_REQ#

CLK_PCIE_REQ1#

CLK_PCIE_REQ2#

PCI_GNT0#
GNT#1

C717 0.1UC717 0.1U
C718 0.1UC718 0.1U

C714 0.1UC714 0.1U
C715 0.1UC715 0.1U

C711 0.1UC711 0.1U
C710 0.1UC710 0.1U

C712 0.1UC712 0.1U
C713 0.1UC713 0.1U

C721 0.1UC721 0.1U
C722 0.1UC722 0.1U

CLK_PCIE_REQ1#

CLK_PCIE_REQ2#

MINI1CLK_REQ#

CARD_CLK_REQ#

CLK_PCIE_REQ5#

LOM_CLK_REQ#

PCIECLKRQ{0,3,4,5,6,7}# should have a
10K pull-up to +V3.3A.PCIECLKRQ{1,2}
should have a 10K pull-up to +3.3S

IBEX PEAK-M (PCI-E,SMBUS,CLK)

U3035B

U3035B

BG30

PCIE_TXN1_C
PCIE_TXP1_C

PCIE_TXN2_C
PCIE_TXP2_C

PCIE_TXN4_C
PCIE_TXP4_C

PCIE_TXN5_C
PCIE_TXP5_C

PCIE_TXN6_C
PCIE_TXP6_C

CLK_PEG0_REQ#

R883 0R883 0

R1100 0R1100 0

R884 0R884 0

R885 0R885 0

R888 0R888 0

R894 0R894 0

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4# / GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IbexPeak-M_R1P0

IbexPeak-M_R1P0

CLKOUT_PEG_A_P/N,CLKOUT_PEG_B_P/N,
CLKOUT_DMI_P/N,support GEN-1 and GEN-2

SMB_CLK_ME1

SMB_DATA_ME1

2

PCI-E*

PCI-E*

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1ALERT# / GPIO74

SMBus

SMBus

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

Link

Controller

Controller

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

PEG

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P

From CLK BUFFER

From CLK BUFFER

CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

Clock Flex

Clock Flex

+3.3V_SUS+3.3V_RUN

Q82

Q82

2

2N7002W-7-F

2N7002W-7-F

31

+3.3V_SUS

Q83

Q83

2

2N7002W-7-F

2N7002W-7-F

31

RSV_SMBALERT#

B9

ICH_SMBCLK

H14

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1
CL_DATA1
CL_RST1#

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_BCLK_N
CLKIN_BCLK_P

CLKIN_DOT_96N
CLKIN_DOT_96P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

ICH_SMBDATA

C8

RSV_ICH_CL_RST1#

J14

SMB_CLK_ME0

C6

SMB_DATA_ME0

G8

LPD_SPI_INTR#

M14

SMB_CLK_ME1

E10

SMB_DATA_ME1

G12

T13
T11
T9

PEG_CLKREQ#

H1

AD43
AD45

AN4
AN2

AT1
AT3

AW24
BA24

AP3
AP1

F18
E18

AH13
AH12

P41

CLK_PCI_FB

J42

AH51
AH53

XCLK_RCOMP

AF38

CLK_FLEX0

T45

CLK_FLEX1

P43

CLK_FLEX2

T42

CLK_FLEX3

N50

CLKOUTFLEX3:
EDS(V1.0) :support 48MHz
33MHz and 14.31818MHz.

CLKOUTFLEX[0..3]:
PDG v1.1: 22 ohm series resistor is
recommend (PCI & non PCI routing,
single & double load)

SMBCLK1 29

SMBDAT1 29

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

COMPUTER

IBEX PEAK-M 3/6

IBEX PEAK-M 3/6

IBEX PEAK-M 3/6

FM9 1A

FM9 1A

FM9 1A

T165T165

ICH_SMBCLK 32,41,60
ICH_SMBDATA 32,41,60

T166T166

T167T167

SML0CLK/SML0DATA:
DG(V1.1) P255: The 82577 SMBus
signals
(SMB_DATA and SMB_CLK) cannot be
connected to any other
devices other than the PCH.
Connect the SMB_DATA and SMB_CLK
pins
to the PCH SML0DATA and SML0CLK
pins,
respectively.

T171T171

CLK_PCIE_VGA# 16
CLK_PCIE_VGA 16

CLK_PCIE_3GPLL# 3
CLK_PCIE_3GPLL 3

CLK_BUF_PCIE_3GPLL# 15
CLK_BUF_PCIE_3GPLL 15

CLK_BUF_BCLK_N 15
CLK_BUF_BCLK_P 15

CLK_BUF_DREFCLK# 15
CLK_BUF_DREFCLK 15

CLK_BUF_DREFSSCLK# 15
CLK_BUF_DREFSSCLK 15

CLK_ICH_14M 15

CLKIN_PCILOOPBACK:
PDG (V1.1): 22 ohm series resistor
is recommend

0214

DG(V1.1) P256: XTAL_OUT and XTAL_IN
are the signal names for the PHY.

R886 90.9/FR886 90.9/F

+1.05V_PCH

T179T179

T176T176

T177T177

T184T184

1

0214

9 64Thursday, February 26, 2009

9 64Thursday, February 26, 2009

9 64Thursday, February 26, 2009

5

4

3

2

1

IBEX PEAK-M (GPIO,VSS_NCTF,RSVD)

U3035F

S_GPIO

SIO_EXT_SMI#29
SIO_EXT_SCI#29

D D

LAN_PCIE_PWR_CTRL29,41

PCIE_MCARD1_DET#32

GPIO24 register not cleared by CF9h reset event.
GPIO27 reserve for internal VR.

BT_RADIO_DIS#32

C C

WWAN_RADIO_DIS#31

CRIT_TEMP_REP#29

B B

SIO_EXT_WAKE#29

R926 *0_NCR926 *0_NC

TEST_WOOFER_EN39

R942 0R942 0

PCIE_MCARD2_DET#31

R995 *10K_NCR995 *10K_NC

USB_MCARD2_DET#31

WLAN_RADIO_DIS#32

R940 0R940 0

R945 0R945 0
R946 0R946 0

SIO_EXT_SMI#
SIO_EXT_SCI#
SIO_EXT_WAKE#
RSV_WOL_EN

LAN_PHY_PWR_CTRL
TEST_WOOFER_EN
SATA4GP
PCIE_MCARD1_DET#_R
PCIE_MCARD2_DET#

GPIO27
TP_PCH_GPIO28
USB_MCARD2_DET#
GPIO35
SATA2GP
SATA3GP
WLAN_RADIO_DIS#
CRB_SV_DET
GPIO45
GPIO46
SV_SET_UP
SATA5GP
GPIO57

U3035F

Y3

BMBUSY# / GPIO0

C38

TACH1 / GPIO1

D37

TACH2 / GPIO6

J32

TACH3 / GPIO7

F10

GPIO8

K9

LAN_PHY_PWR_CTRL / GPIO12

T7

GPIO15

AA2

SATA4GP / GPIO16

F38

TACH0 / GPIO17

Y7

SCLOCK / GPIO22

H10

GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI# / GPIO34

V6

SATACLKREQ# / GPIO35

AB7

SATA2GP / GPIO36

AB13

SATA3GP / GPIO37

V3

SLOAD / GPIO38

P3

SDATAOUT0 / GPIO39

H3

PCIECLKRQ6# / GPIO45

F1

PCIECLKRQ7# / GPIO46

AB6

SDATAOUT1 / GPIO48

AA4

SATA5GP / GPIO49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

IbexPeak-M_R1P0

IbexPeak-M_R1P0

MISC

MISC

CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P

GPIO

GPIO

CPU

CPU

NCTF

NCTF

RSVD

RSVD

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CLKOUT_PCIE7N
CLKOUT_PCIE7P

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18

TP19
NC_1
NC_2
NC_3
NC_4
NC_5

INIT3_3V#

TP24

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9

AH45
AH46

AF48
AF47

U2

AM3
AM1
BG10
T1
BE10
BD10

BA22
AW22
BB22
AY45
AY46
AV43
AV45
AF13
M18
N18
AJ24
AK41
AK42
M32
N32
M30
N30
H12
AA23
AB45
AB38
AB42
AB41
T39

P6
C10

PCH_THRMTRIP#_R

SIO_A20GATE 29

CLK_CPU_BCLK# 3
CLK_CPU_BCLK 3
H_PECI 3
SIO_RCIN# 29
H_PWRGOOD 3,60

R934 54.9/FR934 54.9/F

(Both these should be close to PCH)

+1.1V_VTT

R933

R933
56/F

56/F

TEST_WOOFER_EN
RSV_WOL_EN
TP_PCH_GPIO28
GPIO45
GPIO46
GPIO57
LAN_PHY_PWR_CTRL

SIO_EXT_SMI#
SIO_EXT_SCI#
SIO_EXT_WAKE#
PCIE_MCARD2_DET#

PCIE_MCARD1_DET#_R

WLAN_RADIO_DIS#
CRB_SV_DET

SIO_RCIN#

H_THERM 3

SIO_A20GATE
SATA2GP
SATA5GP
SATA3GP
SATA4GP
USB_MCARD2_DET#
CRIT_TEMP_REP#

DMI Termination Voltage

NV_CLE

NV_ALE9
NV_CLE9

Set to Vcc when LOW
Set to Vcc/2 when HIGH

R947 *1K_NCR947 *1K_NC
R948 *1K_NCR948 *1K_NC

Danbury Technology Enabled

NV_ALE

High = Enable
Low = Disable

R920 1KR920 1K
R921 10K/FR921 10K/F
R922 10K/FR922 10K/F
R923 10K/FR923 10K/F
R924 10K/FR924 10K/F
R925 10K/FR925 10K/F
R1001 10K/FR1001 10K/F

R927 10K/FR927 10K/F
R928 10K/FR928 10K/F
R929 10K/FR929 10K/F
R930 10K/FR930 10K/F

R1012 10K/FR1012 10K/F
R1070 10K/FR1070 10K/F
R1071 10K/FR1071 10K/F

R935 10K/FR935 10K/F
R936 10K/FR936 10K/F
R937 10K/FR937 10K/F
R938 10K/FR938 10K/F
R939 10K/FR939 10K/F
R941 10K/FR941 10K/F
R943 10K/FR943 10K/F
R944 10K/FR944 10K/F

+3.3V_SUS

+3.3V_RUN

+NVRAM_VCCQ

R1072 10K/FR1072 10K/F

A A

R950 *1K/F_NCR950 *1K/F_NC

A16 swap override Strap/Top-Block
Swap Override jumper

GNT3#

GPIO35

Low = A16 swap
override/Top-Block
Swap Override enabled
High = Default

5

GNT3# 9

S_GPIO
SV_SET_UP

R530 10K/FR530 10K/F
R951 10K/FR951 10K/F

SV_SET_UP 1-X High = Strong (Default)

4

3

+3.3V_RUN

6

BMBUSY#:
If not used, require a weak pull-up (8.2- KΩ to 10 kΩ) to Vcc3_3.
CRB(V1.0)P28: it has 1K PU and 100 ohm on this net for validation purpose.

BMBUSY#:(Intel feedback)
Follow CRB checklist, 1K is
for intel BIOS validation purpose.

Title

Title

Title

IBEX PEAK-M 4/6

IBEX PEAK-M 4/6

IBEX PEAK-M 4/6

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

FM9 1A

FM9 1A

FM9 1A

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

10 64Thursday, February 26, 2009

10 64Thursday, February 26, 2009

10 64Thursday, February 26, 2009

1

5

U3035G

IBEX PEAK-M (POWER)

D D

VCCAPLLEXP = 100mA max

PJP32

PJP32

12

POWER_JP

POWER_JP

+1.05V_PCH

VCCAPLLEXP:
This pin can be left as no connect in
On-Die VR enabled mode (default).

+1.05V_PCH

VCCIO = 3.208A max

C C

L111 *1uH_NCL111 *1uH_NC

+1.05V_VCCIO

C1307

C1307
10U

10U

4

4
0805

0805

+1.05V_PCH

+1.05V_PCH

C13081UC1308
1U

+3.3V_RUN

VCCCORE=1.524A max

C12921UC1292

C1291

C1291
10U

10U

1U

4

4
0805

0805

+1.05V_LAN_VCCAPLL_EXP

C1298

C1298
*10U_NC

*10U_NC

C13091UC1309
1U

C13101UC1310
1U

C13111UC1311
1U

VCC3_3 = 0.357A max

C1423

C1423

0.1U

0.1U

VCCFDIPLL = 100mA max

+1.05V_PCH

B B

A A

L112 *1uH_NCL112 *1uH_NC

5

VCCVRM = 0.035A max

+1.5VS_1.8VS

+1.05V_VCCFDIPLL

+1.05V_PCH

C1324

C1324
*10U_NC

*10U_NC

VCCIO = 3.208A max

+1.05V_PCH

U3035G

AB24

VCCCORE[1]

AB26

VCCCORE[2]

AB28

VCCCORE[3]

AD26

VCCCORE[4]

AD28

VCCCORE[5]

AF26

VCCCORE[6]

AF28

VCCCORE[7]

AF30

VCCCORE[8]

AF31

VCCCORE[9]

AH26

VCCCORE[10]

AH28

VCCCORE[11]

AH30

VCCCORE[12]

AH31

VCCCORE[13]

AJ30

VCCCORE[14]

AJ31

VCCCORE[15]

AK24

VCCIO[24]

BJ24

VCCAPLLEXP

AN20

VCCIO[25]

AN22

VCCIO[26]

AN23

VCCIO[27]

AN24

VCCIO[28]

AN26

VCCIO[29]

AN28

VCCIO[30]

BJ26

VCCIO[31]

BJ28

VCCIO[32]

AT26

VCCIO[33]

AT28

VCCIO[34]

AU26

VCCIO[35]

AU28

VCCIO[36]

AV26

VCCIO[37]

AV28

VCCIO[38]

AW26

VCCIO[39]

AW28

VCCIO[40]

BA26

VCCIO[41]

BA28

VCCIO[42]

BB26

VCCIO[43]

BB28

VCCIO[44]

BC26

VCCIO[45]

BC28

VCCIO[46]

BD26

VCCIO[47]

BD28

VCCIO[48]

BE26

VCCIO[49]

BE28

VCCIO[50]

BG26

VCCIO[51]

BG28

VCCIO[52]

BH27

VCCIO[53]

AN30

VCCIO[54]

AN31

VCCIO[55]

AN35

VCC3_3[1]

AT22

VCCVRM[1]

BJ18

VCCFDIPLL

AM23

VCCIO[1]

IbexPeak-M_R1P0

IbexPeak-M_R1P0

+1.8V_RUN

+3.3V_RUN

L114 10uHL114 10uH

L115 10uHL115 10uH

R959 *0_NCR959 *0_NC
R960 *0_NCR960 *0_NC
R961 0R961 0
R962 0R962 0
R963 *0_NCR963 *0_NC

+1.05V_PCH

PCH EDS(V1.0) P84
+NVRAM_VCCQ:

1.8 V supply for Dual Channel NAND interface.
This power is supplied by core
well. If unused, this pin should
be connected to Vcc3_3.

4

POWER

POWER

VCC CORE

VCC CORE

PCI E*

PCI E*

+1.1V_VCCADPLLA

+

+

C1333

C1333
220U

220U

3528

3528

+1.1V_VCCADPLLB

+

+

C1340

C1340
220U

220U

3528

3528

4

L109

+VCCA_DAC_1_2

AE50

VCCADAC[1]

AE52

VCCADAC[2]

AF53

VSSA_DAC[1]
VSSA_DAC[2]

VCCALVDS

VSSA_LVDS

VCC3_3[2]
VCC3_3[3]
VCC3_3[4]

VCCVRM[2]

VCCDMI[1]
VCCDMI[2]

VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]

VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]

AF51

AH38
AH39

AP43
AP45
AT46
AT45

AB34
AB35
AD35

AT24

AT16
AU16

AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15

AM8
AM9
AP11
AP9

CRTLVDS

CRTLVDS

VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]

HVCMOS

HVCMOS

DMI

DMI

NAND / SPI

NAND / SPI

FDI

FDI

VCCME3_3:
EDS(V1.0)P84:supply for the Intel Management Engine.This is a separate power plane
that may or may not be powered in S3–S5 states.
This plane must be on in S0
and other times the Intel Management Engine is used.

+1.5VS_1.8VS+1.5V_RUN

+NVRAM_VCCQ

C13361UC1336
1U

C13381UC1338
1U

C1293

C1293

0.01U

0.01U

VCC3_3 = 0.357A max

+3.3V_RUN

C1305

C1305

0.1U

0.1U

VCCVRM = 0.035A max

+1.5VS_1.8VS

VCCDMI = 0.061A max

C13151UC1315
1U R956 100R956 100

VCCPNAND = 0.156A max

+NVRAM_VCCQ

C1319

C1319

0.1U

0.1U

VCCME3_3 = 0.085A max

+3.3V_RUN

C1326

C1326

0.1U

0.1U

HCB1608KF-181T15

HCB1608KF-181T15

C1294

C1294

C1295

C1295

10U

10U

0.1U

0.1U

10

10

+1.05V_PCH

R954 0R954 0
R955 *0_NCR955 *0_NC

L109

L110 *10uH_NCL110 *10uH_NC

VCCME = 1.998A max

+1.05V_PCH

+1.05V_PCH

+1.1V_VTT
+1.05V_PCH

3

VCCADAC = 100mA max

+3.3V_RUN

VCCACLK = 100mA max

+1.1V_LAN_VCCA_CLK

C13121UC1312

1U

C1300

C1300

C1306

C1306

22U

22U

22U

22U

C1316 0.1UC1316 0.1U

+1.5VS_1.8VS

VCCADPLLA = 0.072A max

+1.1V_VCCADPLLA

VCCADPLLB = 0.073A max

+1.1V_VCCADPLLB

VCCIO = 3.208A max

+1.05V_PCH

C13211UC1321
1U

C1327 0.1UC1327 0.1U

C1330 0.1UC1330 0.1U

VCCSUS3_3 = 0.163A max

+3.3V_SUS

VCC3_3 = 0.357A max

+3.3V_RUN

V_CPU>1mA

+1.1V_VTT

C1334

C1334

4.7U

4.7U

+RTC_CELL

VCCRTC = 2mA max

3

C1296

C1296
*10U_NC

*10U_NC

DCPSUSBYP

C1299

C1299

0.1U

0.1U

C13141UC1314

C13221UC13221UC13231UC1323

C1335

C1335

0.1U

0.1U

C14851UC1485
1U

1U

DCPRTC

1U

DCPSST

DCPSUS

C1451

C1451

0.1U

0.1U

C1332

C1332

0.1U

0.1U

C1337

C1337

0.1U

0.1U

C1339

C1339

0.1U

0.1U

C1297

C1297
*1U_NC

*1U_NC

C1342

C1342

0.1U

0.1U

AP51
AP53

AF23
AF24

AD38
AD39
AD41
AF43
AF41
AF42

AU24

BB51
BB53

BD51
BD53

AH23
AJ35
AH35

AF34
AH34
AF32

AT18

AU18

U3035J

U3035J

VCCACLK[1]
VCCACLK[2]

VCCLAN[1]
VCCLAN[2]

Y20

DCPSUSBYP

VCCME[1]
VCCME[2]
VCCME[3]
VCCME[4]
VCCME[5]
VCCME[6]

V39

VCCME[7]

V41

VCCME[8]

V42

VCCME[9]

Y39

VCCME[10]

Y41

VCCME[11]

Y42

VCCME[12]

V9

DCPRTC

VCCVRM[3]

VCCADPLLA[1]
VCCADPLLA[2]

VCCADPLLB[1]
VCCADPLLB[2]

VCCIO[21]
VCCIO[22]
VCCIO[23]

VCCIO[2]
VCCIO[3]
VCCIO[4]

V12

DCPSST

Y22

DCPSUS

P18

VCCSUS3_3[29]

U19

VCCSUS3_3[30]

U20

VCCSUS3_3[31]

U22

VCCSUS3_3[32]

V15

VCC3_3[5]

V16

VCC3_3[6]

Y16

VCC3_3[7]

V_CPU_IO[1]

V_CPU_IO[2]

A12

VCCRTC

IbexPeak-M_R1P0

IbexPeak-M_R1P0

POWER

POWER

Clock and Miscellaneous

Clock and Miscellaneous

CPU

CPU

RTC PCI/GPIO/LPC

RTC PCI/GPIO/LPC

USB

USB

PCI/GPIO/LPC

PCI/GPIO/LPC

SATA

SATA

HDA

HDA

2

VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]

VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]

VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]

VCCSUS3_3[28]

VCCIO[56]

V5REF_SUS

V5REF

VCC3_3[8]

VCC3_3[9]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

VCC3_3[14]

VCCSATAPLL[1]
VCCSATAPLL[2]

VCCIO[9]

VCCVRM[4]

VCCIO[10]

VCCIO[11]

VCCIO[12]

VCCIO[13]

VCCIO[14]

VCCIO[15]

VCCIO[16]

VCCIO[17]

VCCIO[18]

VCCIO[19]

VCCIO[20]

VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]

VCCSUSHDA

2

V24
V26
Y24
Y26

V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26

U23
V23
F24

K49

J38
L38
M36
N36
P36
U35

AD13

AK3
AK1

AH22

AT20

AH19
AD20
AF22
AD19

AF20
AF19
AH20

AB19
AB20
AB22
AD22

AA34
Y34
Y35
AA35

L30

+V5REF_SUS

+V5REF

C1328

C1328
*1U_NC

*1U_NC

C13011UC1301
1U

C1303

C1303

C1304

C1304

0.1U

0.1U

0.1U

0.1U

VCCIO = 3.208A max

+1.05V_PCH

C13171UC1317
1U

C13181UC1318
1U

C1320

C1320

0.1U

0.1U

C1325

C1325

0.1U

0.1U

+1.05V_VCCSATAPLL

C1329

C1329
*10U_NC

*10U_NC

VCCVRM = 0.035A max

+1.5VS_1.8VS

VCCME = 1.998A max

+1.05V_PCH

C13411UC1341
1U

1

VCCIO = 3.208A max

+1.05V_PCH

VCCSUS3_3 = 0.163A max

+3.3V_SUS

+5V_SUS

D33 RB500V-40D33 RB500V-40

R957 100R957 100
D34 RB500V-40D34 RB500V-40

+3.3V_RUN

L113 *10uH_NCL113 *10uH_NC

VCC3_3 = 0.357A max

+3.3V_SUS

+5V_RUN
+3.3V_RUN

V5REF_SUS>1mA

V5REF>1mA

+1.05V_PCH

VCCIO = 3.208A max

+1.05V_PCH

C13311UC1331
1U

R9650 R9650

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

VCCSUSHDA = 6mA max

+3.3V_SUS

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

IBEX PEAK-M 5/6

IBEX PEAK-M 5/6

IBEX PEAK-M 5/6

FM9 1A

FM9 1A

FM9 1A

1

11 64Thursday, February 26, 2009

11 64Thursday, February 26, 2009

11 64Thursday, February 26, 2009

5

IBEX PEAK-M (GND)

D D

U3035H

U3035H

AB16

VSS[0]

AA19

VSS[1]

AA20

VSS[2]

AA22

VSS[3]

AM19

VSS[4]

AA24

VSS[5]

AA26

VSS[6]

AA28

VSS[7]

AA30

VSS[8]

AA31

VSS[9]

AA32

VSS[10]

AB11

VSS[11]

AB15

VSS[12]

AB23

VSS[13]

AB30

VSS[14]

AB31

VSS[15]

AB32

VSS[16]

AB39

VSS[17]

AB43

VSS[18]

AB47

C C

B B

A A

5

AB5
AB8

AC2
AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49

AD7

AE2

AE4

AF12

Y13
AH49

AU4

AF35
AP13
AN34

AF45

AF46

AF49

AF5
AF8

AG2
AG52
AH11
AH15
AH16
AH24
AH32
AV18
AH43
AH47

AH7

AJ19

AJ2

AJ20
AJ22
AJ23
AJ26
AJ28
AJ32
AJ34

AT5

AJ4
AK12
AM41
AN19
AK26
AK22
AK23
AK28

VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

IbexPeak-M_R1P0

IbexPeak-M_R1P0

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

4

AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47

4

BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49

BC10
BC14
BC18

BC2
BC22
BC32
BC36
BC40
BC44
BC52

BH9
BD48
BD49

BD5
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50

BE6

BE8

BF3

BF49

BF51
BG18
BG24

BG4
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47

BH7

C12

C50

D51

G10

G14

G18

G22

G32

G36

G40

G44

G52

AF39

H16

H20

H30

H34

H38

H42

AY7
B11
B15
B19
B23
B31
B35
B39
B43
B47

BB5

E12
E16
E20
E24
E30
E34
E38
E42
E46
E48

F49

B7

E6
E8

F5

G2

3

U3035I

U3035I

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

IbexPeak-M_R1P0

IbexPeak-M_R1P0

3

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]

H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14

2

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

COMPUTER

IBEX PEAK-M 6/6

IBEX PEAK-M 6/6

IBEX PEAK-M 6/6

FM9 1A

FM9 1A

FM9 1A

1

12 64Thursday, February 26, 2009

12 64Thursday, February 26, 2009

12 64Thursday, February 26, 2009

1

5

4

3

2

1

+3.3V_SUS

+1.5V_SUS

PM_EXTTS#0

U57

U57

1

VCC

3
4

R980 *0_NCR980 *0_NC

RW

SCL

GND

SDA

ISL90727WIE627Z-TK

ISL90727WIE627Z-TK

+1.5V_SUS

JDIM1B

JDIM1B

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

AS0A626-UARN-7F

AS0A626-UARN-7F

6

RH

5
2

+SMDDR_VREF_DIMM
+DDR_VTTREF

+M_VREF_DQ_DIMM0
+SMDDR_VREF_DQ0

R971

R971

12.1K/F

12.1K/F

R974

R974

12.1K/F

12.1K/F

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

2

(204P)

(204P)

C1344

C1344
1U

1U

603

603
10

10

44

VSS16

48

VSS17

49

VSS18

54

VSS19

55

VSS20

60

VSS21

61

VSS22

65

VSS23

66

VSS24

71

VSS25

72

VSS26

127

VSS27

128

VSS28

133

VSS29

134

VSS30

138

VSS31

139

VSS32

144

VSS33

145

VSS34

150

VSS35

151

VSS36

155

VSS37

156

VSS38

161

VSS39

162

VSS40

167

VSS41

168

VSS42

172

VSS43

173

VSS44

178

VSS45

179

VSS46

184

VSS47

185

VSS48

189

VSS49

190

VSS50

195

VSS51

196

VSS52

203

VTT1

204

VTT2

G1

G1

G2

G2

SIO_SLP_S4#7

+3.3V_SUS+1.5V_SUS

52

U58

U58
OPA343NA/3K

OPA343NA/3K

3

+

+

4

1

-

-

Title

Title

Title

DDR3 DIMM-0

DDR3 DIMM-0

DDR3 DIMM-0

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

FM9 1A

FM9 1A

FM9 1A

Date: Sheet of

Date: Sheet of

Date: Sheet of

+3.3V_RUN

R966 *10K/F_NCR966 *10K/F_NC

Intel is requesting that customers implement
all methods (M1 and M2 and M3
described below) to generate and control
Reference voltage for Data/Strobe inputs
(VREFDQ) on Clarksfield based platforms.
for fine tuning of the VREFDQ levels to
optimize the voltage and timing margins.

M1:Fixed voltage resistor divider or
DDR Voltage Regulator drives the Vref
M2:A set of Digital potentiometers
and op amps are added on the motherboard (one pair
for each channel). This circuit is controlled by
SMBUS (SMB_CLK & SMB_DATA) on PCH.
M3:Intel investigating future processor
VREF_DQ generation to replace M1 and M2. This
would require routing processor signal balls
J17 and H17 to SO-DIMM connectors
directly.

+0.75V_DDR_VTT

2N7002W-7-F

2N7002W-7-F

R972 2.2R972 2.2

*1U_NC

*1U_NC

PP_S4GT

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

Q84

Q84

C1345

C1345

603

603
10

10

+5V_ALW

2

2

R969

R969
100K

100K

31

R9701MR970
1M

+SMDDR_VREF_DQ0

R973 *0_NCR973 *0_NC

R97510R975
10

31

2N7002W-7-F

2N7002W-7-F
Q85

Q85

1

11

PM_EXTTS#0

PP_S4GT 14

13 64Thursday, February 26, 2009

13 64Thursday, February 26, 2009

13 64Thursday, February 26, 2009

JDIM1A

107

119

109
108

114
121
101
103
102
104

115
110
113
197
201
202
200

116
120

136
153
170
187

137
154
171
188

135
152
169
186

C1356

C1356

0.1U

0.1U

C13671UC1367
1U

98
97
96
95
92
91
90
86
89
85

84
83

80
78

79

73
74

11
28
46
63

12
29
47
64

10
27
45
62

JDIM1A

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA

ODT0
ODT1

DM0
DM1
DM2
DM3
DM4
DM5
DM6

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

DM7
DQS0

DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

AS0A626-UARN-7F

AS0A626-UARN-7F

+

+

C1358

C1358

C1357

C1357
330U

330U

0.1U

0.1U

7343

7343

2.5

2.5

C13681UC1368
1U

4

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

(204P)

(204P)

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

+SMDDR_VREF_DIMM

C1359

C1359

2.2U/6.3V_6

2.2U/6.3V_6

C1360

C1360

0.1U

0.1U

C1370

C1370

C1369

C1369

10U

10U

10U

10U

4

4

4

4

0805

0805

0805

0805

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

C1361

C1361

2.2U/6.3V_6

2.2U/6.3V_6

C1371

C1371
10U

10U

4

4
0805

0805

M_A_A[15:0]4

D D

M_A_BS04
M_A_BS14
M_A_BS24
M_A_CS0#4
M_A_CS1#4
M_A_CLK04
M_A_CLK0#4
M_A_CLK14
M_A_CLK1#4
M_A_CKE04
M_A_CKE14
M_A_CAS#4
M_A_RAS#4

C1348

C1348
10U

10U

M_A_WE#4

EC_SMBCLK014,15,38
EC_SMBDAT014,15,38

M_A_ODT04
M_A_ODT14

M_A_DM[7:0]4

M_A_DQS[7:0]4

M_A_DQS#[7:0]4

Place these Caps near So-Dimm1.

C1351

C1349

C1349
10U

10U

C1364

C1364

0.1U

0.1U

5

C1351
10U

10U

C1350

C1350
10U

10U

+0.75V_DDR_VTT

C13651UC1365
1U

R967 10K/F_4R967 10K/F_4
R968 10K/F_4R968 10K/F_4

C C

B B

+1.5V_SUS

C1347

C1347
10U

10U

C1346

C1346

10U

10U

A A

+3.3V_RUN

C1363

C1363

2.2U/6.3V_6

2.2U/6.3V_6

C1352

C1352

0.1U

0.1U

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

DIMM0_SA0
DIMM0_SA1
EC_SMBCLK0
EC_SMBDAT0

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

C1353

C1353

0.1U

0.1U

C13661UC1366
1U

C1354

C1354

0.1U

0.1U

C1355

C1355

0.1U

0.1U

M_A_DQ[63:0] 4

PM_EXTTS#03

DDR3_DRAMRST#3,14

EC_SMBCLK014,15,38
EC_SMBDAT014,15,38

C1362 470P/50VC1362 470P/50V

R977 *10K/F_NCR977 *10K/F_NC

3

+3.3V_RUN

+SMDDR_VREF_DQ0
+SMDDR_VREF_DIMM

C1343

C1343
1U

1U

603

603
10

10

EC_SMBCLK0
EC_SMBDAT0

R976 0R976 0

R978 *10K/F_NCR978 *10K/F_NC

R979 0R979 0

5

4

3

2

1

JDIM2A

107

119

109
108

114
121
101
103
102
104

115
110
113
197
201
202
200

116
120

136
153
170
187

137
154
171
188

135
152
169
186

C1384

C1384

0.1U

0.1U

98
97
96
95
92
91
90
86
89
85

84
83

80
78

79

73
74

11
28
46
63

12
29
47
64

10
27
45
62

JDIM2A

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA

ODT0
ODT1

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

AS0A626-U2RN-7F

AS0A626-U2RN-7F

C1385

C1385

0.1U

0.1U

C13951UC1395
1U

+

+

4

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

C1386

C1386
330U

330U

7343

7343

2.5

2.5

C13961UC1396
1U

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

(204P)

(204P)

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

+SMDDR_VREF_DIMM

C1387

C1387

0.1U

0.1U

C1397

C1397
10U

10U

4

4
0805

0805

C1388

C1388

2.2U/6.3V_6

2.2U/6.3V_6

C1389

C1389

0.1U

0.1U

C1398

C1398
10U

10U

4

4
0805

0805

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

C1390

C1390

2.2U/6.3V_6

2.2U/6.3V_6

C1399

C1399
10U

10U

4

4
0805

0805

EC_SMBCLK013,15,38
EC_SMBDAT013,15,38

M_B_A[15:0]4

D D

M_B_BS04
M_B_BS14
M_B_BS24
M_B_CS0#4
M_B_CS1#4
M_B_CLK04
M_B_CLK0#4
M_B_CLK14
M_B_CLK1#4
M_B_CKE04
M_B_CKE14
M_B_CAS#4
M_B_RAS#4

C1376

C1376
10U

10U

EC_SMBCLK013,15,38
EC_SMBDAT013,15,38

C1377

C1377
10U

10U

5

M_B_WE#4

M_B_ODT04
M_B_ODT14

M_B_DM[7:0]4

M_B_DQS[7:0]4

M_B_DQS#[7:0]4

Place these Caps near So-Dimm2.

C1378

C1378
10U

10U

C1379

C1379
10U

10U

+0.75V_DDR_VTT

C1392

C1392

0.1U

0.1U

R982 10K/F_4R982 10K/F_4
R983 10K/F_4R983 10K/F_4

+3.3V_RUN

C C

B B

+1.5V_SUS

C1375

C1375
10U

10U

A A

+3.3V_RUN

C1391

C1391

2.2U/6.3V_6

2.2U/6.3V_6

C1380

C1380
10U

10U

C1381

C1381

0.1U

0.1U

C13931UC1393
1U

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

DIMM1_SA0
DIMM1_SA1
EC_SMBCLK0
EC_SMBDAT0

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

C1382

C1382

0.1U

0.1U

C1383

C1383

0.1U

0.1U

C13941UC1394
1U

M_B_DQ[63:0] 4

PM_EXTTS#13

DDR3_DRAMRST#3,13

+SMDDR_VREF_DQ1
+SMDDR_VREF_DIMM

C1372

C1372
1U

1U

603

603
10

10

EC_SMBCLK0
EC_SMBDAT0

+SMDDR_VREF_DIMM

3

+3.3V_SUS

R989 0R989 0

1
3

4

+1.5V_SUS

+3.3V_RUN

PM_EXTTS#1

U59

U59

VCC

RH

RW

SCL

GND

SDA

ISL90728WIE627Z-TK

ISL90728WIE627Z-TK

R990 *0_NCR990 *0_NC

JDIM2B

JDIM2B

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

AS0A626-U2RN-7F

AS0A626-U2RN-7F

+1.5V_SUS +3.3V_SUS

C1373

C1373

R984

R984

1U

1U

12.1K/F

12.1K/F

603

603
10

6
5

2

10

R987

R987

12.1K/F

12.1K/F

+M_VREF_DQ_DIMM1
+SMDDR_VREF_DQ1

2

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

3
4

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

(204P)

(204P)

VTT1
VTT2

52

U60

U60
OPA343NA/3K

OPA343NA/3K

+

+

-

-

PP_S4GT13

44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

203
204

G1

G1

G2

G2

1

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

+0.75V_DDR_VTT

R985 2.2R985 2.2

C1374

C1374

*1U_NC

*1U_NC

603

603
10

10

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

DDR3 DIMM-1

DDR3 DIMM-1

DDR3 DIMM-1

FM9 1A

FM9 1A

FM9 1A

R986 *0_NCR986 *0_NC

31

2

+3.3V_RUN

+SMDDR_VREF_DQ1

R98810R988
10

2N7002W-7-F

2N7002W-7-F
Q86

Q86

R981

R981
*10K/F_NC

*10K/F_NC

1

12

PM_EXTTS#1

14 64Thursday, February 26, 2009

14 64Thursday, February 26, 2009

14 64Thursday, February 26, 2009

5

D D

4

3

2

1

+3.3V_RUN

L116BLM21PG600SN1D

L116BLM21PG600SN1D

805

805

8

C C

CK_PWRGD_R42

CLK_ICH_14M9

IDT: 0.1uFx5pcs, 10uFx1pcs

C1401

C1401

C1400

C1400
10U/6.3V

10U/6.3V

0.1uF near the every power pin.

+3.3V_RUN

CLK_ICH_14M

Place the 33 ohm
resistors close to the CK 505

0.1U

0.1U

C1402

C1402

C1403

C1403

0.1U

0.1U

0.1U

0.1U

R991 10KR991 10K
R994 33R994 33

U61

U61

C1405

C1405

0.1U

0.1U

+3.3V_CLK_VDD

+VDDIO_CLK

CPU_SEL

XTAL_OUT
XTAL_IN

EC_SMBDAT0
EC_SMBCLK0

1

VDD_USB

5

VDD_LCD

17

VDD_SRC

24

VDD_CPU

29

VDD_REF

15

VDD_SRC_IO

18

VDD_CPU_IO

9

VSS_SATA

2

VSS_USB

8

VSS_LCD

12

VSS_SRC

21

VSS_CPU

26

VSS_REF

16

CPU_STOP#

25

CK_PWRGD/PD#_3.3

30

REF_0/CPU_SEL

27

XOUT

28

XIN

31

SDATA

32

SCLK

SLG8SP585VTR

SLG8SP585VTR

CK505

CK505

QFN32

QFN32

CPU-0

CPU-0#

CPU-1

CPU-1#

DOT96T_LPR

DOT96C_LPR

SRC-1

SRC-1#

SATA

SATA#

27MHz_nonSS

27MHz_SS

GND

23
22

20
19

3
4

13
14

10
11

6
7

33

40mil

C1404

C1404

0.1U

0.1U

EC_SMBDAT013,14,38
EC_SMBCLK013,14,38

Realtek: 0.1uFx6pcs, 22uFx1pcs

Place within 0.5" of CLKGEN

CLK_BUF_BCLK_P
CLK_BUF_BCLK_N

CLK_BUF_DREFCLK
CLK_BUF_DREFCLK#

CLK_BUF_PCIE_3GPLL
CLK_BUF_PCIE_3GPLL#

CLK_BUF_DREFSSCLK
CLK_BUF_DREFSSCLK#

CLK_VGA_27M_R
CLK_VGA_27M_SS_R

R992 33R992 33
R993 33R993 33

Realtek: 0.1uFx3pcs, 22uFx1pcs

CLK_BUF_BCLK_P 9
CLK_BUF_BCLK_N 9

CLK_BUF_DREFCLK 9
CLK_BUF_DREFCLK# 9

CLK_BUF_PCIE_3GPLL 9
CLK_BUF_PCIE_3GPLL# 9

CLK_BUF_DREFSSCLK 9
CLK_BUF_DREFSSCLK# 9

CLK_VGA_27M 17
CLK_VGA_27M_SS 17

IDT: 0.1uFx2pcs, 10uFx1pcs

+3.3V_RUN

Add capacitor pads for improving WWAN.

C1288

C1288

*27P_NC

*27P_NC

50

50

CLK_ICH_14M

B B

XTAL_IN XTAL_OUT

C1409

C1409
33P

33P

50

50

Y7

Y7

21

14.318MHZ

14.318MHZ

1 2

C1410

C1410
33P

33P

50

50

R996 *0_NCR996 *0_NC

+1.05V_PCH

R998 0R998 0

SLG,IDT: +1.05V
Realtek: +3.3V

L117BLM21PG600SN1D

L117BLM21PG600SN1D

805

805

HP: 10u x2pcs

Place each 0.1uF cap as close as
possible to each VDD IO pin. Place
the 10uF caps on the VDD_IO plane.

C1406

C1406
10U

10U

40mil

C1407

C1407

0.1U

0.1U

+VDDIO_CLK

C1408

C1408

0.1U

0.1U

+VDDIO_CLK:
SLG date sheet (V0.2) P15: Min 1.05V,Max3.465V.

+3.3V_RUN

7

R999

R999
*4.7K_NC

*4.7K_NC

A A

1 2

CPU_SEL

R1000

R1000

4.7K

4.7K

1 2

5

C1411

C1411
*10P_NC

*10P_NC

EMI Capacitor

PIN 30 CPU_0 CPU_1

0(default)

1(0.7V-1.5V)

133MHz

100MHz 100MHz

133MHz

4

CPU_SEL:
SLG date sheet (V0.2) P15:
High Voltage: Min 0.7V, Max 1.5V.
Low Voltage: Min Vss-0.3V, Max 0.35V.
Realtek date sheet(V1.2) P11:
High Voltage: Min 0.7V, Max 1.5V.
Low Voltage: Min Vss-0.3V, Max 0.35V.
IDT date sheet(V0.7) P10:
High Voltage: Min 0.7V, Max 1.5V.
Low Voltage: Min Vss-0.3V, Max 0.35V.

3

2

Realtek date sheet(V1.2) P11: Min 1.05V,Max 3.3V.
IDT date sheet(V0.7) P10: Min 0.9975V,Max 3.465V.

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

COMPUTER

Clock Generator

Clock Generator

Clock Generator

FM9 1A

FM9 1A

FM9 1A

15 64Thursday, February 26, 2009

15 64Thursday, February 26, 2009

15 64Thursday, February 26, 2009

1

5

PCIE_MTX_GRX_N[0..15]3 PCIE_MRX_GTX_N[0..15]3

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0

D D

C C

B B

100 MHz (+/-300 ppm) input frequency, 0-0.7 V single-ended swing.
clock must be provided less than 400ns
after CLKREQ# is asserted

CLK_PCIE_VGA9
CLK_PCIE_VGA#9

PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1

PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2

PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3

PCIE_MTX_GRX_P4
PCIE_MTX_GRX_N4

PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N5

PCIE_MTX_GRX_P6
PCIE_MTX_GRX_N6

PCIE_MTX_GRX_P7
PCIE_MTX_GRX_N7

PCIE_MTX_GRX_P8
PCIE_MTX_GRX_N8

PCIE_MTX_GRX_P9
PCIE_MTX_GRX_N9

PCIE_MTX_GRX_P10
PCIE_MTX_GRX_N10

PCIE_MTX_GRX_P11
PCIE_MTX_GRX_N11

PCIE_MTX_GRX_P12
PCIE_MTX_GRX_N12

PCIE_MTX_GRX_P13
PCIE_MTX_GRX_N13

PCIE_MTX_GRX_P14
PCIE_MTX_GRX_N14

PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N15

AF30

AE31

AE29
AD28

AD30
AC31

AC29
AB28

AB30
AA31

AA29

W31

W29

AK30
AK32

U31

U29

N29
M28

M30

Y28

Y30

V28

V30

T28

T30
R31

R29
P28

P30
N31

L31

L29
K30

4

U32A

U32A

PCIE_RX0P
PCIE_RX0N

PCIE_RX1P
PCIE_RX1N

PCIE_RX2P
PCIE_RX2N

PCIE_RX3P
PCIE_RX3N

PCIE_RX4P
PCIE_RX4N

PCIE_RX5P
PCIE_RX5N

PCIE_RX6P
PCIE_RX6N

PCIE_RX7P
PCIE_RX7N

PCIE_RX8P
PCIE_RX8N

PCIE_RX9P
PCIE_RX9N

PCIE_RX10P
PCIE_RX10N

PCIE_RX11P
PCIE_RX11N

PCIE_RX12P
PCIE_RX12N

PCIE_RX13P
PCIE_RX13N

PCIE_RX14P
PCIE_RX14N

PCIE_RX15P
PCIE_RX15N

PCIE_REFCLKP
PCIE_REFCLKN

PART 1 OF 10

PART 1 OF 10

PCI-EXPRESS INTERFACE

PCI-EXPRESS INTERFACE

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

PCIE_TX8P
PCIE_TX8N

PCIE_TX9P
PCIE_TX9N

PCIE_TX10P
PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIE_TX13P
PCIE_TX13N

PCIE_TX14P
PCIE_TX14N

PCIE_TX15P
PCIE_TX15N

PCIE_CALRN
PCIE_CALRP

AH30
AG31

AG29
AF28

AF27
AF26

AD27
AD26

AC25
AB25

Y23
Y24

AB27
AB26

Y27
Y26

W24
W23

V27
U26

U24
U23

T26
T27

T24
T23

P27
P26

P24
P23

M27
N26

AA22
Y22

PCIE_CALRN
PCIE_CALRP

PCIE_MRX_GTX_C_P0
PCIE_MRX_GTX_C_N0

PCIE_MRX_GTX_C_P1
PCIE_MRX_GTX_C_N1

PCIE_MRX_GTX_C_P2
PCIE_MRX_GTX_C_N2

PCIE_MRX_GTX_C_P3
PCIE_MRX_GTX_C_N3

PCIE_MRX_GTX_C_P4
PCIE_MRX_GTX_C_N4

PCIE_MRX_GTX_C_P5
PCIE_MRX_GTX_C_N5

PCIE_MRX_GTX_C_P6
PCIE_MRX_GTX_C_N6

PCIE_MRX_GTX_C_P7
PCIE_MRX_GTX_C_N7

PCIE_MRX_GTX_C_P8
PCIE_MRX_GTX_C_N8

PCIE_MRX_GTX_C_P9
PCIE_MRX_GTX_C_N9

PCIE_MRX_GTX_C_P10
PCIE_MRX_GTX_C_N10

PCIE_MRX_GTX_C_P11
PCIE_MRX_GTX_C_N11

PCIE_MRX_GTX_C_P12
PCIE_MRX_GTX_C_N12

PCIE_MRX_GTX_C_P13
PCIE_MRX_GTX_C_N13

PCIE_MRX_GTX_C_P14
PCIE_MRX_GTX_C_N14

PCIE_MRX_GTX_C_P15
PCIE_MRX_GTX_C_N15

3

(1.1V)

+PCIE_VDDC

R5912.0K R5912.0K
R5921.27K R5921.27K

2

PCIE_MRX_GTX_P[0..15]3PCIE_MTX_GRX_P[0..15]3

PCIE_MRX_GTX_P0 PCIE_MRX_GTX_C_P0
PCIE_MRX_GTX_P1
PCIE_MRX_GTX_P2
PCIE_MRX_GTX_P3
PCIE_MRX_GTX_P4
PCIE_MRX_GTX_P5
PCIE_MRX_GTX_P6
PCIE_MRX_GTX_P7
PCIE_MRX_GTX_P8
PCIE_MRX_GTX_P9
PCIE_MRX_GTX_P10
PCIE_MRX_GTX_P11
PCIE_MRX_GTX_P12
PCIE_MRX_GTX_P13
PCIE_MRX_GTX_P14
PCIE_MRX_GTX_P15

PCIE_MRX_GTX_N0
PCIE_MRX_GTX_N1
PCIE_MRX_GTX_N2
PCIE_MRX_GTX_N3
PCIE_MRX_GTX_N4
PCIE_MRX_GTX_N5
PCIE_MRX_GTX_N6
PCIE_MRX_GTX_N7
PCIE_MRX_GTX_N8
PCIE_MRX_GTX_N9
PCIE_MRX_GTX_N10
PCIE_MRX_GTX_N11
PCIE_MRX_GTX_N12
PCIE_MRX_GTX_N13
PCIE_MRX_GTX_N14
PCIE_MRX_GTX_N15

12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

C8140.1U 10C8140.1U 10
C8150.1U 10C8150.1U 10
C8160.1U 10C8160.1U 10
C8170.1U 10C8170.1U 10
C8180.1U 10C8180.1U 10
C8190.1U 10C8190.1U 10
C8200.1U 10C8200.1U 10
C8210.1U 10C8210.1U 10
C8220.1U 10C8220.1U 10
C8230.1U 10C8230.1U 10
C8240.1U 10C8240.1U 10
C8250.1U 10C8250.1U 10
C8260.1U 10C8260.1U 10
C8270.1U 10C8270.1U 10
C8280.1U 10C8280.1U 10
C8290.1U 10C8290.1U 10

C8300.1U 10C8300.1U 10
C8310.1U 10C8310.1U 10
C8320.1U 10C8320.1U 10
C8330.1U 10C8330.1U 10
C8340.1U 10C8340.1U 10
C8350.1U 10C8350.1U 10
C8360.1U 10C8360.1U 10
C8370.1U 10C8370.1U 10
C8380.1U 10C8380.1U 10
C8390.1U 10C8390.1U 10
C8400.1U 10C8400.1U 10
C8410.1U 10C8410.1U 10
C8420.1U 10C8420.1U 10
C8430.1U 10C8430.1U 10
C8440.1U 10C8440.1U 10
C8450.1U 10C8450.1U 10

PCIE_MRX_GTX_C_P1
PCIE_MRX_GTX_C_P2
PCIE_MRX_GTX_C_P3
PCIE_MRX_GTX_C_P4
PCIE_MRX_GTX_C_P5
PCIE_MRX_GTX_C_P6
PCIE_MRX_GTX_C_P7
PCIE_MRX_GTX_C_P8
PCIE_MRX_GTX_C_P9
PCIE_MRX_GTX_C_P10
PCIE_MRX_GTX_C_P11
PCIE_MRX_GTX_C_P12
PCIE_MRX_GTX_C_P13
PCIE_MRX_GTX_C_P14
PCIE_MRX_GTX_C_P15

PCIE_MRX_GTX_C_N0
PCIE_MRX_GTX_C_N1
PCIE_MRX_GTX_C_N2
PCIE_MRX_GTX_C_N3
PCIE_MRX_GTX_C_N4
PCIE_MRX_GTX_C_N5
PCIE_MRX_GTX_C_N6
PCIE_MRX_GTX_C_N7
PCIE_MRX_GTX_C_N8
PCIE_MRX_GTX_C_N9
PCIE_MRX_GTX_C_N10
PCIE_MRX_GTX_C_N11
PCIE_MRX_GTX_C_N12
PCIE_MRX_GTX_C_N13
PCIE_MRX_GTX_C_N14
PCIE_MRX_GTX_C_N15

1

AL27

PLTRST#3,9,26,28,29,31,32,41

A A

5

PERSTB

M92-S2/M92-XT

M92-S2/M92-XT

4

M92-S2 XT AJ072800T04 100-CG1675(216-0728004)
M92-S2 AJ072800T03 100-CG1643(216-0728003)

3

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

COMPUTER

VGA-M92-XT (PCIe)

VGA-M92-XT (PCIe)

VGA-M92-XT (PCIe)

FM9 1A

FM9 1A

FM9 1A

1

16 64Thursday, February 26, 2009

16 64Thursday, February 26, 2009

16 64Thursday, February 26, 2009

5

MEMORY APERTURE SIZE SELECT

MEMORY
SIZE

128MB

256MB

64MB

D D

512MB

+3.3V_DELAY

GPIO Straps
table

GPIO0

GPIO1

GPIO2

GPIO3

C C

GPIO4

GPIO5

GPIO6

+3.3V_DELAY

R603 *10K_NCR603 *10K_NC
R604 *10K_NCR604 *10K_NC
R605 *10K_NCR605 *10K_NC
R606 *10K_NCR606 *10K_NC
R607 *10K_NCR607 *10K_NC
R608 *10K_NCR608 *10K_NC

R611 10KR611 10K
R613 *10K_NCR613 *10K_NC
R614 10KR614 10K
R615 10KR615 10K
R620 10KR620 10K

R628 *10K_NCR628 *10K_NC
R627 *10K_NCR627 *10K_NC
R624 10KR624 10K

B B

+1.8V_RUN_GFX

A A

Memory Straps

800MHz
512MB(64M*16) Samsung

800MHz
512MB(64M*16) Hynix

CFG2

CFG3
GPIO9 GPIO13 GPIO12 GPIO11

0

0 0 1

0 1 0

1 0 0

R595 10KR595 10K

1 2

R597 *10K_NCR597 *10K_NC

1 2

R599 *10K_NCR599 *10K_NC

1 2

DESCRIPTION OF DEFAULT SETTINGS

GPIO(0) - TX_PWRS_ENB (Transmitter Power Sa vings Enable)

0: 50% Tx output swing fo r mobile mode

1: full Tx output swing (Defa ult setting for Desktop)

GPIO(1) - TX_DEEMPH_EN (Transmitter De-emp hasis Enable)

0: Tx de-emphasis d isabled for mobile mod e

1: Tx de-emphasis e nabled (Default setting fo r Desktop)

GPIO(2) - BIF_GEN2_EN (5.0 GT/s Enable )

0 : Default. (Driver Controlled Ge n2)

1 : Strap Controlled Gen2

ATI reserved configuration straps.
ATI reserved configuration straps.

GPIO_5_AC_BATT
0 : Battery saving mode = 0.0 V
1 : AC (Performance mode) = 3 .3 V

ATI Internal use only

1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2

R596 10KR596 10K

1 2

R598 *10K_NCR598 *10K_NC

1 2

R600 *10K_NCR600 *10K_NC

1 2

RAM_TYPE
_CFG2

CFG0

CFG1

0 0

RAM_CFG0
RAM_CFG1
RAM_CFG2

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5

HDMI_HD_EN
TEMP_FAIL
GFX_CLKREQ#
VGAVSYNC
VGAHSYNC

VGAVSYNC
VGAHSYNC
TEMP_FAIL

RAM_TYPE_CFG0
RAM_TYPE_CFG1
RAM_TYPE_CFG2

RAM_TYPE

RAM_TYPE

_CFG0

_CFG1

00 1

0 1 0

5

GFX_ON19,29,50

FM9
setting

0

0

0

0
0

0

0

Quanta PN
(QuantaBuy)

AKD5LGGT502

R651 *75K/F_NCR651 *75K/F_NC

C868

C868

*0.1U_NC

*0.1U_NC

25

25
603

603

OPTIONAL RC NETWORK
TO FINE TUNE
POWER SEQUENCING

OSC_SPREAD

CLK_VGA_27M_SS15

CLK_VGA_27M15

OSC_OUT

Spread Spectrum

If U4, the discrete spread spectrum chip
is not used, then pop R48 in order to
pull-down BXTALOUT for EMI reasons.

R664 *10K _reserveR664 *10K_reserve

OSC_OUT

R669 *0_reserveR669 *0_reserve

1 2

OSC_SPREAD

Quanta PN
(WinBuy)

4

R1151 0 603R1151 0 603

Q69

Q69

*SI2303BDS-T1-E3_NC

*SI2303BDS-T1-E3_NC

3

2

31

2

R635 0R635 0

1 2

1 2

R643 *182R_reserveR643 *182R_reserve

R644

R644
*1M_reserve

*1M_reserve

1 2

1 2

R640 *0_reserveR640 *0_reserve

12

C861

C861
*12P_reserve

*12P_reserve

50

50

+3.3V_RUN

R659

R659
*10K_reserve

*10K_reserve

8
7
6
5

1

12

R649

R649
*100K_NC

*100K_NC

Q72

Q72
*2N7002W-7-F_NC

*2N7002W-7-F_NC

CLK_VGA_27M_SSIN_R

R638 *221/F_reserveR638 *221/F_reserve

R660

R660
*10K_reserve

*10K_reserve

+3VL

C955

C955

12

*10U_reserve

*10U_reserve

805

805
10

10

12

R636

R636
*10K_NC

*10K_NC

L81

L81

C956

C956

12

*0.1U_reserve

*0.1U_reserve

10

10

+3.3V_DELAY +3.3V_RUN

C867

C867
*0.1U_NC

*0.1U_NC

10

10

R631 *0_reserveR631 *0 _reserve

1 2

R633 *0_NCR633 *0_NC

1 2

R634 100/FR634 100/F
R637 120/FR637 120/F

Y4

Y4

21

*27MHZ_reserve

*27MHZ_reserve

R642 *1M_reserveR642 *1M_reserve

12

C860

C860
*12P_reserve

*12P_reserve

50

50

U45

U45

1

XIN/CLKIN

XOUT

2

VSS

VDD

3

SO

PD#

4

SSCLK

REFCLK

*P1819GF-08SR_reserve

*P1819GF-08SR_reserve

S0

-1.75% (DOWN) 0

Vendor PN 31 level PN

K4W1G1646E-HC12

H5TQ1G63BFR-12CAKD5LZGTW00

4

3

U32B

U32B

For Park S3:
Install All components in this Box
L86,C960,C905,C898,L84,
C959,C891,C890,R142,
R143,R144,R145

DPC_VDD18#1 and DPC_VDD18#2 are for
Future ASIC

For M92-S2: DO NOT Install any Component
in this Box.

+1.8V_RUN_GFX +1.8V_RUN_GFX

L86 *BLM15BD121SN1D_NCL86 *BLM15BD121S N1D_NC

+PCIE_VDDC

L84 *BLM15BD121SN1D_NCL84 *BLM15BD121S N1D_NC

+DPC_VDD18

+DPC_VDD18

C905

C905
*1U_NC

*1U_NC

C891

C891
*1U_NC

*1U_NC

R143 *0_NCR143 *0_NC

1 2

R144 *0_NCR144 *0_NC

1 2

R146 *0_NCR146 *0_NC

1 2

R145 *0_NCR145 *0_NC

1 2

R142 *0_NCR142 *0_NC

1 2

RAM_TYPE_CFG0
RAM_TYPE_CFG1
RAM_TYPE_CFG2

AC10

U1

AC7

Y2
U5

AA1

Y4

Y7
V2
Y8
V4

AB7

W1

AB8

W3

AB9

W5

AC6

W6
AD7
AA3
AC8
AA5
AE8
AA6
AE9
AB4
AD9
AB2

AC5

As M82 design, for GPIO use

XTALIN 21

XTALOUT 21

*BLM11A05S_reserve

*BLM11A05S_reserve

+3.3V_RUN

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4

BB_ENA18

R639 499/FR639 499/F

1 2

R641 249/FR641 249/F

C859 0.1UC859 0.1U

GPIO5

HDMI_HD_EN

RAM_CFG0
RAM_CFG1
RAM_CFG2

CLK_VGA_27M_SSIN_R

R141 *0_NCR141 *0_NC

1 2

TEMP_FAIL

GFX_CLKREQ#

R449 1KR449 1K

HPD1

12

1 2

R645 0R645 0

R621

R621

R57 1KR57 1K

10K

10K

1 2

GFX_CORE_CNTRL250

GFX_CORE_CNTRL050

GFX_CORE_CNTRL150

BIA_PWM24

3

PANEL_BKEN29

THERMAL_INT#19

+1.8V_RUN_GFX

ENVDD24

T158 PADT158 PAD
T159 PADT159 PAD

T86 PADT86 PAD

T23 PADT23 PAD

T89 PADT89 PAD

T13 PADT13 PAD
T28 PADT28 PAD
T24 PADT24 PAD
T25 PADT25 PAD

T21 PADT21 PAD
T20 PADT20 PAD
T22 PADT22 PAD
T10 PADT10 PAD
T12 PADT12 PAD

T29 PADT29 PAD
T27 PADT27 PAD

T26 PADT26 PAD

T77 PADT77 PAD
T49 PADT49 PAD

T161 PADT161 PAD

12

VREFG

AB13

AD10

AC14

AC16

AB22
AC22

AB16
AB12
AB11

AF24

U6
U10
T10

U8

U7

T9

T8

T7
P10

P4

P2

N6

N5

N3

Y9

N1

M4

R6

W10

M2

P8

P7

N8

N7

L6
L5
L3
L1

K4

W8
W9
W7

N10

L9

N9

PART 2 OF 10

PART 2 OF 10

DVP PORT DAC1

DVP PORT DAC1

DVPCLK
DVPCNTL_0

DVPCNTL_1
DVPCNTL_2

DVPCNTL_MVP_0
DVPCNTL_MVP_1

DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

I/O

I/O

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6_TACH
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO

GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4

HPD1

VREFG

RESERVED

RESERVED

NC_PWRGOOD
RSVD#8

RSVD#9

NC#1
NC#2

RSVD#3
RSVD#2
RSVD#1

TESTEN

M92-S2/M92-XT

M92-S2/M92-XT

2

AM26

R

AK26

RB

AL25

G

AJ25

GB

AH24

B

AG25

BB

AH26

HSYNC

AJ27

VSYNC

AG24

AVDD

AE22

AVSSQ

AE23

VDD1DI

AD23

VSS1DI

RSET

AD22

RSET

DAC2

DAC2

AM12

R2

AK12

R2B

AL11

G2

AJ11

G2B

AK10

B2

AL9

B2B

AL13

H2SYNC

AJ13

V2SYNC

AH12

C

AM10

Y

AJ9

COMP

AE20

A2VDD

C846

C846
10nF

10nF

AE17

A2VDDQ

AE19

A2VSSQ

Keep A2VSSQ away from noisy ground.

+VDD2DI

AD19

VDD2DI

AC19

VSS2DI

R2SET

AG13

R2SET

2

C856

C856
*0.1U_NC

*0.1U_NC

+1.8V_RUN_GFX

C863

C863
*0.1U_NC

*0.1U_NC

R612 499RR612 499R

VGA_RED

VGA_GRN

VGA_BLU

VGAHSYNC
VGAVSYNC

+A2VDD

C8481UC848

C847

C847

0.1U

0.1U

1U

+A2VDDQ

C8581UC858

C857

C857

0.1U

0.1U

1U

C850

C850

C851

C851

0.1U

0.1U

10nF

10nF

Place very close to ASIC balls.

R646 715R646 715

AVDD=70mA max

VDD1DI=45mA max

VGA_RED 25

VGA_GRN 25

VGA_BLU 25

VGAHSYNC 25
VGAVSYNC 25

L82 BLM15BD121SN1DL82 BLM15BD121SN1D

C849

C849

4.7uF

4.7uF

L85 BLM15BD121SN1DL85 BLM15BD121SN1D

L83 BLM15BD121SN1DL83 BLM15BD121SN1D

C8521UC852
1U

1

VGA_BLU
VGA_GRN
VGA_RED

R415

R415
150/F

150/F

R616

R616
10K

10K

2

Q67

Q67

+3.3V_DELAY

DIS only

Layout Note:
Place 150 ohm
termination resistors
close to ATI CHIP.

+3.3V_DELAY

R617

R617
10K

10K

2

Q68

Q68

1 3

DTC114TUAT106

DTC114TUAT106

HDMI_DET 24

12

R625

R625
100K

100K

HPD1

R413

R413

R414

R414

150/F

150/F

150/F

150/F

1 3

MMST3904-7-F

MMST3904-7-F

A2VDD=65mA max

+1.8V_RUN_GFX

A2VDDQ=1mA max

+1.8V_RUN_GFX

VDD2DI=40mA max

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

Title

Title

Title

VGA-M92-XT (PCIe)

VGA-M92-XT (PCIe)

VGA-M92-XT (PCIe)

Size Docum ent Number Rev

Size Docum ent Number Rev

Size Docum ent Number Rev

FM9 1A

FM9 1A

FM9 1A

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

17 64Thursday, February 26, 2009

17 64Thursday, February 26, 2009

17 64Thursday, February 26, 2009

+1.5V_RUN

C869

C869
10nF

10nF

D D

C C

B B

BB_ENA17

A A

5

layout note: close to VDDR1#[1:17]

C875

C875

C874

L87

L87

C874

C873

C873
10nF

10nF

C8821UC882
1U

100nF

100nF

C8831UC883
1U

100nF

100nF

C886

C886
100nF

100nF

VDD_CT#[1..4]=110mA max

C909

C909
10U

10U

+3.3V_DELAY

VDDR3#[1..4]=50mA max

C9141UC914
1U

+1.8V_RUN_GFX

VDDR4#[1..4] & VDDR5#[1..4]=340mA max

C9191UC919
1U

C9231UC923

1U

3 1

+1.8V_RUN_GFX

2

C870

C870
10nF

10nF

C8791UC879
1U

C895

C895
10U

10U

For M92-S2: Install R147,R148,R149
Use R150 0R to VDDR4
M93-S3 and Park: Remove R147,R148,R149
Use R45 150 Ohms Pull Down

+1.5V_RUN

+BBP

6.3

6.3

C871

C871
10nF

10nF

C8801UC880
1U

+1.5V_RUN

C896

C896
10U

10U

+1.8V_RUN_GFX

L88 BLM15BD121SN1DL88 BLM15BD121SN1D

Q71

Q71

3

12

C866

C866

2

1U

1U

402

402

31

2

R653

R653
10K

10K

C872

C872
10nF

10nF

C8811UC881
1U

SI2301BDS-T-GE3

SI2301BDS-T-GE3

C897

C897
10U

10U

BLM15BD121SN1D

BLM15BD121SN1D

1

Q74

Q74
2N7002W-7-F

2N7002W-7-F

C910

C910
100nF

100nF

C920

C920
100nF

100nF

C9241UC924

1U

Q70

Q70
2N7002W-7-F

2N7002W-7-F

1 2

R652 100KR652 100K

C9151UC915
1U

C877

C877
100nF

100nF

4

VDDR1#[1..17]=2A max

C878

C878
100nF

100nF

+1.5V_RUN

+VDD_CT

C913

C913

C9121UC912

C9111UC911
1U

C9211UC921
1U

C916

C916
100nF

100nF

1U

C908

C908
100nF

100nF

R45 *150/F_NCR45 *150/F_NC

C922

C922
100nF

100nF

+VDDRH1

(0.9~1.2V)

+VCC_GFX_CORE

+5V_RUN

100nF

100nF

U32D

12

R150 0R150 0

1 2

R147 0R147 0

1 2

R148 0R148 0

1 2

R149 0R149 0

1 2

AA20
AA21
AB20
AB21

AA17
AA18
AB17
AB18

AA11
AA12

H13
H16
H19
J10
J23
J24

J9
K10
K23
K24

K9
L11
L12
L13
L20
L21
L22

Y11
Y12

U11
U12
V11
V12

L17

L16

U32D

VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17

VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4

VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4

VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#4

VDDR5#1
VDDR5#2
VDDR5#3
VDDR5#4

VDDRHA

VSSRHA

M92-S2/M92-XT

M92-S2/M92-XT

PART 4 OF 10

PART 4 OF 10

POWER

POWER

layout note: close to VDDC#[1:25]

C9251UC925

C9261UC926

1U

1U

C9311UC931

C9321UC932
1U

C947

C947
10U

10U

C9331UC933
1U

(0.9~1.2V)

+VCC_GFX_CORE

C946

C946
10U

10U

1U

PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8

PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25

VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8

C9271UC927
1U

C9341UC934
1U

C948

C948
10U

10U

VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9

C9291UC929
1U

C9351UC935
1U

3

AB23
AC23
AD24
AE24
AE25
AE26
AF25
AG26

L23
L24
L25
L26
M22
N22
N23
N24
R22
T22
U22
V22

AA15
M11
M12
N15
N17
R13
R16
R18
R21
T12
T15
T17
T20
U13
U16
U18
U21
V15
V17
V20
V21
Y13
Y16
Y18
Y21

M13
M15
M16
M17
M18
M20
M21
N20

PCIE_VDDR#[1..8]=500mA max

C8881UC888
1U

(0.9~1.2V)

+VCC_GFX_CORE

C917

C917
100nF

100nF

DDCI=2A max

+VDDCI

(0.9~1.2V)

(0.9~1.2V)

+VCC_GFX_CORE

C9301UC930
1U

C9371UC937

C9361UC936

1U

1U

C893

C8891UC889
1U

+BBP

C9001UC900
1U

C893
10nF

10nF

C892

C892
100nF

100nF

C8991UC899
1U

VDDC#[2..3]=120mA max

C9181UC918
1U

C9391UC939
1U

2

+1.8V_RUN_GFX

C894

C894
10U

10U

PCIE_VDDC#[1..12]=2A max

C9011UC901

C9021UC902

1U

1U

U32E

U32E

AA27

PCIE_VSS#1

AB24

PCIE_VSS#2

AB32

PCIE_VSS#3

AC24

PCIE_VSS#4

AC26

PCIE_VSS#5

AC27

PCIE_VSS#6

AD25

PCIE_VSS#7

AD32

PCIE_VSS#8

AE27

PCIE_VSS#9

AF32

PCIE_VSS#10

AG27

PCIE_VSS#11

AH32

PCIE_VSS#12

K28

PCIE_VSS#13

K32

PCIE_VSS#14

L27

PCIE_VSS#15

M32

PCIE_VSS#16

N25

PCIE_VSS#17

N27

PCIE_VSS#18

P25

PCIE_VSS#19

P32

PCIE_VSS#20

R27

PCIE_VSS#21

T25

PCIE_VSS#22

T32

PCIE_VSS#23

U25

PCIE_VSS#24

U27

PCIE_VSS#25

V32

PCIE_VSS#26

W25

PCIE_VSS#27

W26

PCIE_VSS#28

W27

PCIE_VSS#29

Y25

PCIE_VSS#30

Y32

PCIE_VSS#31

A3

GND#1

A30

GND#2

AA13

GND#3

AA16

GND#4

AB10

GND#5

AB15

GND#6

AB6

GND#7

AC9

GND#8

AD6

GND#9

AD8

GND#10

AE7

GND#11

AG12

GND#12

AH10

GND#13

AH28

GND#14

B10

GND#15

B12

GND#16

B14

GND#17

B16

GND#18

B18

GND#19

B20

GND#20

B22

GND#21

B24

GND#22

B26

GND#23

B6

GND#24

B8

GND#25

C1

GND#26

C32

GND#27

E28

GND#28

F10

GND#29

F12

GND#30

F14

GND#31

F16

GND#32

M92-S2/M92-XT

M92-S2/M92-XT

(0.9~1.2V)

C941

C941
100nF

100nF

C9031UC903
1U

C9041UC904
1U

PART 5 OF 10

PART 5 OF 10

GND

GND

C942

C942
100nF

100nF

VSS_MECH#1
VSS_MECH#2
VSS_MECH#3

+VDDCI

C9431UC943

1U

(1.1V)

+PCIE_VDDC

C9061UC906
1U

GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60
GND#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89

1U

C9441UC944

F18
F2
F20
F22
F24
F26
F6
F8
G10
G27
G31
G8
H14
H17
H2
H20
H6
J27
J31
K11
K2
K22
K6
M6
N11
N12
N13
N16
N18
N21
P6
P9
R12
R15
R17
R20
T13
T16
T18
T21
T6
U15
U17
U20
U3
U9
V13
V16
V18
V6
Y10
Y15
Y17
Y20
Y6
T11
R11

A32
AM1
AM32

L12 BLM18PG121SN1DL12 BLM18PG121SN1D

C168

C168
10U

10U

603

603

1 2

6.3

6.3

C68

C68
10U

10U

603

603

1 2

6.3

6.3

C907

C907
10U

10U

L89

L89

BLM18EG221SN1D

C945

C945
10U

10U

BLM18EG221SN1D

1

(PCIE_VDDC 1.0~1.1V +/- 5%@ 2A )

(1.1V)

C211

C211

0.1U

0.1U

10

10

C196

C196

0.1U

0.1U

10

10

+PCIE_VDDC+1.1V_GFX_PCIE

12

C183

C183
1U

1U

402

402

6.3

6.3

12

C74

C74
1U

1U

402

402

6.3

6.3

(0.9~1.2V)

+VCC_GFX_CORE

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

COMPUTER

VGA-M92-XT (PCIe)

VGA-M92-XT (PCIe)

VGA-M92-XT (PCIe)

FM9 1A

FM9 1A

FM9 1A

1

18 64Thursday, February 26, 2009

18 64Thursday, February 26, 2009

18 64Thursday, February 26, 2009

5

4

3

2

1

MEMORY INTERFACE

U32C

D D

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23

QSA#[7..0]20

C C

QSA[7..0]20
DQMA#[7..0]20

MDA[63..0]20

MAA[12..0]20

A_BA[2..0]20

QSA#[7..0]
QSA[7..0]
DQMA#[7..0]
MDA[63..0]
MAA[12..0]

A_BA[2..0]

DIVIDER RESISTORS DDR3

R656

R656
100R

100R

R657

R657
100R

100R

MVREFS_A

MVREF TO 1.5V
MVREF TO GND

MVREFD_A

C952

C952

0.1U

0.1U

C950

C950

0.1U

0.1U

C953

C953
10nF

10nF

B B

+1.5V_RUN

+1.5V_RUN

R658

R658
100R

100R

R665

R665
100R

100R

A A

C951

C951
10nF

10nF

+1.5V_RUN

100R
100R

MAA1320

R661

R661

4.7K

4.7K

R662

R662

4.7K

4.7K

R663

R663
243R

243R

MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

CLKTESTA
CLKTESTB

MEMTEST

R667 243RR667 243R
R668 243RR668 243R
R670 243RR670 243R

Reserve for Park-S3

5

U32C

K27

DQA_0

J29

DQA_1

H30

DQA_2

H32

DQA_3

G29

DQA_4

F28

DQA_5

F32

DQA_6

F30

DQA_7

C30

DQA_8

F27

DQA_9

A28

DQA_10

C28

DQA_11

E27

DQA_12

G26

DQA_13

D26

DQA_14

F25

DQA_15

A25

DQA_16

C25

DQA_17

E25

DQA_18

D24

DQA_19

E23

DQA_20

F23

DQA_21

D22

DQA_22

F21

DQA_23

E21

DQA_24

D20

DQA_25

F19

DQA_26

A19

DQA_27

D18

DQA_28

F17

DQA_29

A17

DQA_30

C17

DQA_31

E17

DQA_32

D16

DQA_33

F15

DQA_34

A15

DQA_35

D14

DQA_36

F13

DQA_37

A13

DQA_38

C13

DQA_39

E11

DQA_40

A11

DQA_41

C11

DQA_42

F11

DQA_43

A9

DQA_44

C9

DQA_45

F9

DQA_46

D8

DQA_47

E7

DQA_48

A7

DQA_49

C7

DQA_50

F7

DQA_51

A5

DQA_52

E5

DQA_53

C3

DQA_54

E1

DQA_55

G7

DQA_56

G6

DQA_57

G1

DQA_58

G3

DQA_59

J6

DQA_60

J1

DQA_61

J3

DQA_62

J5

DQA_63

K26

MVREFDA

J26

MVREFSA

K8

CLKTESTA

L7

CLKTESTB

J8

MEM_CALRP1

G20

NC_MAA_13

G14

NC_MAA_14

K7

NC_MEM_CALRN1

K25

NC_MEM_CALRP0

J25

NC_MEM_CALRN0

M92-S2/M92-XT

M92-S2/M92-XT

4

PART 3 OF 10

PART 3 OF 10

MEMORY

MEMORY

INTERFACE

INTERFACE

READ STROBE

READ STROBE

WRITE STROBE

WRITE STROBE

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8

MAA_9
MAA_10
MAA_11

MAA_BA0
MAA_BA1

MAA_12

MAA_BA2

DQMA_0
DQMA_1
DQMA_2
DQMA_3
DQMA_4
DQMA_5
DQMA_6
DQMA_7

QSA_0

QSA_1

QSA_2

QSA_3

QSA_4

QSA_5

QSA_6

QSA_7

QSA_0B
QSA_1B
QSA_2B
QSA_3B
QSA_4B
QSA_5B
QSA_6B
QSA_7B

ODTA0

ODTA1

CLKA0

CLKA1

CLKA0B
CLKA1B

RASA0B
RASA1B

CASA0B
CASA1B

CSA0B_0
CSA0B_1

CSA1B_0
CSA1B_1

CKEA0

CKEA1

WEA0B
WEA1B

DRAM_RST

MAA0

K17

MAA1

J20

MAA2

H23

MAA3

G23

MAA4

G24

MAA5

H24

MAA6

J19

MAA7

K19

MAA8

J14

MAA9

K14

MAA10

J11

MAA11

J13

A_BA0

J16

A_BA1

L15

MAA12

H11

A_BA2

G11

DQMA#0

E32

DQMA#1

E30

DQMA#2

A21

DQMA#3

C21

DQMA#4

E13

DQMA#5

D12

DQMA#6

E3

DQMA#7

F4

QSA0

H28

QSA1

C27

QSA2

A23

QSA3

E19

QSA4

E15

QSA5

D10

QSA6

D6

QSA7

G5

QSA#0

H27

QSA#1

A27

QSA#2

C23

QSA#3

C19

QSA#4

C15

QSA#5

E9

QSA#6

C5

QSA#7

H4

L18
K16

H26
G9

H25
H9

G22
G17

G19
G16

H22
J22

G13
K13

K20
J17

G25
H10

L10

ODTA0 20
ODTA1 20

CLKA0 20
CLKA1 20

CLKA0# 20
CLKA1# 20

RASA0# 20
RASA1# 20

CASA0# 20
CASA1# 20

CSA0_0# 20

CSA1_0# 20

CKEA0 20
CKEA1 20

WEA0# 20
WEA1# 20

C8841UC884

1U

1 2

R192

R192

4.7K

4.7K

+1.5V_RUN

R151

R151

4.7K

4.7K

3

SMBCLK229

SMBDAT229

THERMAL_INT#17

DRAM_RST# 20

+3.3V_ADM1032A

2

3 1

MB_THERM#
THERMAL_INT#

2

3 1

2N7002W-7-F

2N7002W-7-F

Q76

Q76

2N7002W-7-F

2N7002W-7-F

+3.3V_ADM1032A

Q75

Q75

12

12

R671

R671

4.7K

4.7K

THERMAL_INT#

R673 10KR673 10K
R674 10KR674 10K

12
12

+3.3V_ADM1032A +3.3V_SUS

GFX_ON17,29,50

2

THERMAL MONITOR

R672

R672

4.7K

4.7K

U46

U46

8

SCLK

7

SDATA

6

ALERT#

5

GND

THERM#

ADM1032ARMZ-1

ADM1032ARMZ-1

+3.3V_ADM1032A

Q80

Q80
SI2303BDS-T1-E3

SI2303BDS-T1-E3

3

2

31

2

VDD

D+

D-

1

Q81

Q81
2N7002W-7-F

2N7002W-7-F

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

+3.3V_ADM1032A

1
2
3

MB_THERM#

4

12

C958

C958

0.1U

0.1U

10

10

12

R686

R686
100K

100K

VGA-M92-XT (PCIe)

VGA-M92-XT (PCIe)

VGA-M92-XT (PCIe)

FM9 1A

FM9 1A

FM9 1A

12

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

C957

C957
2200P

2200P

50

50

1

VGA_THERMDP 21

VGA_THERMDN 21

MB_THERM# 46

19 64Thursday, February 26, 2009

19 64Thursday, February 26, 2009

19 64Thursday, February 26, 2009