Quanta FH5 DA0FH5MB6F0, LifeBook A531, LifeBook AH531 Schematic
5
IV@ For UMA
EV@ For Pure Dis.
SP@ For special setting
SPI@ For Optimus & UMA special setting
SPE@ For Pure Dis.special setting
D D
VA@ For Audio version A setting
VB@ For Audio version B setting
@3G For 3G setting
PIV@ For UMA Power
PEV@ For Pure Dis. Power
4
3
)+%/2&.',$*5$0
intel
<MCH Processor>
SandyBridge 0.61
Fan Driver
(PWM Type)
P42
ALS (SM/BUS)
2
GPU CORE PWR
RT8204
GPU IO PWR
UP6111AQDD
Discharger/+3V_M
+1.8V
UP61111AQDD
CPU iGPU_CORE
RT8204
CHARGER
P45
ISL88731
3/5V SYS PWR
P46
RT8206
CPU CORE PWR
P54
ISL95831
CPU +1.05V_VTT
P51
UP61111AQDD
PCH +1.05V
P45
UP61111AQDD
1
P53
P52
P43~P44
P47
P49
01
+0.85V
X'TAL
25MHz
ISL62871
P33
Mini Card
WiFi
USB3
CRT R-SW
LVDS
Switchable
HDMI R-SW
PCIE1 PCIE2
DDR III
SO-DIMM 0
SO-DIMM 1
C C
HDD (SATA)
ODD (SATA)
USB CNNs
USB0,1,2 P27
B B
Bluetooth
USB9 P27
P14, 15
P25
P25
Dual Channel
1066/1333 MHz
FDI interface
SATA0
SATA3
USB 2.0
Azalia
DDR SYSTEM MEMORY
SATA Gen3
SATA Gen2
USB
HDA
CCD
P24USB6
CardReader
RTS5138
USB5
P23
Audio CODEC
RTL ALC269VB
P30
Dual SPI ROM
4MB x1 (Basic ME+Braidwood)
rPGA 988
(37.5mm X 37.5mm)
FDI
intel
<PCH>
CougarPoint 0.7
mBGA 989
(25mm X 25mm)
SPI
WPCE791/FLASH
P9
PECI3.0
PCI-E
X16
DMI
P4~P7
X4 DMI interface
5GT/s2.7GT/s
DMIFDI
iGFX Interfaces
RTC
P9
PCI-E
P8~P13
LPC
P31
PCIE
5GT/s
nVIDIA GPU
N12P Fermi
Package GB2-128
Optimus (Muxle ss)
INT_CRT
INT_LVDS
INT_HDMI
X'TAL
32.768KHz
PCI-Express Gen2
5GT/s
X'TAL
25MHz
Transformer
Realtek
RTL8111E-GR
USB8
PCIE4
PCIE6
RJ45
X'TAL
27.0MHz
P16~P22
P26
P26
NewCard
USB8
P26
P48
P28
DDR3 PWR
RT8207A
P24
P24
P24
USB3
P50
CRT
LVDS
HDMI
Mini Card
3G
P28USB4
USB4
SIM Card Conn
DB
P24
P24
P24
P28
A A
P31
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Monday, September 27, 2010
Monday, September 27, 2010
Monday, September 27, 2010
Date: Sheet
Date: Sheet of
Date: Sheet of
PROJECT :
Block Diagram
Block Diagram
Block Diagram
FH5
FH5
FH5
1
1A
1A
1A
of
141
141
141
1RWH
+0GRHVQRWVXSSRUW86%
+0GRHVQRWVXSSRUW6$7$
5
HP Jack MIC Jack DMIC
P30 P30
SPK
P30
4
P24
SPI ROM
P31
Touch Pad
3
P29
Keyboard
P29
Light Sensor
P33
Button on
mechanical key
2
1
2
3
4
5
6
7
8
02
N12P-GE Power Up Sequence
MS15-UMA Power-ON Sequence
ACIN
A A
MAINON
+3VPCU/+5VPCU
NBSWON#
DGPU_VRON
S5_ON
+3V_GPU(VDD3)
+1.05V_GPU(PEX_VDD)
+VGPU_CORE(NVVDD)
tNVVDD
tNV-IFPAB_IOVDD
SLP_S5#,SLP_S4#,SLP_S3#
+1.8V_GPU(IFPAB_IOVDD)
tNV-FBVDDQ
B B
+1.5V_GPU(FBVDDQ)
+1.05V_PCH/+1.05V_VTT/+0.75V_DDR_VTT
+1.5VSUS/+3VSUS/+5VSUS
RSMRST#
EC_PWRBTN#
SUSON
MAINON
MAINON2
+1.5V/+1.8V/+3V/+5V
T1
T2
T3
T5
N12P-GE Power up Sequence
tNVVDD>0
tNV-IFPAB_IOVDD>0
tNV-FBVDDQ>0
HWPG
VRON
T10
CPU SVID BUS
+VCC_CORE
+VCC_GFX
T9
+3V_DSW
Deep S4/S5 off-on Sequence
DWPROK
SUSWARN#
C C
SUS_ACK#
SLP_SUS#
RSMRST#
S5_ON
T1
IMVP_PWRGD
EC_PWROK
SYS_PWROK
DRAMPWROK
UNCOREPWRGOOD
SUS_STAT#
PLTRST#
T4
T8
T6
T7
System Power Sequence
T1: S5_ON TO RSMRST# = 30ms (spec:mini 10ms)
T2: RSMRST# TO EC_PWRBTN# = 110ms (spec:mini 100ms)
+3V_S5/+5V_S5
T3: MAINON2 TO VRON = 110ms (spec:mini 99ms)
T4: VRON TO EC_PWROK = 10ms (HWPG NEED TO BE HIGH at that time)
Deep S4/S5 Sequence
T1: S5_ON TO RSMRST# = 30ms (spec:mini 10ms)
T5: MAINON to MAINON2 =500us
T6: EC_PWROK to UNCOREPWRGOOD =2ms(Min)
T7: SUS_STAT# to PLTRST# =60us(Min)
T8: SYS_PWROK to SUS_STAT# =1ms(Min)
T9: +VCC_CORE to IMVP_PWRGD =5ms(Max)
T10: VRON to accept SVID command. =5ms(Max)
D D
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Monday, September 27, 2010
Monday, September 27, 2010
Monday, September 27, 2010
Date: Sheet of
Date: Sheet of
1
2
3
4
5
6
Date: Sheet
7
PROJECT :
Frontpage
Frontpage
Frontpage
FH5
FH5
FH5
of
241
241
241
8
1A
1A
1A
5
4
3
2
1
03
D D
+3V_S5
+3V_S5
+3V_GPU
2.2Kȍ
2.2Kȍ
SMB_ME0_CLK
SMB_ME0_DAT
+3V_S5
+3V_S5
C C
intel
<PCH>
SMB_ME1_CLK
2.2Kȍ
2.2Kȍ
CougarPoint 0.7
S
+3V_S5
G
NMOS
G
NMOS
+3VPCU
DS
D
6.8Kȍ
+3VPCU
6.8Kȍ
MBCLK
MBDATASMB_ME1_DAT
G
D
NMOS
G
D
NMOS
+3V_GPU +3V_GPU
I2CS_SCL
S
I2CS_SDA
S
EC
ITE 8518
2.2Kȍ2.2Kȍ
N12P-GE
mBGA 989
(25mm X
25mm)
B B
SMB_PCH_CLK
SMB_PCH_DAT
A A
5
+3V_S5
2.2Kȍ
4
+3V_S5
+3V_S5
2.2Kȍ
G
DS
NMOS
G
D
NMOS
SMB_RUN_CLK
SMB_RUN_DAT
S
+3V
4.7Kȍ
+3V
Slave ADDRESS :A0H Slave ADDRESS :A4H
4.7Kȍ
3
DDR3 DIMM-0-STD
(5.2H)
VREF DQ 0
M2 Solution
DDR3 DIMM-1-STD
(9.2H)
VREF DQ 1
M2 Solution
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Monday, September 27, 2010
Monday, September 27, 2010
Monday, September 27, 2010
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
PROJECT :
SMBus Address
SMBus Address
SMBus Address
FH5
FH5
FH5
341
341
1
341
1A
1A
1A
5
4
3
2
1
04
Sandy Bridge Processor (DMI,PEG,FDI)
D D
C C
B B
DMI_TXN08
DMI_TXN18
DMI_TXN28
DMI_TXN38
DMI_T XP08
DMI_T XP18
DMI_T XP28
DMI_T XP38
DMI_RXN08
DMI_RXN18
DMI_RXN28
DMI_RXN38
DMI_RXP08
DMI_RXP18
DMI_RXP28
DMI_RXP38
FDI_TXN08
FDI_TXN18
FDI_TXN28
FDI_TXN38
FDI_TXN48
FDI_TXN58
FDI_TXN68
FDI_TXN78
FDI_TXP08
FDI_TXP18
FDI_TXP28
FDI_TXP38
FDI_TXP48
FDI_TXP58
FDI_TXP68
FDI_TXP78
FDI_FSYNC08
FDI_FSYNC18
FDI_INT8
FDI_LSYNC08
FDI_LSYNC18
eDP_COMP
INT_eDP_HPD_Q
FDI_FSYNC0
FDI_FSYNC1
FDI_INT
FDI_LSYNC0
FDI_LSYNC1
B27
B25
A25
B24
B28
B26
A24
B23
G21
E22
F21
D21
G22
D22
F20
C21
A21
H19
E19
F18
B21
C20
D18
E17
A22
G19
E20
G18
B20
C19
D19
F17
J18
J17
H20
J19
H17
A18
A17
B16
C15
D15
C17
F16
C16
G15
C18
E16
D16
F15
U28A
U28A
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC
eDP_COMPI O
eDP_ICOMPO
eDP_HPD
eDP_AUX
eDP_AUX#
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
CPU-989P-rPGA
CPU-989P-rPGA
J22
PEG_ICOMPI
J21
PEG_ICOMPO
H22
PEG_RCOMPO
K33
PEG_RX#[0]
M35
PEG_RX#[1]
L34
PEG_RX#[2]
J35
PEG_RX#[3]
J32
PEG_RX#[4]
H34
PEG_RX#[5]
H31
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
G33
G30
F35
E34
E32
D33
D31
B33
C32
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
IMVP_PW RGD8,36
DMI
DMI
Intel(R) FDI
Intel(R) FDI
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
eDP
eDP
PEG_COM P
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN1 0
PEG_RXN1 1
PEG_RXN1 2
PEG_RXN1 3
PEG_RXN1 4
PEG_RXN1 5
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
PEG_TXN0_ C
C207 EV@0.1U/10V_4C207 EV@0.1U/10V_4
PEG_TXN1_ C PEG_TXN1
C231 EV@0.1U/10V_4C231 EV@0.1U/10V_4
PEG_TXN2_ C
C206 EV@0.1U/10V_4C206 EV@0.1U/10V_4
PEG_TXN3_ C
C229 EV@0.1U/10V_4C229 EV@0.1U/10V_4
PEG_TXN4_ C
C204 EV@0.1U/10V_4C204 EV@0.1U/10V_4
PEG_TXN5_ C
C227 EV@0.1U/10V_4C227 EV@0.1U/10V_4
PEG_TXN6_ C
C201 EV@0.1U/10V_4C201 EV@0.1U/10V_4
PEG_TXN7_ C
C225 EV@0.1U/10V_4C225 EV@0.1U/10V_4
PEG_TXN8_ C
C200 EV@0.1U/10V_4C200 EV@0.1U/10V_4
PEG_TXN9_ C
C223 EV@0.1U/10V_4C223 EV@0.1U/10V_4
PEG_TXN10_C
C198 EV@0.1U/10V_4C198 EV@0.1U/10V_4
PEG_TXN11_C
C221 EV@0.1U/10V_4C221 EV@0.1U/10V_4
PEG_TXN12_C
C195 EV@0.1U/10V_4C195 EV@0.1U/10V_4
PEG_TXN13_C
C219 EV@0.1U/10V_4C219 EV@0.1U/10V_4
PEG_TXN14_C
C194 EV@0.1U/10V_4C194 EV@0.1U/10V_4
PEG_TXN15_C
C217 EV@0.1U/10V_4C217 EV@0.1U/10V_4
PEG_TXP0_C
C208 EV@0.1U/10V_4C208 EV@0.1U/10V_4
PEG_TXP1_C
C230 EV@0.1U/10V_4C230 EV@0.1U/10V_4
PEG_TXP2_C
C205 EV@0.1U/10V_4C205 EV@0.1U/10V_4
PEG_TXP3_C
C228 EV@0.1U/10V_4C228 EV@0.1U/10V_4
PEG_TXP4_C
C203 EV@0.1U/10V_4C203 EV@0.1U/10V_4
PEG_TXP5_C
C226 EV@0.1U/10V_4C226 EV@0.1U/10V_4
PEG_TXP6_C
C202 EV@0.1U/10V_4C202 EV@0.1U/10V_4
PEG_TXP7_C
C224 EV@0.1U/10V_4C224 EV@0.1U/10V_4
PEG_TXP8_C
C199 EV@0.1U/10V_4C199 EV@0.1U/10V_4
PEG_TXP9_C
C222 EV@0.1U/10V_4C222 EV@0.1U/10V_4
PEG_TXP10_ C
C197 EV@0.1U/10V_4C197 EV@0.1U/10V_4
PEG_TXP11_ C
C220 EV@0.1U/10V_4C220 EV@0.1U/10V_4
PEG_TXP12_ C
C196 EV@0.1U/10V_4C196 EV@0.1U/10V_4
PEG_TXP13_ C
C218 EV@0.1U/10V_4C218 EV@0.1U/10V_4
PEG_TXP14_ C
C193 EV@0.1U/10V_4C193 EV@0.1U/10V_4
PEG_TXP15_ C
C216 EV@0.1U/10V_4C216 EV@0.1U/10V_4
0.22uF AC coupling Caps for PCIE GEN1/2/3
PM_THRM TRIP#
2
1 3
PEG_RXN[0..15] 16
PEG_RXP[ 0..15] 16
3
Q4
FDV301NQ4FDV301N
1
R162
R162
1K_4
1K_4
2
Q3
MMBT3904Q3MMBT3904
PEG_TXN0
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
+1.05V_VTT
PEG_TXN[0..15] 16
PEG_TXP[0 ..15] 16
SYS_SHDN# 35
H_SNB_IVB#9
H_PROCHOT#31,36
PM_THRM TRIP#11
+1.05V_VTT
EC_PECI11, 31
SNB_IVB# N.A at SNB EDS #27637 0.7v1
TP12TP12
TP9TP9
H_PROCHOT#
R152 56/J_4R152 56/J_4
PM_SYNC8
H_PWRGOOD11
74LVC1G07GW
74LVC1G07GW
GND3OUT
2
IN
1
VCC5NC
U8
U8
R157 *1.5K/F_4R157 *1.5K/F_4
R159 0/J_4R159 0/J_4
C692 *0.1U/10V_4C692 *0.1U/10V_4
R132 0/J_4R132 0/J_4
R154 10K/J_4R154 10K/J_4
R122 75/J_4R122 75/J_4
CPU_PLTRST#
4
+3V_S5
PLTRST# 10,16,26,28,31,32
Sandy Bridge Processor (CLK,MISC,JTAG)
SKTOCC#
TP_CATERR#
H_PROCHOT#_R
PM_SYNC_R
H_PWRGOOD_R
PM_DRAM_PWRGD_Q_R
R155
R155
43/J_4
43/J_4
C209
C209
0.1U/10V_4
0.1U/10V_4
CPU_PLTRST#_R
SYS_PWROK8,31
PM_DRAM_PWRGD8
C26
AN34
AL33
AN33
AL32
AN32
AM34
AP33
AR33
R156
R156
*750/F_4
*750/F_4
V8
U28B
U28B
PROC_SELECT#
SKTOCC#
CATERR#
PECI
PROCHOT#
THERMTRIP#
PM_SYNC
UNCOREPWRGOOD
SM_DRAMPWROK
RESET#
CPU-989P-rPGA
CPU-989P-rPGA
PM_DRAM_PWRGD_R
R182
R182
0/J_4
0/J_4
R177
R177
*3K/F_4
*3K/F_4
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
2
1
DPLL_REF_CLK
DPLL_REF_CLK#
CLOCKS
CLOCKS
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
DDR3
MISC
DDR3
MISC
JTAG & BPM
JTAG & BPM
+3V_S5
C297
C297
0.1U/10V_4
0.1U/10V_4
U11
U11
4
TC7SH08
TC7SH08
3 5
A28
BCLK
A27
BCLK#
A16
A15
R8
AK1
A5
A4
AP29
PRDY#
AP27
PREQ#
AR26
TCK
AR27
TMS
AP30
TRST#
AR28
TDI
AP26
TDO
AL35
DBR#
AT28
BPM#[0]
AR29
BPM#[1]
AR30
BPM#[2]
AT30
BPM#[3]
AP32
BPM#[4]
AR31
BPM#[5]
AT31
BPM#[6]
AR32
BPM#[7]
PM_DRAM_PWRGD_Q
R186 *39/J_4R186 *39/J_4
CLK_CPU_BCLKP_R
CLK_CPU_BCLKN_R
CLK_DPLL_SSCLKP_R
CLK_DPLL_SSCLKN_R
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
XDP_PRDY #
XDP_PREQ #
XDP_TCLK
XDP_TMS
XDP_TRST #
XDP_TDI _R
XDP_TDO
XDP_DBR ST#
XDP_BPM0
XDP_BPM1
XDP_BPM2
XDP_BPM3
XDP_BPM4
XDP_BPM5
XDP_BPM6
XDP_BPM7
+1.5V_CPU
R413
R413
0X2
0X2
3
1
R415
R415
SPI@0X2
SPI@0X2
3
1
Zď
R414 *SPE@1K/J_4R414 *SPE@1K/J_4
R417 *SPE@1K/J_4R417 *SPE@1K/J_4
ZĐ
R427 140/F_4R427 140/F_4
R180 25.5/F_4R180 25.5/F_4
R181 200/F_4R181 200/F_4
TP14TP14
TP20TP20
TP24TP24
TP17TP17
TP3TP3
TP6TP6
TP21TP21
XDP_DBR ST# 8
TP16TP16
TP19TP19
TP15TP15
TP13TP13
TP11TP11
TP10TP10
TP7TP7
TP8TP8
R183
R183
200/F_4
200/F_4
R179 130/F_4R179 130/F_4
3
1
Q7 *2N7002KQ7 *2N7002K
2
4
2
4
2
ZĂ
CPU_DRAMRST# 5
PM_DRAM_PWRGD_Q_R
CLK_CPU_BCLKP 10
CLK_CPU_BCLKN 10
CLK_DPLL_SSCLKP 10
CLK_DPLL_SSCLKN 10
ZĂ
Zď
ZĐ
EV UMA
E
ϭ<ͲŽŚŵ
ϭ<ŽŚŵ
+1.05V_VTT
Terminate DPLL_REF_SSCLK to GND and DPLL_REF_SSCLK# to
VCCP on Processor if motherboard only supports external
graphics.
DG 1.0 : SM_RCOMP[1] value to 25.5
(CS02552FB16)from 26 due to
component selection issue
CRB 1.0 change R480 to 25.5/F
MAINON_ON_G 6,41
ϬŽŚŵ
E
E
FDI Disabling (Discrete Only) DP & PEG Compensation
FDI_INT
R421 *EV@0/J_4R421 *EV@0/J_4
R422 *EV@0/J_4R422 *EV@0/J_4
R418
R418
*EV@1K/F_4
*EV@1K/F_4
R420 *EV@0/J_4R420 *EV@0/J_4
R419
R419
*EV@1K/F_4
*EV@1K/F_4
A A
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
FDI_FSYNC can gang
all these 4
signals together
and tie them with
only one 1K
resistor to GND
(DG V0.5 Ch2.2.9).
5
R173 24.9/F_4R173 24.9/F_4
eDP_COMPIO and ICOMPO signals should
be shorted near balls and routed with
typical impedance <25 mohms
+1.05V_VTT+1.05V_VTT
R171 24.9/F_4R171 24.9/F_4
PEG_ICOMPI and RCOMPO signals should
be routed within 500 mils
typical impedance = 43 mohms
PEG_ICOMPO signals should
be routed within 500 mils
typical impedance = 14.5 mohms
4
PEG_COM PeDP_COMP
eDP Hot-plug
CAD Note: Place PU resistor within 2 inches of CPU
HPD disable
INT_eDP_HPD_Q
3
+1.05V_VTT
R172
R172
10K/J_4
10K/J_4
Processor pull-up(CPU)
H_PROCHOT#
R130 62/J_4R130 62/J_4
XDP_TDO
R165 51/J_4R165 51/J_4
XDP_TMS
R163 51/J_4R163 51/J_4
XDP_TDI _R
R160 51/J_4R160 51/J_4
XDP_PREQ #
R164 *51/J_4R164 *51/J_4
XDP_TCLK
R166 51/J_4R166 51/J_4
XDP_TRST #
R133 51/J_4R133 51/J_4
2
+1.05V_VTT
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Nu mb e r Rev
Monday, September 27, 2010
Monday, September 27, 2010
Monday, September 27, 2010
Date: Sheet of
Date: Sheet of
Date: Sheet
PROJECT :
Sandy Bridge 1/4
Sandy Bridge 1/4
Sandy Bridge 1/4
1
FH5
FH5
FH5
of
441
441
441
1A
1A
1A
5
4
3
2
1
Sandy Bridge Processor (DDR3)
U28C
U28C
M_A_DQ[63:0]14
D D
C C
B B
M_A_BS#014
M_A_BS#114
M_A_BS#214
M_A_CAS#14
M_A_RAS#14
M_A_WE#14
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M10
AG6
AG5
AH5
AH6
AH8
AH9
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
AD9
C5
SA_DQ[0]
D5
SA_DQ[1]
D3
SA_DQ[2]
D2
SA_DQ[3]
D6
SA_DQ[4]
C6
SA_DQ[5]
C2
SA_DQ[6]
C3
SA_DQ[7]
F10
SA_DQ[8]
F8
SA_DQ[9]
G10
SA_DQ[10]
G9
SA_DQ[11]
F9
SA_DQ[12]
F7
SA_DQ[13]
G8
SA_DQ[14]
G7
SA_DQ[15]
K4
SA_DQ[16]
K5
SA_DQ[17]
K1
SA_DQ[18]
J1
SA_DQ[19]
J5
SA_DQ[20]
J4
SA_DQ[21]
J2
SA_DQ[22]
K2
SA_DQ[23]
M8
SA_DQ[24]
N10
SA_DQ[25]
N8
SA_DQ[26]
N7
SA_DQ[27]
SA_DQ[28]
M9
SA_DQ[29]
N9
SA_DQ[30]
M7
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
AK6
SA_DQ[34]
AK5
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
AJ5
SA_DQ[38]
AJ6
SA_DQ[39]
AJ8
SA_DQ[40]
AK8
SA_DQ[41]
AJ9
SA_DQ[42]
AK9
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
AL9
SA_DQ[46]
AL8
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
V6
SA_BS[2]
AE8
SA_CAS#
SA_RAS#
AF9
SA_WE#
RSVD_TP[10]
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]
SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AB6
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7
M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_CLKP0 14
M_A_CLKN0 14
M_A_CKE0 14
M_A_CLKP1 14
M_A_CLKN1 14
M_A_CKE1 14
M_A_CS#0 14
M_A_CS#1 14
M_A_ODT0 14
M_A_ODT1 14
M_A_DQSN[7:0] 14
M_A_DQSP[7:0] 14
M_A_A[15:0] 14
M_B_DQ[63:0]15
M_B_BS#015
M_B_BS#115
M_B_BS#215
M_B_CAS#15
M_B_RAS#15
M_B_WE#15
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AM5
AM6
AR3
AN3
AN2
AN1
AN9
AN8
AR6
AR5
AR9
AJ11
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA10
D10
K10
AP3
AP2
AP5
AT5
AT6
AP6
AT8
AT9
AA9
AA7
AB8
AB9
J10
C9
A7
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K9
J9
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
R6
U28D
U28D
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
AE2
SB_CLK[0]
AD2
SB_CLK#[0]
R9
SB_CKE[0]
AE1
SB_CLK[1]
AD1
SB_CLK#[1]
R10
SB_CKE[1]
SB_CS#[0]
SB_CS#[1]
SB_ODT[0]
SB_ODT[1]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
M_B_DQSN0
M_B_DQSN1
M_B_DQSN2
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7
M_B_DQSP0
M_B_DQSP1
M_B_DQSP2
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
RSVD_TP[17]
RSVD_TP[18]
RSVD_TP[19]
RSVD_TP[20]
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
M_B_CLKP0 15
M_B_CLKN0 15
M_B_CKE0 15
M_B_CLKP1 15
M_B_CLKN1 15
M_B_CKE1 15
M_B_CS#0 15
M_B_CS#1 15
M_B_ODT0 15
M_B_ODT1 15
M_B_DQSN[7:0] 15
M_B_DQSP[7:0] 15
M_B_A[15:0] 15
05
CPU-989P-rPGA
CPU-989P-rPGA
+1.5V_SUS
02/25 Add 1K ohm
A A
DRAMRST_CNTRL_PCH10
5
R300 1K/F_4R300 1K/F_4
#PGU 0.71 440484
R298
R298
1K/F_4
1K/F_4
R312 0/J_4R312 0/J_4
4
R303 *0/J_4R303 *0/J_4
3
Q11
Q11
2N7002K
2N7002K
2
C427
C427
0.047U/10V_4
0.047U/10V_4
1
R311
R311
4.99K/F_4
4.99K/F_4
CPU_DRAMRST# 4DDR3_DRAMRST#14,15
3
CPU-989P-rPGA
CPU-989P-rPGA
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Monday, September 27, 2010
Monday, September 27, 2010
Monday, September 27, 2010
Date: Sheet
Date: Sheet of
2
Date: Sheet of
PROJECT :
Sandy Bridge 2/4
Sandy Bridge 2/4
Sandy Bridge 2/4
FH5
FH5
FH5
1A
1A
1A
of
541
541
1
541
5
22uF_8 x7 Socket TOP cavity
22uF_8 x5 Socket BOT cavity
22uF_8 x2 Socket TOP cavity (no stuff)
22uF_8 x5 Socket BOT cavity (no stuff)
330uF_7343 x2
Sandy Bridge Processor (POWER)
+VCC_CORE
+
+
C620
C620
470u/2V_7343
470u/2V_7343
SNB: 55A
C257
C257
22U/6.3VS_8
22U/6.3VS_8
C612
C612
22U/6.3VS_8
22U/6.3VS_8
C622
C622
22U/6.3VS_8
22U/6.3VS_8
C268
C268
22U/6.3VS_8
22U/6.3VS_8
C274
C274
*22U/6.3VS_8
*22U/6.3VS_8
C269
C269
22U/6.3VS_8
22U/6.3VS_8
C585
C585
22U/6.3VS_8
22U/6.3VS_8
C232
C232
*22U/6.3VS_8
*22U/6.3VS_8
C621
C621
22U/6.3VS_8
22U/6.3VS_8
C581
C581
22U/6.3VS_8
22U/6.3VS_8
+
+
C616
C616
470u/2V_7343
470u/2V_7343
C256
C256
22U/6.3VS_8
22U/6.3VS_8
C258
C258
22U/6.3VS_8
22U/6.3VS_8
C250
C250
22U/6.3VS_8
22U/6.3VS_8
C613
C613
22U/6.3VS_8
22U/6.3VS_8
C264
C264
22U/6.3VS_8
22U/6.3VS_8
C273
C273
22U/6.3VS_8
22U/6.3VS_8
C251
C251
22U/6.3VS_8
22U/6.3VS_8
C624
C624
22U/6.3VS_8
22U/6.3VS_8
C234
C234
22U/6.3VS_8
22U/6.3VS_8
C270
C270
*22U/6.3VS_8
*22U/6.3VS_8
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
D D
+
+
C247
C247
470u/2V_7343
470u/2V_7343
C265
C265
22U/6.3VS_8
22U/6.3VS_8
C623
C623
22U/6.3VS_8
22U/6.3VS_8
C263
C263
22U/6.3VS_8
22U/6.3VS_8
C272
C272
22U/6.3VS_8
C C
B B
A A
22U/6.3VS_8
C252
C252
22U/6.3VS_8
22U/6.3VS_8
C582
C582
22U/6.3VS_8
22U/6.3VS_8
C266
C266
22U/6.3VS_8
22U/6.3VS_8
C583
C583
*22U/6.3VS_8
*22U/6.3VS_8
C233
C233
22U/6.3VS_8
22U/6.3VS_8
C584
C584
22U/6.3VS_8
22U/6.3VS_8
22uF_8 x8 Socket TOP cavity
22uF_8 x10 Socket BOT cavity
22uF_8 x8 Socket TOP edge
470uF_7343 x3
3/26 DB change 10U FP to 0805.
U28F
U28F
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
CPU-989P-rPGA
CPU-989P-rPGA
POWER
POWER
CORE SUPPLY
CORE SUPPLY
4
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
PEG AND DDR
PEG AND DDR
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDALERT#
VIDSCLK
VIDSOUT
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
VSSIO_SENSE
SENSE LINES SVID
SENSE LINES SVID
SPI@ For Optimus & UMA
SPE@ For Pure Dis.
SP@ For special setting
+1.05V_VTT
+
+
+
+
C634
C634
C635
C635
*330U/2V_7343
*330U/2V_7343
330u/2V_7343
330u/2V_7343
C629
C629
22U/6.3VS_8
22U/6.3VS_8
C618
C618
22U/6.3VS_8
22U/6.3VS_8
C47
C47
*22U/6.3VS_8
*22U/6.3VS_8
C26
C26
22U/6.3VS_8
22U/6.3VS_8
C625
C625
*22U/6.3VS_8
*22U/6.3VS_8
C282
C282
*22U/6.3VS_8
*22U/6.3VS_8
+1.05V_VTT_40
R146 0/J_4R146 0/J_4
R145 0/J_4R145 0/J_4
R409 0/J_4R409 0/J_4
R410 0/J_4R410 0/J_4
SNB: 8.5A
R416 *0_shortR 416 *0_short
C281
C281
22U/6.3VS_8
22U/6.3VS_8
C280
C280
22U/6.3VS_8
22U/6.3VS_8
C628
C628
22U/6.3VS_8
22U/6.3VS_8
C27
C27
*22U/6.3VS_8
*22U/6.3VS_8
C626
C626
22U/6.3VS_8
22U/6.3VS_8
C286
C286
22U/6.3VS_8
22U/6.3VS_8
+1.05V_VTT
R124 100/J_4R124 100/J_4
R123 100/J_4R123 100/J_4
VCCP_SENSE 37
VSSP_SENSE 37
MAIND35,38,41
C619
C619
22U/6.3VS_8
22U/6.3VS_8
C563
C563
22U/6.3VS_8
22U/6.3VS_8
C627
C627
22U/6.3VS_8
22U/6.3VS_8
C562
C562
*22U/6.3VS_8
*22U/6.3VS_8
C285
C285
22U/6.3VS_8
22U/6.3VS_8
+VCC_CORE
MAIND
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
AJ29
AJ30
AJ28
AJ35
AJ34
B10
A10
H_CPU_SVIDALRT#
H_CPU_SVIDCLKH_CPU_SVIDCLK
H_CPU_SVIDDAT
CPU VCCPL
SNB 45W:3A
330uF/7mohm x 1
10uF x 1
1uF x 2
C698
C698
*0.1U/10V_4
*0.1U/10V_4
VCCSENSE 36
VSSSENSE 36
R428 *0/J_8R428 *0/J_8
3
2
Q25
Q25
2N7002K
2N7002K
3
+VDDR_REF_CPU+SMDDR_VREF
1
C699
C699
*0.1U/10V_4
*0.1U/10V_4
+VDDR_REF_CPU
R429
R429
100K/J_4
100K/J_4
CPU VGT
SNB 45W:22A
470uF/4mohm x 2
22uF x 12
+VCC_GFX
SPI@330U/2V_7343
SPI@330U/2V_7343
SPI@22U/6.3V_8
SPI@22U/6.3V_8
SPI@22U/6.3V_8
SPI@22U/6.3V_8
SPI@22U/6.3V_8
SPI@22U/6.3V_8
*SPI@10U/6.3V_6
*SPI@10U/6.3V_6
+1.8V
VR_SVID _CLK
VR_SVID _DATA
VR_SVID _ALER T#
C697
C697
*0.1U/10V_4
*0.1U/10V_4
+
+
C288
C288
SPI@330U/2V_7343
SPI@330U/2V_7343
C617
C617
C260
C260
SPI@10U/6.3V_6
SPI@10U/6.3V_6
C277
C277
C283
C283
SPI@22U/6.3V_8
SPI@22U/6.3V_8
C271
C271
C261
C261
SPI@10U/6.3V_6
SPI@10U/6.3V_6
22uF (Reserved)
C267
C267
C275
C275
*SPI@22U/6.3V_8
*SPI@22U/6.3V_8
ZĂ
R174 *SPE@0/J_4R174 *SPE@0/J_4
ZĂ ϬŽŚŵsE
C303
C303
C301
C301
10U/6.3V_6
10U/6.3V_6
1U/6.3V_4
1U/6.3V_4
2
Sandy Bridge Processor (GRAPHIC POWER)
POWER
R120
R120
75/J_4
75/J_4
R126 0/J_4R126 0/J_4
POWER
VSSAXG_SENSE
SENSE
LINES
SENSE
LINES
VREFMISC
VREFMISC
GRAPHICS
GRAPHICS
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
SA RAIL
SA RAIL
1.8V RAIL
1.8V RAIL
SVID CLK
+1.05V_VTT
Close to VR
R127
R127
54.9/F_4
54.9/F_4
SVID DATA
Close to VR
R125
R125
130/F_4
130/F_4
SVID ALERT
VAXG_SENSE
SM_VREF
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
VCCSA_SENSE
FC_C22
VCCSA_VID1
VR_SVID _CLK 36
VR_SVID _DATA 36
VR_SVID _ALER T# 36
AK35
AK34
AL1
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
M27
M26
L26
J26
J25
J24
H26
H25
H23
C22
C24
U28G
U28G
AT24
VAXG1
AT23
VAXG2
AT21
+
+
+
+
C307
C307
C300
C300
*SPI@330U/2V_7343
*SPI@330U/2V_7343
C254
C254
C615
C615
SPI@22U/6.3V_8
SPI@22U/6.3V_8
SPI@10U/6.3V_6
SPI@10U/6.3V_6
C253
C253
C278
C278
SPI@22U/6.3V_8
SPI@22U/6.3V_8
SPI@22U/6.3V_8
SPI@22U/6.3V_8
C259
C259
C262
C262
SPI@10U/6.3V_6
SPI@10U/6.3V_6
SPI@22U/6.3V_8
SPI@22U/6.3V_8
C284
C284
C255
C255
*SPI@22U/6.3V_8
*SPI@22U/6.3V_8
*SPI@22U/6.3V_8
*SPI@22U/6.3V_8
hD
+
+
C654
C654
C302
C302
*330U/2V_7343
*330U/2V_7343
1U/6.3V_4
1U/6.3V_4
Layout note: need routing
together and ALERT need
between CLK and DATA
H_CPU_SVIDCLK
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
B6
A6
A2
R149 0/J_4R149 0/J_4
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
VCCPLL1
VCCPLL2
VCCPLL3
CPU-989P-rPGA
CPU-989P-rPGA
Place PU resistor close to CPU
+1.05V_VTT +1.05V_VTT
R119
R119
130/F_4
H_CPU_SVIDDAT
Place PU resistor close to CPU
H_CPU_SVIDALRT#
130/F_4
R148 43/J_4R148 43/J_4
R147 0/J_4R147 0/J_4
+1.05V_VTT
1
TP4TP4
R150
R150
R128 100/J_4R128 100/J_4
0/J_4
0/J_4
0/J_4
0/J_4
R129 100/J_4R129 100/J_4
R151
R151
TP5TP5
10 mil
+VDDR_REF_CPU
CAD Note: +VDDR_REF_CPU should
have 10 mil trace width
R169 0/J_4R169 0/J_4
H_FC_C22
+VDDR_REF_CPU
C292
C292
C298
C298
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
C295
C295
C306
C306
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
C249
C249
C248
C248
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
R170 10K/J_4R170 10K/J_4
VCCSA_SEL 40
MAIND
MAINON_ON_G4,41
10U/6.3V_6
10U/6.3V_6
+
+
C299
C299
*330U/2V_7343
*330U/2V_7343
10U/6.3V_6
10U/6.3V_6
VCCSA_SENSE 40
4.5A
JP5
JP5
*SHORT PAD
*SHORT PAD
8
7
5
+VCC_GFX
CPU MCH
SNB 45W: 5A
330uF/6mohm x 1
10uF x 6
C293
C293
C294
C294
10U/6.3V_6
10U/6.3V_6
C304
C304
22U/6.3V_8
22U/6.3V_8
22uF (Reserved)
VCCSA
+
+
C565
C565
*330U/2V_7343
*330U/2V_7343
C614
C614
CPU SA
SNB 45W: 6A
330uF/7mohm x 1
10uF x 3
+1.5V_CPU+1.5V_SUS
12
1
2
36
Q5
4
AO4496Q5AO4496
C296
C296
*470P/ 50V_4
*470P/ 50V_4
2
06
VCC_AXG_SENSE 36
VSS_AXG_SENSE 36
+1.5V_CPU
C305
C305
22U/6.3V_8
22U/6.3V_8
R187
R187
220/J_8
220/J_8
3
Q6
DMN601K-7Q6DMN601K-7
1
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Nu mb e r Rev
Monday, September 27, 2010
Monday, September 27, 2010
Monday, September 27, 2010
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet
PROJECT :
Sandy Bridge 3/4
Sandy Bridge 3/4
Sandy Bridge 3/4
1
FH5
FH5
FH5
of
641
641
641
1A
1A
1A
5
4
3
2
1
Sandy Bridge Processor (GND)
U28I
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
K35
K32
K29
K26
H33
H30
H27
H24
H21
H18
H15
H13
H10
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29
U28I
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
L33
VSS188
L30
VSS189
L27
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
VSS196
L2
VSS197
L1
VSS198
VSS199
VSS200
VSS201
VSS202
J34
VSS203
J31
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
H9
VSS214
H8
VSS215
H7
VSS216
H6
VSS217
H5
VSS218
H4
VSS219
H3
VSS220
H2
VSS221
H1
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
SMDDR_VREF_DQ0_M314
SMDDR_VREF_DQ1_M315
Voltage selection for VCCIO:
this pin must be pulled high
on the motherboard
On CRB
H_SNB_IVB#_PWRCTRL = low, 1.0V
H_SNB_IVB#_PWRCTRL = high/NC, 1.05V
Sandy Bridge Processor (RESERVED, CFG)
U28E
U28E
3/26 Remove XDP
R176
R176
*1K/J_4
*1K/J_4
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
R178
R178
*1K/J_4
*1K/J_4
TP22TP22
TP18TP18
TP23TP23
02/20 Add for Pre-ES1
TP25TP25
AK28
CFG[0]
AK29
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
B4
RSVD6
D1
RSVD7
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
A19
VCCIO_SEL
J15
RSVD27
CPU-989P-rPGA
CPU-989P-rPGA
RESERVED
RESERVED
VCC_DIE_SENSE
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD54
RSVD55
RSVD56
RSVD57
RSVD58
KEY
L7
AG7
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AH27
AN35
AM35
AT2
AT1
AR1
B1
07
For rPGA socket, RSVD59 pin sh ould be left NC
U28H
U28H
AT35
VSS1
AT32
VSS2
AT29
VSS3
AT27
VSS4
AT25
VSS5
AT22
VSS6
AT19
VSS7
AT16
VSS8
AT13
VSS9
D D
C C
B B
AT10
AR25
AR22
AR19
AR16
AR13
AR10
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AJ25
AT7
AT4
AT3
AR7
AR4
AR2
AP7
AP4
AP1
AN7
AN4
AL7
AL4
AL2
AK7
AK4
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
CPU-989P-rPGA
CPU-989P-rPGA
CPU-989P-rPGA
Processor Strapping
The CFG signals have a default v alue of '1' if not terminated on the board.
10
CFG2
(PEG Static Lane Reversal)
A A
CFG3
PEG Static x4 Lane
CFG4
(DP Presence Strap)
CFG7
(PEG Defer Training)
Normal Operation Lane Reversed
Normal Operation Lane Reversed
Disable; No physical DP attached to eDP
PEG train immediately following
xxRESETB de assertion
5
CPU-989P-rPGA
Enable; An ext DP device is connected to eDP
PEG wait for BIOS training
4
CFG2
CFG4
CFG7
R167 *1K/F_4R167 *1K/F_4
R131 *1K/F_4R131 *1K/F_4
3
CFG5
CFG6
R158 *1K/F_4R158 *1K/F_4R168 1K/F_4R168 1K/F_4
R153 *1K/F_4R153 *1K/F_4
CFG[6:5] (PCIE Port Bifurcation S trap s)
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Monday, September 27, 2010
Date: Sheet of
Monday, September 27, 2010
Date: Sheet of
2
Monday, September 27, 2010
PROJECT :
Sandy Bridge 4/4
Sandy Bridge 4/4
Sandy Bridge 4/4
FH5
FH5
FH5
741
741
1
741
1A
1A
1A
of
5
4
3
2
1
R317
R317
*20K/J_4
*20K/J_4
08
INT. HDMI
INT_HDMI_HPD 24
Cougar Point (DMI,FDI,PM)
U30C
U30C
DMI_COMP
SUSACK#_R
SYS_PWROK_RSYS_PWROK
APWROK_R
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN#/SUSPWRDNACK/GPIO30
E20
PWRBTN#
H20
ACPRESENT / GPIO31
E10
BATLOW# / GPIO72
A10
RI#
CougarPoint_R1P0
CougarPoint_R1P0
DMI
FDI
DMI
FDI
+3V
CLKRUN# / GPIO32
+3V_S5
SUS_STAT# / GPIO61
+3V_S5
SUSCLK / GPIO62
+3V_S5
SLP_S5# / GPIO63
System Power Management
System Power Management
DSW
+3V_S5
+3V_S5
SLP_LAN# / GPIO29
DMI_RXN04
DMI_RXN14
DMI_RXN24
DMI_RXN34
DMI_RXP04
D D
XDP_DBRST#4
C C
EC_PWROK31,33
PM_DRAM_PWRGD4
RSMRST#31
EC_PWRBTN#31
B B
DMI_RXP14
DMI_RXP24
DMI_RXP34
DMI_TXN04
DMI_TXN14
DMI_TXN24
DMI_TXN34
DMI_TXP04
DMI_TXP14
DMI_TXP24
DMI_TXP34
R535 49.9/F_4R535 49.9/F_4
+1.05V_PCH
R538 750/F_4R538 750/F_4
SUS_PWR_ACK
XDP_DBRST#
EC_PWROK EC_PWROK_R
PM_DRAM_PWRGD
RSMRST#
SUS_PWR_ACK
AC_PRESENT
PM_BATLOW#
PM_RI#
R207 *0/J_4R207 *0/J_4
R205 0/J_4R205 0/J_4
R201 *0/J_4R201 *0/J_4
R202 0/J_4R202 0/J_4
R200 0/J_4R200 0/J_4
R533 0/J_4R533 0/J_4
T11T11
EC_PWRBTN#_R
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
DPWROK
SLP_S4#
+3V_S5
SLP_S3#
SLP_SUS#
PMSYNCH
FDI_IN T
WAKE#
SLP_A#
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
SLP_SUS#
DSWVREN
R217 0/J_4R217 0/J_4
PCIE_WAKE#
CLKRUN#
T13T13
T12T12
SLP_LAN#
T15T15
T14T14
T40T40
FDI_TXN0 4
FDI_TXN1 4
FDI_TXN2 4
FDI_TXN3 4
FDI_TXN4 4
FDI_TXN5 4
FDI_TXN6 4
FDI_TXN7 4
FDI_TXP0 4
FDI_TXP1 4
FDI_TXP2 4
FDI_TXP3 4
FDI_TXP4 4
FDI_TXP5 4
FDI_TXP6 4
FDI_TXP7 4
FDI_INT 4
FDI_FSYNC0 4
FDI_FSYNC1 4
FDI_LSYNC0 4
FDI_LSYNC1 4
RSMRST#
DPWROK
PCIE_WAKE# 26,32
CLKRUN# 31
SUS_STAT#
PCH_SUSCLK 31
SLP_S4# 31,32
SLP_S3# 31,32
PM_SYNC 4
INT_LVDS_BLON33
INT_LVDS_VDDEN33
INT_LVDS_BRIGHT33
INT_EDIDCLK33
INT_EDIDDAT33
+3V
INT_TXLCLKOUTN33
INT_TXLCLKOUTP33
INT_TXLOUTN033
INT_TXLOUTN133
INT_TXLOUTN233
INT_TXLOUTP033
INT_TXLOUTP133
INT_TXLOUTP233
R place close to PCH
R481 150/F_4R481 150/F_4
R485 150/F_4R485 150/F_4
R490 150/F_4R490 150/F_4
INT_CRT_HSYNC24
INT_CRT_VSYNC24
SYNC RS
33ohm for Direct Connect
20ohm for Dock Support
20ohm for Switchable Graphics Device Down Topology
10ohm for Switchable Graphics Dock Support
INT_CRT_BLU
INT_CRT_GRE
INT_CRT_RED
INT_CRT_BLU24
INT_CRT_GRE24
INT_CRT_RED24
INT_DDCCLK24
INT_DDCDAT24
R473 33/F_4R473 33/F_4
R478 33/F_4R478 33/F_4
INT_EDIDCLK
INT_EDIDDAT
R263 2.2K/J_4R263 2.2K/J_4
R262 2.2K/J_4R262 2.2K/J_4
R285 2.37K/F_4R285 2.37K/F_4
T16T16
INT_TXLCLKOUTN
INT_TXLCLKOUTP
INT_TXLOUTN0
INT_TXLOUTN1
INT_TXLOUTN2
INT_TXLOUTP0
INT_TXLOUTP1
INT_TXLOUTP2
INT_CRT_BLU
INT_CRT_GRE
INT_CRT_RED
INT_CRT_HSYNC_R
INT_CRT_VSYNC_R
Cougar Point (LVDS,DDI)
U30D
U30D
J47
DAC_IREF
R264
R264
1K/F_4
1K/F_4
AF37
AF36
AE48
AE47
AK39
AK40
AN48
AM47
AK47
AJ48
AN47
AM49
AK49
AJ47
AF40
AF39
AH45
AH47
AF49
AF45
AH43
AH49
AF47
AF43
M45
P45
T40
K47
T45
P39
N48
P49
T49
T39
M40
M47
M49
T43
T42
L_BKLTEN
L_VDD_EN
L_BKLTCTL
L_DDC_CLK
L_DDC_DATA
L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG
LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
CougarPoint_R1P0
CougarPoint_R1P0
SDVO_TVCLKINN
SDVO_CTRLDATA
LVDS
LVDS
DDPC_CTRLDATA
Digital Display Interface
Digital Display Interface
DDPD_CTRLDATA
CRT
CRT
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_INTN
SDVO_INTP
SDVO_CTRLCLK
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_CTRLCLK
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
INT_HDMI_TXDN2
AV42
INT_HDMI_TXDP2
AV40
INT_HDMI_TXDN1
AV45
INT_HDMI_TXDP1
AV46
INT_HDMI_TXDN0
AU48
INT_HDMI_TXDP0
AU47
INT_HDMI_TXCN
AV47
INT_HDMI_TXCP
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
INT_HDMI_HPD_Q
INT_HDMI_HPD_Q
R290
R290
*100K/J_4
*100K/J_4
R316 0/J_4R316 0/J_4
+3V
R314
R314
*1M/F_4
*1M/F_4
2
1
INT_HDMI_SCL 24
INT_HDMI_SDA 24
INT_HDMI_TXDN2 24
INT_HDMI_TXDP2 24
INT_HDMI_TXDN1 24
INT_HDMI_TXDP1 24
INT_HDMI_TXDN0 24
INT_HDMI_TXDP0 24
INT_HDMI_TXCN 24
INT_HDMI_TXCP 24
3
Q12
Q12
*2N7002K
*2N7002K
PCH Pull-high/low(CLG) System PWR_OK(CLG)
+3V
CLKRUN#
R484 8.2K/J_4R484 8.2K/J_4
XDP_DBRST#
R476 10K/J_4R476 10K/J_4 R221 8.2K/J_4R221 8.2K/J_4
R471 *1K/J_4R471 *1K/J_4
RSMRST#
R214 10K/J_4R214 10K/J_4
SYS_PWROK
R196 10K/J_4R196 10K/J_4
A A
PM_RI#
PM_BATLOW#
PCIE_WAKE#
SLP_LAN#
SUS_PWR_ACK
AC_PRESENT
PM_DRAM_PWRGD
DG 0.9 PU 200ohm to +3V_S5
DG 1.0 without DDR Power Gating
dno't PU to +3V_S5
5
R450 10K/J_4R450 10K/J_4
R449 10K/J_4R449 10K/J_4
R211 *10K/J_4R211 *10K/J_4
R208 10K/J_4R208 10K/J_4
R216 10K/J_4R216 10K/J_4
R454 200/F_4R454 200/F_4
+3V_S5
SYS_PWROK4,31
SYS_PWROK
4
U10
U10
4
TC7SH08
TC7SH08
+3V_S5
+3V_RTC
C291
C291
*0.1U/10V_4
*0.1U/10V_4
2
1
3 5
R185
R185
100K/J_4
100K/J_4
IMVP_PWRGD 4,36
EC_PWROK
DSWVREN
DEEP S4/S5 well
On Die DSW VR Enable
High = Enable (Default)
Low = Disable
R197
R197
330K/J_4
330K/J_4
R455
R455
*330K/J_4
*330K/J_4
3
DPWROK FOR DSW (Deep Sx Well )
PR174 *0/J_6PR174 *0/J_6
PD8
PD8
*RB500V-40
*RB500V-40
+3V_DSW
PQ43
PQ43
*DTC144EUA
*DTC144EUA
2
+3VPCU
+3V_S5
1 3
PR175
PR175
*10K/J_4
*10K/J_4
+3VPCU+3VPCU
PR176
PR176
*30.1K/J_4
*30.1K/J_4
3
PQ44
PQ44
2
*2N7002K
*2N7002K
1
add cap to timing tune
2
R425 *0/J_4R425 *0/J_4
PC130
PC130
*0.22U/6.3V_4
*0.22U/6.3V_4
DPWROK
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Monday, September 27, 2010
Monday, September 27, 2010
Monday, September 27, 2010
Date: Sheet of
Date: Sheet of
Date: Sheet
PROJECT :
Cougar Point 1/6
Cougar Point 1/6
Cougar Point 1/6
FH5
FH5
FH5
1
1A
1A
1A
of
841
841
841
5
RTC Circuitry(RTC)
20mils
R557 *0/J_6R557 *0/J_6
+3V_DSW
R558 0/J_6R558 0/J_6
+3VPCU
+3V_RTC_1
20MIL
R553
R553
1K/J_4
D D
1K/J_4
20MIL
CON9
CON9
1
1
2
2
AAA-BAT-054-K01
AAA-BAT-054-K01
bat-23_2-4_2
bat-23_2-4_2
RESET JUMP
RTC_RST#
C C
D16
D16
BAT54C
BAT54C
SRTC_RST#
G1
G1
*SHORT_ PAD
*SHORT_ PAD
+3V_RTC
R560 20K/J_4R560 20K/J_4
30mils
R559 20K/J_4R559 20K/J_4
C683
C683
1U/6.3V_4
1U/6.3V_4
(Near ROOM DOOR)
CL1
CL1_CL1
CL1_CL1
*PAD
*PAD
CL2
B-01
1 2
C684
C684
1U/6.3V_4
1U/6.3V_4
C682
C682
1U/6.3V_4
1U/6.3V_4
RTC_RST#
SRTC_RST#
HDA Bus(CLG)
ACZ_BITCLK30
ACZ_SYNC30
ACZ_RST#30
ACZ_SDOUT30
R230 33/J_4R230 33/J_4
R440 33/J_4R440 33/J_4
R247 33/J_4R247 33/J_4
R457 33/J_4R457 33/J_4
ACZ_BITCLK_R
ACZ_SYNC_R
ACZ_RST#_R
ACZ_SDOUT_R
PCH JTAG Debug (CLG)
B B
R472
R472
51/J_4
51/J_4
PCH_SPI_CS0#
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO
A A
R319 0_4R319 0_4
R318 0_4R318 0_4
R323 0_4R323 0_4
+3V_S5
R246
R246
210/F_4
210/F_4
R251
R251
100/F_4
100/F_4
R320 3.3K_4R320 3.3K_4
+3V
Vender
EON
Winbond
Socket
5
Modify for B test.
R242
R242
210/F_4
210/F_4
PCH_JTAG_TMS_R
PCH_JTAG_TDI_R
PCH_JTAG_TCK_R
R243
R243
100/F_4
100/F_4
PCH SPI ROM(CLG)
U13
U13
1
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
PCH_SPI1_SO_R
C443
C443
*22P/50V_4
*22P/50V_4
CE#
6
SCK
5
SI
2
SO
HOLD#
3
WP#
SPI Flash Socket
SPI Flash Socket
Size
P/N
4MB
AKE39FN0Q00 (EN25F32-100HIP)
AKE391P0N00 (W25Q32BVSSIG)
4MB
DG008000031
VDD
VSS
8
R322 3.3K_4R322 3.3K_4
7
4
C442
C442
0.1U/10V_4
0.1U/10V_4
+3V
4
PCH2(CLG)
C640 15p/50V_4C640 15p/50V_4
C639 15p/50V_4C639 15p/50V_4
Add MOSFET to separat e CODEC SYNC signal
R446 10K/J_4R446 10K/J_4
+5V
ACZ_SYNC_R ACZ_SYNC_Q
Change SIZE 8/24
14
23
Y3
32.768KHzY332.768KHz
+3V_RTC
2
1
3
Q262N7002K Q262N7002K
R228 1M/J_4R228 1M/J_4
SPKR30
ACZ_SDIN030
Flash Descriptor Security Override
Low = Enabled
GPIO33
High = Disabled
(Internal 20K/F pull high to +3V)
Note : GPIO33 is a signal used for Flash
Descriptor Security Override/ME Debug
Mode.This signal should be only asserted
lowthrough an external pull-down in
manufacturing or debug environments
ONLY.
3/26 Remove XDP
TP52TP52
R492 *10K/J_4R492 *10K/J_4
+3VPCU
PCH Strap Table
Pin Name
SPKR
GNT3# / GPIO55
INTVRMEN
GNT1# / GPIO51
GPIO19
HDA_SDO RSMRST
DF_TVS
GPIO28
HDA_SYNC RSMRST
GPIO15
4
Strap description
No reboot mode setting
internal PD
Top-Block Swap Ov er r ide
internal PU
Integrated 1.05V VRM enable ALWAYS Should be always pull-up
Boot BIOS Selection 1 [bit-1]
internal PU
Boot BIOS Selection 0 [bit-0]
internal PU
Flash Descriptor Security
internal PD
DMI/FDI Termination voltage
internal PD
On-die PLL Voltage Regul ator
internal PU
On-Die PLL VR Voltage Select
internal PD
Intel ME Crypto Tr ansport Lay er
Security (TLS) cipher suite
internal PD
R464
R464
10M/J_4
10M/J_4
Sampled
PWROK
PWROK
PWROK
PWROK
PWROK
RSMRST#
RSMRST
3
Cougar Point (HDA,JTAG,SATA)
U30A
RTC_X1
RTC_X2
RTC_RST#
SRTC_RST#
SM_INTRUDER#
PCH_INVRMEN
ACZ_BITCLK_R
SPKR
ACZ_RST#_R
ACZ_SDOUT_R
TP47TP47
PCH_JTAG_TCK_R
PCH_JTAG_TMS_R
PCH_JTAG_TDI_R
PCH_JTAG_TDO_R
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_SI
PCH_SPI_SO
Configuration
0 = Default (weak pu ll-down 20K)
1 = Setting to No-Reboot mode
0 = "top-block swap" mode
1 = Default (weak pu ll-up 20K)
0 = Default (weak pull-up 20K)
1 = Overri de
0 = Set to Vss
1 = Set to Vcc (weak pu ll-up 20K)
0 = Disable
1 = Enable (Default)
0 = Support by 1.8V (weak pull-down)
1 = Support by 1.5V
0 = Intel ME TLS wit h no c onfidentiality
1 = Intel ME TLS with confidentiality
3
U30A
A20
RTCX1
C20
RTCX2
D20
RTCRST#
G22
SRTCRST#
K22
INTRUDER#
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN# / GPIO33
N32
HDA_DOCK_RST# / GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
CougarPoint_R1P0
CougarPoint_R1P0
GNT0#GNT1#
11
00
Boot Location
SPI
LPC
2
1
09
C38
FWH0 / LAD0
A38
FWH1 / LAD1
B37
FWH2 / LAD2
C37
FWH3 / LAD3
LPC
LPC
FWH4 / LFRAME#
+3V
LDRQ1# / GPIO23
RTCIHDA
RTCIHDA
+3V
SATA
SATA
+3V_S5
JTAG
JTAG
SATA3RCOMPO
SPI
SPI
+3V
SATA0GP / GPIO21
+3V
SATA1GP / GPIO19
+3V_RTC
+3V
*
+3V_S5
LDRQ0#
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA 6G
SATA 6G
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3COMPI
SATA3RBIAS
SATALED#
R508 *1K/J_4R508 *1K/J_4
+3V
R237 *1K/J_4R237 *1K/J_4
R195 330K/J_4R195 330K/J_4
R465 1K/J_4R465 1K/J_4
R475 1K/J_4R475 1K/J_4
R468 *1K/J_4R468 *1K/J_4
R489 *1K/J_4R489 *1K/J_4
R441 *1K/J_4R441 *1K/J_4
+3V
R522 2.2K/J_4R522 2.2K/J_4
R523 1K/J_4R523 1K/J_4
R270 *1K/J_4R270 *1K/J_4
R434 1K/J_4R434 1K/J_4
D36
PCH_DRQ#0
E36
PCH_DRQ#1
K36
SERIRQ
V5
AM3
AM1
SATA_TXN0_C
AP7
SATA_TXP0_C
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
SATA_TXN3_C
AF3
SATA_TXP3_C
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
SATA_COMP
Y10
AB12
SATA3_COMP
AB13
SATA3_RBIAS
AH1
R491 10KR491 10K
P3
GPIO21
V14
BBS_BIT0
P1
SPKR
PCH_INVRMEN
BBS_BIT0
ACZ_SDOUT_R
ME_WR#31
R436 0_4R436 0_4
+1.8V
ACZ_SYNC_Q
Need check schematic
R241 1K_4R241 1K_4
+3V_S5
2
LAD0 28,31
LAD1 28,31
LAD2 28,31
LAD3 28,31
LFRAME# 28,31
TP28TP28
TP30TP30
SERIRQ 31
C431 0.01U/25V_4C431 0.01U/25V_4
C434 0.01U/25V_4C434 0.01U/25V_4
C649 0.01U/25V_4C649 0.01U/25V_4
C650 0.01U/25V_4C650 0.01U/25V_4
R283 37.4/F_4R283 37.4/F_4
R281 49.9/F_4R281 49.9/F_4
R512 750/F_4R512 750/F_4
+3V
SATA_ACT# 29
PCI_GNT3# 10
BBS_BIT1 10
DF_TVS 11
H_SNB_IVB# 4
PLL_ODVR_EN 11
PCH_GPIO15 11
SERIRQ
GPIO21
SATA_RXN0 25
SATA_RXP0 25
SATA_TXN0 25
SATA_TXP0 25
SATA_RXN3 25
SATA_RXP3 25
SATA_TXN3 25
SATA_TXP3 25
+1.05V_PCH
Default weak pull-up on GNT0/1#
[Need external pull-down for LPC BIOS]
GNT[3:0]# functionality is not available on Mobile.
Used as GPIO only.
Default weak pull - up on GNT0/ 1#
[Need external pull-down for LPC BIOS]
R8361 change to 1K ohm follow DG1.0 and chklist 1.0
It needs to be connected to PROC_SELECT with a
1K±5% pull-up resistor to PCH VCCPNAND rail and a
4.7K±5% series resistor.
New Add in CPT EDS Rev1.0 at 0316
, Needs to be pulled High for
Huron River platform.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
R279 8.2K/J_4R279 8.2K/J_4
R266 *10K/J_4R266 *10K/J_4
SATA HDD
SATA ODD
Cougar Point 2/6
Cougar Point 2/6
Cougar Point 2/6
Monday, September 27, 2010
Monday, September 27, 2010
Monday, September 27, 2010
+3V
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
FH5
FH5
FH5
941
941
941
1A
1A
1A
5
4
3
2
1
Cougar Point-M (PCI-E,SMBUS,CLK)
Cougar Point-M (PCI,USB,NVRAM)
U30E
U30E
BG26
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
GPIO53
C316
C316
*10P/50V_4
*10P/50V_4
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
B21
M20
AY16
BG46
BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
K40
K38
H38
G38
C46
C44
E40
D47
E42
F46
G42
G40
C42
D44
K10
C6
H49
H43
J48
K42
H40
C319
C319
*10P/50V_4
*10P/50V_4
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
TP21
TP22
TP23
TP24
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40
PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
PME#
PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
CougarPoint_R1P0
CougarPoint_R1P0
RSVD
RSVD
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
PCI
PCI
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
USB
USB
D D
C C
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
DGPU_EDIDSEL#
DGPU_SELECT#
BBS_BIT19
PCI_GNT3#9
CLK_PCI_LPC28
CLK_PCI_EC31
B B
CLK_PCI_FB CLK_PCI_FB_R
TP29TP29
R256 22/J_4R256 22/J_4
R226 22/J_4R226 22/J_4
R224 22/J_4R224 22/J_4
MPC_PWR_CTRL#
GPIO03
EXTTS_SNI_DRV0_PCH
EXTTS_SNI_DRV1_PCH
PCI_PME#
PCI_PLTRST#
CLK_PCI_LPC_R
CLK_PCI_EC_R
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
NV_ALE
AV5
AV10
AT8
AY5
BA2
AT12
BF3
USBP0-
C24
USBP0+
A24
USBP1-
C25
USBP1+
B25
USBP2-
C26
USBP2+
A26
USBP3-
K28
USBP3+
H28
USBP4-
E28
USBP4+
D28
USBP5-
C28
USBP5+
A28
C29
B29
N28
M28
USBP8-
L30
USBP8+
K30
USBP9-
G30
USBP9+
E30
USBP6-
C30
USBP6+GPIO54
A30
L32
K32
G32
E32
C32
A32
USB_BIAS
C33
B33
USB_OC0#
A14
USB_OC1#
K20
USB_OC2#
B17
USB_OC3#
C16
USB_OC4#
L16
USB_OC5#
A16
USB_OC6#
D14
USB_OC7#
C14
USBP0- 27
USBP0+ 27
USBP1- 27
USBP1+ 27
USBP2- 27
USBP2+ 27
USBP3- 28
USBP3+ 28
USBP4- 28
USBP4+ 28
USBP5- 23
USBP5+ 23
USBP8- 32
USBP8+ 32
USBP9- 27
USBP9+ 27
USBP6- 33
USBP6+ 33
TP46TP46
TP49TP49
R456 22.6/F_4R456 22.6/F_4
USB_OC0# 27
TP37TP37
USB CNN (Charge)
USB CNN
USB CNN
WLAN
WWAN
Card Reader
New Card
BlueTooth
CCD on LVDS
EHCI1
EHCI2
WLAN
WWAN
New Card
GLAN
WLAN
WWAN
New Card
LAN
PCIE_RXN128
PCIE_RXP128
PCIE_TXN128
PCIE_TXP128
PCIE_RXN228
PCIE_RXP228
PCIE_TXN228
PCIE_TXP228
PCIE_RXN432
PCIE_RXP432
PCIE_TXN432
PCIE_TXP432
PCIE_RXN6_LAN26
PCIE_RXP6_LAN26
PCIE_TXN6_LAN26
PCIE_TXP6_LAN26
CLK_PCIE_WLANN28
CLK_PCIE_WLANP28
PCIE_CLKREQ_WLAN#28
CLK_PCIE_WWANN28
CLK_PCIE_WWANP28
PCIE_CLKREQ_WW AN#28
CLK_PCIE_NEWN32
CLK_PCIE_NEWP32
PCIE_CLKREQ_NEW#32
CLK_PCIE_LANN26
CLK_PCIE_LANP26
PCIE_CLKREQ_LAN#26
C430 0.1U/10V_4C430 0.1U/10V_4
C429 0.1U/10V_4C429 0.1U/10V_4
C438 0.1U/10V_4C438 0.1U/10V_4
C437 0.1U/10V_4C437 0.1U/10V_4
C445 0.1U/10V_4C445 0.1U/10V_4
C444 0.1U/10V_4C444 0.1U/10V_4
C441 0.1U/10V_4C441 0.1U/10V_4
C440 0.1U/10V_4C440 0.1U/10V_4
TP63TP63
TP64TP64
TP41TP41
TP40TP40
TP65TP65
TP43TP43
TP45TP45
TP44TP44
TP42TP42
TP38TP38
TP39TP39
TP56TP56
TP55TP55
TP31TP31
TP34TP34
TP32TP32
TP33TP33
TP36TP36
TP35TP35
PCIE_TXN1_C
PCIE_TXP1_C
PCIE_TXN2_C
PCIE_TXP2_C
PCIE_TXN4_C
PCIE_TXP4_C
PCIE_TXN6_LAN_C
PCIE_TXP6_LAN_C
CLK_PCIE_WLANN
CLK_PCIE_WLANP
PCIE_CLKREQ_WLAN#
CLK_PCIE_WWANN
CLK_PCIE_WWANP
PCIE_CLKREQ_WWAN#
PCIE_CLKREQ_USB3#
CLK_PCIE_NEWN
CLK_PCIE_NEWP
PCIE_CLKREQ_NEW#
PCIE_CLKREQ_REV1#
CLK_PCIE_LANN
CLK_PCIE_LANP
PCIE_CLKREQ_LAN#
GPIO56
CLK_PCIE_REQ6#
GPIO46
U30B
U30B
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2# / GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5# / GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6# / GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7# / GPIO46
AK14
CLKOUT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
CougarPoint_R1P0
CougarPoint_R1P0
+3V_S5
+3V_S5
SMBUSController
SMBUSController
+3V_S5
SML1ALERT# / PCHHOT# / GPIO74
+3V_S5
+3V_S5
PCI-E*
PCI-E*
+3V_S5
+3V_S5
CLOCKS
CLOCKS
+3V
+3V
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V
+3V
+3V_S5
+3V
+3V
SMBALERT# / GPIO11
SMBDATA
SML0ALERT# / GPIO60
SML0DATA
SML1CLK / GPIO58
SML1DATA / GPIO75
CL_DATA1
Link
Link
CL_RST1#
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
FLEX CLOCKS
FLEX CLOCKS
SMBCLK
SML0CLK
CL_CLK1
E12
H14
C9
A12
C8
G12
C13
E14
M16
M7
T11
P10
M10
AB37
AB38
AV22
AU22
AM12
AM13
BF18
BE18
BJ30
BG30
G24
E24
AK7
AK5
K45
H45
V47
V49
Y47
K43
F47
H47
K49
CLK_PCIE_VGAN
CLK_PCIE_VGAP
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
CLK_FLEX0
CLK_FLEX1
CLK_FLEX2
C641
C641
*10P/50V_4
*10P/50V_4
SMBALERT#
SMB_PCH_CLK
SMB_PCH_DAT
DRAMRST_CNTRL_PCH
SMB_ME0_CLK
SMB_ME0_DAT
SML1ALERT#_R
SMB_ME1_CLK
SMB_ME1_DAT
PCIE_CLKREQ_PEG#
CLK_BUF_PCIE_3GPLLN
CLK_BUF_PCIE_3GPLLP
CLK_BUF_BCLKN
CLK_BUF_BCLKP
CLK_BUF_DREFCLKN
CLK_BUF_DREFCLKP
CLK_BUF_DREFSSCLKN
CLK_BUF_DREFSSCLKP
CLK_PCH_14M
CLK_PCI_FB
R511 90.9/F_4R511 90.9/F_4
C321
C321
*10P/50V_4
*10P/50V_4
R451 *0_4R451 *0_4
+1.05V_PCH
R236 *22/J_4R236 *22/J_4
R238 22/J_4R238 22/J_4
R469 22/J_4R469 22/J_4
C326
C326
*10P/50V_4
*10P/50V_4
DRAMRST_CNTRL_PCH 5
CL_CLK1 28
CL_DATA1 28
CL_RST1# 28
PCIE_CLKREQ_PEG# 16
CLK_PCIE_VGAN 16
CLK_PCIE_VGAP 16
CLK_CPU_BCLKN 4
CLK_CPU_BCLKP 4
CLK_DPLL_SSCLKN 4
CLK_DPLL_SSCLKP 4
CLK_PCI_FB
R507
R507
1M/J_4
1M/J_4
10
SML1ALERT# 11,31
For EC
C353
C353
*10P/50V_4
*10P/50V_4
C648 18P/50V_4C648 18P/50V_4
21
Y4
25MHzY425MHz
C647 18P/50V_4C647 18P/50V_4
CLK_27M_VGA 18
CLK_48M_CARD 23
CLK_25M_LAN 26
CLK_REQ/Strap Pin(CLG) SMBus/Pull-up(CLG)
+3V
EXTTS_SNI_DRV0_PCH
EXTTS_SNI_DRV1_PCHUSB_OC2#
DGPU_EDIDSEL#
DGPU_SELECT#
+3V_S5
R477 10K/J_4R477 10K/J_4
R445 10K/J_4R445 10K/J_4
R219 10K/J_4R219 10K/J_4
R223 10K/J_4R223 10K/J_4
R267 10K/J_4R267 10K/J_4
R240 10K/J_4R240 10K/J_4
R220 10K/J_4R220 10K/J_4
+3V
R479 10K/J_4R479 10K/J_4
R278 10K/J_4R278 10K/J_4
+3V_S5
R261 10K/J_4R261 10K/J_4
R260 *10K/J_4R260 *10K/J_4
CLK_BUF_BCLKN
CLK_BUF_BCLKP
CLK_BUF_PCIE_3GPLLN
CLK_BUF_PCIE_3GPLLP
CLK_BUF_DREFCLKN
CLK_BUF_DREFCLKP
CLK_BUF_DREFSSCLKN
CLK_BUF_DREFSSCLKP
CLK_PCH_14M
R536 10K/J_4R536 10K /J _4
R537 10K/J_4R537 10K /J _4
R310 10K/J_4R310 10K /J _4
R309 10K/J_4R309 10K /J _4
R234 10K/J_4R234 10K /J _4
R235 10K/J_4R235 10K /J _4
R286 10K/J_4R286 10K /J _4
R287 10K/J_4R287 10K/J_4
R249 10K/J_4R249 10K /J _4
CLOCK TERMINATION for FCIM
PCIE_CLKREQ_WLAN#
PCIE_CLKREQ_NEW#
PCIE_CLKREQ_REV1#
PCIE_CLKREQ_LAN#
CLK_PCIE_REQ6#
GPIO56
GPIO46
PCIE_CLKREQ_WWAN#
PCIE_CLKREQ_USB3#
PCIE_CLKREQ_PEG#
C333 *10P/50V_4C333 *10P/50V_4
Q28
Q28
2N7002K
R493
R493
R474
R474
R453 1K/J_4R453 1K/J_4
R452 10K/J_4R452 10K/J_4
R210 10K/J_4R210 10K/J_4
R206 2.2K/J_4R206 2.2K/J_4
R218 2.2K/J_4R218 2.2K/J_4
R209 2.2K/J_4R209 2.2K/J_4
R222 2.2K/J_4R222 2.2K/J_4
1
1
2N7002K
2
2
Q27
Q27
2N7002K
2N7002K
DRAMRST_CNTRL_PCH
SML1ALERT#_R
SMBALERT#
SMB_PCH_CLK
SMB_PCH_DAT
SMB_ME0_CLK
SMB_ME0_DAT
3
MBCLK2 31
3
MBDATA2 31
SMB_PCH_CLK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
SMB_ME1_CLK SMB_PCH_DAT
2.2K/J_4
2.2K/J_4
+3V_S5 +3V
2.2K/J_4
2.2K/J_4
SMB_ME1_DAT
+3V_S5
2
Check
3
2
2
3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Cougar Point 3/6
Cougar Point 3/6
Cougar Point 3/6
Monday, September 27, 2010
Monday, September 27, 2010
Monday, September 27, 2010
1
2N7002K
2N7002K
Q34
Q34
Q33
Q33
2N7002K
2N7002K
1
1
SMB_RUN_DAT 14,15,28
4.7K/J_4
4.7K/J_4
R550
R550
R544
R544
4.7K/J_4
4.7K/J_4
SMB_RUN_CLK 14,15,28
FH5
FH5
FH5
10 41
10 41
10 41
1A
1A
1A
of
MPC_PWR_CTRL#
GPIO03
GPIO54
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
GPIO53
PLTRST#(CLG)
+3V_S5
C638
C638
0.1U/10V_4
0.1U/10V_4
PCI_PLTRST#
A A
2
1
3 5
U29
U29
TC7SH08FU
TC7SH08FU
PLTRST#
4
R447
R447
100K/J_4
100K/J_4
PLTRST# 4,16,26,28,31,32
PCI/USBOC# Pull-up(CLG)
+3V_S5
10
USB_OC4#
9
USB_OC1#
8
7 4
USB_OC3#
R426
R426
10KX8
10KX8
USB_OC6#
1
USB_OC0#
2
USB_OC7#
3
USB_OC5#
56
MPC Switch Control
MPC_PWR_CTRL#
MPC_PWR_CTRL#
5
4
R432 8.2K/J_4R432 8.2K/J_4
R443 8.2K/J_4R443 8.2K/J_4
R437 8.2K/J_4R437 8.2K/J_4
R442 8.2K/J_4R442 8.2K/J_4
R444 *10K/J_4R444 *10K/J_4
+3V
R439
R439
10
1
9
2
8
3
7 4
56
10KX8
10KX8
Low = MPC ON
High = MPC OFF (Default)
R184 *1K/J_4R184 *1K/J_4
3
5
SGPIO
S_GPIO
D D
R509 1K/J_4R509 1K/J_4
R510 *1K/J_4R510 *1K/J_4
GPIO15
Intel ME Crypto Transport Layer
Security (TLS) cipher suite internal PD
0 = Intel ME TLS with no confidentiality
1 = Intel ME TLS with confidentiality
GPUCORE_ON
GPU_PWR_ON
C C
B B
SATA[3:2]GP/GPIO[37:36] internal Pull-down 20K
SATA2GP/GPIO36 (FDI_OVRVLTG) & SATA3GP/GPIO37 (DMI_OVRVLTG)
Sampled at Rising edge of PWROK.
Weak internal pull-down. (weak internal pull-down is disabled after PLTRST# de-asserts)
NOTE: This signal should NOT be pulled high when strap is sampled
R506 *100K/J_4R506 *100K/J_4
A A
FDI TERMINATION
VOLTAGE OVERRIDE
FDI_OVRVLTG DMI_OVRVLTG BIOS_REC
+3V
EC_EXT_SMI#31
EC_EXT_SCI#31
PCH_GPIO159
DGPU_HOLD_RST#16
BIOS_WP#31
PLL_ODVR_EN9
dGPU_VRON31,39,41
dGPU_PWR_EN41
dGPU_PRSNT#
SML1ALERT#10,31
R500 *1K/J_4R500 *1K/J_4
LOW - Tx, Rx terminated
to same voltage
5
GFXPG16,31
dGPU_PWR_EN
R501 EV@0_4R501 EV@0_4
DMI TERMINATION
VOLTAGE OVERRIDE
S_GPIO
EC_EXT_SMI#
BOARD_ID1
EC_EXT_SCI#
ICC_EN#
TP48TP48
LAN_DISABLE#
TP27TP27
GFXPG
BIOS_REC
+3V_S5
GPIO27
STP_PCI#
R274 EV@0_4R274 EV@0_4
FDI_OVRVLTGFDI_OVRVLTG
MFG_MODE
BOARD_ID0
TEST_SET_UP
R498 0_4R498 0_4
SV_DET
4
Cougar Point (GPIO,VSS_NCTF,RSVD)
U30F
U30F
T7
BMBUSY# / GPIO0
A42
TACH1 / GPIO1
H36
TACH2 / GPIO6
E38
TACH3 / GPIO7
C10
GPIO8
C4
LAN_PHY_PWR_CTRL / GPIO12
G2
GPIO15
U2
SATA4GP / GPIO16
D40
TACH0 / GPIO17
T5
R239 1K/F_4R239 1K/F_4
DMI_OVRVLTGDMI_OVRVLTG
CRIT_TEMP_REP#
R282 *200K/F_4R282 *200K/F_4
Low = Tx, Rx terminated to
same voltage (DC Coupling Mode)
(DEFAULT)
4
SCLOCK / GPIO22
E8
GPIO24 / MEM_LED
E16
GPIO27
P8
GPIO28
K1
STP_PCI# / GPIO34
K4
GPIO35
V8
SATA2GP / GPIO36
M5
SATA3GP / GPIO37
N2
SLOAD / GPIO38
M3
SDATAOUT0 / GPIO39
V13
SDATAOUT1 / GPIO48
V3
SATA5GP / GPIO49
D6
GPIO57
A4
VSS_NCTF_1
A44
VSS_NCTF_2
A45
VSS_NCTF_3
A46
VSS_NCTF_4
A5
VSS_NCTF_5
A6
VSS_NCTF_6
B3
VSS_NCTF_7
B47
VSS_NCTF_8
BD1
VSS_NCTF_9
BD49
VSS_NCTF_10
BE1
VSS_NCTF_11
BE49
VSS_NCTF_12
BF1
VSS_NCTF_13
BF49
VSS_NCTF_14
CougarPoint_R1P0
CougarPoint_R1P0
3
C40
R461 1.5K/F_4R461 1.5K/F_4
B41
R462 1.5K/F_4R462 1.5K/F_4
C41
R460 1.5K/F_4R460 1.5K/F_4
A40
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71
+3V_S5
+3V_S5
+3V_S5
DSW
+3V_S5
+3V
+3V
+3V
+3V
+3V_S5
+3V
+3V
+3V
+3V
GPIO
GPIO
PROCPWRGD
THRMTRIP#
CPU/MISC
CPU/MISC
A20GATE
PECI
RCIN#
INIT3_3V#
DF_TVS
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
NC_1
P4
AU16
P5
AY11
AY10
T14
AY1
AH8
AK11
AH10
AK10
P37
PCH_THRMTRIP#
+3V
+3V
+3V
+3V_S5
+3V+3V +3V
NCTF
NCTF
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
BIOS RECOVERY
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
R272 10K/J_4R272 10K/J_4
R271 *1K/J_4R271 *1K/J_4
High = Disable (Default)
Low = Enable
3
BOARD_ID2
+3V
EC_A20GATE
R294 *0_4R294 *0_4
EC_RCIN#
R292 390/J_4R292 390/J_4
TEST_SET_UP
MFG_MODE
2
Muxed with STP_PCI#
If not used, 8.2-kȍ to 10-kȍ pull-up to +V3.3S.
EC_A20GATE 31
EC_PECI 4,31
EC_RCIN# 31
H_PWRGOOD 4
PM_THRMTRIP# 4
DF_TVS 9
Un-multiplexed. Can be configured as wake input to allow wakes from Deep Sleep.
If not used then use 8.2-kȍ to 10-kȍ pull-down to GND.
SV_SET_UP
High = Strong (Default)
R430 10K/J_4R430 10K/J_4
R435 *1K/J_4R435 *1K/J_4
MFG-TEST
+3V
R482 10K/J_4R482 10K/J_4
R488 *1K/J_4R488 *1K/J_4
2
1
11
GPIO Pull-up/Pull-down(CLG)
LAN_DISABLE#
PLL_ODVR_EN
ICC_EN#
EC_EXT_SMI#
EC_EXT_SCI#
STP_PCI#
EC_A20GATE
EC_RCIN#
GFXPG
CRIT_TEMP_REP#
dGPU_PWR_EN
GPIO27
+3V_S5
R231 *10K/J_4R231 *10K/J_4
+3V
[ID0:D1]
Fuction
0:0
UMA
Board ID2 reserve PD
R250 *SP@10K/J_4R250 *SP@10K/J_4
R190 SP@10K/J_4R190 SP@10K/J_4
R458 SP@10K/J_4R458 SP@10K/J_4
+3V
R504
R504
SPE@10K/J_4
SPE@10K/J_4
Ra Rb
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Cougar Point 4/6
Cougar Point 4/6
Cougar Point 4/6
Monday, September 27, 2010
Monday, September 27, 2010
Monday, September 27, 2010
R229 10K/J_4R229 10K/J_4
R496 10K/J_4R496 10K/J_4
R448 *10K/J_4R448 *10K/J_4
R463 10K/J_4R463 10K/J_4
R433 10K/J_4R433 10K/J_4
R480 10K/J_4R480 10K/J_4
R259 10K/J_4R259 10K/J_4
R258 10K/J_4R258 10K/J_4
R431 *10K/J_4R431 *10K/J_4
R497 10K/J_4R497 10K/J_4
R280 10K/J_4R280 10K/J_4
R225 10K/J_4R225 10K/J_4
SV_DET
R233 100K/J_4R233 100K/J_4
0:1 1:0 1:1
BOARD_ID0
BOARD_ID1
BOARD_ID2
EV
Optimus
(Samsung)
R245 SP@10K/J_4R245 SP@10K/J_4
R189 *SP@10K/J_4R189 *SP@10K/J_4
R459 *SP@10K/J_4R459 *SP@10K/J_4
UMA
(Hynix)
Ra RbStuff
DGPU_PRSNT#
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
*SPI@100K/J_4
*SPI@100K/J_4
FH5
FH5
FH5
11 41
11 41
11 41
R505
R505
+3V_S5
+3V
Rev.Optimus
+3V
1A
1A
1A
5
4
3
2
1
12
PCH5(CLG)
COUGAR POINT (POWER)
POWER
POWER
U30G
D D
C C
B B
+1.05V_PCH +1.05V_PCH_VCC
R546 0.002/F_1206R546 0.002/F_1206
+1.05V_PCH_VCCDPL L_EXP+1.05V_PCH
R540 0/J_6R540 0/J_6
+1.05V_PCH +1.0 5V_VCCAPLL_EXP
L30 *1uH/25mA_6L30 *1uH/25mA_6
+1.05V_PCH +1.05V_VCCIO
R321 0.002/F_1206R321 0.002/F_1206
+1.05V_PCH
VccCORE =1.3 A(60mils)
C368
C368
C373
C373
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
C665
C665
*10U/6.3V_6
*10U/6.3V_6
VccIO =2.925 A(140mils)
C393
C393
C401
C401
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
C391
C391
1U/6.3V_4
1U/6.3V_4
R547 0/J_8R547 0/J_8
+VCCAFDI_VRM
+1.05V_PCH
R517 0/J_6R517 0/J_6
+1.5V
R514 *0/J_ 6R514 *0 /J_6
+3V
C693
C693
*0.1U/10V_4
*0.1U/10V_4
C381
C381
1U/6.3V_4
1U/6.3V_4
C394
C394
1U/6.3V_4
1U/6.3V_4
C395
C395
10U/6.3V_6
10U/6.3V_6
+3V_VCC_EXP+3V
C667
C667
0.1U/10V_4
0.1U/10V_4
R313 *0/J_8R313 *0/J_8
R539 0/J_8R539 0/J_8
+1.05V_VTT
+VCCAFDI_VRM
C695
C695
C694
C694
*0.1U/10V_4
*0.1U/10V_4
*0.1U/10V_4
*0.1U/10V_4
C382
C382
10U/6.3V_6
10U/6.3V_6
+VCCAFDI_VRM
+1.05V_VCCAPLL_FDI
+1.05V_VCCDPLL _FDI
+VCCAFDI_VRM
VCCVRM: 1.8V (Destop) 02/20 del for Pre-ES1
1.5V (Mobile)
C696
C696
*0.1U/10V_4
*0.1U/10V_4
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
AN19
BJ22
AN16
AN17
AN21
AN26
AN27
AP21
AP23
AP24
AP26
AT24
AN33
AN34
BH29
AP16
BG6
AP17
AU20
U30G
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]
VCCIO[28]
VCCAPLLEXP
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]
VCCIO[25]
VCCIO[26]
VCC3_3[3]
VCCVRM[2]
VccAFDIPLL
VCCIO[27]
VCCDMI[2]
CougarPoint_R1P0
CougarPoint_R1P0
CRTLVDS
CRTLVDS
VCC CORE
VCC CORE
DMI
DMI
VCCIO
VCCIO
DFT / SPI HVCMOS
DFT / SPI HVCMOS
FDI
FDI
VCCADAC
VSSADAC
VCCALVDS
VSSALVDS
VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]
VCC3_3[6]
VCC3_3[7]
VCCVRM[3]
VCCDMI[1]
VCCCLKDMI
VCCDFTERM[1]
VCCDFTERM[2]
VCCDFTERM[3]
VCCDFTERM[4]
VCCSPI
U48
U47
AK36
AK37
AM37
AM38
AP36
AP37
V33
V34
AT16
AT20
AB36
AG16
AG17
AJ16
AJ17
V1
VccADAC =1mA(8mils)
C646
C646
R486
R486
0.01U/25V_4
0.01U/25V_4
*0/J_6
*0/J_6
VccALVDS=1mA(8mils)
VccTX_LVDS=60mA(10mils)
C396
C396
SPI@0.01U/25V_4
SPI@0.01U/25V_4
R483 0/J_6R483 0/J_6
C361
C361
0.1U/10V_4
0.1U/10V_4
+VCCAFDI_VRM
C374
C374
1U/6.3V_4
1U/6.3V_4
C366
C366
*10U/6.3V_6
*10U/6.3V_6
R531 0/J_8R531 0/J_8
C386
C386
0.1U/10V_4
0.1U/10V_4
R494 0/J_6R494 0/J_6
C644
C644
1U/6.3V_4
1U/6.3V_4
+VCCAFDI_VRM
C400
C400
SPI@0.01U/25V_4
SPI@0.01U/25V_4
+3V+3V_VCC_GIO
L28
L28
*10uH/100mA_8
*10uH/100mA_8
+1.8V+VCCP_ NAND
+3V+3V_VCCME_SPI
+VCCA_DAC_1_2
L26 180ohm/5AL26 180ohm/5A
C643
C643
C645
C645
10U/6.3V_6
10U/6.3V_6
0.1U/10V_4
0.1U/10V_4
+VCCALVDS +3V
R529 SPI@0/J_4R529 SPI@0/J_4
ZĂ
R284 *SPE@0/J_4R284 *SPE@0/J_4
L13 SPI@0.1uH_8L13 SPI@0.1uH_8
Zď
R289 *SPE@0/J_4R289 *SPE@0/J_4
C428
C428
SPI@22U/6.3V_8
SPI@22U/6.3V_8
s hD
ZĂ
ϬŽŚŵ E
ϬŽŚŵ
Zď E
VCCDMI = 42mA(10mils)
C399
C399
1U/6.3V_4
1U/6.3V_4
VCCCLKDMI = 20mA(8mils)
+VCC_DMI_CCI +1.05V_PCH+1.1V_VCC_DMI_CCI
R515 *1/F_4R515 *1/F_4
R516 0/J_4R516 0/J_4
VCCPNAND = 190 mA(15mils)
VCCSPI = 20mA(8mils)
+3V
+1.8V+VCC_TX_LVDS
+1.05V_VTT+1.1V_ VCC_DMI
1mA(8mils)
VCCRTC<1mA(8mils)
+3V_S5
+3V_DSW
+1.05V_PCH
L31 *10uH/100mA_8L31 *10uH/100mA_8
VCCME(+1.05V) = ??A(??mils)
+1.05V_PCH
R530 0.002/F_1206R530 0.002/F_1206
+1.05V_PCH
R518 0/J_6R518 0 /J_6
R288 0/J_6R288 0 /J_6
R542 0/J_6R542 0/J_6
+1.05V_PCH
R520 *0/J_ 6R520 *0 /J_6
+1.05V_VTT
R315 0/J_4R315 0/J_4
+3V_RTC
R499 0/J_4R499 0/J_4
R503 *0/J_ 4R503 *0/J_4
+VCCAPLL_CPY_PCH
C672
C672
*10U/6.3V_6
*10U/6.3V_6
+1.05V_VCCEPW
VccASW =1.01 A(60mils)
C367
C367
1U/6.3V_4
1U/6.3V_4
C652
C652
1U/6.3V_4
1U/6.3V_4
C379
C379
1U/6.3V_4
1U/6.3V_4
C668
C668
1U/6.3V_4
1U/6.3V_4
C344
C344
*1U/6.3V_4
*1U/6.3V_4
C664
C664
4.7U/6.3V_6
4.7U/6.3V_6
C317
C317
1U/6.3V_4
1U/6.3V_4
+1.05V_PCH
VCCDSW3_3= 3mA
C348
C348
0.1U/10V_4
0.1U/10V_4
+1.05V_PCH
C356
C356
1U/6.3V_4
1U/6.3V_4
C655
C655
22U/6.3V_8
22U/6.3V_8
VCCDIFFCLKN= 55mA(10mils)
VCCSSC= 95mA(10mils)
C425
C425
0.1U/10V_4
0.1U/10V_4
C314
C314
0.1U/10V_4
0.1U/10V_4
R524 *0/J_8R524 *0/J_8
C357
C357
*0.1U/10V_4
*0.1U/10V_4
R548 0/J_6R548 0/J_6
C392
C392
*1U/6.3V_4
*1U/6.3V_4
C341
C341
1U/6.3V_4
1U/6.3V_4
C656
C656
22U/6.3V_8
22U/6.3V_8
C332 0.1U/10V_4C332 0.1U/10V_4
+VCCAFDI_VRM
65mA(10mils)
8mA(8mils)
C355 0.1U/10V_4C355 0.1U/10V_4
C426
C426
0.1U/10V_4
0.1U/10V_4
C315
C315
0.1U/10V_4
0.1U/10V_4
+VCCACLK
+VCCPDSW
PCH_VCCDSW
+3V_SUS_CLKF33
+VCCDPLL_CPY
+VCCSUS1
+VCCRTCEXT
+VCCAFDI_VRM
+1.05V_VCCA_A_DPL
+1.05V_VCCA_B_DPL
+VCCDIFFCLK
+VCCDIFFCLKN
+V1.05V_SSCVCC
+VCCSST
+V1.05M_VCCSUS
+VTT_VCCPCPU
Cougar Point-M (POWER)
POWER
POWER
U30J
U30J
AD49
T16
V12
T38
BH23
AL29
AL24
AA19
AA21
AA24
AA26
AA27
AA29
AA31
AC26
AC27
AC29
AC31
AD29
AD31
W21
W23
W24
W26
W29
W31
W33
N16
Y49
BD47
BF47
AF17
AF33
AF34
AG34
AG33
V16
T17
V19
BJ8
A22
VCCACLK
VCCDSW3_3
DCPSUSBYP
VCC3_3[5]
VCCAPLLDMI2
VCCIO[14]
DCPSUS[3]
VCCASW[1]
VCCASW[2]
VCCASW[3]
VCCASW[4]
VCCASW[5]
VCCASW[6]
VCCASW[7]
VCCASW[8]
VCCASW[9]
VCCASW[10]
VCCASW[11]
VCCASW[12]
VCCASW[13]
VCCASW[14]
Clock and Miscellaneous
Clock and Miscellaneous
VCCASW[15]
VCCASW[16]
VCCASW[17]
VCCASW[18]
VCCASW[19]
VCCASW[20]
DCPRTC
VCCVRM[4]
VCCADPLLA
VCCADPLLB
VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]
VCCSSC
DCPSST
DCPSUS[1]
DCPSUS[2]
V_PROC_IO
CPURTC
CPURTC
VCCRTC
CougarPoint_R1P0
CougarPoint_R1P0
PCI/GPIO/LPCMISC
PCI/GPIO/LPCMISC
SATA USB
SATA USB
HDA
HDA
VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[6]
VCCIO[34]
V5REF_SU S
DCPSUS[4]
VCCSUS3_3[1]
V5REF
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCC3_3[1]
VCC3_3[8]
VCC3_3[4]
VCC3_3[2]
VCCIO[5]
VCCIO[12]
VCCIO[13]
VCCIO[6]
VCCAPLLSATA
VCCVRM[1]
VCCIO[2]
VCCIO[3]
VCCIO[4]
VCCASW[22]
VCCASW[23]
VCCASW[21]
VCCSUSHDA
N26
P26
P28
T27
T29
T23
T24
V23
V24
P24
T26
M26
AN23
AN24
P34
N20
N22
P20
P22
AA16
W16
T34
AJ2
AF13
AH13
AH14
AF14
AK1
VCCVRM= 114mA(15mils)
AF11
AC16
AC17
AD17
T21
V21
T19
P32
+3V_VCCPUSB
+3V_VCCAUBG
+VCCAUPLL
+5V_PCH_VCC5REFSUS
+VCCA_USBSUS
+3V_VCCPSUS
+5V_PCH_VCC5REF
+3V_VCCPSUS
+3V_VCCPCORE
+3V
C347
C347
0.1U/10V_4
0.1U/10V_4
+V1.05S_SATA3
+V1.1LAN_VCCAPL L
+VCCAFDI_VRM
R526 0/J_6R526 0/J_6
C372
C372
1U/6.3V_4
1U/6.3V_4
+1.05V_VCCEPW
+V3.3A_1.5A_HDA_IO
C337
C337
*1U/6.3V_4
*1U/6.3V_4
R495 0/J_6R495 0/J_6
C398
C398
*1U/6.3V_4
*1U/6.3V_4
L27 *10uH/100mA_8L27 *10uH/100mA_8
C651
C651
*10U/6.3V_6
*10U/6.3V_6
VCCME = 1.01A(60mils)
R188 0/J_4R188 0/J_4
C339
C339
0.1U/10V_4
0.1U/10V_4
+1.05V_PCH+1.05V_VCCUSBCORE
R438 0/J_8R438 0/J_8
C346
C346
1U/6.3V_4
1U/6.3V_4
VCCSUS3_3 = 119mA(15mils)
+3V_S5
R487 0/J_6R487 0/J_6
C334
C334
0.1U/10V_4
0.1U/10V_4
R204 0/J_6R204 0/J_6
C335
C335
0.1U/10V_4
0.1U/10V_4
+1.05V_PCH
R193 10/F_4R193 10/F_4
D2 RB500V-40D2 RB500V-40
C309
C309
0.1U/10V_4
0.1U/10V_4R291 0/J_4R291 0/J_4
V5REF= 1mA
R467 10/F_4R467 10/F_4
D15 RB500V-40D15 RB500V-40
C338
C338
1U/6.3V_4
1U/6.3V_4
R203 0/J_6R203 0/J_6
VCCSUS3_3 = 119mA(15mils)
C336
C336
1U/10V_4
1U/10V_4
R525 0/J_6R525 0/J_6
VCCPCORE = 28mA(10mils)
C363
C363
0.1U/10V_4
0.1U/10V_4
+3V
C388
C388
0.1U/10V_4
0.1U/10V_4
R528 0/J_8R528 0/J_8
C387
C387
1U/10V_4
1U/10V_4
??mA(??mils)
+1.05V_PCH
+3V_S5
VCC5REFSUS=1mA
+5V_S5
+3V_S5
+5V
+3V
+3V_S5
+3V
+1.05V_PCH
+1.05V_PCH
VCCSUSHDA= 10mA(8mils)
L33 10uH/100mAL33 10uH/100mA
+1.05V_PCH
+3V
R470 *0/J_ 6R470 *0/J_6
R466 1/F_4R466 1/F_4
A A
5
4
3
L25 10uH/100mA_8L25 10uH/100mA_8
C642
C642
10U/6.3V_6
10U/6.3V_6
+3V_SUS_CLKF33
C349
C349
1U/10V_4
1U/10V_4
L32 10uH/100mAL32 10uH/100mA
2
+
+
C670
C670
220U/2.5V_3528
220U/2.5V_3528
+
+
C669
C669
220U/2.5V_3528
220U/2.5V_3528
+1.05V_VCCA_A_DPL
C420
C420
1U/6.3V_4
1U/6.3V_4
+1.05V_VCCA_B_DPL
C423
C423
1U/6.3V_4
1U/6.3V_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Cougar Point 5/6
Cougar Point 5/6
Cougar Point 5/6
Monday, September 27, 2010
Monday, September 27, 2010
Monday, September 27, 2010
1
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
FH5
FH5
FH5
12 41
12 41
12 41
1A
1A
1A
5
4
3
2
1
PCH6(CLG)
13
U30I
U30I
AY4
VSS[159]
IBEX PEAK-M (GND)
D D
U30H
U30H
H5
VSS[0]
AA17
VSS[1]
AA2
VSS[2]
AA3
VSS[3]
AA33
VSS[4]
AA34
VSS[5]
AB11
VSS[6]
AB14
VSS[7]
AB39
VSS[8]
AB4
VSS[9]
AB43
VSS[10]
AB5
VSS[11]
AB7
VSS[12]
AC19
VSS[13]
AC2
VSS[14]
AC21
VSS[15]
AC24
VSS[16]
AC33
VSS[17]
AC34
VSS[18]
AC48
C C
B B
A A
5
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
CougarPoint_R1P0
CougarPoint_R1P0
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
CougarPoint_R1P0
CougarPoint_R1P0
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
3
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
Monday, September 27, 2010
Monday, September 27, 2010
2
Monday, September 27, 2010
PROJECT :
Cougar Point 6/6
Cougar Point 6/6
Cougar Point 6/6
1
FH5
FH5
FH5
13 41
13 41
13 41
1A
1A
1A
of
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