Quanta CT6 DA0CT6MB6F1, Pavilion dv1000, Pavilion dv1600, Pavilion dv1700, Pavilion dv9000 Schematic
1
2
3
4
5
6
7
8
PCB STACK UP
LAYER 1 : TOP
LAYER 2 : GND
LAYER 3 : IN1
A A
LAYER 4 : IN2
LAYER 5 : VCC
LAYER 6 : BOT
CPU Yonah/Merom
XXX Pins (uPGA)
PG 3,4
HyperThansport I/O BUS
CABLE DOCK
PG 30
Daughter Board
TV, USB, BLUE TOOTH
PG 31
Power Board
B B
PG 31
CRT port
LCD Panel
S-VIDEO
PG 29
PG 18
R.G,B
LVDS X1
TV-OUT
PG 18
Link 16x16
NORTH BRIDGE
Calistoga
XXX BGA
INTEGRADED VGA FUNCTION
PG 6,7,8,9,10,11
DDRII
266,333 MHz
DDRII
266,333 MHz
CPU THERMAL
SENSOR
PG 5
CPUCLK,
CPUCLK#
SBLINKCLK, SBLINKCLK#
NBSRCCLK, NBSRCCLK#
HTREFCLK
OSC14M
DDRII-SODIMM1
DDRII-SODIMM2
DMI LINK
32.768KHz
USB PORT 0, 1, 2
USB 2.0
PG 21
1st SATA - HDD
SATA 150MB
PG 32
2nd IDE - CDROM
C C
PG 31
PCI DEVICES IRQ ROUTING
DEVICE PCI_INT
INTEL ETHERNET
MINIPCI SLOT
CardBus/1394
AD24 (D8)
AD22
AD25
REQ/GNT #IDSEL #
C(A~E)
1
C,D
E,F,G0
ATA 66/100/133
32.768KHz
PC87541L
LPC
TQFP XXX
2X
PCI-E
ICH-7m
XXX BGA
PG 28
PG 14,15,16,17
3.3V LPC, 33MHz
Express Card x1
NEW CARD
PCLK_E
PG 33
NBSRCCLK, NBSRCCLK#
33MHZ, 3.3V PC I
PCLK_E
Azalia
PWRCLKP
PWRCLKN
DIB_DATAN
DIB_DATAP
SMARTDAA
MODEM,
PG 24
WIRE
Azalia
CX20551-22
MBAMC20493-010
AMP
TPA0312
PG 23
CT6 BLOCK DIAGRAM
Calistoga / Yonah /ICH-7m
PG 12,13
PG 12,13
PG 22
14.318MHz
CLOCK GEN
IDTXXX/ ICSXXXX
56pins
PG 2
LAN
Intel
Ekron
82562GT
PG 25
25MHz
MINI-Card
PG 33
CARD
READER
SD/MMC,
SM, MS, XD
5 IN 1
SYSTEM POWER MAX1845
(1.2V/NB_CORE/1.25V)
CPU CORE MAX1544
POWER VCORE 1.2V /44A
SYSTEM MAX1999
POWER(3/5V)
SYSTEM POWER MAX1845
(1.8VSUS/0.9V SMDDR_VREF)
BATT CHARGER
MAX1722
DISCHARGE
24.576MHz
CARDREADER / IEEE 1394
CONTROLLER/CF
RICOH 832
PG 19,20,21
PG 21
PG 38
PG 39
PG 36
PG 37
PG 35
PG 34
1394
CONN
PG 20
D D
FAN
Touchpad
PG 29
1
2
Keyboard
PG 31PG 31
3
FLASH
PG 27
4
RJ11
JACK
JACK
HEADPHONE,
2ND HEADPHONE,
MIC
PG 23
5
RJ45
JACK
PG 25PG 24
Size Document Number Rev
BLOCK DIAGRAM
6
Date: Sheet
7
PROJECT : CT6
Quanta Computer Inc.
144Friday, September 23, 2005
of
8
1BCustom
A
FSC FSB FSA CPU SRC PCI
1 0 1 100 100 33
0 0 1 133 100 33
Default
0 1 1 166 100 33
0 1 0 200 100 33
0 0 0 266 100 33
1 0 0 333 100 33
4 4
1 1 0 400 100 33
1 1 1 200 100 33
L32
ACB2012L-120-T
+3V
120 ohms@100Mhz
3 3
PDAT_SMB16,33
PCLK_SMB16,33
2 2
25 mils
VDD_PCI
R300 2.2/F
VDD_48
VDD_REF
R299 1
+3V
R303
Q30
RHU002N06
RHU002N06
BSEL strappings need to be set for 533MHz Moby Dick (Intel?915GM - Calistoga Interposer)
(if Calistoga is designed for 667MHz board).
2
3
+3V
Q31
2
3
SMbus address D2 /IDT
C360
0.1U/10V
C364
0.1U/10V
R308
10K
10K
CGDAT_SMB
1
CGCLK_SMB
1
C362
0.1U/10V
C368
0.1U/10V
C356
10U
C366
10U
C363
10U
DREFCLK8
DREFCLK#8
B
C358 33P/0402
C357 33P/0402
PM_STPPCI#16
PM_STPCPU#16
CGCLK_SMB12,13,33
CGDAT_SMB12,13,33
CLKUSB_4816
CLK_BSEL0
CLK_BSEL1
CLK_BSEL2
+3V
VR_PWRGD_CK410#39
Use 1% R
Iref=5mA,
Ioh=4*Iref
R314 475/F
DREFCLK R_DOT96
DREFCLK#
RP39
1
3
33X2
+3V
+3V5,9,13,14,15,16,17,18,22,23,26,28,29,30,31,32,33,34,36,39,41,42
+1.05V14,17,38,42
+3V
+1.05V
Close to IC <500mils
CG_XIN
21
CL=20 - 22P
Y4
14.318MHZ
R127 33
R122 2.2K/B
R110 4.7K
CG_XOUT RHCLK_CPU
R534 *10K
VR_PWRGD_CK410#
PM_STPPCI#
PM_STPCPU#
CGCLK_SMB
CGDAT_SMB
VDD_REF
VDD_SRC_CPU
VDD_PCI
VDD_SRC_CPU
VDD_48
IREF
2
R_DOT96#
4
L35
ACB2012L-120-T
120 ohms@100Mhz
VDD_A
U15
50
XTAL_IN
49
XTAL_OUT
10
Vtt_PwrGd#/PD
55
PCI/SRC_STOP#
54
CPU_STOP#
46
SCLK
47
SDATA
12
FSA/USB_48MHz
16
FSB/TEST_MODE
53
FSC/REF1
48
VDD_REF
42
VDD_CPU
1
VDD_PCI_1
7
VDD_PCI_2
21
VDD_SRC0
28
VDD_SRC1
34
VDD_SRC2
11
VDD_48
39
IREF
14
DOT96MHz
15
DOT96MHz#
ICS954206AG-T
C
R318 2.2/F
37
VDDA
CK-410M
GND_REF
GND_PCI_2
GND_PCI_1
GND_48
51
62945
2
13
VDD_SRC_CPU
C378
C380
0.1U/10V
0.1U/10V
VDD_A
38
REF0
GNDA
CPU0
CPU0#
CPU1
CPU1#
CPU2_ITP/SRC7
CPU2#_ITP/SRC7#
SRC6
SRC6#
SRC5
SRC5#
SRC4_SATA
SRC4#_SATA
SRC3
SRC3#
SRC2
SRC2#
SRC1
SRC1#
SRC0/DREFSSCLK
SRC0#/DREFSSCLK#
GND_SRC
GND_CPU
PCI5
PCI4
PCI3
PCI2
PCIF1/100_96M#
PCIF0/ITP_EN
D
25 mils
C370
C372
0.1U/10V
C373
0.1U/10V
C374
10U
0.1U/10V
C382
10U
Place these termination to close CK410M.
14M_REF
52
44
RHCLK_CPU#
43
RHCLK_MCH
41
RHCLK_MCH#
40
36
35
CLK_PCIE_MINI_
33
CLK_PCIE_MINI_#
32
RSRC_MCH
31
RSRC_MCH#
30
RSRC_SATA
26
RSRC_SATA#
27
CLK_PCIE_NEW
24
CLK_PCIE_NEW#
25
RSRC_ICH
22
RSRC_ICH#
23
19
20
R_DREFSSCLK
17
R_DREFSSCLK#
18
R_PCLK_591
5
R_PCLK_7411
4
R_PCLK_LAN
3
PCLK_MINI_LPC
56
R_PCLK_ICH
9
R_PCLK_SIO
8
RP38
1
3
RP41
1
3
RP44
1
3
RP46
1
3
RP45
3
1
RP43
3
1
RP42
3
1
RP40
3
1
DREFSSCLK Frequency Select.
"0" : 96MHz
2
4
2
4
T66
T67
2
4
2
4
4
2
4
2
4
2
T65
T68
4
2
R118 33
R120 10K
R124 *10K
R125 10K
"1" : 100MHz
33X2
33X2
33X2
33X2
33X2
33X2
33X2
33X2
R114 33
R109 33
R526 *22
R527 22
+3V
+3V
Use 1% R
Use 33R/1%
R301 33
CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
CLK_PCIE_MINI 33
CLK_PCIE_MINI# 33
CLK_PCIE_3GPLL 8
CLK_PCIE_3GPLL# 8
CLK_PCIE_SATA 14
CLK_PCIE_SATA# 14
CLK_PCIE_NEW_C 33
CLK_PCIE_NEW_C# 33
CLK_PCIE_ICH 15
CLK_PCIE_ICH# 15
DREFSSCLK 8
DREFSSCLK# 8
PCLK_591 28
PCI_CLK_7411 19
PCLK_LAN
PCLK_MINI 41
PCLK_LPC_DEBUG 28,33
PCLK_ICH 15
E
14M_ICH 16
C359
*10P
Place these termination
to close CK410M.
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_PCIE_3GPLL
CLK_PCIE_3GPLL#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_PCIE_MINI
CLK_PCIE_MINI#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_NEW_C
CLK_PCIE_NEW_C#
DREFSSCLK
DREFSSCLK#
DREFCLK
DREFCLK#
R304 49.9/F/B
R307 49.9/F/B
R310 49.9/F/B
R313 49.9/F/B
R328 49.9/F/B
R330 49.9/F/B
R327 49.9/F/B
R329 49.9/F/B
R324 49.9/F/B
R326 49.9/F/B
R316 49.9/F/B
R317 49.9/F/BR123 33
R321 49.9/F/B
R325 49.9/F/B
R312 49.9/F/B
R315 49.9/F/B
R306 49.9/F/B
R309 49.9/F/B
+1.05V
CPU_BSEL03
+1.05V
CPU_BSEL13
1 1
Stuff 0 ohm for 533MHz, NC for 667MHz
+1.05V
CPU_BSEL23 MCH_BSEL2 8
A
R111 56/F
R112 0
R116 1K
R104 1K
R101 0
R105 *0
R107 1K
R99 0
R102 *0
CLK_BSEL0
XDP_OBS2
CLK_BSEL1
XDP_OBS1
CLK_BSEL2
XDP_OBS0
R117 1K
R113 *0
R106 0
R103 1K
R108 *0
R100 0
R98 1K
R97 *0
R96 0
MCH_BSEL0 8
XDP_BPM#1 3
MCH_BSEL1 8
C540
XDP_BPM#2 3
Cross moat
XDP_BPM#3 3
B
Check Intel
0.1U/10V
C
IDT CV140 /56pins
ICS954206AGT /56pins
+3V
C542
10U
3VPCU
PCLK_591
PCI_CLK_7411
PCLK_LAN
PCLK_ICH
C159
*0.1U/10V
C154
*0.1U/10V
C152
*0.1U/10V
C158
*0.1U/10V
PCLK_591 28
PCI_CLK_7411 19
PCLK_LAN
PCLK_ICH 15
PROJECT : CT6
Size Document Number Rev
D
Date: Sheet
Quanta Computer Inc.
CLOCK GENERATOR
244Friday, September 23, 2005
E
of
1ACustom
5
H_A#[31:3]6
D D
H_ADSTB#06
H_REQ#[4:0]6
H_A#[31:3]6
C C
H_ADSTB#16
H_A20M#14
H_FERR#14
T11PAD
T127PAD
T125PAD
T124PAD
T126PAD
T130PAD
T131PAD
T129PAD
T128PAD
T135PAD
T15PAD
H_IGNNE#14
R29 0/F
H_INTR14
H_NMI14
H_SMI#14
T7PAD
H_STPCLK#14
B B
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_STPCLK_R#
TP_A32#
TP_A33#
TP_A34#
TP_A35#
TP_A36#
TP_A37#
TP_A38#
TP_A39#
TP_APM0#
TP_APM1#
TP_HFPLL
XDP_TMS
XDP_TDI
U7A
J4
A[3]#
L4
A[4]#
M3
A[5]#
K5
A[6]#
M1
A[7]#
N2
A[8]#
J1
A[9]#
N3
A[10]#
P5
A[11]#
P2
A[12]#
L1
A[13]#
P4
A[14]#
P1
A[15]#
R1
A[16]#
L2
ADSTB[0]#
K3
REQ[0]#
H2
REQ[1]#
K2
REQ[2]#
J3
REQ[3]#
L5
REQ[4]#
Y2
A[17]#
U5
A[18]#
R3
A[19]#
W6
A[20]#
U4
A[21]#
Y5
A[22]#
U2
A[23]#
R4
A[24]#
T5
A[25]#
T3
A[26]#
W3
A[27]#
W5
A[28]#
Y4
A[29]#
W2
A[30]#
Y1
A[31]#
V4
ADSTB[1]#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
AA1
RSVD[01]#
AA4
RSVD[02]#
AB2
RSVD[03]#
AA3
RSVD[04]#
M4
RSVD[05]#
N5
RSVD[06]#
T2
RSVD[07]#
V3
RSVD[08]#
B2
RSVD[09]#
C3
RSVD[10]#
B25
RSVD[11]#
PZ47903-2741-01
R16 54.9/F
R19 54.9/F
ADDR GROUP 0
DEFER#
DRDY#
DBSY#
CONTROL
LOCK#
RESET#
TRDY#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TRST#
XDP/ITP SIGNALSTHERMH CLK
PROCHOT
THERMDA
THERMDC
THERMTRIP#
BCLK[0]
BCLK[1]
RSVD[12]#
RSVD[13]#
RSVD[14]#
RSVD[15]#
RSVD[16]#
RESERVED
RSVD[17]#
RSVD[18]#
RSVD[19]#
RSVD[20]#
+1.05V
XDP PU_R < 0.2"
XDP_BPM#5
A A
Why BMP5 need PH ?
5
XDP_TCK
XDP_TRST#
R13 54.9/F
R17 54.9/F
R14 54.9/F
ADS#
BNR#
BPRI#
BR0#
IERR#
INIT#
RS[0]#
RS[1]#
RS[2]#
HIT#
HITM#
TCK
TDI
TDO
TMS
DBR#
4
T4 PAD
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
B1
H_RS#0
F3
H_RS#1
F4
H_RS#2
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
XDP_BPM#5
AC1
XDP_TCK
AC5
XDP_TDI
AA6
XDP_TDO
AB3
XDP_TMS
AB5
XDP_TRST#
AB6
XDP_DBRESET#
C20
D21
A24
A25
C7
A22
A21
TP_EXTBREF
T22
TP_SPARE0
D2
TP_SPARE1
F6
TP_SPARE2
D3
TP_SPARE3
C1
TP_SPARE4
AF1
TP_SPARE5
D22
TP_SPARE6
C23
TP_SPARE7
C24
H_PROCHOT#
T9 PAD
T8 PAD
H_ADS# 6
H_BNR# 6
H_BPRI# 6
H_DEFER# 6
H_DRDY# 6
H_DBSY# 6
H_BREQ#0 6
H_INIT# 14
H_LOCK# 6
H_CPURST# 6
H_TRDY# 6
H_HIT# 6
H_HITM# 6
XDP_BPM#0
XDP_BPM#1 2
XDP_BPM#2 2
XDP_BPM#3 2
T234 PAD
H_THERMDA 5
H_THERMDC 5
PM_THRMTRIP# 8,14
CLK_CPU_BCLK 2
CLK_CPU_BCLK# 2
T2 PAD
T18 PAD
T5 PAD
T21 PAD
T132 PAD
T123 PAD
T10 PAD
T12 PAD
T13 PAD
Use 1% R
change part
number (
need to use
1% resistor
)
XDP_TCK PD 27.4/1% ?
XDP_TRST PD 510ohm /5% ?
XDP_TDI PU 150ohm /1.05V
XDP_TMS PU 39.2/1%?
XDP_TDO PU 54.9ohm?
For ITP700
4
+1.05V
R38
56/F
T133 PAD
H_RS#[2:0] 6
T232
T3 PAD
PAD
XDP PU_R < 0.2"
+1.05V
R25
SYS_RST# 16
Layout note: 0.5" max for GTLREF
56/F
+1.05V
R18
1K/F
R15
2K/F
XDP_DBRESET#
H_PROCHOT#
3
+1.05V
XDP_BPM#4
+1.05V 14,17,38,42
H_D#[63:0]6
T233
H_DSTBN#06
H_DSTBP#06
H_DINV#06
H_D#[63:0]6
CKL : R1514/68ohm
For IMVP6
H_DSTBN#16
H_DSTBP#16
H_DINV#16
H_GTLREF
20/15mils
CPU_BSEL02
CPU_BSEL12
CPU_BSEL22
R260 *54.9/F
+1.05V
2
1 3
Q49
*MMBT3904
3
Near to MCH <500mils
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
R259
R258
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
*1K/F
51
PAD
SI-2 modified ( intel
request ww25 document
)
+1.05V
R538
*330
Shall install it ?
pull up 3V_S0 in CRB
VR_TT# 39
E22
F24
E26
H22
F23
G25
E25
E23
K24
G24
H26
F26
K22
H25
H23
G22
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
M24
N25
M26
AD26
C26
D25
B22
B23
C21
J24
J23
J26
U7B
D[0]#
D[1]#
D[2]#
DATA GRP 0 DATA GRP 1
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
GTLREF
MISC
TEST1
TEST2
BSEL[0]
BSEL[1]
BSEL[2]
PZ47903-2741-01
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
DATA GRP 2
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
DATA GRP 3
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
2
H_D#[63:0] 6
H_D#32
AA23
H_D#33
AB24
H_D#34
V24
H_D#35
V26
H_D#36
W25
H_D#37
U23
H_D#38
U25
H_D#39
U22
H_D#40
AB25
H_D#41
W22
H_D#42
Y23
H_D#43
AA26
H_D#44
Y26
H_D#45
Y22
H_D#46
AC26
H_D#47
AA24
W24
Y25
V23
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
AD23
AE24
AC20
R26
U26
U1
V1
E5
B5
D24
D6
D7
AE6
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0
COMP1
COMP2
COMP3
R26 0/F
27.4/F
ICH_DPRSTP# 14,39
H_DPSLP# 14
H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#2 6
H_D#[63:0] 6
Trcae width : ?
placement <0.5"
25/25mils
H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6
R24
R2354.9/F
R2127.4/F
R2054.9/F
PAD
T6
H_CPUSLP# 6,14
PSI# 39
H_PWRGD is CMOS driving by ICH
T14
PAD
+1.05V
1
R28
*200/F
H_DPWR# 6
H_PWRGD 14
TO VRD
PROJECT : CT6
Quanta Computer Inc.
Size Document Number Rev
2
Date: Sheet
CPU(1 OF 2 )
344Friday, September 23, 2005
1
of
1AB
5
U7C
A7
VCC[001]
A9
VCC[002]
A10
VCC[003]
A12
VCC[004]
A13
VCC[005]
A15
D D
VCC_CORE
C296
C37
22U
22U
C17
C9
22U
22U
C22
C C
B B
22U
C298
22U
C8
22U
C21
22U
C295
22U
C317
22U
C40
22U
C38
22U
C39
22U
C5
22U
C299
22U
C16
22U
C292
22U
C287
22U
C293
22U
C20
22U
C302
22U
C41
22U
C42
22U
C289
22U
C288
22U
C319
22U
C301
22U
C19
22U
C318
22U
C7
22U
C18
22U
C36
22U
change to 0805
VCC_CORE
A A
C10
22U
C11
22U
C12
22U
C13
22U
+1.05V
A17
A18
A20
B10
B12
B14
B15
B17
B18
B20
C10
C12
C13
C15
C17
C18
D10
D12
D14
D15
D17
D18
E10
E12
E13
E15
E17
E18
E20
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
B7
B9
C9
D9
E7
E9
F7
F9
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[100]
VCC[034]
VCC[035]
VCCP[01]
VCC[036]
VCCP[02]
VCC[037]
VCCP[03]
VCC[038]
VCCP[04]
VCC[039]
VCCP[05]
VCC[040]
VCCP[06]
VCC[041]
VCCP[07]
VCC[042]
VCCP[08]
VCC[043]
VCCP[09]
VCC[044]
VCCP[10]
VCC[045]
VCCP[11]
VCC[046]
VCCP[12]
VCC[047]
VCCP[13]
VCC[048]
VCCP[14]
VCC[049]
VCCP[15]
VCC[050]
VCCP[16]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCCSENSE
VCC[066]
VCC[067]
VSSSENSE
PZ47903-2741-01
C31
C25
0.1U
0.1U
VCC[68]
VCC[69]
VCC[70]
VCC[71]
VCC[72]
VCC[73]
VCC[74]
VCC[75]
VCC[76]
VCC[77]
VCC[78]
VCC[79]
VCC[80]
VCC[81]
VCC[82]
VCC[83]
VCC[84]
VCC[85]
VCC[86]
VCC[87]
VCC[88]
VCC[89]
VCC[90]
VCC[91]
VCC[92]
VCC[93]
VCC[94]
VCC[95]
VCC[96]
VCC[97]
VCC[98]
VCC[99]
VCCA
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
C26
0.1U
4
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
V6
G21
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
AD6
AF5
AE5
AF4
AE3
AF2
AE2
AF7
AE7
C30
0.1U
3
VCC_COREVCC_CORE
C34
0.1U
+1.05V
VCC_CORE
+1.5V
H_VID0 39
H_VID1 39
H_VID2 39
H_VID3 39
H_VID4 39
H_VID5 39
H_VID6 39
Use 1% R
C33
0.1U
+
+1.5V
+1.05V
C28
330U/2.5V/ESR-9/POS
VCC_CORE
+1.05V 14,17,38,42
VCC_CORE 34
+1.5V 15,17,33
ESR :12m ohm
+1.5V
C320
C313
10U/X6S
0.01U
R11
100/F
VCCSENSE 39
VSSSENSE 39
Connect to PWM , special layout
R12
100/F
U7D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
VSS[007]
A26
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080]
P3
VSS[081]
PZ47903-2741-01
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
AF3
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF24
2
1
PROJECT : CT6
reserve dummy cap--Allen
5
Size Document Number Rev
4
3
2
Date: Sheet
Quanta Computer Inc.
CPU(2 OF 2 )
444Friday, September 23, 2005
1
of
1AB
5
4
3
2
1
+3V
D D
LM86VCC
R271
R270
10K/B
10K/B
THERM_ALERT#16
C C
MBDATA28,35
THERM_ALERT#
Q27
RHU002N06
3
+3V
2
1 2
R370 *0
LM86_SMD
1
LM86__SMC
LM86_SMD
R263
10K/B
R261
200/B
8
7
6
4
CRB use 8.2k PH
25mils
U8
VCC
SCLK
DXP
SDA
DXN
ALERT#
GND
OVERT#
MAX6657/GMT-781
ADDRESS: 98H
C315
0.1U
10/20mils
1
2
3
5
H_THERMDA
C314
2200P/50V
H_THERMDC
SYS_SHDN#
H_THERMDA 3
H_THERMDC 3
2
Q26
2N7002E
R279 *0
+3V
R267
1M/F
3
1
2
C322
0.1U/16V_0603
3
1
Q28
2N7002E
1999_SHDN# 36
add hardware protect
Unstall R267 , Q28 , Q26 for Intel
sighting -> CPU thermal die bug
/0506
B0 stepping CPU can fix this issue
+3V
Q29
RHU002N06
B B
MBCLK28,35
2
3
LM86__SMC
1
..
A A
PROJECT : CT6
Quanta Computer Inc.
Size Document Number Rev
5
4
3
2
Date: Sheet
Thermal Sensor LM86
1
544Friday, September 23, 2005
of
1AB
5
H_XRCOMP
R43
24.9/F/B
D D
+1.05V
+1.05V
R46
54.9/F/B
15 mils/10mils
H_XSCOMP
H_D#[63:0]3
Use 1% R
R47
221/F/B
H_XSWING
C C
B B
A A
+1.05V
+1.05V
R48
100/F/B
R39
54.9/F/B
H_YSCOMP
R40
221/F/B
H_YSWING
R41
100/F/B
H_YRCOMP
R42
24.9/F/B
C67
0.1U
C63
0.1U
15 mils/10mils
Use 1% R
CLK_MCH_BCLK2
CLK_MCH_BCLK#2
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
Short Stub < 100mils
extract from same point
T20 PAD
T16 PAD
4
K11
T10
W11
U11
T11
AB7
AA9
Y10
AB8
AA4
AA7
AA2
AA6
AA10
AA1
AB4
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5
AD10
AD4
AC8
AG2
AG1
F1
J1
H1
J6
H3
K2
G1
G2
K9
K1
K7
J8
H4
J3
G4
T3
U7
U9
W9
T1
T8
T4
W7
U5
T9
W6
T5
W4
W3
Y3
Y7
W5
W2
Y8
E1
E2
E4
Y1
U1
W1
U14A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
H_CLKIN
H_CLKIN#
Calistoga
HOST
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
3
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_VREF_0
H_BNR#
H_BPRI#
H_BREQ#0
H_CPURST#
H_DBSY#
H_DEFER#
H_DPWR#
H_DRDY#
H_VREF_1
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_HIT#
H_HITM#
H_LOCK#
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
H_SLPCPU#
H_TRDY#
H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14
E8
B9
C13
J13
C6
F6
C7
B7
A7
C3
J9
H8
K13
J7
W8
U3
AB10
K4
T7
Y5
AC4
K3
T6
AA5
AC5
D3
D4
B3
D8
G8
B8
F8
A8
B4
E6
D6
E3
E7
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
R264 0
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
2
H_A#[31:3] 3
H_ADS# 3
H_ADSTB#0 3
H_ADSTB#1 3
H_BNR# 3
H_BPRI# 3
H_BREQ#0 3
H_CPURST# 3
H_DBSY# 3
H_DEFER# 3
H_DPWR# 3
H_DRDY# 3
H_DINV#[3:0] 3
H_DSTBN#[3:0] 3
H_DSTBP#[3:0] 3
H_HIT# 3
H_HITM# 3
H_LOCK# 3
H_REQ#[4:0] 3
H_RS#[2:0] 3
H_CPUSLP# 3
H_TRDY# 3
+1.05V
C71
0.1U
C74
0.1U
+1.05V
+1.05V 14,17,38,42
R56
100/F/B
H_VREF
R55
200/F/B
H_VREF
1
< 0.1"
Use 1% R
H_VREF :10 mils/20 mils space
PROJECT : CT6
Quanta Computer Inc.
Size Document Number Rev
5
4
3
2
Date: Sheet
GMCH HOST(1 OF 6 )
1
644Friday, September 23, 2005
of
1AB
5
4
3
2
1
M_B_DQ[63:0]13
D D
M_A_DQ[63:0]13
C C
B B
A A
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
5
AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8
U14D
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
Calistoga
AU12
SA_BS_0
AV14
SA_BS_1
BA20
SA_BS_2
AY13
SA_CAS#
AJ33
SA_DM_0
AM35
SA_DM_1
AL26
SA_DM_2
AN22
SA_DM_3
AM14
SA_DM_4
AL9
SA_DM_5
AR3
SA_DM_6
AH4
SA_DM_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_RAS#
SA_WE#
AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5
AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5
AY16
AU14
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12
AW14
AK23
AK24
AY14
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_RCVENIN#
SA_RCVENOUT#
DDR SYSTEM MEMORY A
4
M_A_BS#0
M_A_BS#1
M_A_BS#2
M_A_CAS#
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
TP_MA_RCVENIN#
TP_MA_RCVENOUT#
M_A_BS#0 12,13
M_A_BS#1 12,13
M_A_BS#2 12,13
M_A_CAS# 12,13
M_A_DM[7:0] 13
M_A_DQS[7:0] 13
M_A_DQS#[7:0] 13
M_A_A[13:0] 12,13
M_A_RAS# 12,13
T33
PAD
T38
PAD
M_A_WE# 12,13
3
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AK39
AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3
U14E
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
Calistoga
AT24
SB_BS_0
AV23
SB_BS_1
AY28
SB_BS_2
AR24
SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
DDR SYSTEM MEMORY B
SB_WE#
AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4
AM39
AT39
AU35
AR29
AR16
AR10
AR7
AN5
AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5
AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23
AU23
AK16
AK18
AR27
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
TP_MB_RCVENIN#
TP_MB_RCVENOUT#
PROJECT : CT6
Quanta Computer Inc.
Size Document Number Rev
2
Date: Sheet
GMCH DDR(2 OF 6)
M_B_BS#0 12,13
M_B_BS#1 12,13
M_B_BS#2 12,13
M_B_CAS# 12,13
M_B_DM[7:0] 13
M_B_DQS[7:0] 13
M_B_DQS#[7:0] 13
M_B_A[13:0] 12,13
M_B_RAS# 12,13
T31
PAD
T32
PAD
M_B_WE# 12,13
744Friday, September 23, 2005
1
1AB
of
5
Check
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
D D
PAD
PAD
PAD
PAD
MCH_BSEL02
MCH_BSEL12
MCH_BSEL22
PAD
PAD
MCH_CFG_139
FROM VRD/1.05V ?
C C
DELAY_VR_PWRGOOD16,39
PLT_RST-R#15
Added -Allen
SDVO_DATA is a strap pin
B B
+3V
MCH_ICH_SYNC15
15mils/10mils
T51PAD
T42
T45
T142
T141
T27
T30
T25
T58
T46
T47
T150
T145
T144
T41
T143
T26
T138
T29PAD
T60PAD
T59PAD
T134PAD
T147PAD
T136PAD
T52PAD
T53PAD
T54PAD
T23PAD
T22PAD
T19PAD
T148PAD
T137PAD
T55PAD
T17PAD
T56PAD
T24PAD
T149PAD
T140PAD
T146PAD
T139PAD
T57PAD
T28PAD
PM_THRMTRIP#3,14
R90
PM_BMBUSY#16
PM_EXTTS#013
PM_EXTTS#116
100/F/B
T35PAD
T34PAD
R84 *10K/F/B
1.8VSUS
CLK_MCH_OE#
MCH_RSVD_1
MCH_RSVD_2
MCH_RSVD_3
MCH_RSVD_4
MCH_RSVD_5
MCH_RSVD_6
MCH_RSVD_7
MCH_RSVD_8
TV_DCONSEL0
TV_DCONSEL1
MCH_RSVD_11
MCH_RSVD_12
MCH_RSVD_13
MCH_RSVD_14
MCH_RSVD_15
MCH_CFG_3
MCH_CFG_4
MCH_CFG_5
MCH_CFG_6
MCH_CFG_7
MCH_CFG_8
MCH_CFG_9
MCH_CFG_10
MCH_CFG_11
MCH_CFG_12
MCH_CFG_13
MCH_CFG_14
MCH_CFG_15
MCH_CFG_16
MCH_CFG_17
MCH_CFG_18
MCH_CFG_19
MCH_CFG_20
RST IN# MCH
TP_MCH_NC0
TP_MCH_NC1
TP_MCH_NC2
TP_MCH_NC3
TP_MCH_NC4
TP_MCH_NC5
TP_MCH_NC6
TP_MCH_NC7
TP_MCH_NC8
TP_MCH_NC9
TP_MCH_NC10
TP_MCH_NC11
TP_MCH_NC12
TP_MCH_NC13
TP_MCH_NC14
TP_MCH_NC15
TP_MCH_NC16
TP_MCH_NC17
TP_MCH_NC18
R50
80.6/F/B
M_RCOMP#
M_RCOMP
R53
80.6/F/B
AG11
AF11
G16
G15
G18
G28
AH33
AH34
BA41
BA40
BA39
BA3
BA2
BA1
AY41
AW41
AW1
H32
T32
R32
K30
A41
A35
A34
D28
D27
K16
K18
F18
E15
F15
E18
D19
D16
E16
D15
K15
C15
H16
H15
K27
F25
H26
H28
H27
K28
C41
B41
AY1
A40
A39
F3
F7
H7
J19
J29
J18
J25
J26
G6
D1
C1
B2
A4
A3
U14B
RSVD_0
RSVD_1
RSVD_2
RSVD_3
RSVD_4
RSVD_5
RSVD_6
RSVD_7
RSVD_8
RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_14
RSVD_15
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM_BMBUSY#
PM_EXTTS#_0
PM_EXTTS#_1
PM_THRMTRIP#
PWROK
RSTIN#
SDVO_CTRLCLK
SDVO_CTRLDATA
LT_RESET#
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
+3V
CFGRSVD
PM
MISC
NC
Calistoga
R80 10K/F/B
R82 *10K/F/B
MCH_CFG_6
MCH_CFG_7
MCH_CFG_9
PM_EXTTS#0
PM_EXTTS#1
R66 *10K/F/B
R68 *10K/F/B
R59 *10K/F/B
4
SM_CK_0
SM_CK_1
SM_CK_2
SM_CK_3
SM_CK#_0
SM_CK#_1
SM_CK#_2
SM_CK#_3
SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
SM_OCDCOMP_0
SM_OCDCOMP_1
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
SM_RCOMP#
SM_RCOMP
DDR MUXINGCLKDMI
SM_VREF_0
SM_VREF_1
G_CLKIN#
G_CLKIN
D_REFCLKIN#
D_REFCLKIN
D_REFSSCLKIN#
D_REFSSCLKIN
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
R66, R68 can be deleted --Allen
AY35
AR1
AW7
AW40
AW35
AT1
AY7
AY40
AU20
AT20
BA29
AY29
AW13
AW12
AY21
AW21
AL20
AF10
BA13
BA12
AY20
AU21
AV9
AT9
AK1
AK41
AF33
AG33
A27
A26
C40
D41
AE35
AF39
AG35
AH39
AC35
AE39
AF35
AG39
AE37
AF41
AG37
AH41
AC37
AE41
AF37
AG41
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
M_CLK_DDR0 13
M_CLK_DDR1 13
M_CLK_DDR2 13
M_CLK_DDR3 13
M_CLK_DDR#0 13
M_CLK_DDR#1 13
M_CLK_DDR#2 13
M_CLK_DDR#3 13
M_CKE0 12,13
M_CKE1 12,13
M_CKE2 12,13
M_CKE3 12,13
M_CS#0 12,13
M_CS#1 12,13
M_CS#2 12,13
M_CS#3 12,13
M_OCDCOMP_0
M_OCDCOMP_1
M_ODT0 12,13
M_ODT1 12,13
M_ODT2 12,13
M_ODT3 12,13
M_RCOMP#
M_RCOMP
SMDDR_VREF_MCH
CLK_PCIE_3GPLL# 2
CLK_PCIE_3GPLL 2
DREFCLK# 2
DREFCLK 2
DREFSSCLK# 2
DREFSSCLK 2
< 0.1" . 15mils/15mils space
use 1% R
remove
it for
intel
spec
+3V
SMDDR_VREF_MCH
C631
0.1uF
PV-I modified
for fix
SMDDR_VREF_MCH
power noise
15mils/15mils
Layout as short as passable
NC from WW45
DMI_TXN[3:0] 15
S-CVBS130
S-YD130
S-CD130
DMI_TXP[3:0] 15
DMI_RXN[3:0] 15
CRT_B29
CRT_G29
CRT_R29
DMI_RXP[3:0] 15
3
R37 0/B
R36 *10K/F
C632
0.1uF
R51
*40.2/F/B
*10K/F
R44
PAD
R72
*40.2/F/B
DPST_PWM18
LCD_BLON18
EDIDCLK18
EDIDDATA18
T50
DISP_ON18
Use 1% R
Shall be 10K divider of 1.8V_SUS
R266 0/B
R269 0/B
R285 0/B
R284 150/F/B
R268 150/F/B
R265 150/F/B
< 0.1" . 15mils/15mils space
R295 0/B
R291 0/B
R287 0/B
DDCCLK29
DDCDAT29
HSYNC29
VSYNC29
RP25 0X2
TXLCLKOUT-18
TXLCLKOUT+18
TXLOUT0-18
TXLOUT0+18
3
1
RP30 0X2
1
3
SMDDR_VREF_DIMM
1.8VSUS
T44PAD
T43PAD
L_IBG
T217PAD
T218PAD
T219PAD
T220PAD
R93
1.5K/F/B
T49PAD
T39PAD
T40PAD
T48PAD
T36PAD
T37PAD
TV_COMP1
TV_Y/G1
TV_C/R1
R73 4.99K/F/B
CRT_BLUE
CRT_GREEN
CRT_RED
R286 150/F/B
R290 150/F/B
R294 150/F/B
R76 0/B
R81 0/B
39/F/B
R75
R74 255/F
R79 39/F/B
4
2
2
4
R87 0/B
L_CLKCTLA
L_CLKCTLB
EDIDCLK
EDIDDATA
L_IBG
L_VBG
DISP_ON
L_VREFH
L_VREFL
LA_CLK#
LA_CLK
LB_CLK#
LB_CLK
LA_DATAN0
LA_DATAN1
LA_DATAN2
LA_DATAP0
LA_DATAP1
LA_DATAP2
LB_DATAN0
LB_DATAN1
LB_DATAN2
LB_DATAP0
LB_DATAP1
LB_DATAP2
TVIREF
HSYNC1
CRTIREF
VSYNC1
LA_CLK#
LA_CLK
LA_DATAN0
LA_DATAP0
2
change part number ( need
to use 1% resistor )
U14C
D32
H30
H29
G26
G25
B38
C35
F32
C33
C32
A33
A32
E27
E26
C37
B35
A37
B37
B34
A36
G30
D30
F29
F30
D29
F28
A16
C18
A19
B16
B18
B19
E23
D23
C22
B22
A21
B21
C26
C25
G23
H23
J30
J20
J22
Calistoga
L_BKLTCTL
L_BKLTEN
L_CLKCTLA
L_CLKCTLB
L_DDC_CLK
L_DDC_DATA
L_IBG
L_VBG
L_VDDEN
L_VREFH
L_VREFL
LA_CLK#
LA_CLK
LB_CLK#
LB_CLK
LA_DATA#_0
LA_DATA#_1
LA_DATA#_2
LA_DATA_0
LA_DATA_1
LA_DATA_2
LB_DATA#_0
LB_DATA#_1
LB_DATA#_2
LB_DATA_0
LB_DATA_1
LB_DATA_2
TV_DACA_OUT
TV_DACB_OUT
TV_DACC_OUT
TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_IREF
CRT_VSYNC
L_CLKCTLA
L_CLKCTLB
LVDS
TV
VGA
R88 10K/F/B
R86 10K/F/B
EXP_A_COMPI
EXP_A_COMPO
EXP_A_RXN_0
EXP_A_RXN_1
EXP_A_RXN_2
EXP_A_RXN_3
EXP_A_RXN_4
EXP_A_RXN_5
EXP_A_RXN_6
EXP_A_RXN_7
EXP_A_RXN_8
EXP_A_RXN_9
EXP_A_RXN_10
EXP_A_RXN_11
EXP_A_RXN_12
EXP_A_RXN_13
EXP_A_RXN_14
EXP_A_RXN_15
EXP_A_RXP_0
EXP_A_RXP_1
EXP_A_RXP_2
EXP_A_RXP_3
EXP_A_RXP_4
EXP_A_RXP_5
EXP_A_RXP_6
EXP_A_RXP_7
EXP_A_RXP_8
EXP_A_RXP_9
EXP_A_RXP_10
EXP_A_RXP_11
EXP_A_RXP_12
EXP_A_RXP_13
EXP_A_RXP_14
EXP_A_RXP_15
EXP_A_TXN_0
EXP_A_TXN_1
EXP_A_TXN_2
EXP_A_TXN_3
EXP_A_TXN_4
EXP_A_TXN_5
EXP_A_TXN_6
EXP_A_TXN_7
EXP_A_TXN_8
EXP_A_TXN_9
EXP_A_TXN_10
EXP_A_TXN_11
EXP_A_TXN_12
PCI-EXPRESS GRAPHICS
EXP_A_TXN_13
EXP_A_TXN_14
EXP_A_TXN_15
EXP_A_TXP_10
EXP_A_TXP_11
EXP_A_TXP_12
EXP_A_TXP_13
EXP_A_TXP_14
EXP_A_TXP_15
EXP_A_TXP_0
EXP_A_TXP_1
EXP_A_TXP_2
EXP_A_TXP_3
EXP_A_TXP_4
EXP_A_TXP_5
EXP_A_TXP_6
EXP_A_TXP_7
EXP_A_TXP_8
EXP_A_TXP_9
+3V
1
20mils/20mils space
EXP_A_COMPX
D40
D38
F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38
D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38
F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40
D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40
remove N/C PIN
+V1.5_PCIE
R92 24.9/F/B
RP29 0X2
3
3
1
RP27 0X2
1
3
TXLOUT1+18
A A
+V1.5_PCIE
+3V
SMDDR_VREF
1.8VSUS
MCH_CFG_[12:5]9
MCH_CFG_[20:16]9
+V1.5_PCIE 10
+3V 5,9,13,14,15,16,17,18,22,23,26,28,29,30,31,32,33,34,36,39,41,42
SMDDR_VREF 13
1.8VSUS 13,35
MCH_CFG_[12:5]
MCH_CFG_[20:16]
5
4
TXLOUT1-18
TXLOUT2-18
TXLOUT2+18
LA_DATAP1
4
LA_DATAN1
2
LA_DATAN2
2
LA_DATAP2
4
Size Document Number Rev
2
Date: Sheet
PROJECT : CT6
Quanta Computer Inc.
GMCH DMI VEDIO(3 OF 6)
844Friday, September 23, 2005
1
of
1ACustom
5
C52
+1.05V +1.05V
330U/2.5V/ESR-9/POS
+
D D
C C
B B
A A
5
AA33
W33
N33
AA32
W32
N32
M32
AA31
W31
R31
N31
M31
AA30
W30
U30
R30
N30
M30
AA29
W29
U29
R29
M29
AB28
AA28
U28
R28
N28
M28
N27
M27
N26
N25
M25
N24
M24
AB23
AA23
N23
M23
AC22
AB22
W22
N22
M22
AC21
AA21
W21
N21
M21
AC20
AB20
W20
N20
M20
AB19
AA19
N19
M19
N18
M18
N17
M17
N16
M16
U14G
VCC_0
VCC_1
P33
VCC_2
VCC_3
L33
VCC_4
J33
VCC_5
VCC_6
Y32
VCC_7
VCC_8
V32
VCC_9
P32
VCC_10
VCC_11
VCC_12
L32
VCC_13
J32
VCC_14
VCC_15
VCC_16
V31
VCC_17
T31
VCC_18
VCC_19
P31
VCC_20
VCC_21
VCC_22
VCC_23
Y30
VCC_24
VCC_25
V30
VCC_26
VCC_27
T30
VCC_28
VCC_29
P30
VCC_30
VCC_31
VCC_32
L30
VCC_33
VCC_34
Y29
VCC_35
VCC_36
V29
VCC_37
VCC_38
VCC_39
P29
VCC_40
VCC_41
L29
VCC_42
VCC_43
VCC_44
Y28
VCC_45
V28
VCC_46
VCC_47
T28
VCC_48
VCC_49
P28
VCC_50
VCC_51
VCC_52
L28
VCC_53
P27
VCC_54
VCC_55
VCC_56
L27
VCC_57
P26
VCC_58
VCC_59
L26
VCC_60
VCC_61
VCC_62
L25
VCC_63
P24
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
Y23
VCC_69
P23
VCC_70
VCC_71
VCC_72
L23
VCC_73
VCC_74
VCC_75
Y22
VCC_76
VCC_77
P22
VCC_78
VCC_79
VCC_80
L22
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
L21
VCC_87
VCC_88
VCC_89
Y20
VCC_90
VCC_91
P20
VCC_92
VCC_93
VCC_94
L20
VCC_95
VCC_96
VCC_97
Y19
VCC_98
VCC_99
VCC_100
L19
VCC_101
VCC_102
VCC_103
L18
VCC_104
P17
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
L16
VCC_110
VCC
Calistoga
VCC_SM_100
VCC_SM_101
VCC_SM_102
VCC_SM_103
VCC_SM_104
VCC_SM_105
VCC_SM_106
VCC_SM_107
VCC_SM_0
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_SM_37
VCC_SM_38
VCC_SM_39
VCC_SM_40
VCC_SM_41
VCC_SM_42
VCC_SM_43
VCC_SM_44
VCC_SM_45
VCC_SM_46
VCC_SM_47
VCC_SM_48
VCC_SM_49
VCC_SM_50
VCC_SM_51
VCC_SM_52
VCC_SM_53
VCC_SM_54
VCC_SM_55
VCC_SM_56
VCC_SM_57
VCC_SM_58
VCC_SM_59
VCC_SM_60
VCC_SM_61
VCC_SM_62
VCC_SM_63
VCC_SM_64
VCC_SM_65
VCC_SM_66
VCC_SM_67
VCC_SM_68
VCC_SM_69
VCC_SM_70
VCC_SM_71
VCC_SM_72
VCC_SM_73
VCC_SM_74
VCC_SM_75
VCC_SM_76
VCC_SM_77
VCC_SM_78
VCC_SM_79
VCC_SM_80
VCC_SM_81
VCC_SM_82
VCC_SM_83
VCC_SM_84
VCC_SM_85
VCC_SM_86
VCC_SM_87
VCC_SM_88
VCC_SM_89
VCC_SM_90
VCC_SM_91
VCC_SM_92
VCC_SM_93
VCC_SM_94
VCC_SM_95
VCC_SM_96
VCC_SM_97
VCC_SM_98
VCC_SM_99
4
4
AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1
VCC_SM1
VCC_SM2
VCC_SM106
VCC_SM107
25mils
25mils
C146 0.47U
C145 0.47U
+
PC40
330U
2.5
C112
0.47U
place C49 on AJ23 Ball
place C51 on BA15 Ball
C77
0.47U
MCH_CFG_6 shall be PH !!
depopulate R2504 if use Calistoga
intel WW51 recommand
25mils
C64 0.47U
C65 0.47U
3
C51
330U/2.5V/ESR-9/POS
+
C116
10U/X6S
1.8VSUS
C72
10U/X6S
C125
C94
0.47U
10U/X6S
C100
place C50 on BA23 Ball
0.47U
Have to review again
ADD Matrix in silkscreen
MCH_CFG_58
MCH_CFG_68
MCH_CFG_78
MCH_CFG_98
MCH_CFG_108
MCH_CFG_118
MCH_CFG_128
MCH_CFG_138
MCH_CFG_168
MCH_CFG_188
MCH_CFG_198
MCH_CFG_208
3
C124
C87
1U
10U/X6S
10U to 1U-Allen
120mils
C73
C105
0.1U
0.1U
Why Difference ?
+1.5V_AUX10
+1.05V14,17,38,42
1.8VSUS13,35
GMCH Strap pin
R62 *2.2K/B
R70 *2.2K/B
R71 *2.2K/B
R65 *2.2K/B
R67 *2.2K/B
R63 *2.2K/B
R58 2.2K/B
R64 2.2K/B
R69 *2.2K/B
R77 1K/F/B
R85 *1K/F/B
R83 *1K/F/B
C101
C84
0.1U
+1.5V_AUX
C69
0.1U
0.1U
C68
0.1U
+1.05V
1.8VSUS
Depopulate R2504 for Calistoga-Allen
CFG_RSVD_0_R
+3V
+3V
2
AD27
AC27
AB27
AA27
Y27
W27
V27
U27
T27
R27
AD26
AC26
AB26
AA26
Y26
W26
V26
U26
T26
R26
AD25
AC25
AB25
AA25
Y25
W25
V25
U25
T25
R25
AD24
AC24
AB24
AA24
Y24
W24
V24
U24
T24
R24
AD23
V23
U23
T23
R23
AD22
V22
U22
T22
R22
AD21
V21
U21
T21
R21
AD20
V20
U20
T20
R20
AD19
V19
U19
T19
AD18
AC18
AB18
AA18
Y18
W18
V18
U18
T18
no stuff (
from intel
WW31 form
recommend )
R78
*0/B
2
AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17
AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15
1
+3V
U14F
VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72
NCTF
Calistoga
1.MCH_CFG_5 Low = DMI X2, High=DMIX4
2.MCH_CFG_6 DDR : Low =Moby Dick, High= Calistoga (Default)
3.MCH_CFG_7 CPU Strap Low=RSVD, High=Mobile CPU
4.MCH_CFG_9 PCI Exp Graphics Lane: Low =Reserved,High=Mobility
5.MCH_CFG_10 Host PLL VCC Select: Low=Reserved, High=Mobility
6.MCH_CFG_11: Low=Calistoga, High=Reserved
7.MCH_CFG_16 FSB Dynmic ODT: Low=Dynamic ODT Disabled,
High=Dynamic ODT Enabled.
8.MCH_CFG_18 VCC Select: LOW=1.05V, High=1.5V
9.MCH_CFG_19 DMI LANE Reversal:Low=Normal,High=LANES Reversed.
10.MCH_CFG_20 PCIE Backward interpoerability mode: Low= only SDVO
or PCIE x1 is operational (defaults) ,High=SDVO and PCIE x1 are
operation simultaneously via the PEG port.
VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57
PROJECT : CT6
Size Document Number Rev
Date: Sheet
Quanta Computer Inc.
GMCH PW & STRAP(4 OF 6)
1
+1.5V_AUX
944Friday, September 23, 2005
100mils
1ACustom
of
5
+1.5V +V1.5_DPLLA
L30 10uH/0805
+
L31 10uH/0805
D D
+
L9 FCM2012C-121
L10 FCM2012C-121
22U
in Capell Rev0.93
C C
C349
330U
C351
330U
C59
10U/X6S
C58
10U/X6S
R89
10
L12
FCM2012C-121
C344
0.1U
C352
0.1U
C62
0.1U
C61
0.1U
+V1.5_DPLLB
+V1.5_HPLL
+V1.5_MPLL
25mils
VCCGFOLLOW
+V3.3_TVDAC
L11
FCM2012C-121
C96
10U/0805
Oreginal FCM2012C-181
"CX000181008"
470U change to 330U
Why 1.5V is AUX ?
D2
PDZ5.6B
21
80mils
+1.05V+2.5V
+V2.5_CRTDAC
+V3.3_ATVBG
C330
0.1U
+V3.3_ATVBG
C333
0.1U
+V3.3_ATVBG
C331
0.1U
+V3.3_ATVBG
Check power plane
+V1.5_PCIE
B B
+V3.3_TVDAC +3V
A A
+1.05V
+1.5V
+V1.5_PCIE
+2.5V
+3V
Oreginal FCM2012C-181
"CX000181008"
+
60mils
R298
0/A
RC0805
C353
330U
C354
C355
10U/X6S
10U/X6S
R94
0.5/F
+1.5V_AUX +1.5V
C122
0.1U
30mils
V1_5SFOLLOW
R276
10
D11
PDZ5.6B
RC0805
R57 0/A
R617 *0/A
+1.05V 14,17,38,42
+1.5V 15,17,33
+V1.5_PCIE 8
+2.5V 34
+3V 5,9,13,14,15,16,17,18,22,23,26,28,29,30,31,32,33,34,36,39,41,42
5
L19
1uH
60mils
L18
100nH
PCIE_L
60mils
3GPLL_FB_L3GPLL_FB_R
+1.5V
3V-TV +5V
3V-TV
21
C619
*10U
R297
0/A
RC0805
R95
0/A
RC0805
C620
*0.01U
+1.5V
U41
4
BYP
*AAT3218
+1.5V+V1.5_3GPLL
GND
INOUT
EN
4
+V3.3_ATVBG
C75
0.022U
+V3.3_ATVBG
C88
0.022U
+V3.3_ATVBG
C79
0.022U
+V3.3_ATVBG
change part
number for
ME request (
hight limit
)
+3V +1.5V
C81
10U/X6S
0.002ohm/1%
+V1.5_TVDAC +1.5V
+V1.5_QTVDAC
15
2
3
C621
*1U/16V
4
+V1.5_3GPLL
C148
0.1U
+V2.5_CRTDAC
C97
0.1U
+2.5V
C144
0.01U
+V3.3_ATVBG
C328
0.1U
C106
C66
0.1U
0.1U
C99
0.022U
C86
0.022U
FCM2012C-121
C107
0.1U
FCM2012C-121
C95
0.1U
Oreginal FCM2012C-181
"CX000181008"
SI-2
modified..
reserve for
TV_OUT noise
C149
10U/X6S
C102
0.022U
C127
0.1U
C327
0.022U
L14
L13
C60
10U/X6S
V15_TVDAC_R
+2.5V
+2.5V
+V1.5_HPLL
+1.5V
+3V
40mils
+1.5V_AUX
60mils
Oreginal FCM2012C-181
"CX000181008"
3
+2.5V
C142
0.1U
+V1.5_PCIE
C121
0.1U
+V1.5_DPLLB
+V3.3_ATVBG
+V3.3_ATVBG
+V1.5_TVDAC
+V1.5_QTVDAC
R296
0/A
RC0805
3
C147
10U/X6S
+V1.5_DPLLA
+V1.5_MPLL
+V3.3_ATVBG
H22
C30
B30
A30
AJ41
AB41
Y41
V41
R41
N41
L41
AC33
G41
H41
F21
E21
G21
B26
C39
AF1
A38
B39
AF2
H20
G20
E19
F19
C20
D20
E20
F20
AH1
AH2
A28
B28
C28
D21
A23
B23
B25
H19
AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14
AG14
AF14
AE14
Y14
AF13
AE13
AF12
AE12
AD12
U14H
VCCSYNC
VCC_TXLVDS0
VCC_TXLVDS1
VCC_TXLVDS2
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_LVDS
VSSA_LVDS
VCCA_MPLL
VCCA_TVBG
VSSA_TVBG
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
VCCD_HMPLL0
VCCD_HMPLL1
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
VCCD_TVDAC
VCC_HV0
VCC_HV1
VCC_HV2
VCCD_QTVDAC
VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31
VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40
POWER
Calistoga
2
2
VTT_0
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VTT_26
VTT_27
VTT_28
VTT_29
VTT_30
VTT_31
VTT_32
VTT_33
VTT_34
VTT_35
VTT_36
VTT_37
VTT_38
VTT_39
VTT_40
VTT_41
VTT_42
VTT_43
VTT_44
VTT_45
VTT_46
VTT_47
VTT_48
VTT_49
VTT_50
VTT_51
VTT_52
VTT_53
VTT_54
VTT_55
VTT_56
VTT_57
VTT_58
VTT_59
VTT_60
VTT_61
VTT_62
VTT_63
VTT_64
VTT_65
VTT_66
VTT_67
VTT_68
VTT_69
VTT_70
VTT_71
VTT_72
VTT_73
VTT_74
VTT_75
VTT_76
1
+1.05V
AC14
AB14
W14
V14
T14
R14
P14
N14
M14
L14
AD13
AC13
AB13
AA13
Y13
W13
V13
U13
T13
R13
N13
M13
L13
AB12
AA12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
L12
R11
P11
N11
M11
R10
P10
N10
M10
P9
N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
D2
AB1
R1
P1
N1
M1
Shall Add more bypass caps for 1.05V
C622 0.47U/X5R
add 0.47uf cap on
pin A6 , D2 , AB1
for intel recommend
C630 0.22U/X5R
C623 0.47U/X5R
C53
330U/2.5V/ESR-9/POS
+
C126
0.22U
C111
4.7U/6.3V/0805
C118
0.22U
C113
2.2U/6.3V
+2.5V
C133
0.1U
PROJECT : CT6
Quanta Computer Inc.
Size Document Number Rev
Date: Sheet
GMCH POWER (5 OF 6)
1
+1.05V
C108
0.1U
C117
0.47U/X5R
C123
4.7U
10 44Friday, September 23, 2005
+1.05V
C98
10U/X6S
C76
0.47U/X5R
of
1ACustom
5
4
3
2
1
U14I
AC41
VSS_0
AA41
VSS_1
W41
VSS_2
T41
VSS_3
P41
VSS_4
M41
VSS_5
J41
VSS_6
F41
VSS_7
AV40
VSS_8
D D
C C
B B
A A
5
AP40
AN40
AK40
AJ40
AH40
AG40
AF40
AE40
B40
AY39
AW39
AV39
AR39
AN39
AJ39
AC39
AB39
AA39
Y39
W39
V39
R39
P39
N39
M39
H39
G39
D39
AT38
AM38
AH38
AG38
AF38
AE38
C38
AK37
AH37
AB37
AA37
Y37
W37
V37
R37
P37
N37
M37
H37
G37
D37
AY36
AW36
AN36
AH36
AG36
AF36
AE36
AC36
C36
B36
BA35
AV35
AR35
AH35
AB35
AA35
Y35
W35
V35
R35
P35
N35
M35
H35
G35
D35
AN34
T39
L39
J39
F39
T37
L37
J37
F37
T35
L35
J35
F35
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
Calistoga
VSS
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
4
AK34
AG34
AF34
AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
3
AT23
AN23
AM23
AH23
AC23
W23
K23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21
AN21
AL21
AB21
Y21
P21
K21
H21
C21
AW20
AR20
AM20
AA20
K20
B20
A20
AN19
AC19
W19
K19
G19
C19
AH18
P18
H18
D18
A18
AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
F16
C16
AN15
AM15
AK15
N15
M15
L15
B15
A15
BA14
AT14
AK14
AD14
AA14
U14
K14
H14
E14
AV13
AR13
AN13
AM13
AL13
AG13
P13
F13
D13
B13
AY12
AC12
K12
H12
E12
AD11
AA11
Y11
U14J
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
J23
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
J21
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
J16
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS
Calistoga
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
J11
D11
B11
AV10
AP10
AL10
AJ10
AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1
PROJECT : CT6
Quanta Computer Inc.
Size Document Number Rev
2
Date: Sheet
GMCH GND(6 OF 6)
of
11 44Friday, September 23, 2005
1
1ACustom
1
2
3
4
5
6
7
8
DDRII DUAL CHANNEL A,B.
A A
DDRII A CHANNEL DDRII B CHANNEL
SMDDR_VTERM
C135
0.1U
C90
0.1U
SMDDR_VTERM
C136
C134
0.1U
0.1U
M_A_A[13..0] M_B_A[13..0]
SMDDR_VTERM
C91
C119
0.1U
0.1U
M_A_A[13..0] 7 M_B_A[13..0] 7
C104
0.1U
SMDDR_VTERM 34,37
C115
C109
0.1U
0.1U
C130
0.1U
C129
0.1U
C89
0.1U
C103
0.1U
SMDDR_VTERM
C114
0.1U
C128
0.1U
C132
0.1U
C93
0.1U
C110
0.1U
1.8VSUS
+3V
C120
0.1U
C131
0.1U
1.8VSUS 13,35
+3V 5,9,13,14,15,16,17,18,22,23,26,28,29,30,31,32,33,34,36,39,41,42
C138
0.1U
C137
0.1U
C83
0.1U
C82
0.1U
C80
0.1U
C85
0.1U
Layout note: Place one cap close to every 2 pullup resistors terminated to SMDDR_VTERM
B B
CGCLK_SMB2,13,33
CGDAT_SMB2,13,33
PM_EXTTS#013
M_ODT0
M_A_A13
M_A_A7
M_A_A5
M_A_A3
M_A_A1
M_A_A11
M_CKE1
M_A_A10
M_A_BS#0
M_A_A8
M_A_A6
M_A_A2
M_A_A4
M_A_A0
M_A_BS#1
M_A_A12
M_A_A9
M_A_CAS#
M_CS#1
PM_EXTTS#1PM_EXTTS#1
M_ODT08
M_CKE18
M_A_BS#07
M_A_BS#17
C C
D D
PM_EXTTS#116
Allen
1
M_A_CAS#7
M_CS#18
RP1 56X2
RP20 56X2
RP14 56X2
RP23 56X2
RP12 56X2
RP17 56X2
RP15 56X2
RP10 56X2
RP22 56X2
RP5 56X2
CGCLK_SMB
CGDAT_SMB
PM_EXTTS#0
R628 *0/B
2
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
U3
8
SCLK
7
SDA
6
ALERT#
4
OVERT#
*LM86CIMM
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
VCC
DXP
DXN
GND
1
2
3
5
3
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
R262
*200/B
LM86_3V
+3V
C321
*0.1U
DDR_THERMDA
DDR_THERMDC
Uninstall
13
Q8
2
*PMST3904
4
M_B_BS#17
M_CKE28
M_B_BS#27
M_CS#38
M_B_RAS#7
M_B_WE#7
M_B_CAS#7
M_B_BS#07
5
M_A_RAS#7
M_A_BS#27
M_CS#08
M_ODT28
M_ODT38
M_A_WE#7
M_ODT18
M_CKE38
M_CS#28
M_CKE08
M_B_A0
M_B_BS#1
M_B_A3
M_B_A1
M_B_A12
M_B_A5
M_B_A2
M_B_A4
M_B_A8
M_B_A9
M_B_A6
M_B_A11
M_CKE2
M_B_BS#2
M_CS#3
M_B_RAS#
M_B_WE#
M_B_CAS#
M_B_A10
M_B_BS#0
RP9 56X2
1
3
RP13 56X2
1
3
RP18 56X2
1
3
RP16 56X2
1
3
RP21 56X2
1
3
RP19 56X2
1
3
RP26 56X2
1
3
RP7 56X2
1
3
RP6 56X2
1
3
RP11 56X2
1
3
M_A_RAS#
M_CS#0
M_ODT2
M_B_A13
M_ODT3
M_CS#2
M_A_WE#
M_ODT1
M_B_A7
M_CKE3
M_A_BS#2
M_CKE0
6
RP8 56X2
RP3 56X2
RP2 56X2
RP4 56X2
RP24 56X2
RP28 56X2
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
1
3
1
3
1
3
1
3
1
3
1
3
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
2
4
2
4
2
4
2
4
2
4
2
4
SMDDR_VTERM
PROJECT : CT6
Quanta Computer Inc.
Size Document Number Rev
Date: Sheet
7
DDR RES. ARRAY
12 44Friday, September 23, 2005
of
8
1AB
1
+3V
1.8VSUS SMDDR_VREF_DIMM
A A
B B
C C
D D
+3V 2,5,8,9,10,12,14,15,16,17,18,22,23,28,29,30,31,32,33,34,36,39,41,42
1.8VSUS 8,9,35,37
M_A_DQ1
M_A_DQ5
M_A_DQS#0
M_A_DQS0
M_A_DQ2
M_A_DQ3
M_A_DQ12
M_A_DQ8 M_A_DM1
M_A_DQS#1
M_A_DQS1
M_A_DQ9
M_A_DQ15
M_A_DQ21
M_A_DQ17
M_A_DQS#2
M_A_DQS2
M_A_DQ23
M_A_DQ19
M_A_DQ24
M_A_DQ25
M_A_DM3
M_A_DQ26
M_A_DQ27
M_CKE08 M_CKE28 M_CKE3 8
M_A_BS#27
M_A_BS#07
M_A_WE#7
M_A_CAS#7
M_CS#18
M_ODT18
M_CKE0
M_A_BS#2
M_A_A12
M_A_A9
M_A_A8
M_A_A5
M_A_A3
M_A_A1
M_A_A10
M_A_BS#0
M_A_WE#
M_A_CAS#
M_CS#1
M_ODT1
M_A_DQ35
M_A_DQS#4
M_A_DQS4
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DM5
M_A_DQ42
M_A_DQ46
M_A_DQ48
M_A_DQ49
M_A_DQS#6
M_A_DQS6
M_A_DQ50
M_A_DQ56
M_A_DQ60
M_A_DM7
M_A_DQ62
CGCLK_SMB
+3V
1
SMDDR_VREF_DIMM
1.8VSUS
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
1
3
5
7
9
2
CN14
VREF
VSS47
DQ0
DQ1
VSS37
DQS#0
DQS0
VSS48
DQ2
DQ3
VSS38
DQ8
DQ9
VSS49
DQS#1
DQS1
VSS39
DQ10
DQ11
VSS50
VSS18
DQ16
DQ17
VSS1
DQS#2
DQS2
VSS19
DQ18
DQ19
VSS22
DQ24
DQ25
VSS23
DM3
NC4
VSS9
DQ26
DQ27
VSS4
CKE0
VDD7
NC1
A16_BA2
VDD9
A12
A9
A8
VDD5
A5
A3
A1
VDD10
A10/AP
BA0
WE#
VDD2
CAS#
S1#
VDD3
ODT1
VSS11
DQ32
DQ33
VSS26
DQS#4
DQS4
VSS2
DQ34
DQ35
VSS27
DQ40
DQ41
VSS29
DM5
VSS51
DQ42
DQ43
VSS40
DQ48
DQ49
VSS52
NCTEST
VSS30
DQS#6
DQS6
VSS31
DQ50
DQ51
VSS33
DQ56
DQ57
VSS3
DM7
VSS34
DQ58
DQ59
VSS14
SDA
SCL
VDD(SPD)
DDR2_SODIMM
CLOCK 0,1 CLOCK 3,4
VSS46
VSS15
VSS16
VSS17
VSS53
VSS41
VSS54
VSS20
VSS21
VSS24
VSS25
DQS#3
DQS3
VSS10
PC4800 DDR2
VDD11
VDD12
VSS12
VSS28
VSS42
VSS55
VSS43
DQS#5
DQS5
VSS56
VSS44
VSS57
VSS45
VSS32
VSS35
DQS#7
DQS7
VSS36
VSS13
H 5.2 H 9.2
2
1.8VSUS 1.8VSUS 1.8VSUS
2
4
DQ4
6
DQ5
8
10
DM0
12
VSS5
14
DQ6
16
DQ7
18
20
DQ12
22
DQ13
24
26
DM1
28
30
CK0
32
CK0#
34
36
DQ14
38
DQ15
40
42
44
DQ20
46
DQ21
48
VSS6
50
NC3
52
DM2
54
56
DQ22
58
DQ23
60
62
DQ28
64
DQ29
66
68
70
72
74
DQ30
76
DQ31
78
VSS8
80
CKE1
82
SDRAM SO-DIMM
(200P)
VDD8
84
A15
86
A14
88
90
A11
92
A7
94
A6
96
VDD4
98
A4
100
A2
102
A0
104
106
BA1
108
RAS#
110
S0#
112
VDD1
114
ODT0
116
A13
118
VDD6
120
NC2
122
124
DQ36
126
DQ37
128
130
DM4
132
134
DQ38
136
DQ39
138
140
DQ44
142
DQ45
144
146
148
150
152
DQ46
154
DQ47
156
158
DQ52
160
DQ53
162
164
CK1
166
CK1#
168
170
DM6
172
174
DQ54
176
DQ55
178
180
DQ60
182
DQ61
184
VSS7
186
188
190
192
DQ62
194
DQ63
196
198
SA0
200
SA1
M_A_DQ4
M_A_DQ0
M_A_DM0
M_A_DQ7
M_A_DQ6
M_A_DQ13
M_A_DQ14
M_CLK_DDR0
M_CLK_DDR#0
M_A_DQ10 M_B_DQ14
M_A_DQ11
M_A_DQ20
M_A_DQ16
PM_EXTTS#0 PM_EXTTS#0
M_A_DM2
M_A_DQ18
M_A_DQ22
M_A_DQ29
M_A_DQ28
M_A_DQS#3
M_A_DQS3
M_A_DQ30
M_A_DQ31
M_A_A11
M_A_A7
M_A_A6
M_A_A4
M_A_A2
M_A_A0
M_A_BS#1
M_A_RAS#
M_CS#0
M_ODT0
M_A_A13
M_A_DQ32
M_A_DQ36M_A_DQ37
M_A_DM4
M_A_DQ33
M_A_DQ34
M_A_DQ44
M_A_DQ45
M_A_DQS#5
M_A_DQS5
M_A_DQ43
M_A_DQ47
M_A_DQ52
M_A_DQ53
M_CLK_DDR1
M_CLK_DDR#1
M_A_DM6
M_A_DQ54
M_A_DQ55M_A_DQ51
M_A_DQ61
M_A_DQ57
M_A_DQS#7
M_A_DQS7
M_A_DQ59M_A_DQ58
M_A_DQ63
R32 10K/B
R31 10K/B
M_CKE1
3
M_CLK_DDR0 8
M_CLK_DDR#0 8
M_CKE1 8
M_A_BS#1 7
M_A_RAS# 7
M_CS#0 8
M_ODT0 8
M_CLK_DDR1 8
M_CLK_DDR#1 8
3
M_A_DM[0..7] 7
M_A_DQ[0..63] 7
M_A_DQS[0..7] 7
M_A_DQS#[0..7] 7
PM_EXTTS#0 8,12
4
SMDDR_VREF_DIMM
CN15
1
VREF
3
M_B_DQ0
M_B_DQ5
M_B_DQS#0
M_B_DQS0
M_B_DQ7
M_B_DQ3
M_B_DQ9
M_B_DQ8 M_B_DM1
M_B_DQS#1
M_B_DQS1
M_B_DQ11
M_B_DQ10
M_B_DQ20
M_B_DQ17
M_B_DQS#2
M_B_DQS2
M_B_DQ19
M_B_DQ23
M_B_DQ29
M_B_DQ28
M_B_DM3
M_B_DQ31
M_B_DQ30
M_CKE2
M_B_BS#27
M_B_BS#07
M_B_WE#7
M_B_CAS#7
M_CS#38
M_ODT38
CGDAT_SMB2,12,33
CGCLK_SMB2,12,33
M_B_BS#2
M_B_A12
M_B_A9
M_B_A8
M_B_A5
M_B_A3
M_B_A1
M_B_A10
M_B_BS#0
M_B_WE#
M_B_CAS#
M_CS#3
M_ODT3
M_B_DQ37
M_B_DQ33
M_B_DQS#4
M_B_DQS4
M_B_DQ39
M_B_DQ35
M_B_DQ41
M_B_DQ40
M_B_DM5
M_B_DQ46
M_B_DQ43
M_B_DQS#6
M_B_DQS6
M_B_DQ54
M_B_DQ60
M_B_DQ57
M_B_DM7
M_B_DQ58
M_B_DQ59
CGDAT_SMBCGDAT_SMB
CGCLK_SMB
+3V
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
VSS47
DQ0
DQ1
VSS37
DQS#0
DQS0
VSS48
DQ2
DQ3
VSS38
DQ8
DQ9
VSS49
DQS#1
DQS1
VSS39
DQ10
DQ11
VSS50
VSS18
DQ16
DQ17
VSS1
DQS#2
DQS2
VSS19
DQ18
DQ19
VSS22
DQ24
DQ25
VSS23
DM3
NC4
VSS9
DQ26
DQ27
VSS4
CKE0
VDD7
NC1
A16_BA2
VDD9
A12
A9
A8
VDD5
A5
A3
A1
VDD10
A10/AP
BA0
WE#
VDD2
CAS#
S1#
VDD3
ODT1
VSS11
DQ32
DQ33
VSS26
DQS#4
DQS4
VSS2
DQ34
DQ35
VSS27
DQ40
DQ41
VSS29
DM5
VSS51
DQ42
DQ43
VSS40
DQ48
DQ49
VSS52
NCTEST
VSS30
DQS#6
DQS6
VSS31
DQ50
DQ51
VSS33
DQ56
DQ57
VSS3
DM7
VSS34
DQ58
DQ59
VSS14
SDA
SCL
VDD(SPD)
2-1734073-2
CKE 2,3CKE 0,1
4
5
2
VSS46
4
DQ4
6
DQ5
8
VSS15
10
DM0
12
VSS5
14
DQ6
16
DQ7
18
VSS16
20
DQ12
22
DQ13
24
VSS17
26
DM1
28
VSS53
30
CK0
32
CK0#
34
VSS41
36
DQ14
38
DQ15
40
VSS54
42
VSS20
44
DQ20
46
DQ21
48
VSS6
50
NC3
52
DM2
54
VSS21
56
DQ22
58
DQ23
60
VSS24
62
DQ28
64
DQ29
66
VSS25
68
DQS#3
70
DQS3
72
VSS10
74
DQ30
76
DQ31
78
VSS8
80
CKE1
82
VDD8
84
A15
86
A14
88
VDD11
90
PC4800 DDR2
SDRAM SO-DIMM
(200P)
A11
92
A7
94
A6
96
VDD4
98
A4
100
A2
102
A0
104
VDD12
106
BA1
108
RAS#
110
S0#
112
VDD1
114
ODT0
116
A13
118
VDD6
120
NC2
122
VSS12
124
DQ36
126
DQ37
128
VSS28
130
DM4
132
VSS42
134
DQ38
136
DQ39
138
VSS55
140
DQ44
142
DQ45
144
VSS43
146
DQS#5
148
DQS5
150
VSS56
152
DQ46
154
DQ47
156
VSS44
158
DQ52
160
DQ53
162
VSS57
164
CK1
166
CK1#
168
VSS45
170
DM6
172
VSS32
174
DQ54
176
DQ55
178
VSS35
180
DQ60
182
DQ61
184
VSS7
186
DQS#7
188
DQS7
190
VSS36
192
DQ62
194
DQ63
196
VSS13
198
SA0
200
SA1
5
M_B_DQ4
M_B_DQ1
M_B_DM0
M_B_DQ2
M_B_DQ6
M_B_DQ12
M_B_DQ13
M_CLK_DDR3
M_CLK_DDR#3
M_B_DQ15
M_B_DQ16
M_B_DQ21
M_B_DM2
M_B_DQ18
M_B_DQ22
M_B_DQ24
M_B_DQ25
M_B_DQS#3
M_B_DQS3
M_B_DQ26
M_B_DQ27
M_CKE3
M_B_A11
M_B_A7
M_B_A6
M_B_A4
M_B_A2
M_B_A0
M_B_BS#1
M_B_RAS#
M_CS#2
M_ODT2
M_B_A13
M_B_DQ32
M_B_DQ36
M_B_DM4
M_B_DQ34
M_B_DQ38
M_B_DQ44
M_B_DQ45
M_B_DQS#5
M_B_DQS5
M_B_DQ47
M_B_DQ42
M_B_DQ52M_B_DQ53
M_B_DQ48M_B_DQ49
M_CLK_DDR2
M_CLK_DDR#2
M_B_DM6
M_B_DQ55M_B_DQ51
M_B_DQ50
M_B_DQ56
M_B_DQ61
M_B_DQS#7
M_B_DQS7
M_B_DQ62
M_B_DQ63
R34 10K/B
R33 10K/B
+3V
SMbus address A4SMbus address A0
6
M_B_DM[0..7] 7
M_B_DQ[0..63] 7
M_B_DQS[0..7] 7
M_B_DQS#[0..7] 7
M_B_A[0..13] 7M_A_A[0..13] 7
M_CLK_DDR3 8
M_CLK_DDR#3 8
PM_EXTTS#0 8,12
PV-I modified for
intel recommend
M_B_BS#1 7
M_B_RAS# 7
M_CS#2 8
M_ODT2 8
M_CLK_DDR2 8
M_CLK_DDR#2 8
6
7
1.8VSUS
Place these Caps near So-Dimm1.
C336
C348
2.2U
1.8VSUS
Place these Caps near So-Dimm1.
C340
0.1U
SMDDR_VREF_DIMM
C155
0.1U
2.2U
C347
0.1U
C153
2.2U
C345
2.2U
C604
0.1U
+3V
C55
2.2U
C605
0.1U
8
C635
0.1U
C56
0.1U
Place these Caps near So-Dimm1.
No Vias Between the Trace of PIN to
CAP.
1.8VSUS
Place these Caps near So-Dimm2.
C343
C337
2.2U
C341
0.1U
C156
2.2U
C350
2.2U
C606
0.1U
+3V
C57
2.2U
C92
0.1U
C54
0.1U
C637
0.1U
2.2U
1.8VSUS
Place these Caps near So-Dimm2
C346
0.1U
SMDDR_VREF_DIMM
C157
0.1U
Place these Caps near So-Dimm2.
No Vias Between the Trace of PIN to
CAP.
R121
*10K/F
SMDDR_VREF_DIMM
Add for memory margin --Allen /0228
R115
R119 0/B
*10K/F
SMDDR_VREF 8,37
1.8VSUS
PROJECT : CT6
Size Document Number Rev
Date: Sheet
Quanta Computer Inc.
DDR SO-DIMM(200P)
7
13 44Friday, September 23, 2005
of
8
C636
0.1U
C638
0.1U
1ACustom
5
D4
CH500H-40
D5
CH500H-40
R189 1K
R383
8.2K
INTVRMEN
1
0
VCCRTC
+3V
R384
10K
R388
4.7K
VCCRTC
R198
20K
R207
1M/F
VCCRTC
C229
1U/16V
VCCRTC_3VCCRTC_1
SATA_LED#
CKL:1n ~ 20nF
CLK_PCIE_SATA#2
CLK_PCIE_SATA2
25mils/15mils
PDIORDY
IRQ14
R206
332K
ICH_INTVRMEN
R205
*0/F
RTC
3VPCU
VCCRTC_2
R196
D D
5VPCU
C C
B B
A A
1K
12
BT1
BAT_CONN
20MIL 20MIL
R190 1.2K
R201
4.7K
R203
15K
add RTC Bat rechargeable circuit
SATA_LED#26
Review current rating
+3V
ICH7 internal VR
enable strap
Enable
(default)
Disable
12
C220
1U/16V
Q18
MMBT3904
2
Internal PU
SATA_RXN032
SATA_RXP032
SATA_TXN032
SATA_TXP032
Place near to Mini-door
G1
SHORT_ PAD1
Internal PU
LAN_EEP_CS25
LAN_EEP_SK25
LAN_EEP_DOUT25
LAN_EEP_DIN25
13
LAN_RSTSYNC25
C219 3900P
C225 3900P
C471 3900P
C466 3900P
T225PAD
T226PAD
T227PAD
T228PAD
R419 24.9/F
Place within 500
mils of ICH7
4
CKL:C1/C2: 18pF -> CL:12.5pF
C1/C: 10pF -> CL Value =
8.5pF
change footprint for SMT request
CLK_32KX1
C254
18P
23
R204
10M
4 1
CLK_32KX2
RTCRST#
SM_INTRUDER#
ICH_INTVRMEN
LAN_EEP_CS
LAN_EEP_SK
LAN_EEP_DOUT
LAN_EEP_DIN
LAN_JCLK
LAN_RSTSYNC
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
ACZ_BCLK
ACZ_SYNC
ACZ_RST#
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
ACZ_SDOUT
SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_C
SATA_TXP0_C
SATA_RXN2_C
SATA_RXP2_C
SATA_TXN2_C
SATA_TXP2_C
SATA_BIAS
IRQ14
PDIORDY
AB1
AB2
AA3
Y5
W4
W1
Y1
Y2
W3
V3
U3
U5
V4
T5
U7
V6
V7
U1
R6
R5
T2
T3
T1
T4
AF18
AF3
AE3
AG2
AH2
AF7
AE7
AG6
AH6
AF1
AE1
AH10
AG10
AF15
AH15
AF16
AH16
AG16
AE15
PM_THRMTRIP# THERM_CPUDIE_L#
LAN_JCLK25
LAN_RXD025
LAN_RXD125
LAN_RXD225
LAN_TXD025
LAN_TXD125
LAN_TXD225
PDIORDY32
PDDREQ32
ACZ_SDIN022
PDIOR#32
PDIOW#32
PDDACK#32
IRQ1432
32.768KHZ
C244
18P
Y2
T118
T188
U19A
RTXC1
RTCX2
RTCRST#
INTRUDER#
INTVRMEN
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN
LAN_CLK
LAN_RSTSYNC
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
ACZ_BIT_CLK
ACZ_SYNC
ACZ_RST#
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
ACZ_SDOUT
SATALED#
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA_CLKN
SATA_CLKP
SATARBIASN
SATARBIASP
DIOR#
DIOW#
DDACK#
IDEIRQ
IORDY
DDREQ
ICH7-M
RTCLAN
AC-97/AZALIA
SATA
IDE
+1.05V
R141
*1K
2
1 3
Q14
*MMBT3904
LPCCPU
3V_S5
3
LDRQ1#/GPIO23
LFRAME#
A20GATE
CPUSLP#
TP1/DPRSTP#
TP2/DPSLP#
GPIO49/CPUPWRGD
INIT3_3V#
STPCLK#
THERMTRIP#
R451
10K
LAD0
LAD1
LAD2
LAD3
LDRQ0#
A20M#
FERR#
IGNNE#
INIT#
INTR
RCIN#
SMI#
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
DCS1#
DCS3#
NMI
DA0
DA1
DA2
AA6
AB5
AC4
Y6
AC3
AA5
AB3
AE22
AH28
AG27
AF24
AH25
AG26
AG24
AG22
AG21
AF22
AF25
AG23
AH24
AF23
AH22
AF26
AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15
AH17
AE17
AF17
AE16
AD16
R136
0/F
LDRQ#0
LDRQ#1
GATEA20
TP_H_CPUSLP#
H_DPRSTP#_R
H_DPSLP#_R
T170
RCIN#
H_SMI#_R
H_THERMTRIP_R
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
PDA0
PDA1
PDA2
LAD0 28,33
LAD1 28,33
LAD2 28,33
LAD3 28,33
LDRQ#0 28
T107
LFRAME# 28,33
GATEA20 28
H_A20M# 3
R139 *0/F
R351 *0/F
R357 0/F
R152 0/F
THERM_CPUDIE# 28
PDD[15:0] 32
PDA[2:0] 32
PDCS1# 32
PDCS3# 32
2
R5506 close to MCH
H_CPUSLP# 3
H_PWRGD 3
H_IGNNE# 3
H_INIT# 3
H_INTR 3
RCIN# 28
H_NMI 3
H_SMI# 3
H_STPCLK# 3
+1.05V
R159
R348
*56/F
*56/F
R153 *0/F
H_DPSLP# 3
R145 24.9/F
Should be 2" close ICH7
O ohm ?
ACZ_SDOUT
ACZ_SYNC
ACZ_BCLK
ACZ_RST#
R208 39/B
R209 39/B
R467 39/B
R183 39/B
RCIN#
GATEA20
+3V
R358
10K
+1.05V
ICH_DPRSTP# 3
+1.05V
R140
56/F
C257
*10P
C258
*10P
C495
*10P
1
+3V
R363
10K
R150
56/F
H_FERR# 3
PM_THRMTRIP# 3,8
ACZ_SDOUT_AUDIO 22
ACZ_SYNC_AUDIO 22
BIT_CLK_AUDIO 22
ACZ_RST#_AUDIO 22
PROJECT : CT6
Size Document Number Rev
Date: Sheet of
5
4
3
2
Quanta Computer Inc.
ICH7-M HOST (1 OF 4)
14 44Friday, September 23, 2005
1
1ACustom
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