Quanta CT3 Schematic
1
2
3
4
5
6
7
8
PCB STACK UP
CT3 BLOCK DIAGRAM
LAYER 1 : TOP
LAYER 2 : GND
LAYER 3 : IN1
A A
LAYER 4 : IN2
LAYER 5 : VCC
LAYER 6 : BOT
CPU THERMAL
SENSOR
MAX6657 / GMT-781
+3V
PAGE: 3
VCC_CORE
VCCP
VCCA
PCB THICKNESS: 1.2mm
CRT port
LCD Panel
B B
MINI-DIN
PAGE: 30
PAGE: 15
PAGE: 32
R.G,B
LVDS
S-VIDEO
Processor
Intel Pentium-M
Intel Celeron-M
478 Pins (micro FC-PGA)
FSB
400/533 MHZ
Alviso-GM
GMCH
VCCP
2.5VSUS
+1.5V
+2.5V
+3V
DMI interface
82875GM/GME
1257 PCBGA
PAGE: 3, 4
PAGE: 5, 6, 7
32.768KHz
DDR I/F 2.5V
333MHz
Single Channel
HCLK_CPU
HCLK_CPU#
HCLK_MCH
HCLK_MCH#
SRC_MCH
SRC_MCH#
SRC_ICH
SRC_ICH#
DREFSSCLK
DREFSSCLK#
DOT96
DOT96#
100MHZ
100MHZ
100MHZ
100MHZ
100MHZ
96MHZ
CLOCK GEN
+3V
DDR-SODIMM1
2.5VSUS
SMDDR_VTERM
DDR-SODIMM2
PENTIUM-M / ALVISO / ICH6-M
14.318MHz
ICS954206A
CY28411ZXC
PAGE: 2
PAGE: 13
33MHZ
33MHZ
33MHZ
33MHZ
33MHZ
48MHZ
14MHZ
PCLK_591
PCLK_7411
PCLK_ICH
PCLK_MINI
PCLK_LAN
CLK48_USB
14M_ICH
SYSTEM POWER MAX1845
2.5VSUS/1.5V_S5
CPU CORE MAX1907
POWER 1.356V
SYSTEM POWER MAX1999
POWER(3V/5V/15V)
SYSTEM POWER MAX1992
VCCP
NS L2996
VTT_DDR
BATT CHARGER
MAX1772
PAGE: 38
PAGE: 33
PAGE: 36
PAGE: 37
PAGE: 39
PAGE: 34
100MHZ 4X
DISCHARGE
USB PORT 0, 1
1st IDE - HDD
2nd IDE - CDROM
C C
CABLE DOCK
PAGE: 31
AV BOARD
PAGE: 32
PAGE: 19
PAGE: 28
PAGE: 28
Daughter Board
TV, USB, BLUE
TOOTH
PAGE: 32
Power Board
PAGE: 32
USB 2.0
ATA 66/100
ATA 66/100
+5V
5VSUS
+3V
3V_S5
3VSUS
+2.5V
+1.5V
1.5V_S5
VCCRTC
GMCH_VTT
32.768KHz
3VPCU
+3V
VCCRTC
ICH6-M
82801FBM
609 BGA
PAGE: 8, 9, 10
3.3V LPC, 33MHz
PC97551
TQFP 176
PAGE: 27
33MHZ, 3.3V PCI
AC97
PWRCLKP
PWRCLKN
DIB_DATAN
DIB_DATAP
SMARTDAA
MODEM,
MDC
PAGE: 22
WIRE
24.576MHz
AC97
CX20468-31
MBAMC20493-010
PAGE: 20
AMP
TPA0312
PAGE: 21
25MHz
LANVCC
LAN
Realtek
8100CL
PAGE: 23
RJ45
JACK
PAGE: 24
24.576MHz
MINI-PCI
+3V
+5V
LANVCC 3VSUS
PAGE: 14
CARDBUS / IEEE 1394
CONTROLLER/CF
5 IN 1
CARD
READER
Intel WLAN
W2200
802.11b/g
SD/MMC,
SM, MS,
XD
PAGE: 18
TI 7411
PAGE: 16, 17, 18, 19
CARDBUS
SLOT X1
PAGE: 16
PCI DEVICES IRQ ROUTING
DEVICE
GBIT ETHERNET
D D
MINIPCI SLOT
CardBus/1394
IDSEL #
AD16
AD22
AD25
REQ/GNT #
2
1
0
PCI_INT
A
C,D
E,F,G
FAN
Touchpad
Keyboard
PAGE: 32
FLASH
PAGE: 26PAGE: 32PAGE: 30
RJ11
JACK
PAGE: 24
JACK
HEADPHONE,
2ND HEADPHONE,
MIC
PAGE: 21
PROJECT : CT3
PAGE: 35
48MHz
1394
CONN
PAGE: 19
Quanta Computer Inc.
Size Document Number Rev
1
2
3
4
5
6
Date: Sheet
7
BLOCK DIAGRAM
of
142Friday, March 04, 2005
8
1ACustom
1
2
3
4
5
6
7
8
+3V
A A
+3V
B B
L51
ACB2012L-120
120 ohms@100Mhz
L52
ACB2012L-120
120 ohms@100Mhz
FSC FSB FSA CP U SRC PCI
1 0 1 100 100 33
0 0 1 133 100 33
0 1 1 166 100 33
0 1 0 200 100 33
0 0 0 266 100 33
1 0 0 333 100 33
1 1 0 400 100 33
1 1 1 RESERVED
C C
* Frequence select by CPU auto sense.
SELPSB1_CLK3
SELPSB0_CLK3
D D
CLKVDD
C637
0.1U
R438 2 . 2 R
R450 2 . 2 R
R457 1R
R469 0R
R471 0R
CLK_VDDA
CLKVDD1
CLK_VDD48
CLK_VDDREF
+3V VCCPVCCP
C638
0.1U
R466
10K
R473
*10K
C639
0.1U
C644
0.1U
C1032
C648
0.1U
0.1U
C650
0.1U
DOTHAN FSB 400
DOTHAN FSB 533
R467
*1K
R474
*0R
C640
0.1U
C645
4.7U/10V
C649
4.7U/10V
C651
4.7U/10V
C652
0.1U
R468
*1K
CG_BSEL0
CG_BSEL1
CG_BSEL2
R475
*0R
C641
0.1U
C646
0.01U_0402
R470 1K
R472 1K
SI stage:
Enable CLK48M from CKG. by
R705 for the PLL circuit of 7411,
and disable the ocsillator circuit
at PCI7411 side.
Sting 10/12/2004
CLK48M17
CLK48_USB11
+3V
Q44
2
2N7002E
PDAT_SMB11 SMBDT 13
PCLK_SMB11 SMBCK 13
MCH_BSEL1 5
MCH_BSEL2 5
3
Q45
2N7002E
3
+3V
2
C642
Iref=2.32mA,
Ioh=4*Iref
DOT965
DOT96#5
R464
10K
1
33P
C643
33P
CLK48_USB
CG_BSEL2
R465
10K
R437
*2M
CLK_EN#33
STP_PCI#11
STP_CPU#11,33
R705 22R
R444 22R
R447 4.7K
R458 475/F
DOT96
DOT96#
SMBDTSMBDTSMBDTSMBDT
SMBDTSMBDTSMBDTSMBDT
21
1
3
To DDR-SODIMMTo ICH6-M
SMBCKSMBCKSMBCK
1
PV stage:
Add C1048 for CLK48M to get better EMI
performance.
SMBCKSMBCKSMBCK
XIN
CL=20pF
Y9
14.318MHZ
XOUT
SMBCK
SMBDT
CG_BSEL0
CG_BSEL1
U18_FSC
CLK_VDDREF
CLKVDD
CLKVDD1
CLKVDD
CLK_VDD48
IREF
RP16
33X2
R_DOT96
2
R_DOT96#
4
Sting 11/29/2004
U34
50
XTAL_IN
49
XTAL_OUT
10
VTT_PWRGD#/PD
55
PCI_STOP#
54
CPU_STOP#
46
SCLK
47
SDATA
12
FSA/USB_48
16
FSB/TEST_MODE
53
FSC/TEST_SEL
48
VDD_REF
42
VDD_CPU
1
VDD_PCI_1
7
VDD_PCI_2
21
VDD_SRC0
28
VDD_SRC1
34
VDD_SRC2
11
VDD_48
39
IREF
14
DOT96
15
DOT96#
CK-410M
ICS954206A
CLK_VDDA
CK-410M
GND_48
51
13
EMI
48MHZ
CLK48_USB
CLK48M
33MHZ
PCLK_591
PCLK_7411
PCLK_ICH
PCLK_MINI
PCLK_LAN
14.318MHZ
14M_ICH
37
VDDA
GND_REF
GND_PCI_26GND_SRC29GND_CPU
GND_PCI_1
2
45
C1038 *10P
C1048 10P
C1039 *10P
C1040 *10P
C1041 *10P
C1042 *10P
C1043 *10P
C1044 *10P
38
REF
VSSA
CPU0
CPU0#
CPU1
CPU1#
CPU2_ITP/SRC7
CPU2#_ITP/SRC7#
SRC6
SRC6#
SRC5
SRC5#
SRC4
SRC4#
SRC3
SRC3#
SRC2
SRC2#
SRC1
SRC1#
SRC0
SRC0#
PCI5
PCI4
PCI3
PCI2
PCIF1
PCIF0/ITP_EN
250mA ( MAX. )
SMbus address D4
Place these termination to close CK410M.
52
44
43
41
40
36
35
33
32
31
30
26
27
24
25
22
23
19
20
17
18
5
4
3
56
9
8
14M_REF
RHCLK_CPU
RHCLK_CPU#
RHCLK_MCH
RHCLK_MCH#
RSRC_ICH
RSRC_ICH#
RSRC_MCH
RSRC_MCH#
RDREFSSCLK
RDREFSSCLK#
R_PCLK_591
R_PCLK_7411
R_PCLK_ICH
R_PCLK_MINI
R_PCLK_LAN
ITP_EN
R439 12.1/F
RP11
RP12
T131
T132
RP13 33X2
RP14 33X2
T297
T298
T133
T134
T135
T136
T137
T138
RP15
R_PCLK_LAN
0: SRCCLK=96MHZ
1: SRCCLK=100MHZ
1
3
1
3
1
3
1
3
3
1
R459 33R
R460 33R
R461 33R
R462 33R
R463 33R
R440
10K
R_PCLK_LAN
HCLK_CPU
HCLK_CPU#
HCLK_MCH
HCLK_MCH#
SRC_MCH
SRC_MCH#
SRC_ICH
SRC_ICH#
DREFSSCLK
DREFSSCLK#
DOT96
DOT96#
2
4
2
4
2
4
2
4
4
2
33X2
33X2
33X2
ITP_EN
0: SRC_7 Pair
1: CPU_2 ITP Pair
R441 10K
R442 49.9/F
R443 49.9/F
R445 49.9/F
R446 49.9/F
R448 49.9/F
R449 49.9/F
R451 49.9/F
R452 49.9/F
R453 49.9/F
R454 49.9/F
R455 49.9/F
R456 49.9/F
14M_ICH 11
HCLK_CPU 3
HCLK_CPU# 3
HCLK_MCH 5
HCLK_MCH# 5
SRC_ICH 11
SRC_ICH# 11
SRC_MCH 6
SRC_MCH# 6
DREFSSCLK 5
DREFSSCLK# 5
PCLK_591 27
PCLK_7411 17
PCLK_ICH 10
PCLK_MINI 14
PCLK_LAN 23
+3V
R469,R471
Dothan-A can remove so that the FSB frequency will be selected by
hardware setting(R474,R475, R467,R468).
Dothan-B should be populated.
1
2
3
PROJECT : CT3
Quanta Computer Inc.
Size Document Number Rev
4
5
6
Date: Sheet
7
CLOCK GENERATOR
242Friday, March 04, 2005
3ACustom
of
8
A
B
C
D
E
+3V
P4
U4
V3
R3
V2
W1
T4
W2
Y4
Y1
U1
AA3
Y3
AA2
U3
R2
P3
T2
P1
T1
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1
AE5
C2
D3
A3
C6
D1
D4
B4
R487
1K
Q46
MMBT3904
1 3
U36A
A3#
A4#
ADDR GROUP 0 ADDR GROUP 1
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
ADSTB#0
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
ADSTB#1
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
Dothan_478P
THRM_EC 27
THRM_EC
To EC --> Send FANSIG to control fan.
DEFER#
DRDY#
DBSY#
LOCK#
CONTROLXTP/ITP SIGNALS
RESET#
TRDY#
BPM#0
BPM#1
BPM#2
BPM#3
PRDY#
PREQ#
TRST#
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
THERM
ITP_CLK1
ITP_CLK0
BCLK1
BCLK0
H CLK
ADS#
BNR#
BPRI#
BR0#
IERR#
INIT#
RS0#
RS1#
RS2#
HIT#
HITM#
TCK
TDO
TMS
DBR#
TDI
N2
L1
J3
L4
H2
M2
N4
A4
B5
J2
B11
H1
K1
L2
M3
K3
K4
C8
B8
A9
C9
A10
B10
A13
C12
A12
C11
B13
A7
B17
B18
A18
C17
A15
A16
B14
B15
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
HBREQ0#
IERR#
CPUINIT#
HLOCK#
CPURST#
RS#0
RS#1
RS#2
HTRDY#
HIT#
HITM#
BPM#0
BPM#1
BPM#2
BPM#3
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
CPU_PROCHOT#
THERMDA
THERMDC
THRMTRIP#
HCLK_CPU#
HCLK_CPU
ADS# 5
BNR# 5
BPRI# 5
DEFER# 5
DRDY# 5
DBSY# 5
HBREQ0# 5
CPUINIT# 10
HLOCK# 5
CPURST# 5
RS#0 5
RS#1 5
RS#2 5
HTRDY# 5
HIT# 5
HITM# 5
T141
T142
T143
T144
T145
T146
DBR# 11
THRMTRIP# 5,10
T148
T149
HCLK_CPU# 2
HCLK_CPU 2
VCCP
VCCP
R477
56R
R476
56R
VCCP
HD#[0..63]5
HDSTBN0#5
HDSTBP0#5
HDSTBN1#5
HDSTBP1#5
DINV#15
SELPSB0_CLK2
SELPSB1_CLK2
R483 1K/F
HD#[0..63]
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HDSTBN0#
DINV#05
HDSTBP0#
HD#[0..63]
HDSTBN1#
HDSTBP1#
Layout note : 0.5" max lengt h.
R484
2K/F
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
PM_PSI#
T147
SELPSB0_CLK
SELPSB1_CLK
T150
T151
T152
T153
T154
H_GTLREF
H_GTLREF = 2/3 * VCCP +-2%
Can't shared with GMCH
G25
M26
H24
G24
M23
N24
M25
H26
N25
K25
K24
C16
C14
AF7
AC1
E26
AD26
A19
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
C23
C22
D25
H23
L23
F25
J23
J25
L26
L24
J26
E1
B2
C3
U36B
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#
PSI#
BSEL0
BSEL1
RSVD
RSVD
RSVD
RSVD
RSVD
GTLREF
Dothan_478P
DATA GRP 2 DATA GRP 3
DATA GRP 0DATA GRP 1
MISC
RSVD/DPRSTP#
PWRGOOD
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DSTBN2#
DSTBP2#
DINV2#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DSTBN3#
DSTBP3#
DINV3#
COMP0
COMP1
COMP2
COMP3
DPSLP#
DPWR#
SLP#
TEST1
TEST2
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
W25
W24
T24
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26
AE24
AE25
AD20
P25
P26
AB2
AB1
G1
B7
C19
E4
A6
C5
F23
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
COMP0
COMP1
COMP2
COMP3
DPWR#
CPUPWRGD
H_TEST1
H_TEST2
R485
*1K
HD#[0..63]
HDSTBN2#
HDSTBP2#
HD#[0..63]
HDSTBN3#
HDSTBP3#
R478 27.4/F
R479 54.9R
R480 27.4/F
R481 54.9R
H_DPRSTP# 10
H_DPSLP# 10
DPWR# 5
H_CPUSLP# 5,10
R486
*1K
HDSTBN2# 5
HDSTBP2# 5
DINV#2 5
HDSTBN3# 5
HDSTBP3# 5
DINV#3 5
VCCP
R482
200/F
CPUPWRGD 10
HA#[3..31]5
4 4
HADSTB0#5
HREQ#05
HREQ#15
HREQ#25
HREQ#35
HREQ#45
3 3
2 2
HADSTB1#5
THRMTRIP#THRMTRIP#THRMTRIP#
HA#[3..31]
HA#[3..31]
A20M#10
FERR#10
IGNNE#10
STPCLK#10
INTR10
NMI10
SMI#10
VCCP
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HADSTB0#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HADSTB1#
A20M#
FERR#
IGNNE#
STPCLK#
INTR
NMI
R488
56R
R489 330R
2
+3V
+3V +3V
+3V
R494
2
Q47 2N7002E
MBDATA27,34
1 1
MBCLK27,34
3
Q48 2N7002E
3
10K
1
+3V
2
1
R495
10K
THDAT_SMB
THCLK_SMB
C660
0.1U/0402
1999_RST#36
THERMDA THDAT_SMB
C661
2200P
THERMDC
H/W Shutdown
A
SI stage:
Remove H/W shutdown circuit
(R613&Q54)that supported
ADM1032.
R496
100R
H/W MONITOR
6657VCC
B
1
2
3
4
Sting 10/12/2004
U37
VCC
DXP
DXN
-OVT
SMCLK
SMDATA
-ALT
GND
MAX6657/GMT-781
8
7
6
5
THCLK_SMB
C
ICH_THRM# 11
ICH_THRM#
To SB --> System throttling
TDI
TMS
TDO
CPURST#
PREQ#
TCK
TRST#
D
R490 150/F
R491 39.2R
R492 *54.9R
R493 54.9R
R733 56R
R497 27.4/F
R498 680R
Size Document Number Rev
Custom
Date: Sheet
PV stage:
VCCP
Add R733 as pull-up resistor for PREQ#.
PROJECT : CT3
Quanta Computer Inc.
Dothan CPU (Host Bus)
E
Sting 11/29/2004
of
342Friday, March 04, 2005
3A
A
CPU_CORE
4 4
3 3
2 2
AA11
AA13
AA15
AA17
AA19
AA21
AA5
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC9
AD10
AD12
AD14
AD16
AD18
AD8
AE11
AE13
AE15
AE17
AE19
AE9
AF10
AF12
AF14
AF16
AF18
AF8
D18
D20
D22
E17
E19
E21
G21
D6
D8
E5
E7
E9
F18
F20
F22
F6
F8
U36C
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
Dothan_478P
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCCA0
VCCA1/RSVD
VCCA2/RSVD
VCCA3/RSVD
VCCP0
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCQ0
VCCQ1
VCCSENSE
VSSSENSE
VID0
VID1
VID2
VID3
VID4
VID5
CPU_CORE
G5
H22
H6
J21
J5
K22
U5
V22
V6
W21
W5
Y22
Y6
F26
B1
N1
AC26
D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L21
L5
M22
M6
N21
N5
P22
P6
R21
R5
T22
T6
U21
P23
W4
E2
F2
F3
G3
G4
H4
TP_VCCSENSE
AE7
TP_VSSSENSE
AF6
TP_VCCA1
TP_VCCA2
TP_VCCA3
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
R501
*54.9R
CPU_VCCA
CPU de-coupling
capacitor
CPU_CORE
C712
C711
C710
0.1U
CPU_CORE
0.1U
C725
0.1U
C726
0.1U
A
1 1
0.1U
C727
0.1U
C713
0.1U
C728
0.1U
C714
0.1U
C729
0.1U
CPU_CORE
C715
0.1U
CPU_CORE
C730
0.1U
C716
0.1U
C731
0.1U
T155
T156
T157
CPU_VID0 33
CPU_VID1 33
CPU_VID2 33
CPU_VID3 33
CPU_VID4 33
CPU_VID5 33
R502
*54.9R
C717
0.1U
C732
0.1U
B
C663
0.01U_0402
VCCP
C718
0.1U
C733
0.1U
B
C664
10U/10V/0805
C719
0.1U
C734
0.1U
CPU_VCCA
C665
C666
+
150U/6.3V_7
0.1U
C681
C680
10U/10V/0805
10U/10V/0805
C690
C691
10U/10V/0805
10U/10V/0805
C701
C700
10U/10V/0805
10U/10V/0805
C721
C720
10U/10V/0805
10U/10V/0805
CPU Bypass
capacitor
C
120mA
R499 0R
C662
0.1U
SI stage:
Use X7R type to replace Y5V type
for Decoupl in g/B ypa ss capacitor.
Remove +1.8V optional cause of the
VCCA is powered by +1.5V in Intel
specification.
Sting 10/12/2004
C668
C667
0.1U
CPU_CORE
C682
10U/10V/0805
CPU_CORE
C692
10U/10V/0805
CPU_CORE
C702
10U/10V/0805
CPU_CORE
C722
10U/10V/0805
0.1U
C683
10U/10V/0805
C693
10U/10V/0805
C703
10U/10V/0805
C723
10U/10V/0805
C669
C670
0.1U
0.1U
C684
10U/10V/0805
C694
10U/10V/0805
C704
10U/10V/0805
C724
10U/10V/0805
C
+1.5V
VCCPVCCP
C671
C672
0.1U
0.1U
C686
C685
10U/10V/0805
10U/10V/0805
C695
C696
10U/10V/0805
10U/10V/0805
C705
C706
10U/10V/0805
10U/10V/0805
Sting 08/05/2004
C673
0.1U
CPU_CORE
C687
10U/10V/0805
CPU_CORE
C697
10U/10V/0805
CPU_CORE
C707
10U/10V/0805
C674
C675
0.1U
0.1U
C689
C688
10U/10V/0805
10U/10V/0805
C698
C699
10U/10V/0805
10U/10V/0805
C709
C708
10U/10V/0805
10U/10V/0805
D
A11
A14
A17
A20
A23
A26
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24
B12
B16
B19
B22
B25
C10
C13
C15
C18
C21
C24
D11
A2
A5
A8
B3
B6
B9
C1
C4
C7
D2
D5
D7
D9
U36D
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
Dothan_478P
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
R6
R22
R25
T3
T5
T21
T23
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
E
PROJECT : CT3
Quanta Computer Inc.
Size Document Number Rev
Custom
D
Date: Sheet
CPU POWER / GND
442Friday, March 04, 2005
E
of
2A
1
2
3
4
5
6
7
8
E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2
C1
C2
D1
T1
L1
P1
U38A
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING
ALVISO
HADSTB0#
HADSTB1#
HCPURST#
HOST
HDEFER#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
HEDRDY#
HPCREQ#
HCPUSLP#
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HADS#
HVREF
HBNR#
HBPRI#
BREQ0#
HCLKINN
HCLKINP
HDBSY#
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HDPWR#
HDRDY#
HHIT#
HHITM#
HLOCK#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HRS0#
HRS1#
HRS2#
HTRDY#
HA#[3..31]
HA#3
G9
HA#4
C9
HA#5
E9
HA#6
B7
HA#7
A10
HA#8
F9
HA#9
D8
HA#10
B10
HA#11
E10
HA#12
G10
HA#13
D9
HA#14
E11
HA#15
F10
HA#16
G11
HA#17
G13
HA#18
C10
HA#19
C11
HA#20
D11
HA#21
C12
HA#22
B13
HA#23
A12
HA#24
F12
HA#25
G12
HA#26
E12
HA#27
C13
HA#28
B11
HA#29
D13
HA#30
A13
HA#31
F13
ADS#
F8
HADSTB0#
B9
HADSTB1#
E13
HVREF
J11
BNR#
A5
BPRI#
D5
HBREQ0#
E7
CPURST#
H10
HCLK_MCH#
AB1
HCLK_MCH
AB2
DBSY#
C6
DEFER#
E6
DINV#0
H8
DINV#1
K3
DINV#2
T7
DINV#3
U5
DPWR#
G6
DRDY#
F7
HDSTBN0#
G4
HDSTBN1#
K1
HDSTBN2#
R3
HDSTBN3#
V3
HDSTBP0#
G5
HDSTBP1#
K2
HDSTBP2# M_RCOMPN
R2
HDSTBP3#
W4
F6
HIT#
D4
HITM#
D6
HLOCK#
B3
A11
HREQ#0
A7
HREQ#1
D7
HREQ#2
B8
HREQ#3
C7
HREQ#4
A8
RS#0
A4
RS#1
C5
RS#2
B4
HCPUSLP#
G8
HTRDY#
B5
HA#[3..31] 3
ADS# 3
HADSTB0# 3
HADSTB1# 3
BNR# 3
BPRI# 3
HBREQ0# 3
CPURST# 3
HCLK_MCH# 2
HCLK_MCH 2
DBSY# 3
DEFER# 3
DINV#0 3
DINV#1 3
DINV#2 3
DINV#3 3
DPWR# 3
DRDY# 3
HDSTBN0# 3
HDSTBN1# 3
HDSTBN2# 3
HDSTBN3# 3
HDSTBP0# 3
HDSTBP1# 3
HDSTBP2# 3
HDSTBP3# 3
HIT# 3
HITM# 3
HLOCK# 3
HREQ#0 3
HREQ#1 3
HREQ#2 3
HREQ#3 3
HREQ#4 3
RS#0 3
RS#1 3
RS#2 3
HTRDY# 3
VCCP
R504
100/F
R507
200/F
T178
T181
R510 0R
C735
0.1U
H_CPUSLP# 3,10
DMI_TXN011
DMI_TXN111
DMI_TXN211
DMI_TXN311
DMI_TXP011
DMI_TXP111
DMI_TXP211
DMI_TXP311
DMI_RXN011
DMI_RXN111
DMI_RXN211
DMI_RXN311
DMI_RXP011
DMI_RXP111
DMI_RXP211
DMI_RXP311
CLK_SDRAM013
CLK_SDRAM113
T165
CLK_SDRAM313
CLK_SDRAM413
T166
CLK_SDRAM0#13
CLK_SDRAM1#13
T167
CLK_SDRAM3#13
CLK_SDRAM4#13
T168
CKE07,13
CKE17,13
CKE27,13
CKE37,13
SM_CS0#7,13
SM_CS1#7,13
SM_CS2#7,13
SM_CS3#7,13
SMDDR_VREF
It's point to point, 55ohm trace,
keep as short as possible.
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
CLK_SDRAM0
CLK_SDRAM1
CLK_SDRAM2
CLK_SDRAM3
CLK_SDRAM4
CLK_SDRAM5
CLK_SDRAM0#
CLK_SDRAM1#
CLK_SDRAM2#
CLK_SDRAM3#
CLK_SDRAM4#
CLK_SDRAM5#
CKE0
CKE1
CKE2
CKE3
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
M_OCDCOMP0
M_OCDCOMP1
M_RCOMPP
SMXSLEW
SMYSLEW
AA31
AB35
AC31
AD35
Y31
AA35
AB31
AC35
AA33
AB37
AC33
AD37
Y33
AA37
AB33
AC37
AM33
AL1
AE11
AJ34
AF6
AC10
AN33
AK1
AE10
AJ33
AF5
AD10
AP21
AM21
AH21
AK21
AN16
AM14
AH15
AG16
AF22
AF16
AP14
AL15
AM11
AN10
AK10
AK11
AF37
AD1
AE27
AE28
AF9
AF10
U38C
DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3
DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3
DMITXN0
DMITXN1
DMITXN2
DMITXN3
DMITXP0
DMITXP1
DMITXP2
DMITXP3
SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5
SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT
ALVISO
DMIDDR MUXING
CFG/RSVDPMLCKNC
DREF_SSCLKN
DREF_SSCLKP
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
BM_BUSY#
EXT_TS0#
EXT_TS1#
THRMTRIP#
PWROK
RSTIN#
DREF_CLKN
DREF_CLKP
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25
J23
J21
H22
F5
AD30
AE29
A24
A23
C37
D37
AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37
CFG0
R503 1K
MCH_BSEL1
MCH_BSEL2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1
R508 0R
R509 100R
TP_NC1
TP_NC2
TP_NC3
TP_NC4
TP_NC5
TP_NC6
TP_NC7
TP_NC8
TP_NC9
TP_NC10
TP_NC11
+2.5V
R505
10K
MCH_BSEL1 2
MCH_BSEL2 2
CFG3 6
T158
CFG5 6
CFG6 6
CFG7 6
T159
CFG9 6
T160
CFG11 6
CFG12 6
CFG13 6
T161
T162
CFG16 6
T163
CFG18 6
CFG19 6
T164
R506
10K
THRMTRIP# 3,10
IMVPOK 11,33
PLTRST# 10,11,28
DOT96# 2
DOT96 2
DREFSSCLK# 2
DREFSSCLK 2
T169
T170
T171
T172
T173
T174
T175
T176
T177
T179
T180
VCCP
PM_BMBUSY# 11
HD#[0..63]3
A A
B B
C C
HD#[0..63]
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING
This group should be
routed as 10:20
2.5VSUS
R511
80.6/F
M_RCOMPN
M_RCOMPP
R518
80.6/F
PROJECT : CT3
Quanta Computer Inc.
Size Document Number Rev
6
Date: Sheet
7
ALVISO-Host
of
542Friday, March 04, 2005
8
1ACustom
R514
221/F
R520
100/F
VCCP
R512 54.9R
R515 24.9/F
HYSWING
C737
0.1U
2
VCCP
R521 54.9R
R522 24.9/F
3
HXSCOMP
HXRCOMP
HYSCOMP
HYRCOMP
M_OCDCOMP0
M_OCDCOMP1
R517
R516
*40.2/F
*40.2/F
Route as short
as possible.
4
5
VCCP VCCP
R513
D D
221/F
HXSWING
R519
100/F
1
C736
0.1U
1
2
3
4
5
6
7
8
U38F
T182
T183
SRC_MCH#2
SRC_MCH2
S-CVBS131
S-YD131
A A
CRT_B
R532 150/F
R533 150/F
CRT_G
CRT_R
R534 150/F
Place near chip
VSYNC30
HSYNC30
B B
C C
S-CD131
EDIDDATA15
TXLCLKOUT-15
TXLCLKOUT+15
BKLON15
EDIDCLK15
DISP_ON15
TXLOUT0-15
TXLOUT1-15
TXLOUT2-15
TXLOUT0+15
TXLOUT1+15
TXLOUT2+15
R529 150/F
R530 150/F
R531 150/F
DDCCLK30
DDCDAT30
CRT_B30
CRT_G30
R535 39R
R536 39R
R537 255/F
+2.5V
CRT_R30
R538 100K
R539 100K
R541 2.2K
R542 2.2K
VSYNC_NB
HSYNC_NB
REFSET
R546 1.5 K/F
SRC_MCH#
SRC_MCH
R528 4.99K/F
T216
T217
T223
T225
T227
T299
T300
T301
T302
T303
T305
T304
T306
H24
H25
AB29
AC29
A15
C16
A17
B15
B16
B17
E24
E23
E21
D21
C20
B20
A19
B19
H21
G21
E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27
B30
B29
C25
C24
B34
B33
B32
A34
A33
B31
C29
D28
C27
C28
D27
C26
J18
J20
SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP
TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC
DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET
LBKLT_CTRL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL
LACLKN
LACLKP
LBCLKN
LBCLKP
LADATAN0
LADATAN1
LADATAN2
LADATAP0
LADATAP1
LADATAP2
LBDATAN0
LBDATAN1
LBDATAN2
LBDATAP0
LBDATAP1
LBDATAP2
ALVISO
MISC
TV VGA LVDS
EXP_COMPI
EXP_ICOMPO
EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
PCI-EXPRESS GRAPHICS
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
D36
D34
E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34
D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34
E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36
D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36
EXP_COMP
R523 24.9/F
These pins can't leave as NC
T184
T185
if we didn't use PCI-E on
T186
system cause it also used for
T187
T188
DMI compensation.
T189
T190
T191
T192
T193
T194
T195
T196
T197
T198
T199
T200
T201
T202
T203
T204
T205
T206
T207
T208
T209
T210
T211
T212
T213
T214
T215
T218
T219
T220
T221
T222
T224
T226
T228
T229
T230
T231
T232
T233
T234
T235
T236
T237
T238
T239
T240
T241
T242
T243
T244
T245
T246
T247
T248
T249
T250
T251
T252
VCC3G_PCIE
+1.5v
Strapping
CFG9
R547
*2.2K
Low=DMIx2
High=DMIx4
D D
1
CFG7
CFG75
Low=DT/Transportable CPU
High=Mobile CPU
(Default)
R553
*2.2K
(Default)
Low=PCIE Reverse Lanes
High=PCIE Normal
Operation
CFG185
Low=CPU core VCC 1.05V
High=CPU core VCC 1.5V
2
R548
*2.2K
(Default)
R554
*1K
CFG18
(Default) (Default)
3
CFG125
CFG135CFG95 CFG65CFG55
CFG115
CFG12
CFG13
R549
R550
*2.2K
*2.2K
00 : Reserved Low=FSB Dynamic ODT Disabled
01 : XOR Mode Enabled
10 : All Z Mode Enabled
11 : Normal Operation
CFG11
(Default)
R555
*2.2K
4
CFG6
R551
*2.2K
Low=DDR II
High=DDR
CFG35
Low=DDR533Low=FSB533
(Default)
CFG3
R556
*2.2K
5
CFG165
CFG195
CFG16
R552
2.2K
High=FSB Dynamic ODT Enabled
+2.5V+2.5V
R557
*1K
CFG19
Low=CPU VTT 1.05V
High=CPU VTT 1.2V
6
(Default)
CFG[2:0]
001=533MT/S FSB
101=400MT/S FSB
CFG[3:17] have internal pullup.
CFG[18:19] have internal pulldown.
PROJECT : CT3
Quanta Computer Inc.
Size Document Number Rev
Date: Sheet
ALVISO DMI
7
642Friday, March 04, 2005
1ACustom
of
8
1
MD31
RN63
4P2R-S-10
RN64
4P2R-S-10
RN65
4P2R-S-10
RN66
4P2R-S-10
RN67
4P2R-S-10
RN68
4P2R-S-10
A A
RN69
4P2R-S-10
RN70
4P2R-S-10
RN71
4P2R-S-10
RN72
4P2R-S-10
RN73
4P2R-S-10
RN74
4P2R-S-10
RN75
4P2R-S-10
RN76
4P2R-S-10
RN77
4P2R-S-10
RN78
4P2R-S-10
RN79
4P2R-S-10
RN80
4P2R-S-10
RN81
4P2R-S-10
B B
RN82
4P2R-S-10
RN83
4P2R-S-10
RN84
4P2R-S-10
RN85
4P2R-S-10
RN86
4P2R-S-10
RN87
4P2R-S-10
RN90
4P2R-S-10
RN95
4P2R-S-10
RN100
4P2R-S-10
RN105
4P2R-S-10
RN110
4P2R-S-10
RN115
4P2R-S-10
RN120
4P2R-S-10
C C
MD26
MD30
MD27
MD25
MD24
MD28
MD29
MD19
MD18
MD22
MD23
MD21
MD20
MD16
MD17
MD35
MD34
MD39
MD38
MD36
MD37
MD33
MD32
MD59
MD58
MD62
MD63
MD56
MD60
MD61
MD57
MD51
MD50
MD55
MD54
MD48
MD53
MD49
MD52
MD47
MD46
MD42
MD43
MD44
MD45
MD40
MD41
MD10
MD11
MD15
MD14
MD8
MD9
MD6
MD3
MD2
MD7
MD1
MD0
MD4
MD5
MD13
MD12
1
3
3
1
3
1
1
3
1
3
1
3
3
1
3
1
1
3
1
3
3
1
1
3
3
1
1
3
3
1
1
3
1
3
3
1
3
1
3
1
1
3
1
3
3
1
3
1
1
3
1
3
1
3
1
3
3
1
1
3
1
3
1
3
2
R_MD31
2
R_MD26
4
R_MD30
4
R_MD27
2
R_MD25
4
R_MD24
2
R_MD28
2
R_MD29
4
R_MD19
2
R_MD18
4
R_MD22
2
R_MD23
4
R_MD21
4
R_MD20
2
R_MD16
4
R_MD17
2
R_MD35
2
R_MD34
4
R_MD39
2
R_MD38
4
R_MD36
4
R_MD37
2
R_MD33
2
R_MD32
4
R_MD59
4
R_MD58
2
R_MD62
2
R_MD63
4
R_MD56
4
R_MD60
2
R_MD61
2
R_MD57
4
R_MD51
2
R_MD50
4
R_MD55
4
R_MD54
2
R_MD48
4
R_MD53
2
R_MD49
4
R_MD52
2
R_MD47
2
R_MD46
4
R_MD42
2
R_MD43
4
R_MD44
4
R_MD45
2
R_MD40
4
R_MD41
2
R_MD10
2
R_MD11
4
R_MD15
2
R_MD14
4
R_MD13
2
R_MD8
4
R_MD9
2
R_MD12
4
R_MD6
4
R_MD3
2
R_MD2
2
R_MD7
4
R_MD1
2
R_MD0
4
R_MD4
2
R_MD5
4
R_MD0
R_MD1
R_MD2
R_MD3
R_MD4
R_MD5
R_MD6
R_MD7
R_MD8
R_MD9
R_MD10
R_MD11
R_MD12
R_MD13
R_MD14
R_MD15
R_MD16
R_MD17
R_MD18
R_MD19
R_MD20
R_MD21
R_MD22
R_MD23
R_MD24
R_MD25
R_MD26
R_MD27
R_MD28
R_MD29
R_MD30
R_MD31
R_MD32
R_MD33
R_MD34 M_B_MA3
R_MD35
R_MD36
R_MD37
R_MD38
R_MD39
R_MD40
R_MD41
R_MD42
R_MD43
R_MD44
R_MD45
R_MD46
R_MD47
R_MD48
R_MD49
R_MD50
R_MD51
R_MD52
R_MD53
R_MD54
R_MD55
R_MD56
R_MD57
R_MD58
R_MD59
R_MD60
R_MD61
R_MD62
R_MD63
RN88
4P2R-S-56
RN91
4P2R-S-56
RN98
4P2R-S-56
RN101
4P2R-S-56
RN108
4P2R-S-56
RN111
4P2R-S-56
RN118
4P2R-S-56
RN121
4P2R-S-56
RN127
4P2R-S-56
RN129
4P2R-S-56
RN135
4P2R-S-56
RN137
4P2R-S-56
RN141
4P2R-S-56
RN143
4P2R-S-56
RN147
4P2R-S-56
RN149
4P2R-S-56
3
U38B
AG35
SADQ0
AH35
SADQ1
AL35
SADQ2
AL37
SADQ3
AH36
SADQ4
AJ35
SADQ5
AK37
SADQ6
AL34
SADQ7
AM36
SADQ8
AN35
SADQ9
AP32
SADQ10
AM31
SADQ11
AM34
SADQ12
AM35
SADQ13
AL32
SADQ14
AM32
SADQ15
AN31
SADQ16
AP31
SADQ17
AN28
SADQ18
AP28
SADQ19
AL30
SADQ20
AM30
SADQ21
AM28
SADQ22
AL28
SADQ23
AP27
SADQ24
AM27
SADQ25
AM23
SADQ26
AM22
SADQ27
AL23
SADQ28
AM24
SADQ29
AN22
SADQ30
AP22
SADQ31
AM9
SADQ32
AL9
SADQ33
AL6
SADQ34
AP7
SADQ35
AP11
SADQ36
AP10
SADQ37
AL7
SADQ38
AM7
SADQ39
AN5
SADQ40
AN6
SADQ41
AN3
SADQ42
AP3
SADQ43
AP6
SADQ44
AM6
SADQ45
AL4
SADQ46
AM3
SADQ47
AK2
SADQ48
AK3
SADQ49
AG2
SADQ50
AG1
SADQ51
AL3
SADQ52
AM2
SADQ53
AH3
SADQ54
AG3
SADQ55
AF3
SADQ56
AE3
SADQ57
AD6
SADQ58
AC4
SADQ59
AF2
SADQ60
AF1
SADQ61
AD4
SADQ62
AD5
SADQ63
SMDDR_VTERM
MD58
MD59
MD60
MD56
MD48
MD53
MD47
MD46
MD40
MD41
MD34
MD26
MD31
MD27
MD30
MD25
MD24
MD19
MD18
MD17
MD16
MD11
MD10
MD9
MD12 MD21
MD8
MD13
MD2
MD7
MD0
MD1
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
4
3
2
1
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
SA_BS0#
SA_BS1#
SA_BS2#
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
DDR SYSTEM MEMORY A
SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
ALVISO
MD62
2
1
3
1
3
1
3
3
1
1
3
3
1
1
3
1
3
1
3
1
3
1
3
1
3
3
1
1
3
1
3
1
3
MD63
4
MD57
2
MD61
4
MD54
2
MD55
4
MD51
4
MD50
2
MD33
2
MD32
4
MD45MD35
4
MD44
2
MD39
2
MD38
4
MD37
2
MD36
4
MD29
2
MD28
4
MD23
2
MD22
4
MD3
2
MD6
4
MD5
2
MD4
4
MD20
4
2
MD14
2
MD15
4
MD43
2
MD42
4
MD49
2
MD52
4
AK15
AK16
AL21
AJ37
AP35
AL29
AP24
AP9
AP4
AJ2
AD3
R_SM_DQS0
AK36
R_SM_DQS1
AP33
R_SM_DQS2
AN29
R_SM_DQS3
AP23
R_SM_DQS4
AM8
R_SM_DQS5
AM4
R_SM_DQS6
AJ1
R_SM_DQS7
AE5
AK35
AP34
AN30
AN23
AN8
AM5
AH1
AE4
AL17
AP17
AP18
AM17
AN18
AM18
AL19
AP20
AM19
AL20
AM16
AN20
AM20
AM15
M_A_SCASA#
AN15
M_A_SRASA#
AP16
SA_RCVENIN#
AF29
SA_RCVENOUT#
AF28
M_A_BMWEA#
AP15
RN89
4P2R-S-56
RN92
4P2R-S-56
RN99
4P2R-S-56
4P2R-S-56
RN102
RN109
4P2R-S-56
4P2R-S-56
RN112
RN119
4P2R-S-56
RN122
4P2R-S-56
RN128
4P2R-S-56
RN130
4P2R-S-56
RN136
4P2R-S-56
RN138
4P2R-S-56
RN142
4P2R-S-56
RN144
4P2R-S-56
RN148
4P2R-S-56
RN150
4P2R-S-56
4
M_A_BA0
M_A_BA1
R_SDM0
R_SDM1
R_SDM2
R_SDM3
R_SDM4
R_SDM5
R_SDM6
R_SDM7
M_A_MA0
M_A_MA1
M_A_MA2
M_A_MA3
M_A_MA4
M_A_MA5
M_A_MA6
M_A_MA7
M_A_MA8
M_A_MA9
M_A_MA10
M_A_MA11
M_A_MA12
M_A_MA13
5
U38G
AE31
SBDQ0
AE32
SBDQ1
AG32
SBDQ2
AG36
SBDQ3
AE34
SBDQ4
AE33
SBDQ5
AF31
SBDQ6
AF30
SBDQ7
AH33
SBDQ8
AH32
SBDQ9
AK31
SBDQ10
AG30
SBDQ11
AG34
SBDQ12
AG33
SBDQ13
AH31
SBDQ14
AJ31
SBDQ15
AK30
SBDQ16
AJ30
SBDQ17
AH29
SBDQ18
AH28
SBDQ19
AK29
SBDQ20
AH30
SBDQ21
AH27
SBDQ22
AG28
SBDQ23
AF24
SBDQ24
AG23
SBDQ25
AJ22
SBDQ26
AK22
M_A_MA[0..13]
T77
T80
RN93
M_B_SRASA#
4P2R-S-56
M_B_BMWEA#
RN96
M_B_BA0
4P2R-S-56
M_B_MA12
RN103
CKE3
4P2R-S-56
M_B_MA8
RN106
M_B_MA6
4P2R-S-56
M_B_MA10
RN113
M_B_MA1
4P2R-S-56
M_B_MA3
RN116
M_B_MA5
4P2R-S-56
M_A_BA1
RN123
M_A_SRASA#
4P2R-S-56
M_A_BA0
RN125
M_A_BMWEA#
4P2R-S-56
CKE1
RN131
4P2R-S-56
M_A_MA12
M_A_MA5
RN133
M_A_MA3 M_A_MA7
4P2R-S-56
M_A_MA11
RN139
CKE0
4P2R-S-56
RN145
M_B_MA11
4P2R-S-56
AH24
AH23
AG22
AJ21
AG10
AH11
AH10
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
AG9
SBDQ33
AG8
SBDQ34
AH8
SBDQ35
SBDQ36
SBDQ37
AJ9
SBDQ38
AK9
SBDQ39
AJ7
SBDQ40
AK6
SBDQ41
AJ4
SBDQ42
AH5
SBDQ43
AK8
SBDQ44
AJ8
SBDQ45
AJ5
SBDQ46
AK4
SBDQ47
AG5
SBDQ48
AG4
SBDQ49
AD8
SBDQ50
AD9
SBDQ51
AH4
SBDQ52
AG6
SBDQ53
AE8
SBDQ54
AD7
SBDQ55
AC5
SBDQ56
AB8
SBDQ57
AB6
SBDQ58
AA8
SBDQ59
AC8
SBDQ60
AC7
SBDQ61
AA4
SBDQ62
AA5
SBDQ63
1
3
1
3
1
3
1
3
1
3
1
3
1
3
3
1
3
1
1
3
1
3
1
3
DDR SYSTEM MEMORY B
SB_RCVENOUT#
SMDDR_VTERM
2
1
4
3
2
1
4
3
2
1
4
3
1
2
3
4
1
2
3
4
2
1
4
3
2
1
4
3
4
1
2
3
1
4
3
2
2
1
4
3
2
1
4
3
1
2
3
4
SB_BS0#
SB_BS1#
SB_BS2#
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_WE#
ALVISO
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
6
AJ15
AG17
AG21
AF32
AK34
AK27
AK24
AJ10
AK5
AE7
AB7
AF34
AK32
AJ28
AK23
AM10
AH6
AF8
AB4
AF35
AK33
AK28
AJ23
AL10
AH7
AF7
AB5
AH17
AK17
AH18
AJ18
AK18
AJ19
AK19
AH19
AJ20
AH20
AJ16
AG18
AG20
AG15
AH14
AK14
AF15
AF14
AH16
SM_CS3#
M_B_SCASA#
M_B_MA4
M_B_MA2
M_B_BA1
M_B_MA0
M_B_MA9
M_B_MA7
SM_CS1#
M_A_SCASA#
M_A_MA1
M_A_MA10
M_A_MA0
M_A_MA4
M_A_MA2
M_A_MA8
M_A_MA6
M_A_MA9
SM_CS0#
M_A_MA13
SM_CS2#CKE2
M_B_MA13
M_B_BA0
M_B_BA1
M_B_MA0
M_B_MA1
M_B_MA2
M_B_MA4
M_B_MA5
M_B_MA6
M_B_MA7
M_B_MA8
M_B_MA9
M_B_MA10
M_B_MA11
M_B_MA12
M_B_MA13
M_B_SCASA#
M_B_SRASA#
SB_RCVENIN#
SB_RCVENOUT#
M_B_BMWEA#
RN94
4P2R-S-56
RN97
4P2R-S-56
RN104
4P2R-S-56
RN107
4P2R-S-56
RN114
4P2R-S-56
RN117
4P2R-S-56
RN124
4P2R-S-56
RN126
4P2R-S-56
RN132
4P2R-S-56
RN134
4P2R-S-56
RN140
4P2R-S-56
RN146
4P2R-S-56
M_B_MA[0..13]
T75
T76
7
SDM0
SDM1
SDM2
SM_DQS0
SM_DQS1
SM_DQS3
R_SDM0
R_SDM1
R_SDM2
R_SDM3
R_SDM4
R_SDM5
R_SDM6
R_SDM7
R_SM_DQS4
SMDDR_VTERM
R656 56R
1 2
R658 56R
1 2
R660 56R
1 2
R662 56R
1 2
R664 56R
1 2
R666 56R
1 2
R668 56R
1 2
R670 56R
1 2
R640 10R
R641 10R
R642 10R
R643 10R
R644 10R
R645 10R
R646 10R
R647 10R
R_SM_DQS0
R648 10R
R_SM_DQS1
R649 10R
R_SM_DQS2
R650 10R
R_SM_DQS3
R651 10R
R652 10R
R_SM_DQS5
R653 10R
R_SM_DQS6
R654 10R
R_SM_DQS7
R655 10R
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R657 56R
1 2
R659 56R
1 2
R661 56R
1 2
R663 56R
1 2
R665 56R
1 2
R667 56R
1 2
R669 56R
1 2
R671 56R
1 2
8
SDM4
SDM5
SDM6
SDM7SDM3
SM_DQS4
SM_DQS5
SM_DQS6SM_DQS2
SM_DQS7
SDM0
SDM1
SDM2
SDM3
SDM4
SDM5
SDM6
SDM7
SM_DQS0
SM_DQS1
SM_DQS2
SM_DQS3
SM_DQS4
SM_DQS5
SM_DQS6
SM_DQS7
M_A_MA[0..13]
M_A_BA0
M_A_BA1
SMDDR_VTERM
C994
D D
0.1U
SMDDR_VTERM
C1013
0.1U
1
C995
0.1U
C1014
0.1U
C996
0.1U
C1015
0.1U
C997
0.1U
C1016
0.1U
For terminal R-pack.
C999
C998
0.1U
0.1U
C1018
C1017
0.1U
0.1U
2
C1000
0.1U
C1019
0.1U
C1001
0.1U
C1020
0.1U
C1002
C1003
0.1U
0.1U
C1022
C1021
0.1U
0.1U
3
C1004
0.1U
C1023
0.1U
C1005
0.1U
C1024
0.1U
4
C1006
0.1U
C1025
0.1U
C1007
0.1U
C1026
0.1U
C1008
0.1U
C1027
0.1U
C1011
C1010
C1009
0.1U
0.1U
C1028
C1029
0.1U
0.1U
5
0.1U
C1030
0.1U
C1012
0.1U
C1031
0.1U
M_A_SCASA#
M_A_BMWEA#
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
CKE[0..3]
6
M_A_BA0 13
M_A_BA1 13
M_A_SRASA# 13
M_A_SCASA# 13
M_A_BMWEA# 13
SM_CS0# 5,13
SM_CS1# 5,13
SM_CS2# 5,13
SM_CS3# 5,13
CKE[0..3] 5,13
Size Document Number Rev
Date: Sheet
7
M_B_MA[0..13]
M_B_BA0
M_B_BA1
M_B_SRASA#M_A_SRASA#
M_B_SCASA#
M_B_BMWEA#
MD[0..63]
SM_DQS[0..7]
SDM[0..7]
M_B_MA[0..13] 13M_A_MA[0..13] 13
M_B_BA0 13
M_B_BA1 13
M_B_SRASA# 13
M_B_SCASA# 13
M_B_BMWEA# 13
MD[0..63] 13
SM_DQS[0..7] 13
SDM[0..7] 13
PROJECT : CT3
Quanta Computer Inc.
ALVISO DDR
742Friday, March 04, 2005
8
1ACustom
of
1
A A
0.22U
C772
C773
0.22U
VCCP_GMCH_CAP3
VCCP_GMCH_CAP4
VCCP_GMCH_CAP2
C774
0.47U
C775
0.47U
VCCP_GMCH_CAP1
VCCP
640mA
2
C770
2.2U
VCCP
+2.5V
C771
4.7U/10V
VCCP
C778 0.1U/0402
C779 10U/10V/0805
3
L54 BLM11A121S
R558
10R
D21
RB751V-40
2 1
+2.5V
C766
0.1U
2mA
70mA
C767
0.022U
4
C765
0.1U
150mA
L53 1uH
C764
+
470U
+1.5V
C769
0.1U
L55 1uH
C768
+
470U
45mA
40mA
C777
0.1U
+1.5V
5
C776
+
470U
+1.5V
L56 10uH
40mA
C781
+
0.1U
+1.5V
L57 10uH
C780
470U
6
+1.5V
7
+3V_TV
PV-II stage:
To add a LDO for clear POWER to solve TV problem
C1054
10U/10V/0805
5
4
U48
SET
OUT
G923-330
-SHDN
GND
VCCP
IN
8
+5V
1
2
3
C1055
1U/16V
3.7A
C784
0.1U
+1.5V
21
C785
10U/10V/0805
+3V
R559
10R
C783
C788
0.022U
C782
0.1U
0.1U
D22
RB751V-40
C789
0.1U
AC1
AC2
C35
F19
E19
AA2
AA1
VCCA_HPLL
VCCA_MPLL
VCCA_CRTDAC0
VCCA_CRTDAC1
B23
VCCA_DPLLB
VCCA_DPLLA
VCCH_MPLL0
VCCH_MPLL1
K17
VCC48
K18
VCC47
T18
VCC46
V18
VCC45
W18
VCC44
K19
VCC43
U19
VCC42
V19
VCC41
K20
VCC40
T20
VCC39
U20
VCC38
W20
VCC37
K21
VCC36
K22
VCC35
K23
VCC34
K24
VCC33
J25
VCC32
K25
VCC31
H26
VCC30
K26
VCC29
H27
VCC28
J27
VCC27
L27
K27
VCC26
M27
VCC24
VCC25
N27
VCC23
P27
VCC22
R27
VCC21
T27
VCC20
V27
U27
VCC19
G28
VCC17
VCC18
H28
VCC16
H20
M11
L11
K11
W10
V10
U10
T10
R10
P10
N10
M10
K10
VTT23Y9VTT24W9VTT25U9VTT26R9VTT27P9VTT28N9VTT29M9VTT30L9VTT31J9VTT32N8VTT33M8VTT34N7VTT35M7VTT36N6VTT37M6VTT38A6VTT39N5VTT40M5VTT41N4VTT42M4VTT43N3VTT44M3VTT45N2VTT46M2VTT47B2VTT48V1VTT49N1VTT50M1VTT51
J10
VTT22
VTT21
VTT20
VTT18
VTT19
VTT17
VTT15
VTT16
VTT14
VTT12
VTT13
VTT11
N11
VTT9
VTT10
K12
W11
V11
U11
T11
R11
P11
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
G1
U38H
B B
J13
VTT1
K13
VTT0
G19
VCC_SYNC
VVSSA_CRTDAC
J28
VCC15
K28
VCC14
L28
VCC13
M28
VCC12
N28
VCC11
P28
VCC10
R28
VCC9
VCC8
VCC7
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1
VCC0
T29
R29
N29
M29
K29
J29
V28
U28
T28
POWER
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
VCCA_TVBG
VSSA_TVBG
VCCD_TVDAC
VCCDQ_TVDAC
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
VCCA_LVDS
VCCHV0
VCCHV1
VCCHV2
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64
VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2
VCCA_3GBG
VSSA_3GBG
J37
F37
G37
L37
Y29
Y28
Y27
U37
R37
N37
W37
AF18
AE37
AF19
AP19
AF20
B28
A28
A27
AB9
AP8
AE1
AM1
AB10
AB11
AC11
AD11
AE12
AF12
AG12
AH12
AJ12
AK12
AL12
AM12
AN12
AP12
AE13
AF13
AG13
AH13
AJ13
AK13
AL13
AM13
AN13
AP13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AF25
AG25
AH25
AJ25
AK25
AL25
AM25
AN25
AP25
AE26
AF26
AG26
AH26
AJ26
AK26
AL26
AM26
AN26
AP26
AC27
AD27
AD28
AP29
AH37
AM37
B21
A21
B26
B25
A25
A35
B22
H18
D19
H17
G18
F17
F18
E17
E18
D18
C18
C786
10U/10V/0805
R560
*0R
+3V_TV
C787
10U/10V/0805
120mA
60mA
C802
4.7U/10V
V2.5_DDR_CAP6
V2.5_DDR_CAP3
V2.5_DDR_CAP4
+2.5V
+1.5V
C794
0.1U
C812
+
100U
C817
10U/10V/0805
C795
0.1U
1A
C793
0.1U
Note: All VCCSM pins
shorted internally.
VCC_DDRDLLVCCA_3GPLL
VCC3G_PCIE
3
125mA
C813
0.1U
C818
10U/10V/0805
1.05A
C797
C796
+
10U/10V/0805
330U/6.3V/ESR-25
Note: All VCCSM pins
shorted internally.
L60
BLM11A121S
VCC3G_PCIE
L62
BLM11A121S
C816
+
220U
4
2.5VSUS
+1.5V
+1.5V
C798
10U/10V/0805
C803
0.1U
V2.5_DDR_CAP5
C804
0.1U
C819
0.1U
V2.5_DDR_CAP2
+2.5V
2mA
C820
10U/10V/0805
5
C805
0.1U
V2.5_DDR_CAP1
+2.5V
C821
C822
0.1U
0.01U_0402
10mA
60mA
+1.5V
C823
0.1U
C808
0.022U
C814
0.022U
C824
10U/10V/0805
6
C790
0.022U
C799
C800
0.022U
0.1U
C807
C806
0.1U
0.022U
+1.5V
C809
0.1U
L61 BLM11A121S
C815
0.1U
C791
0.1U
L58 BLM11A121S
24mA
+1.5V
Size D oc u ment Num ber R ev
Date: Sheet
PROJECT : CT3
Quanta Computer Inc.
ALVISO POWER
7
842Friday, March 04, 2005
8
2ACustom
of
500mA
C810
0.1U
VCCA_3GPLL
C792
0.1U
R561 0.5/F
C811
10U/10V/0805
C C
+2.5V
D D
1
VCC3G_PCIE
VCC_DDRDLL
C801
0.1U
L59
BLM11A121S
2
1
A A
B27
J26
G26
E26
A26
AN24
AL24
Y1
B36
U38E
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268J2VSS269G2VSS270D2VSS271
VSSALVDS
2
AJ3
AC3
AB3
AA3
AN2
AL2
AH2
AE2
AD2
VSS247
VSS248
VSS249
VSS250C3VSS251A3VSS252
VSS253
VSS254
VSS255
VSS256
VSS257V2VSS258T2VSS259P2VSS260L2VSS261
3
AG7
AA7
AJ6
AE6
AC6
AP5
AL5
AN4
AF4
VSS235
VSS236W5VSS237E5VSS238
VSS239
VSS240Y4VSS241U4VSS242P4VSS243L4VSS244H4VSS245C4VSS246
AA6
VSS222
VSS223V7VSS224G7VSS225
VSS226
VSS227
VSS228
VSS229T6VSS230P6VSS231L6VSS232J6VSS233B6VSS234
4
L10
D10
AN9
AH9
AE9
AC9
AN7
AK7
VSS220
VSS221
AL8
VSS214Y8VSS215P8VSS216L8VSS217E8VSS218C8VSS219
AA9
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208V9VSS209T9VSS210K9VSS211H9VSS212A9VSS213
5
AG14
K14
J14
F14
B14
A14
J12
D12
B12
AN11
AL11
AJ11
AG11
AF11
AA11
Y11
H11
F11
AA10
Y10
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
6
C19
AL18
U18
B18
A18
AN17
AJ17
AF17
G17
C17
AL16
K16
H16
D16
A16
K15
C15
AN14
AL14
AJ14
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
7
E22
D22
A22
AN21
AF21
F21
C21
AK20
V20
G20
F20
E20
D20
A20
AN19
AG19
W19
T19
J19
H19
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
8
AF23
H23
AL22
AH22
J22
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
J24
F24
D24
E27
G27
W27
AJ24
AG24
AJ27
AL27
AF27
AB27
AA27
AN27
AG27
B24
B B
A29
E28
W28
AB28
AA28
AC28
D29
L29
F29
E29
G29
H29
V29
P29
U29
W29
AA29
Y30
C30
AJ29
AD29
AG29
AM29
AP30
AE30
AB30
AA30
AC30
D31
J31
L31
F31
K31
E31
H31
G31
M31
N31
T31
V31
P31
U31
R31
W31
Y32
A32
C32
AL31
AD31
AG31
AJ32
AB32
AA32
AN32
AD32
AC32
D33
J33
L33
F33
K33
E33
H33
G33
M33
N33
T33
V33
P33
U33
R33
W33
C34
AL33
AF33
AA34
AD33
B35
AB34
AN34
AH34
AD34
AC34
D35
J35
L35
F35
K35
E35
H35
G35
M35
N35
T35
Y35
V35
P35
R35
U35
W35
C36
AA36
AE35
AJ36
AL36
AF36
AE36
AB36
AC36
AN36
AD36
T37
Y37
V37
P37
K37
E37
H37
M37
AG37
VCCP
AB26
AA26
Y26
AB25
AA25
Y25
AB24
AA24
Y24
AB23
AA23
Y23
AB22
AA22
Y22
AB21
AA21
Y21
R21
AB20
AA20
AB19
AA19
AB18
AA18
AB17
AA17
Y17
R17
AB16
AA16
Y16
W16
V16
U16
T16
R16
P16
N16
M16
L16
AB15
AA15
Y15
W15
V15
U15
T15
R15
P15
N15
M15
L15
AB14
AA14
Y14
W14
V14
U14
T14
R14
P14
N14
M14
L14
AA13
Y13
AA12
Y12
U38D
C C
VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VSS_NCTF13
VSS_NCTF14
VSS_NCTF15
VSS_NCTF16
VSS_NCTF17
VSS_NCTF18
VSS_NCTF19
VSS_NCTF20
VSS_NCTF21
VSS_NCTF22
VSS_NCTF23
VSS_NCTF24
VSS_NCTF25
VSS_NCTF26
VSS_NCTF27
VSS_NCTF28
VSS_NCTF29
VSS_NCTF30
VSS_NCTF31
VSS_NCTF32
VSS_NCTF33
VSS_NCTF34
VSS_NCTF35
VSS_NCTF36
VSS_NCTF37
VSS_NCTF38
VSS_NCTF39
VSS_NCTF40
VSS_NCTF41
VSS_NCTF42
VSS_NCTF43
VSS_NCTF44
VSS_NCTF45
VSS_NCTF46
VSS_NCTF47
VSS_NCTF48
VSS_NCTF49
VSS_NCTF50
VSS_NCTF51
VSS_NCTF52
VSS_NCTF53
VSS_NCTF54
VSS_NCTF55
VSS_NCTF56
VSS_NCTF57
VSS_NCTF58
VSS_NCTF59
VSS_NCTF60
VSS_NCTF61
VSS_NCTF62
VSS_NCTF63
VSS_NCTF64
VSS_NCTF65
VSS_NCTF66
VSS_NCTF67
VSS_NCTF68
L12
M12
VTT_NCTF17
VTT_NCTF16
N12
VTT_NCTF15
P12
R12
VTT_NCTF14
T12
VTT_NCTF13
VTT_NCTF12
U12
VTT_NCTF11
V12
VTT_NCTF10
W12
VTT_NCTF9
W13
V13
U13
T13
R13
P13
N13
M13
L13
VTT_NCTF0
VTT_NCTF1
VTT_NCTF2
VTT_NCTF3
VTT_NCTF4
VTT_NCTF5
VTT_NCTF6
VTT_NCTF7
VTT_NCTF8
NCTF
VCCSM_NCTF0
VCCSM_NCTF1
VCCSM_NCTF2
VCCSM_NCTF3
VCCSM_NCTF4
VCCSM_NCTF5
VCCSM_NCTF6
VCCSM_NCTF7
VCCSM_NCTF8
VCCSM_NCTF9
VCCSM_NCTF10
VCCSM_NCTF11
VCCSM_NCTF12
VCCSM_NCTF13
VCCSM_NCTF14
VCCSM_NCTF15
VCCSM_NCTF16
VCCSM_NCTF17
VCCSM_NCTF18
VCCSM_NCTF19
VCCSM_NCTF20
VCCSM_NCTF21
VCCSM_NCTF22
VCCSM_NCTF23
VCCSM_NCTF24
VCCSM_NCTF25
VCCSM_NCTF26
VCCSM_NCTF27
VCCSM_NCTF28
VCCSM_NCTF29
VCCSM_NCTF30
VCCSM_NCTF31
VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72
VCC_NCTF73
VCC_NCTF74
VCC_NCTF75
VCC_NCTF76
VCC_NCTF77
VCC_NCTF78
R22
L23
T22
U22
P23
V22
N23
M23
W22
M18
N18
L19
Y18
P18
R18
L17
N17
M17
D D
L18
T17
V17
P17
U17
W17
M19
N19
L20
Y19
P19
R19
M20
N20
L21
Y20
P20
N21
R20
M21
L22
T21
P21
U21
P22
V21
N22
M22
W21
R23
L24
T23
U23
P24
V23
N24
M24
W23
R24
L25
T24
U24
P25
V24
N25
M25
W24
R25
L26
M26
N26
T26
V26
P26
U26
R26
W26
AB13
AB12
AC12
AD14
AC14
AD13
AC13
AD12
AD17
AC17
AD16
AC16
AD15
AC15
AD20
AC20
AD19
AC19
AD18
AC18
AD23
AC23
AD22
AC22
AD21
AC21
AD26
AC26
AD25
AC25
AD24
AC24
2.5VSUSVCCP
T25
V25
U25
W25
PROJECT : CT3
Quanta Computer Inc.
Size Document Number Rev
1
2
3
4
5
6
Date: Sheet
ALVISO VSS/NCTF
7
of
942Friday, March 04, 2005
8
1ACustom
1
VCCP
FERR#
R562 56 R
H_DPSLP#
R563 *56R
RCIN#
GATEA20
PIORDY
PCI_RST#
R565 10K
R566 10K
R567 4.7K
3VPCU
C829
1000P
+3V
1
2
R584 *0R
1
12
PLTRST#5,11,28
53
A A
B B
C C
D D
D23
2 1
RB500V-40
D24
2 1
RB500V-40
BT1
RTC-BAT
C831 0.1U
4
U42
TC7SH08FU
+3V
+3V
+3V
PCLK_ICH
R676
*22R
C1033
*22P
C825
VCCRTC
1 3
PLTRST#
15P
2
R583 47R
RTC
VCCRTC
R577
20K
1 2
Q49
MMBT3904
RTC_N02
4
2
Y10
32.768KHZ
C827 1U/16V
R578 3K
3VSUS
C830 0.047U
5
U41
2
1
7SZ32
2
R564
10M
C826
15P
VCCRTC
CPUINIT#3
RTCRST#
C828
1U/16V
5VPCU
R579
4.7K
R580
15K
PCI_PME#14,17,23
PCLK_ICH2
CLKRUN#14,17,23
12
PLTRST#_1
PDD[0..15]28
PDDACK#28
PCIRST# 14,17,23,27
NMI3
A20M#3
IGNNE#3
INTR3
RCIN#27
GATEA2027
AD[0..31]14,17,23
12
G1
*SHORT_ PAD1
PDCS1#28
PDCS3#28
PDA028
PDA128
PDA228
PDIOR#28
PDIOW#28
PIORDY28
IRQ1428
PDDREQ28
3
R569 1M
AD[0..31]
+3V
PDD[0..15]
3
CLK_32KX1
CLK_32KX2
RTCRST#
SM_INTRUDER#
NMI
A20M#
FERR#
R571 56R
IGNNE#
INTR
CPUINIT#
RCIN#
GATEA20
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PCLK_ICH
PCI_RST#
PLTRST#_1
R581 8.2K
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
PDCS1#
PDCS3#
PDA0
PDA1
PDA2
PDIOR#
PDIOW#
PIORDY
IRQ14
PDDREQ
PDDACK#
AA2
AA3
AA5
AF25
AF23
AF24
AG26
AG24
AF27
AD23
AF22
AF19
AD14
AF15
AF14
AD12
AE14
AC11
AD11
AB11
AE13
AF13
AB12
AB13
AC13
AE15
AG15
AD13
AD16
AE17
AC16
AB17
AC17
AE16
AC14
AF16
AB16
AB14
AB15
Y1
Y2
E2
E5
C2
F5
F3
E9
F2
D6
E6
D3
A2
D2
D5
H3
B4
J5
K2
K5
D4
L6
G3
H4
H2
H5
B3
M6
B2
K6
K3
A5
L1
K4
P6
G6
R2
R5
4
U40A
RTCX1
RTCX2
RTCRST#
INTRUDER#
INTVRMEN
NMI
A20M#
FERR#
IGNNE#
INTR
INIT#
RCIN#
A20GATE
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PME#
PCICLK
PCIRST#
PLTRST#
CLKRUN#/GPIO32
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
DCS1#
DCS3#
DA0
DA1
DA2
DIOR#
DIOW#
IORDY
IDEIRQ
DDREQ
DDACK#
ICH6-M_14
4
RTC
CPU
PCI
IDE
LAD0
LAD1/FB1
LAD2/FB2
LAD3/FB3
LDRQ0#
LDRQ1#/GPI41
LFRAME#
LPC
CPUPWRGD/GPO49
INIT3_3V#
THRMTRIP#
SMI#
STPCLK#
CPUSLP#
DPSLP#/TP[2]
DPRSLP#/TP[4]
C/BE0#
C/BE1#
C/BE2#
C/BE3#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
SERR#
PERR#
PLOCK#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#/GPI40
REQ5#/GPI1
REQ6#/GPI0
GNT0#
GNT1#
GNT2#
GNT3#
GNT4#/GPO48
GNT5#/GPO17
GNT6#/GPO16
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPI2
PIRQF#/GPI3
PIRQG#/GPI4
PIRQH#/GPI5
SATALED#
SATA0_RXN
SATA0_RXP
SATA0_TXN
SATA0_TXP
SATA2_RXN
SATA2_RXP
SATA2_TXN
SATA2_TXP
SATA_CLKN
SATA
SATA_CLKP
SATARBIAS#
SATARBIAS
ACZ_BIT_CLK
ACZ_SYNC
ACZ_RST#
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
ACZ_SDO
AC-97/
AZALIA
5
P2
N3
N5
N4
N6
GPI41
P4
P3
AG25
AE22
AE23
R573 0R
AG27
AE26
AE27
AD27
AE24
J6
H6
G4
G2
J3
A3
J2
C3
J1
E1
G5
E3
C5
L5
B5
M5
B8
F7
E8
B7
C1
B6
F1
C8
E7
F6
D8
N2
L2
M1
L3
D9
C7
C6
M3
AC19
AE3
AD3
AG2
AF2
AD7
AC7
AF6
AG6
AC2
AC1
AG11
AF11
C10
B9
R706 33R
A10
F11
F10
B10
C9
0-AC97
1-MODEM
5
Internal already pull-up
LAD0/FWH0 27
LAD1/FWH1 27
LAD2/FWH2 27
LAD3/FWH3 27
LPC_DRQ0# 27
LFRAME#/FWH4 27
CPUPWRGD
THERMTRIP#_ICH
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
SERR#
PERR#
PLOCK#
REQ0#
REQ1#AD16
REQ2#
REQ3#
GPI40
LBAYID0
LBAYID1
INTB#
INTH#
AC_SDIN2
CPUPWRGD 3
T257
STPCLK#
R574 *0R
R575 0R
R576 0R
C/BE0# 14,17,23
C/BE1# 14,17,23
C/BE2# 14,17,23
C/BE3# 14,17,23
FRAME# 14,17,23
IRDY# 14,17,23
TRDY# 14,17,23
DEVSEL# 14,17,23
STOP# 14,17,23 CRT_SENSE# 11,30
PAR 14,17,23
SERR# 14,17,23
PERR# 14,17,23
PLOCK# 17
REQ0# 17
REQ1# 14
REQ2# 23
GNT0# 17
GNT1# 14
GNT2# 23
T260
T261
T262
T263
INTA# 23
INTC# 14
INTD# 14
INTE# 17
INTF# 17
INTG# 17
T307
Connect to GND if
T292
T293
S-ATA didn't use on
platform
T294
T295
SI stage:
Intel suggest ed us to add a terminal resistor R706 for
-CODEC_RST to im prov e signal quality.
BITCLK_SB
SYNC1 14,20,22
-CODEC_RST 14,20,22
SDINA 20,22
SDINB 14
T269
SDOUT1 14,20,22
R572 56R
6
VCCP
R570
75R
SMI# 3
STPCLK# 3
H_CPUSLP# 3,5
H_DPSLP# 3
H_DPRSTP# 3
These signals
have internal
pull-up
PIRQA#: RTL8100CL
PIRQB#: NC
PIRQC#: MINI PCI
PIRQD#: MINI PCI
PIRQE#: 7411
PIRQF#: 7411
PIRQG#: 7411
PIRQH#: Internal USB
6
THRMTRIP# 3,5FERR#3
SERIRQ11,14,17,27
PV stage:
GPI40 & GPI41 for bios request.
L69
BK2125HM121-T
BITCLK_SB
7
Description
For Doathan A-X step
For Doathan B-X step & later
R574
56
*0
8
R576
*0
0
PCI Pullups
REQ2#
STOP#
REQ0#
INTB#
+3V
RP52
GPI40
GPI41
6
7
8
9
10
6
7
8
9
10
INTG#
INTF#
INTE#
INTH#
8.2KX8
RP53
8.2KX8
R749 8.2K
R750 8.2K
REQ3#
SERIRQ
+3V
IRDY#
DEVSEL#3VRTC RTC_N01
REQ1#
PLOCK#
+3V
Griffey 12/23/2004
Sting 10/12/2004
BITCLK 20,22
C1051
22P
PV-II stage:
EMI team sug gest us to add a Bead and a Capacity
to improve EMI.
BITCLK_SB 14
Size Document Number Rev
Date: Sheet
ICH6-M (CPU/PCI/IDE)
7
RP51
10
+3V
5
4
3
2
CRT_SENSE#
1
+3V
5
4
3
2
1
RP54
7 8
5 6
3 4
1 2
8P4R-8.2K
6
7
8
9
FRAME#
TRDY#
IRQ14
LBAYID1
PERR#
SERR#
LBAYID0
8.2KX8
+3V
5
4
3
2
1
Mika 02/03/2005
PROJECT : CT3
Quanta Computer Inc.
10 42Friday, March 04, 2005
8
+3V
INTA#
INTD#
INTC#
of
3ACustom
A
B
C
D
E
U40B
USBP0+19
CLK48_USB2
DMI_RXN05
DMI_RXP05
DMI_TXN05
DMI_TXP05
DMI_RXN15
DMI_RXP15
DMI_TXP15
SRC_ICH#2
PCLK_SMB2
PDAT_SMB2
ICH_THRM#3
DPRSLPVR33
DNBSWON#27
RSMRST#27
PM_BMBUSY#5
CRT_SENSE#10,30
D25 1SS355
R738 0
R739 0
5
U44A
1 6
*NC7WZ14P6X
USBP0-19
USBP2+32
USBP2-32
USBP4+31
USBP4-31
SRC_ICH2
RI#17
PWROK27
BATLOW#27
IMVPOK5,33
14M_ICH2
SPK20
KBSMI#27
LCDID015
CLK48_USB 14M_ICH OC7#
DASP_ON
SUSB#
PLTRST#
PWROK
RSMRST#
R678
*22R
C1035
*22P
RF_OFF#14,27
BT_OFF#27,32
PV stage:
1. Add RF_OFF# and BT_OFF#
circuit.
C832
R594
*10K
*0.1U
Griffey 12/ 10 /2004
SCI#27
SWI#27
4 4
3 3
+3V
3VSUS
2 2
R591 *10K
+3V
3V_S5
1 1
R677
22R
C1034
5.6P
R587 10K
R595 *10K
R624 *10K
R588 10K
R590 10K
RP57
SUS_STAT#
7 8
BATLOW#
5 6
DBR#
3 4
RI#
1 2
8P4R-10K
RP58
SWI_#
7 8
5 6
SMLINK1
3 4
SMLINK0
1 2
8P4R-10K
RP59
PDAT_SMB
7 8
PCLK_SMB
5 6
SMBALERT#
3 4
SMB_LINK_ALERT#
1 2
8P4R-10K
R710 10K
R711 10K
R593 680R
SUSC#
ICH_THRM#
SCI_#
PCIE_WAKE#
USBP0+
USBP0ÂOC0#
USBP2+
USBP2ÂOC2#
USBP4+
USBP4ÂOC4#
OC6#
CLK48_USB
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
DMI_RXN1 DMI_RXN3
DMI_RXP1
DMI_TXN1
DMI_TXP1
SRC_ICH#
SRC_ICH
T270
T272
T274
T276
T278
T280
T282
T284
PCLK_SMB
PDAT_SMB
SMBALERT#
RI#
ICH_THRM#
PWROK
DPRSLPVR
BATLOW#
DNBSWON#
RSMRST#
IMVPOK
PM_BMBUSY#
SUS_STAT#
SUSCLK
T296
14M_ICH
SPK
CRT_SENSE#
KBSMI#
21
21
D26 1SS355
SB_RF_OFF#
SB_BT_OFF#
LCDID0
R596
*1K
R598
*0R
SCI_#
SWI_#
D21
C21
C27
C19
D19
B26
D17
E17
C23
D15
C15
C25
A27
T25
T24
R27
R26
V25
V24
U27
U26
AD25
AC25
H25
H24
G27
G26
K25
K24
J27
J26
Y4
W5
W6
T2
AC20
AA1
AE20
V2
U1
Y3
AF21
AD19
W3
V6
E10
F8
AE19
R1
M2
R6
AB21
AD20
AD21
V3
D12
B12
D11
F13
AC5
AD5
AF4
AG4
AC9
3V_S53V_S53V_S5
5
U44B
3 4
*NC7WZ14P6X
USBP0P
USBP0N
OC0#
USBP2P
USBP2N
OC2#
USBP4P
USBP4N
OC4#/GPI9
USBP6P
USBP6N
OC6#/GPI14
CLK48
DMI0_RXN
DMI0_RXP
DMI0_TXN
DMI0_TXP
DMI1_RXN
DMI1_RXP
DMI1_TXN
DMI1_TXP
DMI_CLKN
DMI_CLKP
HSIN0
HSIP0
PCI-EXPRESS
HSON0
HSOP0
HSIN1
HSIP1
HSON1
HSOP1
SMBCLK
SMBDATA
SMBALERT#/GPI11
RI#
THRM#
PWROK
DPRSLPVR/TP1
BATLOW#/TP0
PWRBTN#
RSMRST#
VRMPWRGD
BM_BUSY#/GPIO6
SUS_STAT#/LPCPD#
SUSCLK
CLK14
SPKR
GPI7
GPI8
GPI12
GPI13
GPO19
GPO21
GPO23
GPIO24
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
ICH6-M_14
SM&SMI
MISC&GPIO
RESERVED
RSMRST#
USB
DMI
PM
LAN
USBP1P
USBP1N
OC1#
USBP3P
USBP3N
OC3#
USBP5P
USBP5N
OC5#/GPI10
USBP7P
USBP7N
OC7#/GPI15
USBRBIAS
USBRBIAS#
DMI2_RXN
DMI2_RXP
DMI2_TXN
DMI2_TXP
DMI3_RXN
DMI3_RXP
DMI3_TXN
DMI3_TXP
DMI_ZCOMP
DMI_IRCOMP
HSIN2
HSIP2
HSON2
HSOP2
HSIN3
HSIP3
HSON3
HSOP3
SMLINK0
SMLINK1
LINKALERET#
SLP_S3#
SLP_S4#
SLP_S5#
LAN_RST#
SYS_RESET#
WAKE#
MCH_SYNC#
STP_PCI#/GPO18
STP_CPU#/GPO20
SERIRQ
GPIO25
SATA0GP/GPIO26
GPIO27
GPIO28
SATA1GP/GPIO29
SATA2GP/GPIO30
SATA3GP/GPIO31
GPIO33
GPIO34
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
LAN_CLK
LAN_RSTSYNC
RSVD6
RSVD7
RSVD8
RSVD9
B20
A20
B27
B18
A18
C26
A16
B16
D23
B14
A14
C24
B22
A22
Y25
Y24
W27
W26
AB24
AB23
AA27
AA26
F24
F23
M25
M24
L27
L26
P24
P23
N27
N26
W4
U6
Y5
T4
T5
T6
V5
U2
U5
AG21
AC21
AD22
AB20
P5
AF17
R3
T3
AE18
AF18
AG18
AF20
AC18
E12
E11
C13
C12
C11
E13
F12
B11
AD9
AF8
AG8
U3
LCDID0
LCDID1
LCDID2
USBP1+
USBP1ÂOC1#
OC3#
USBP5+
USBP5ÂOC5#
OC7#
USBRBIAS
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
DMI_RXP3
DMI_TXN3
DMI_TXP3
DMI_ZCOMP
SMLINK0
SMLINK1
SMB_LINK_ALERT#
SUSB#
SUSC#
PLTRST#
DBR#
PCIE_WAKE#
MCH_SYNC#
STP_PCI#
STP_CPU#
SERIRQ
SM_EN#
SATA0GP
FPBACK#
LCDID1
SATA1GP
SATA2GP
SATA3GP
DASP_ON
LCDID2
Enable Cable ID
RN151
1
3
5
7 8
8P4R-10K
USBP1+ 19
USBP1- 19
USBP5+ 32
USBP5- 32
R585 22.6/F
DMI_RXN2 5
DMI_RXP2 5
DMI_TXN2 5
DMI_TXP2 5
DMI_RXN3 5
DMI_RXP3 5
DMI_TXN3 5DMI_TXN15
DMI_TXP3 5
R586 24.9/F
T271
T273
T275
T277
T279
T281
T283
T285
SUSB# 27
SUSC# 27
T286
PLTRST# 5,10,28
DBR# 3
STP_PCI# 2
STP_CPU# 2,33
SERIRQ 10,14,17,27
T288
FPBACK# 15
LCDID1 15
DASP_ON 28
LCDID2 15
+3V
2
4
6
OC5#
OC4#
3VSUS
Place within 500mils of ICH-6
Place within 500mils of ICH-6
+1.5V
LAN_RST# should be connected to
PLTRST# if internal LAN didn't use.
MCH_SYNC#
SI stage:
R589 should be populated, because
MCH_SYNC# is internally ANDed with
PWROK.System will not booting
without this pulled-up resistor.
RP55
6
7
8
9
10
10KX8
R589 10K
5
OC0#OC6#
4
OC3#
3
OC2#
2
OC1#
1
SATA1GP
SATA2GP
SATA3GP
SATA0GP
These signals should be
pulled-up to +3V via a 8.2K~10K
if didn't used as S-ATA interlock
switch or GPI signals.
+3V
Sting 09/24/2004
RP56
2
4
6
8
8P4R-10K
3VSUS
1
3
5
7
+3V
1. Change the power plane of PCIE_WAKE#
from 3VSUS to 3V_S5 to solve system can't
turn off issue.
2. Change the power plane of ICH_THRM#
and SCI_# from 3VSUS to +3V to solve
leakage issue.
A
Sting 10/06/2004
B
C
D
Size Document Number Rev
Date: Sheet
PROJECT : CT3
Quanta Computer Inc.
ICH6-M (USB/HUB/LPC)
11 42Friday, March 04, 2005
E
2ACustom
of
5
4
3
2
1
A12
A15
A19
A21
A23
A26
AA11
AA13
AA16
AA4
AB1
AB10
AB19
AB2
AB7
AB9
AC10
AC12
AC22
AC23
AC24
AC26
AC3
AC6
AD1
AD10
AD15
AD18
AD2
AD24
AD6
AE10
AE11
AE12
AE2
AE21
AE25
AE6
AE7
AF1
AF10
AF12
AF26
AF3
AF7
AG1
AG12
AG14
AG17
AG20
AG22
AG3
AG7
B13
B15
B19
B21
B23
B24
B25
C14
C18
C20
C22
D10
D13
D14
D18
D20
D22
E14
E15
E18
E19
E25
U40D
A1
VSS001
VSS002
VSS003
VSS004
VSS005
VSS006
VSS007
A4
VSS008
A7
VSS009
A9
VSS010
VSS011
VSS012
VSS013
VSS014
VSS015
VSS016
VSS017
VSS018
VSS019
VSS020
VSS021
VSS022
VSS023
VSS024
VSS025
VSS026
VSS027
VSS028
VSS029
VSS030
VSS031
VSS032
VSS033
VSS034
VSS035
VSS036
VSS037
VSS038
VSS039
VSS040
VSS041
VSS042
VSS043
VSS044
VSS045
VSS046
VSS047
VSS048
VSS049
VSS050
VSS051
VSS052
VSS053
VSS054
VSS055
VSS056
VSS057
VSS058
VSS059
VSS060
VSS061
VSS062
VSS063
VSS064
VSS065
VSS066
VSS067
VSS068
C4
VSS069
D1
VSS070
VSS071
VSS072
VSS073
VSS074
VSS075
VSS076
D7
VSS077
VSS078
VSS079
VSS080
VSS081
VSS082
F17
VSS083
F19
VSS084
F22
VSS085
F4
VSS086
GND
ICH6-M_14
VSS087
VSS088
VSS089
VSS090
VSS091
VSS092
VSS093
VSS094
VSS095
VSS096
VSS097
VSS098
VSS099
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
G1
G12
G21
G7
G9
H23
H26
H27
J23
J24
J25
J4
K1
K23
K26
K27
K7
L13
L15
L23
L24
L25
M12
M13
M14
M15
M16
M23
M26
M27
M4
N1
N11
N12
N13
N14
N15
N16
N17
N7
P12
P13
P14
P15
P16
P22
R11
R12
R13
R14
R15
R16
R17
R23
R24
R25
R4
T1
T12
T13
T14
T15
T16
T23
T26
T27
T7
U13
U15
U23
U24
U25
V23
V26
V27
V4
W1
W23
W24
W25
W7
Y23
Y26
Y27
Y6
E27
L63
1 2
+1.5V
BLM41P600SPG
D D
R599 10R
+5V
D27
2 1
+3V
RB751V-40
PV stage:
The root cau se th at is 3V_S5 leakage
current to 5VSUS by R712 on S4/S5 stage.
SI stage:
We can also use 5VSUS to instead of 5V_S5
to save cost if 5V_S5 isn't implemetation on
system.
C C
B B
A A
5V_S5
3V_S5
+3V
3V_S5
+1.5V
+1.5V
3V_S5
3V_S5
R600 10R
D28
2 1
C861
0.1U
R601
1R
C867
10U/10V/0805
C870
0.1U
RB751V-40
+1.5V
C862
0.1U
C875
0.1U
C882
0.1U
+1.5V_PCIE
+
C844
1U/16V
C863
0.1U
L64
BLM11A121S
C871
0.1U
C876
0.1U
C878
0.1U
C883
0.1U
C834
C833
0.1U
220U/4V
V5REF
C845
0.1U
Griffey 12/13/2004
V5REF_SUS
V5REF_SUS
C853
C854
1U/16V
0.1U
+1.5V
12
+3V
C872
0.1U
C879
0.1U
C884
0.1U
600mA
C835
0.1U
Sting 10/12/2004
R712*10R
5VSUS
C856
C857
0.1U
0.1U
C868
0.01U_0402
C885
0.1U
C836
0.1U
C858
0.1U
U40C
AA22
VCC1_5_1
AA23
VCC1_5_2
AA24
VCC1_5_3
AA25
VCC1_5_4
AB25
VCC1_5_5
AB26
VCC1_5_6
AB27
VCC1_5_7
F25
VCC1_5_8
F26
VCC1_5_9
F27
VCC1_5_10
G22
VCC1_5_11
G23
VCC1_5_12
G24
VCC1_5_13
G25
VCC1_5_14
H21
VCC1_5_15
H22
VCC1_5_16
J21
VCC1_5_17
J22
VCC1_5_18
K21
VCC1_5_19
K22
VCC1_5_20
L21
VCC1_5_21
L22
VCC1_5_22
M21
VCC1_5_23
M22
VCC1_5_24
N21
VCC1_5_25
N22
VCC1_5_26
N23
VCC1_5_27
N24
VCC1_5_28
N25
VCC1_5_29
P21
VCC1_5_30
P25
VCC1_5_31
P26
VCC1_5_32
P27
VCC1_5_33
R21
VCC1_5_34
R22
VCC1_5_35
T21
VCC1_5_36
T22
VCC1_5_37
U21
VCC1_5_38
U22
VCC1_5_39
V21
VCC1_5_40
V22
VCC1_5_41
W21
VCC1_5_42
W22
VCC1_5_43
Y21
VCC1_5_44
Y22
VCC1_5_45
AA6
VCC1_5_46
AB4
VCC1_5_47
AB5
VCC1_5_48
AB6
VCC1_5_49
AC4
VCC1_5_50
AD4
VCC1_5_51
AE4
VCC1_5_52
AE5
VCC1_5_53
AF5
VCC1_5_54
AG5
VCC1_5_55
AA7
VCC1_5_56
AA8
VCC1_5_57
AA9
VCC1_5_58
AB8
VCC1_5_59
AC8
VCC1_5_60
AD8
VCC1_5_61
AE8
VCC1_5_62
AE9
VCC1_5_63
AF9
VCC1_5_64
AG9
VCC1_5_65
AC27
VCCDMIPLL
E26
VCC3_3_1
AE1
VCCSATAPLL
AG10
VCC3_3_22
A13
VCCLAN3_3/VCCSUS3_3_1
F14
VCCLAN3_3/VCCSUS3_3_2
G13
VCCLAN3_3/VCCSUS3_3_3
G14
VCCLAN3_3/VCCSUS3_3_4
A11
VCCSUS3_3_1
U4
VCCSUS3_3_2
V1
VCCSUS3_3_3
V7
VCCSUS3_3_4
W2
VCCSUS3_3_5
Y7
VCCSUS3_3_6
A17
VCCSUS3_3_7
B17
VCCSUS3_3_8
C17
VCCSUS3_3_9
F18
VCCSUS3_3_10
G17
VCCSUS3_3_11
G18
VCCSUS3_3_12
ICH6-M_14
VCC1_5_79
VCC1_5_80
VCC1_5_81
VCC1_5_82
VCC1_5_83
VCC1_5_84
VCC1_5_85
VCC1_5_86
VCC1_5_87
VCC1_5_88
VCC1_5_89
VCC1_5_90
VCC1_5_91
VCC
VCCLAN1_5/VCCSUS1_5_1
VCCLAN1_5/VCCSUS1_5_2
VCC1_5_92
VCC1_5_93
VCC1_5_94
VCC1_5_95
VCC1_5_96
VCC1_5_97
VCC1_5_98
VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6
VCC3_3_7
VCC3_3_8
VCC3_3_9
VCC3_3_10
VCC3_3_11
VCC3_3_12
VCC3_3_13
VCC3_3_14
VCC3_3_15
VCC3_3_16
VCC3_3_17
VCC3_3_18
VCC3_3_19
VCC3_3_20
VCC3_3_21
VCCSUS1_5_1
VCCSUS1_5_2
VCCSUS1_5_3
VCC1_5_67
VCC1_5_68
VCC1_5_69
VCC1_5_70
VCC1_5_71
VCC1_5_72
VCC1_5_73
VCC1_5_74
VCC1_5_75
VCC1_5_76
VCC1_5_77
VCC1_5_78
VCC2_5_2
VCC2_5_4
V5REF_SUS
VCCUSBPLL
VCCSUS3_3_20
VCCRTC
V_CPU_IO1
V_CPU_IO2
V_CPU_IO3
VCCSUS3_3_13
VCCSUS3_3_14
VCCSUS3_3_15
VCCSUS3_3_16
VCCSUS3_3_17
VCCSUS3_3_18
VCCSUS3_3_19
V5REF1
V5REF2
AA19
AA20
AA21
L11
L12
L14
L16
L17
M11
M17
P11
P17
T11
T17
U11
U12
U14
U16
U17
F9
A6
B1
E4
H1
H7
J7
L4
L7
M7
P1
AA12
AA14
AA15
AA17
AC15
AD17
AG13
AG16
AG19
AA10
G19
R7
U7
G8
D24
D25
D26
D27
E20
E21
E22
E23
E24
F20
G20
P7
AB18
A8
AA18
F21
A25
A24
AB3
G10
G11
AB22
AD26
AG23
C16
D16
E16
F15
F16
G15
G16
+1.5V
V5REF
V5REF_SUS
VCCRTC
1.5V_S5
C846
0.1U
C850
0.1U
C837
0.1U
C838
0.1U
C847
0.1U
C851
0.1U
C864
1U/16V
C839
0.1U
C848
0.1U
C852
1U/16V
C855
0.1U
C859
0.1U
C865
0.1U
C869
0.1U
C874
0.1U
C877
0.1U
C840
0.1U
+3V
C849
1U/16V
+3V
C860
0.1U
C866
0.1U
3V_S5
VCCP
C880
0.1U
C841
0.01U_0402
1.5V_S5
1.5V_S5
+1.5V
+2.5V
C873
0.01U_0402
VCCRTC
C881
0.1U
C842
10U/10V/0805
+1.5V
+1.5V
C843
10U/10V/0805
PROJECT : CT3
Quanta Compu t er Inc.
Size Document Number Re v
5
4
3
2
Date: Sheet
ICH6-M (POWER)
12 42Friday, March 04, 2005
1
2ACustom
of
1
2
3
4
5
6
7
8
2.5VSUS2.5VSUS
SMDDR_VREFSMDDR_VREF
SODIMM0 SODIMM1
CN14
1
VREF
A A
CLK_SDRAM05
CLK_SDRAM0#5
B B
2.5VSUS
R634 200R
R636 200R
C C
D D
+3V
MD1
MD0
SM_DQS0
MD7
MD2
MD8
MD13
SM_DQS1
MD11
MD10
CLK_SDRAM0
CLK_SDRAM0#
MD16
MD17
SM_DQS2
MD19
MD18
MD24
MD25
SM_DQS3
MD26
MD31
CKE1
M_A_MA12
M_A_MA9
M_A_MA7
M_A_MA5
M_A_MA3
M_A_MA1
M_A_MA10
M_A_BA0
M_A_BMWEA#
SM_CS0#
M_A_MA13
MD33
MD32
SM_DQS4
MD34
MD35
MD40
MD41
SM_DQS5
MD46
MD47
MD53
MD48
SM_DQS6
MD50
MD51
MD56
MD60
SM_DQS7
MD59
MD58
SMBDT
SMBCK
R638 *10K
C992
0.1U
1
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2
93
VDD
95
CKE1
97
DU
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE
121
S0
123
DU(A13)
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD(SPD)
199
VDD(ID)
AMP_DDR_SODIMM_H5.2
VREF
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQ30
DQ31
DU/RESET
CKE0
DU/BA2
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQ46
DQ47
DQ52
DQ53
DQ54
DQ55
DQ60
PC2100 DDR SDRAM SO-DIMM (200P)
DQ61
DQ62
DQ63
2
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
VDD
DM1
VSS
VDD
VDD
VSS
VSS
VDD
DM2
VSS
VDD
DM3
VSS
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
VSS
VSS
VDD
VDD
VSS
VDD
BA1
RAS
CAS
VSS
VDD
DM4
VSS
VDD
DM5
VSS
VDD
CK1
CK1
VSS
VDD
DM6
VSS
VDD
DM7
VSS
VDD
SA0
SA1
SA2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
A11
102
A8
104
106
A6
108
A4
110
A2
112
A0
114
116
118
120
122
S1
124
DU
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DU
MD5
MD4
SDM0
MD6
MD3
MD9
MD12
MD14
MD15
MD20
MD21
SDM2
MD23
MD22
MD28
MD29
SDM3
MD30
MD27
CKE0
M_A_MA11
M_A_MA8
M_A_MA6
M_A_MA4
M_A_MA2
M_A_MA0
M_A_BA1
M_A_SRASA#
M_A_SCASA#
SM_CS1#
MD37
MD36
SDM4
MD38
MD39
MD45
MD44
SDM5
MD43
MD42
CLK_SDRAM1#
CLK_SDRAM1
MD49
MD52
SDM6
MD54
MD55
MD61
MD57
SDM7
MD62
MD63
SMbus address A0
CLK_SDRAM35
CLK_SDRAM3#5
2.5VSUS
CLK_SDRAM1# 5
CLK_SDRAM1 5
3
R635 200R
R637 200R
SMBDT2
SMBCK2
+3V
MD1
MD0
SM_DQS0
MD7
MD2
MD8
MD13
SM_DQS1SDM1
MD11
MD10
CLK_SDRAM3
CLK_SDRAM3#
MD16
MD17
SM_DQS2
MD19
MD18
MD24
MD25
SM_DQS3
MD26
MD31
CKE3
M_B_MA12
M_B_MA9
M_B_MA7
M_B_MA5
M_B_MA3
M_B_MA1
M_B_MA10
M_B_BA0
M_B_BMWEA#
SM_CS2#
M_B_MA13
MD33
MD32
SM_DQS4
MD34
MD35
MD40
MD41
SM_DQS5
MD46
MD47
MD53
MD48
SM_DQS6
MD50
MD51
MD56
MD60
SM_DQS7
MD59
MD58
SMBDT
SMBCK
R639 * 10K
C993
0.1U
SMDDR_VREF
4
CN13
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2
93
VDD
95
CKE1
97
DU
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE
121
S0
123
DU(A13)
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD(SPD)
199
VDD(ID)
AMP_DDR_SODIMM_H9.2
CLOCK 3,4CLOCK 0,1
CKE 2,3CKE 0,1
DU/RESET
DU/BA2
PC2100 DDR SDRAM SO-DIMM (200P)
SMDDR_VREF
2
VREF
4
VSS
6
DQ4
8
DQ5
10
VDD
12
DM0
14
DQ6
16
VSS
18
DQ7
20
DQ12
22
VDD
24
DQ13
26
DM1
28
VSS
30
DQ14
32
DQ15
34
VDD
36
VDD
38
VSS
40
VSS
42
DQ20
44
DQ21
46
VDD
48
DM2
50
DQ22
52
VSS
54
DQ23
56
DQ28
58
VDD
60
DQ29
62
DM3
64
VSS
66
DQ30
68
DQ31
70
VDD
72
CB4
74
CB5
76
VSS
78
DM8
80
CB6
82
VDD
84
CB7
86
88
VSS
90
VSS
92
VDD
94
VDD
96
CKE0
98
100
A11
102
A8
104
VSS
106
A6
108
A4
110
A2
112
A0
114
VDD
116
BA1
118
RAS
120
CAS
122
S1
124
DU
126
VSS
128
DQ36
130
DQ37
132
VDD
134
DM4
136
DQ38
138
VSS
140
DQ39
142
DQ44
144
VDD
146
DQ45
148
DM5
150
VSS
152
DQ46
154
DQ47
156
VDD
158
CK1
160
CK1
162
VSS
164
DQ52
166
DQ53
168
VDD
170
DM6
172
DQ54
174
VSS
176
DQ55
178
DQ60
180
VDD
182
DQ61
184
DM7
186
VSS
188
DQ62
190
DQ63
192
VDD
194
SA0
196
SA1
198
SA2
200
DU
2.5VSUS2.5VSUS
MD5
MD4
SDM0
MD6
MD3
MD9
MD12
SDM1
MD14
MD15
MD20
MD21
SDM2
MD23
MD22
MD28
MD29
SDM3
MD30
MD27
CKE2
M_B_MA11
M_B_MA8
M_B_MA6
M_B_MA4
M_B_MA2
M_B_MA0
M_B_BA1
M_B_SRASA#
M_B_SCASA#
SM_CS3#
MD37
MD36
SDM4
MD38
MD39
MD45
MD44
SDM5
MD43
MD42
CLK_SDRAM4#
CLK_SDRAM4
MD49
MD52
SDM6
MD54
MD55
MD61
MD57
SDM7
MD62
MD63
+3V
SMbus address A1
5
2.5VSUS
C937
0.1U
2.5VSUS
C947
0.1U
2.5VSUS
C957
0.1U
2.5VSUS
C967
0.1U
2.5VSUS
C977
0.1U
SMDDR_VTERM
C986
0.1U
CLK_SDRAM4# 5
CLK_SDRAM4 5
C939
0.1U
C949
0.1U
C959
0.1U
C969
0.1U
C979
0.1U
C988
0.1U
C940
C941
0.1U
0.1U
C951
C950
0.1U
0.1U
C960
C961
0.1U
0.1U
C970
C971
0.1U
0.1U
C981
C980
0.1U
0.1U
2.5VSUS
C989
0.1U
C990
150U/6.3V_7
M_A_MA[0..13]
M_A_BA0
M_A_BA1
M_A_SRASA#
M_A_SCASA#
M_A_BMWEA#
M_B_MA[0..13]
M_B_BA0
M_B_BA1
M_B_SRASA#
M_B_SCASA#
M_B_BMWEA#
MD[0..63]
SM_DQS[0..7]
SDM[0..7]
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
CKE0
CKE1
CKE2
CKE3
Size Document Number Rev
Date: Sheet
7
C938
0.1U
C948
0.1U
C958
0.1U
C968
0.1U
C978
0.1U
C987
0.1U
6
C943
0.1U
C953
0.1U
C963
0.1U
C973
0.1U
C983
0.1U
M_A_MA[0..13] 7
M_A_BA0 7
M_A_BA1 7
M_A_SRASA# 7
M_A_SCASA# 7
M_A_BMWEA# 7
M_B_MA[0..13] 7
M_B_BA0 7
M_B_BA1 7
M_B_SRASA# 7
M_B_SCASA# 7
M_B_BMWEA# 7
MD[0..63] 7
SM_DQS[0..7] 7
SDM[0..7] 7
SM_CS0# 5,7
SM_CS1# 5,7
SM_CS2# 5,7
SM_CS3# 5,7
CKE0 5,7
CKE1 5,7
CKE2 5,7
CKE3 5,7
C944
0.1U
C954
0.1U
C964
0.1U
C974
0.1U
C984
0.1U
C942
0.1U
C952
0.1U
C962
0.1U
C972
0.1U
C982
0.1U
C991
150U/6.3V_7
PROJECT : CT3
Quanta Computer Inc.
DDR1 DIMM
13
8
C945
0.1U
C955
0.1U
C965
0.1U
C975
0.1U
C985
0.1U
of
C946
0.1U
C956
0.1U
C966
0.1U
C976
0.1U
1A
42Friday, March 04, 2005