Quanta BU1 DABU1MB16E0 Schematic
1
2
3
4
5
6
7
8
PCB STACK UP
BU1 Block Diagram
LAYER 1 : TOP
LAYER 2 : SGND
LAYER 3 : IN1
A A
LAYER 4 : IN2
LAYER 5 : VCC
Page 3,4
LAYER 6 : BOT
R.G.B
LVDS X1
VCC_CORE
CRT
Page 18
LCD(WXGA 13W)
Page 18
Intel
Merom
(35W)
FSB(667/800MHZ)
Crestline GM
533/ 667 MHZ DDR II
CLOCK GENERATOR
CK505
Page 2
ICS9LPR363
DDRII-SODIMM1
DDRII-SODIMM2
Page 12,13
+1.5V
SATA - HDD
+1.05V
B B
+1.25V
+1.8VSUS
+3VPCU
+3V_S5
+3VSUS
+3V
+5VPCU
+5V_S5
+5V
SMDDR_VTERM
SMDDR_VREF
C C
BORD
Page 19
IDE - ODD
Page 19
System 0
Page 24
System 1
Page 24
System 2
Page 24
WLAN
Page 23
Finger Printer
Page 24
Bluetooth
Page 24
New Card
Page 24
Reserved
Page 23
Camera
Page 18
AUDIO/FM/USB DAUGHTER BOARD
G SENSOR
USB PORT 0
USB PORT 1
USB PORT 2
USB PORT 3
(BOT)
USB PORT 4
(BOT)
USB PORT 5
(BOT)
USB PORT 6
(BOT)
USB PORT 7
(BOT)
USB PORT 8
SATA
PATA
USB 2.0
Azalia
Page 5,7,8,9,10,11
ICH8M
Page 14,15,16,17
LPC
WPC8763LDG
Page 26
FAN Touch
PAD Board
DMI(x2/x4)
32.768KHz
Key FLASH
ROM
PCI-Express
MINI CARD
WLAN
Page 23
PCI Bus
PCMCIA
Controller
(CB 1410)
Page 21 Page 22
(BOT)
PCMCIA
PCI ROUTING
TABLE
REQ0# / GNT0# R5C832
REQ1# / GNT1# CB1410
Card
Reader/1394
(R5C833)
1394
5 IN 1
(BOT)(BOT)
INTERUPT
IDSEL
INTA#,INTB#
AD17
AD20 INTC#
MINI CARD
Page 23
DEVICE
NEW CARD
Page 24 Page 20
100/10 LAN
RTL8101E
(BOT)(BOT)
Connector
RJ45
RJ11/RJ45/USB DAUGHTER BOARDDAUGHTER
RJ11 USB
2
AUDIO CODEC
(ALC262)
MDC 1.5
Page 25
RJ11
Connector
3
BTO BOM OPTION
CB@ : CARD BUS
FP@ : FINGER PRINTER
BT@ : BLUETOOTH
CM@ : CAMERA
GS@ : G-SENSOR
NEW@ : NEW CARD
LCD@ : LCD TYPE PANEL
LED@ : LED TYPE PANEL
1394@ : 1394
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BU1 Santa Rosa
PROJECT : BU1 Santa Rosa
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
4
5
6
Date: Sheet
7
PROJECT : BU1 Santa Rosa
Block Diagram
Block Diagram
Block Diagram
1A
1A
1A
of
of
of
133Monday, March 26, 2007
133Monday, March 26, 2007
133Monday, March 26, 2007
8
HP
INT SPK
D D
HP AMP
SPK AMP
USB
1
5
4
3
2
1
Clock Generator
R90
R90
0_6
0_6
R404
R404
0_6
0_6
R86 10K_4R86 10K_4
R82 *10K_4R82 *10K_4
R74 *10K_4R74 *10K_4
R79 10K_4R79 10K_4
R409 *10K_4R409 *10K_4
R407 10K_4R407 10K_4
R72 2.2K_4R72 2.2K_4
R87 2.2K_4R87 2.2K_4
R88 33_4R88 33_4
C411 .1U_4C411 .1U_4
C414 .1U_4C414 .1U_4
C408 10U_8C408 10U_8
C43 .1U_4C43 .1U_4
C418 .1U_4C418 .1U_4
C412 .1U_4C412 .1U_4
C415 .1U_4C415 .1U_4
+1.05V
+1.05V
+1.05V
H=1.2mm
U22
IC(64P) ICS9LPRS365BGLFT(TSSOP)
U22
VDD_CK_VDD_PCI
VDD_CK_VDD_48
VDD_CK_VDD_PCI
VDD_CK_VDD_REF
VDD_CK_VDD_PCI
VDD_CK_VDD_CPU
+1.25V_VDD
R85 56_4R85 56_4
R81 56_4R81 56_4
R78 56_4R78 56_4
R405 56_4R405 56_4
R73 22_4R73 22_4
R406 56_4R406 56_4
R71 33_4R71 33_4
CPU_BSEL0[3]
CPU_BSEL1[3]
CPU_BSEL2[3] MCH_BSEL2 [6]
4
PCLK_DEBUG_R
PCLK_PCM_R
PCLK_R5C833_R
PCLK_591_R
PCI_CLK_SIO_R
PCLK_ICH_R
CG_XIN
CG_XOUT
FSA
<check list>
(1)PCI2/TME: PU be used, the CK505 cannot over clock any of the clock for Trust Mode security purposes.
(2)PCI4/SRC5_EN: PU be used, the CK505 will be configured to use Pin37/38 to SRC5 clock.
If PD be detect at powe-on,the CK505 will setting Pin 37/38 to PCI_STOP/CUP_SOTP
(Default is setting to PCI_STOP/CUP_SOTP)
(3)PCIF5/ITP_EN: PU be used, the CK505 will be configured to use Pin46/47 to CPU ITP clock.
If PD be detect at powe-on,the CK505 will setting Pin 46/47 to SRC8
(Default is setting to SRC8)
(4)SLG8SP512 Pin 6 select Pin 17, 18 output is LCDCLK or 27 M, PD is LCDCLK, PU is 27 M ,
Pin 37, 38 will fixed be use CPU_Stop and PCI_Stop.
(5)SLG505YC64 CK505 Standar parts follow standar setting
R59 0_4R59 0_4
R66 *56_4R66 *56_4
R65 *1K_4R65 *1K_4
R80 0_4R80 0_4
R77 *0_4R77 *0_4
R408 *1K_4R408 *1K_4
R55 0_4R55 0_4
R62 *0_4R62 *0_4
R56 *1K_4R56 *1K_4
IC(64P) ICS9LPRS365BGLFT(TSSOP)
2
VDD_PCI
9
VDD_48
16
VDD_PLL3
61
VDD_REF
CK505
39
55
12
20
26
45
36
49
1
3
4
5
6
7
60
59
10
57
62
8
11
15
19
52
23
29
42
58
CK505
VDD_SRC
VDD_CPU
VDD_96_IO
VDD_PLL3_IO
VDD_SRC_IO_1
VDD_SRC_IO_3
VDD_SRC_IO_2
VDD_CPU_IO
PCI0/CR#_A
PCI1/CR#_B
PCI2/TME
PCI3
PCI4/SRC5_EN
PCIF5/ITP_EN
XTAL_IN
XTAL_OUT
USB_48/FSA
FSB/TEST/MODE
REF0/FSC/TESTSEL
VSS_PCI
VSS_48
VSS_IO
VSS_PLL3
VSS_CPU
VSS_SRC1
VSS_SRC2
VSS_SRC3
VSS_REF
CLK_BSEL0
CLK_BSEL1
A1A: (9/20) Remove 0ohm
CLK_BSEL2
SRC5#/CPU_STOP#
CKPWRGD/PWRDWN#
CPU Clock select
ICS9LPRS365BGLFT
SLG8SP512T: AL8SP512K05
48
IO_VOUT
64
SCLK
63
SDA
CPU0
CPU0#
CPU1
CPU1#
SRC8/ITP
SRC8#/ITP#
SRC10#
SRC10
SRC9
SRC9#
SRC6
SRC6#
SRC4
SRC4#
SRC2/SATA
SRC1/SE1
SRC1#/SE2
MCH_BSEL0 [6]
38
37
54
53
51
50
47
46
35
34
33
32
30
31
44
43
41
40
27
28
24
25
21
22
17
18
13
14
56
SRC5/PCI_STOP#
SRC11/CR#_H
SRC11#/CR#_G
SRC7/CR#_F
SRC7#/CR#_E
SRC3/CR#_C
SRC3#/CR#_D
SRC2#/SATA#
SRC0/DOT96
SRC0#/DOT96#
ICS9LPRS365AGLFT/ SLG8SP512T
ICS9LPRS365AGLFT/ SLG8SP512T
FSA
MCH_BSEL1 [6]
FSB
FSC
3
CGCLK_SMB
CGDAT_SMB
CLK_CPU_BCLK_R
CLK_CPU_BCLK#_R
CLK_MCH_BCLK_R
CLK_MCH_BCLK#_R
CLK_PCIE_3GPLL#_R
CLK_PCIE_3GPLL_R
CLK_MCH_OE#_R
NEW_CLKREQ#_R
CLK_PCIE_NEW_R
CLK_PCIE_NEW_R#
CLK_PCIE_MINI2_R
CLK_PCIE_MINI2#_R
CLK_PCIE_MINI_R
CLK_PCIE_MINI#_R
CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R
CLK_PCIE_ICH_R
CLK_PCIE_ICH#_R
CLK_PCIE_SATA_R
CLK_PCIE_SATA#_R
DREFSSCLK_R
DREFSSCLK#_R
DREFCLK_R
DREFCLK#_R
L26 PBY160808T-301Y-N_6L26 PBY160808T-301Y-N_6
+3V
D D
C407 30P_4C407 30P_4
PCLK_DEBUG[23,26]
H=1.5mm
<check list>
PCI4/SRC5_EN: PU be used,
the CK505 will be configured to
use Pin37/38 to SRC5 clock.If
PD be detect at powe-on,the
CK505 will setting Pin 37/38 to
PCI_STOP/CUP_SOTP(Default
is setting to
PCI_STOP/CUP_SOTP)
C C
<check list>
PCIF5/ITP_EN: PU be used,
the CK505 will be configured
to use Pin46/47 to CPU ITP
clock.If PD be detect at
powe-on,the CK505 will setting
Pin 46/47 to SRC8(Default is
setting to SRC8)
CL=20p
B B
C406 30P_4C406 30P_4
<check list>
XTAL length < 500mils
C426
C426
10U_8
10U_8
R68
R68
0_6
0_6
PCLK_PCM[21]
PCLK_R5C833[22]
PCLK_591[26]
PCLK_ICH[15]
CLKUSB_48[16]
14M_ICH[16]
21
+3V
+3V
+3V
CLK_BSEL0
CLK_BSEL1
CLK_BSEL2 FSC
CG_XIN
Y6
Y6
14.318MHZ
14.318MHZ
CG_XOUT
BSEL Frequency Select Table
FSC FSB FSA Frequency
0
0
1
0
0
0
0
A A
1
1
1
1
1
1
0
1
0
1
1
1
1
0
0
0
266Mhz0
133Mhz
166Mhz
200Mhz
400Mhz
Reserved
100Mhz
333Mhz
5
Clock Gen Differential IO power
C428
RP50 0X2RP50 0X2
1
3
RP52 0X2RP52 0X2
1
3
RP58 0X2RP58 0X2
1
3
R410 475_4R410 475_4
R412 475_4R412 475_4
RP59 0X2RP59 0X2
3
1
RP54 0X2RP54 0X2
1
3
RP56 0X2RP56 0X2
1
3
RP57 0X2RP57 0X2
3
1
RP55 0X2RP55 0X2
3
1
RP53 0X2RP53 0X2
3
1
RP13 0X2RP13 0X2
1
3
RP51 0X2RP51 0X2
3
1
Clock Gen I2C
SDATA[13,16,19,23,24]
SCLK[13,16,19,23,24]
+3V
R411 10K_4R411 10K_4
C428
C427
C427
10U_8
10U_8
*10U_8
*10U_8
0.1U close to each VDD_IO Power pin
2
4
2
4
2
4
4
2
2
4
2
4
4
2
4
2
4
2
2
4
4
2
During initial power-up be used to
sample FSB speed with FSA/B/C
+3V
Q3
Q3
RHU002N06
RHU002N06
2
3
+3V
Q4
Q4
RHU002N06
RHU002N06
2
3
NEW_CLKREQ#_R
2
C424
C424
C425
C425
C422
C422
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
PM_STPPCI# [16]
PM_STPCPU# [16]
CLK_CPU_BCLK [3]
CLK_CPU_BCLK# [3]
CLK_MCH_BCLK [5]
CLK_MCH_BCLK# [5]
CLK_PCIE_3GPLL# [6]
CLK_PCIE_3GPLL [6]
CLK_MCH_OE# [6]
NEW_CLKREQ# [24]
CLK_PCIE_NEW [24]
CLK_PCIE_NEW# [24]
CLK_PCIE_MINI2 [23]
CLK_PCIE_MINI2# [23]
CLK_PCIE_MINI [23]
CLK_PCIE_MINI# [23]
CLK_PCIE_LAN [20]
CLK_PCIE_LAN# [20]
CLK_PCIE_ICH [15]
CLK_PCIE_ICH# [15]
CLK_PCIE_SATA [14]
CLK_PCIE_SATA# [14]
DREFSSCLK [6]
DREFSSCLK# [6]
DREFCLK [6]
DREFCLK# [6]
CK_PWRGD [16]
R94
R94
10K_4
10K_4
1
R95
R95
10K_4
10K_4
1
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
CLK. GEN./ CK505
CLK. GEN./ CK505
CLK. GEN./ CK505
Date: Sheet
Date: Sheet
Date: Sheet
+1.25V_VDD +1.25V
L25
L25
PBY160808T-301Y-N_6
PBY160808T-301Y-N_6
'EMI FILTER BKP1608HS181-T(180,1.5A)'
'EMI FILTER BKP1608HS181-T(180,1.5A)'
C416
C416
C419
C419
C420
C420
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
CGDAT_SMB
CGCLK_SMB
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BU1 Santa Rosa
PROJECT : BU1 Santa Rosa
PROJECT : BU1 Santa Rosa
1
1A
1A
233Monday, March 26, 2007
233Monday, March 26, 2007
233Monday, March 26, 2007
1A
of
of
of
5
H_A#[16:3][5]
CPU(HOST)
D D
C C
H_STPCLK#[14]
B B
+1.05V
A A
H_ADSTB0#[5]
H_REQ#[4:0][5]
H_A#[35:17][5]
R26 0_4R26 0_4
H_D#[15:0][5]
H_DSTBN#0[5]
H_DSTBP#0[5]
H_DINV#0[5]
H_D#[31:16][5]
<Check list & CRB>
Layout note: Z=55 ohm
H_GTLREF<0.5"
R11
R11
H_DSTBN#1[5]
1K_4
1K_4
H_DSTBP#1[5]
H_DINV#1[5]
T10T10
T2T2
T11T11
R9
2K_6R92K_6
CPU_BSEL0[2]
CPU_BSEL1[2]
CPU_BSEL2[2]
H_ADSTB1#[5]
H_A20M#[14]
H_FERR#[14]
H_IGNNE#[14]
H_INTR[14]
H_NMI[14]
H_SMI#[14]
T3T3
T5T5
T8T8
T1T1
T146T146
T7T7
T6T6
T9T9
T4T4
T12T12
R21 *1K_4R21 *1K_4
R20 *1K_4R20 *1K_4
C14 *.1U_4C14 *.1U_4
5
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_STPCLK_R#
TP_CPU_RSVD01
TP_CPU_RSVD02
TP_CPU_RSVD03
TP_CPU_RSVD04
TP_CPU_RSVD05
TP_CPU_RSVD06
TP_CPU_RSVD07
TP_CPU_RSVD08
TP_CPU_RSVD09
TP_CPU_RSVD10
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_GTLREF
CPU_TEST1
CPU_TEST2
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST6
U24A
U24A
J4
A[3]#
L5
A[4]#
L4
A[5]#
K5
A[6]#
M3
A[7]#
N2
A[8]#
J1
A[9]#
N3
A[10]#
P5
A[11]#
P2
A[12]#
L2
A[13]#
P4
A[14]#
P1
A[15]#
R1
A[16]#
M1
ADSTB[0]#
K3
REQ[0]#
H2
REQ[1]#
K2
REQ[2]#
J3
REQ[3]#
L1
REQ[4]#
Y2
A[17]#
U5
A[18]#
R3
A[19]#
W6
A[20]#
U4
A[21]#
Y5
A[22]#
U1
A[23]#
R4
A[24]#
T5
A[25]#
T3
A[26]#
W2
A[27]#
W5
A[28]#
Y4
A[29]#
U2
A[30]#
V4
A[31]#
W3
A[32]#
AA4
A[33]#
AB2
A[34]#
AA3
A[35]#
V1
ADSTB[1]#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD[01]
N5
RSVD[02]
T2
RSVD[03]
V3
RSVD[04]
B2
RSVD[05]
C3
RSVD[06]
D2
RSVD[07]
D22
RSVD[08]
D3
RSVD[09]
F6
RSVD[10]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
U24B
U24B
E22
D[0]#
F24
D[1]#
E26
D[2]#
G22
D[3]#
F23
D[4]#
G25
D[5]#
E25
D[6]#
E23
D[7]#
K24
D[8]#
G24
D[9]#
J24
D[10]#
J23
D[11]#
H22
D[12]#
F26
D[13]#
K22
D[14]#
H23
D[15]#
J26
DSTBN[0]#
H26
DSTBP[0]#
H25
DINV[0]#
N22
D[16]#
K25
D[17]#
P26
D[18]#
R23
D[19]#
L23
D[20]#
M24
D[21]#
L22
D[22]#
M23
D[23]#
P25
D[24]#
P23
D[25]#
P22
D[26]#
T24
D[27]#
R24
D[28]#
L25
D[29]#
T25
D[30]#
N25
D[31]#
L26
DSTBN[1]#
M26
DSTBP[1]#
N24
DINV[1]#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
B22
BSEL[0]
B23
BSEL[1]
C21
BSEL[2]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
ADDR GROUP 0 ADDR GROUP 1
ADDR GROUP 0 ADDR GROUP 1
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
XDP/ITP SIGNALS
XDP/ITP SIGNALS
DBR#
THERMAL
THERMAL
PROCHOT#
THERMDA
THERMDC
ICH
ICH
THERMTRIP#
H CLK
H CLK
BCLK[0]
BCLK[1]
RESERVED
RESERVED
DATA GRP 0
DATA GRP 0
DATA GRP 2DATA GRP 3
DATA GRP 2DATA GRP 3
DSTBN[2]#
DSTBP[2]#
DINV[2]#
DATA GRP 1
DATA GRP 1
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
MISC
MISC
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
PWRGOOD
DPWR#
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
SLP#
PSI#
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
D21
A24
B25
C7
A22
A21
4
H_IERR#
XDP_TCK
XDP_TDI
XDP_TMS
XDP_TRST#
XDP_DBRESET#
H_PROCHOT_R#
H_THERMDA
H_THERMDC
THERMTRIP#_PWR
H_D#32
Y22
H_D#33
AB24
H_D#34
V24
H_D#35
V26
H_D#36
V23
H_D#37
T22
H_D#38
U25
H_D#39
U23
H_D#40
Y25
H_D#41
W22
H_D#42
Y23
H_D#43
W24
H_D#44
W25
H_D#45
AA23
H_D#46
AA24
H_D#47
AB25
Y26
AA26
U22
H_D#48
AE24
H_D#49
AD24
H_D#50
AA21
H_D#51
AB22
H_D#52
AB21
H_D#53
AC26
H_D#54
AD20
H_D#55
AE22
H_D#56
AF23
H_D#57
AC25
H_D#58
AE21
H_D#59
AD21
H_D#60
AC22
H_D#61
AD23
H_D#62
AF22
H_D#63
AC23
AE25
AF24
AC20
COMP0
R26
COMP1
U26
COMP2
AA1
COMP3
Y1
E5
B5
D24
D6
D7
AE6
4
H_ADS# [5]
H_BNR# [5]
H_BPRI# [5]
H_DEFER# [5]
H_DRDY# [5]
H_DBSY# [5]
R16 56.2_4R16 56.2_4
R19 0_4R19 0_4
R17 56.2_4R17 56.2_4
R18 *2.2K_4R18 *2.2K_4
<check list>
Default PU 56ohm if no use.
Serial R NC, If connect to power side PU 68ohm. Serial R 2.2K
CLK_CPU_BCLK [2]
CLK_CPU_BCLK# [2]
H_D#[47:32] [5]
H_DSTBN#2 [5]
H_DSTBP#2 [5]
H_DINV#2 [5]
H_D#[63:48] [5]
H_DSTBN#3 [5]
H_DSTBP#3 [5]
R14 27.4_6R14 27.4_6
R13 54.9_4R13 54.9_4
R10 27.4_6R10 27.4_6
R8 54.9_4R8 54.9_4
H_DINV#3 [5]
H_DPSLP# [14]
H_DPWR# [5]
H_CPUSLP# [5]
PSI# [29]
+1.05V
+1.05V
H_BREQ#0 [5]
H_INIT# [14]
H_LOCK# [5]
H_CPURST# [5]
H_RS#0 [5]
H_RS#1 [5]
H_RS#2 [5]
H_TRDY# [5]
H_HIT# [5]
H_HITM# [5]
SYS_RST# [16]
H_PROCHOT# [29]
<Check list & CRB>
Layout note: L<0.5"
COMP0/2 Z=27.4ohm
COMP1/3 Z=54.9
<CRB & Design guide>
Layout Note:Connect from
SB and daisy chain to CPU
CORE VR.Not use T
connect.(SB/VR/CPU/NB)
ICH_DPRSTP# [6,14,29]
H_PWRGD [14]
3
CPU Thermal monitor
MBCLK[18,26,27]
MBDATA[18,26,27]
THERM_ALERT#[16]
3
3
+3V
+3V
CPU FAN
THER_SHD#
VFAN[26]
2
+3V
Q33
Q33
2
RHU002N06
RHU002N06
1
+3V
Q34
Q34
2
RHU002N06
RHU002N06
1
R434
R434
R435 *0_4R435 *0_4
R438 10K_4R438 10K_4
+3V
R458
R458
330_4
330_4
Q37
Q37
2
MMBT3904
MMBT3904
1 3
+5V
C290 .1U_4C290 .1U_4
*10K_4
*10K_4
THERM_ALERT#_R
THER_SHD#
SYS_SHDN# [28]
H=1.75mm
U26
U26
VIN2VO
1
/FON
4
VSET
G995
G995
GND
GND
GND
GND
R431
R431
10K_4
10K_4
3
5
6
7
8
R432
R432
10K_4
10K_4
8
7
6
4
FANSIG[26]
+3V
R437
R437
200_6
200_6
H=1.75mm
U23
U23
VCC
SCLK
DXP
SDA
DXN
ALERT#
GND
OVERT#
MAX6657
MAX6657
ADDRESS: 98H
TH_FAN_POWERTH_FAN_POWER
C489
C489
10U_8
10U_8
1
LM86VCC
1
2
3
5
<check list>
Layout Note:Routing 10:10 mils and away
from noise source with ground gard
C491
C491
.01U_4
.01U_4
C9
*.01U_4C9*.01U_4
C455
C455
.1U_4
.1U_4
C454
C454
2200P_4
2200P_4
+3V
R1
10K_4R110K_4
CN34
CN34
1
2
345
PTI_CWY030-B0G1Z
PTI_CWY030-B0G1Z
H_THERMDA
H_THERMDC
FANPWR = 1.6*VSET
PU/PD (ITP700)
XDP_TMS
XDP_TDI
XDP_TCK
XDP_TRST#
3
R7 39_4R7 39_4
R6 150_4R6 150_4
R5 27_4R5 27_4
R4 680_4R4 680_4
+1.05V
Thermal Trip
DELAY_VR_PWRGOOD[6,16,29]
THERMTRIP#_PWR
<CRB & Design guide>
Layout Note: Thermal trip should connect to ICH8 & GMCH without T-ing
(ZS1 default NC)
2
+1.05V
3
Q1
R23
R23
2
FDV301NQ1FDV301N
+1.05V
R25
R25
56.2_4
56.2_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
1
Q2
Q2
2
MMBT3904
MMBT3904
1 3
R24 *0_4R24 *0_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BU1 Santa Rosa
PROJECT : BU1 Santa Rosa
PROJECT : BU1 Santa Rosa
CPU(1 of 2)/FAN/Thermal
CPU(1 of 2)/FAN/Thermal
CPU(1 of 2)/FAN/Thermal
*10K_4
*10K_4
SYS_SHDN# [28]
PM_THRMTRIP# [6,14]
1
D3
*BAS316D3*BAS316
C35 *1U_6C35 *1U_6
333Monday, March 26, 2007
333Monday, March 26, 2007
333Monday, March 26, 2007
3A
3A
3A
of
of
of
5
CPU(Power)
VCC_CORE
C465
C465
C25
D D
C C
<Check list>
Option1:330U*6(ESR=1.5m ohm aggregate , ESL=0.8nH/6) and 22U*20(ESR=3mohm typ/20 , ESL=0.6nH/20)
Option2:330U*6(ESR=1.5m ohm aggregate , ESL=1.8nH/6) and 22U*32(ESR=3mohm typ/32 , ESL=0.6nH/32)
B B
10U_8
10U_8
C475
C475
10U_8
10U_8
C31
C31
10U_8
10U_8
C468
C468
10U_8
10U_8
+
+
C32
C32
330U_7343
330U_7343
C25
10U_8
10U_8
C469
C469
10U_8
10U_8
C28
C28
10U_8
10U_8
C27
C27
10U_8
10U_8
C466
C466
10U_8
10U_8
C463
C463
10U_8
10U_8
C470
C470
10U_8
10U_8
C458
C458
10U_8
10U_8
+
+
C13
C13
*330U_7343
*330U_7343
C461
C461
10U_8
10U_8
C474
C474
10U_8
10U_8
C462
C462
10U_8
10U_8
C24
C24
10U_8
10U_8
C472
C472
C473
C473
10U_8
10U_8
10U_8
10U_8
C19
C19
C464
C464
10U_8
10U_8
10U_8
10U_8
C30
C30
C467
C467
10U_8
10U_8
10U_8
10U_8
C457
C457
C26
C26
10U_8
10U_8
CH6102K9A01
CH6102K9A01
10U_8
10U_8
'CAP CHIP 10U 10V(+-10%,X5R,0805)'
'CAP CHIP 10U 10V(+-10%,X5R,0805)'
+
+
C29
C29
330U_7343
330U_7343
C471
C471
C477
C477
10U_8
10U_8
10U_8
10U_8
C20
C20
C23
C23
10U_8
10U_8
10U_8
10U_8
DESIGN GUIDE
CHANGE FROM 22UF *20 TO 10UF *32
C21
C21
10U_8
10U_8
C459
C459
10U_8
10U_8
4
C476
C476
10U_8
10U_8
C460
C460
10U_8
10U_8
U24C
U24C
A7
VCC[001]
A9
VCC[002]
A10
VCC[003]
A12
VCC[004]
A13
VCC[005]
A15
VCC[006]
A17
VCC[007]
A18
VCC[008]
A20
VCC[009]
B7
VCC[010]
B9
VCC[011]
B10
VCC[012]
B12
VCC[013]
B14
VCC[014]
B15
VCC[015]
B17
VCC[016]
B18
VCC[017]
B20
VCC[018]
C9
VCC[019]
C10
VCC[020]
C12
VCC[021]
C13
VCC[022]
C15
VCC[023]
C17
VCC[024]
C18
VCC[025]
D9
VCC[026]
D10
VCC[027]
D12
VCC[028]
D14
VCC[029]
D15
VCC[030]
D17
VCC[031]
D18
VCC[032]
E7
VCC[033]
E9
VCC[034]
E10
VCC[035]
E12
VCC[036]
E13
VCC[037]
E15
VCC[038]
E17
VCC[039]
E18
VCC[040]
E20
VCC[041]
F7
VCC[042]
F9
VCC[043]
F10
VCC[044]
F12
VCC[045]
F14
VCC[046]
F15
VCC[047]
F17
VCC[048]
F18
VCC[049]
F20
VCC[050]
AA7
VCC[051]
AA9
VCC[052]
AA10
VCC[053]
AA12
VCC[054]
AA13
VCC[055]
AA15
VCC[056]
AA17
VCC[057]
AA18
VCC[058]
AA20
VCC[059]
AB9
VCC[060]
AC10
VCC[061]
AB10
VCC[062]
AB12
VCC[063]
AB14
VCC[064]
AB15
VCC[065]
AB17
VCC[066]
AB18
VCC[067]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
.
.
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
3
CPU_G21
CPU_V6
+VCCA_PROC
<CRB>
R for test only
R15 0_4R15 0_4
R12 0_4R12 0_4
H_VID0 [29]
H_VID1 [29]
H_VID2 [29]
H_VID3 [29]
H_VID4 [29]
H_VID5 [29]
H_VID6 [29]
2
<REV.NO. 0.5/REF.NO.19343>
Ivcc Max 52A
Ivccp Max 6A(VCCP supply before Vcc stable)
Max 2A(VCCP supply after Vcc stable)
Ivcca Max 130mA
+1.05V
C15
C16
C16
.1U_6
.1U_6
+1.05V
+
+
VCC_CORE
R2
100/F_6R2100/F_6
R3
100/F_6R3100/F_6
C36
C36
330U_7343
330U_7343
C17
C17
C18
C18
.1U_6
.1U_6
.1U_6
.1U_6
<Check list>
ESR=12m ohm
<CRB>
.01U near to B26 ball
R22 0_6R22 0_6
C33
C33
C34
C34
.01U_4
.01U_4
10U_8
10U_8
<Demo board>
Routing 27.4ohm with 50mils spacing
PU/PD near to CPU 1"
C15
C456
C456
.1U_6
.1U_6
.1U_6
.1U_6
+1.5V
VCCSENSE [29]
VSSSENSE [29]
C22
C22
.1U_6
.1U_6
1
U24D
U24D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080]
VSS[081]P3VSS[162]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[163]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
.
.
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BU1 Santa Rosa
PROJECT : BU1 Santa Rosa
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
PROJECT : BU1 Santa Rosa
CPU(2 of 2)
CPU(2 of 2)
CPU(2 of 2)
1
1A
1A
433Monday, March 26, 2007
433Monday, March 26, 2007
433Monday, March 26, 2007
1A
of
of
of
5
4
3
2
1
NB(HOST)
U21A
M10
N12
P13
W10
W6
W9
W3
AD12
AE3
AD9
AC9
AC7
AC14
AD11
AC11
AB2
AD7
AB1
AC6
AE2
AC5
AG3
AJ9
AH8
AJ14
AE9
AE11
AH12
AJ5
AH5
AJ6
AE7
AJ7
AJ2
AE5
AJ3
AH2
AH13
W1
W2
E2
G2
G7
M6
H7
H3
G4
F3
N8
H2
N9
H5
K9
M2
Y8
V4
M3
J1
N5
N3
N2
Y7
Y9
P4
N1
Y3
B3
C2
B6
E5
B9
A9
U21A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
CRESTLINE_1p0
CRESTLINE_1p0
HOST
HOST
3
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19
G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7
K5
L2
AD13
AE13
M7
K3
AD2
AH11
L7
K2
AC2
AJ10
M14
E13
A11
H13
B12
E12
D7
D8
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_D#[63:0][3]
+1.05V
R416
+1.05V
+1.05V
5
R416
221/F_4
221/F_4
R417
R417
100/F_4
100/F_4
R415
R415
24.9/F_4
24.9/F_4
R76
R76
54.9/F_4
54.9/F_4
R75
R75
54.9/F_4
54.9/F_4
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
C436
C436
<check list>
0.1U close to B3
.1U_4
.1U_4
<check list>
10:20 mils(Width:Spacing)
<check list>
Impedance 55ohm
<check list>
Impedance 55ohm
+1.05V
R418
R418
1K_4
1K_4
R422
R422
2K_4
2K_4
C432
C432
.1U_4
.1U_4
H_CPURST#[3]
<check list>
0.1U close to B9
4
D D
C C
B B
A A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
H_AVREF
H_A#[35:3] [3]
H_A#[35:32] are not supported in
Calero Interposer
Crestline support 36 bit address
H_ADS# [3]
H_ADSTB0# [3]
H_ADSTB1# [3]
H_BNR# [3]
H_BPRI# [3]
H_BREQ#0 [3]
H_DEFER# [3]
H_DBSY# [3]
CLK_MCH_BCLK [2]
CLK_MCH_BCLK# [2]
H_DPWR# [3]
H_DRDY# [3]
H_HIT# [3]
H_HITM# [3]
H_LOCK# [3]
H_TRDY# [3]
H_DINV#[3:0] [3]
H_DSTBN#[3:0] [3]
H_DSTBP#[3:0] [3]
H_REQ#[4:0] [3]
H_RS#[2:0] [3]H_CPUSLP#[3]
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
GMCH HOST(1 of 7)
GMCH HOST(1 of 7)
GMCH HOST(1 of 7)
Date: Sheet
Date: Sheet
2
Date: Sheet
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BU1 Santa Rosa
PROJECT : BU1 Santa Rosa
PROJECT : BU1 Santa Rosa
533Monday, March 26, 2007
533Monday, March 26, 2007
533Monday, March 26, 2007
of
of
1
of
1A
1A
1A
5
3
MCH_RSVD1
T30T30
MCH_RSVD2
T32T32
MCH_RSVD3
T31T31
MCH_RSVD4
T28T28
MCH_RSVD5
T40T40
MCH_RSVD6
T41T41
MCH_RSVD7
T36T36
MCH_RSVD8
T37T37
MCH_RSVD9
T22T22
MCH_RSVD10
T39T39
MCH_RSVD11
T38T38
MCH_RSVD12
T35T35
MCH_RSVD13
M_RCOMP#
5
T34T34
T14T14
C41 .1U_4C41 .1U_4
T18T18
T125T125
T112T112
T113T113
T47T47
T51T51
T116T116
T53T53
T49T49
T50T50
T48T48
T46T46
T45T45
T44T44
T52T52
T141T141
T15T15
T132T132
T135T135
T142T142
T145T145
T129T129
T138T138
T131T131
T130T130
T134T134
T29T29
T19T19
T20T20
T33T33
T27T27
T13T13
T23T23
T26T26
T21T21
R50 0_4R50 0_4
R45 0_4R45 0_4
R38 0_4R38 0_4
R97 100_4R97 100_4
R64 *0_4R64 *0_4
R42 0_4R42 0_4
T122T122
T123T123
T120T120
T118T118
T114T114
T117T117
T115T115
T121T121
T124T124
T126T126
T139T139
T127T127
T128T128
T137T137
T136T136
T119T119
R102
R102
20_4
20_4
MCH_RSVD14
MCH_RSVD20
MCH_RSVD21
MCH_RSVD22
MCH_RSVD23
MCH_RSVD24
MCH_RSVD25
MCH_RSVD26
MCH_RSVD27
MCH_RSVD28
MCH_RSVD29
MCH_RSVD30
MCH_RSVD31
MCH_RSVD34
MCH_RSVD35
MCH_RSVD36
MCH_RSVD37
MCH_RSVD38
MCH_RSVD39
MCH_RSVD40
MCH_RSVD41
MCH_RSVD42
MCH_RSVD43
MCH_RSVD44
MCH_RSVD45
MCH_CFG_3
MCH_CFG_4
MCH_CFG_6
MCH_CFG_7
MCH_CFG_8
MCH_CFG_10
MCH_CFG_11
MCH_CFG_14
MCH_CFG_15
MCH_CFG_17
MCH_CFG_18
PM_BMBUSY#_R
ICH_DPRSTP#_R
PM_EXTTS#0
PM_EXTTS#1_R
RST_IN#_MCH
PM_THRMTRIP#_GMCH
PM_DPRSLPVR_GMCH
TP_MCH_NC1
TP_MCH_NC2
TP_MCH_NC3
TP_MCH_NC4
TP_MCH_NC5
TP_MCH_NC6
TP_MCH_NC7
TP_MCH_NC8
TP_MCH_NC9
TP_MCH_NC10
TP_MCH_NC11
TP_MCH_NC12
TP_MCH_NC13
TP_MCH_NC14
TP_MCH_NC15
TP_MCH_NC16
+1.8VSUS
M_RCOMP
D D
M_A_A14[12,13]
M_B_A14[12,13]
C C
MCH_BSEL0[2]
MCH_BSEL1[2]
MCH_BSEL2[2]
MCH_CFG_5[11]
MCH_CFG_9[11]
MCH_CFG_12[11]
MCH_CFG_13[11]
MCH_CFG_16[11]
MCH_CFG_19[11]
MCH_CFG_20[11]
B B
,16,29]
A A
PM_BMBUSY#[16]
ICH_DPRSTP#[3,14,29]
PM_EXTTS#0[13]
PM_EXTTS#1[13]
DELAY_VR_PWRGOOD
PLTRST#_NB[15]
PM_THRMTRIP#[3,14]
PM_DPRSLPVR[16,29]
R105
R105
20_4
20_4
AR12
AR13
AM12
AN13
AR37
AM36
AL36
AM37
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23
BG23
BC23
BD24
BJ29
BE24
BH39
AW20
BK20
AW49
AV20
BJ51
BK51
BK50
BL50
BL49
P36
P37
R35
N35
J12
D20
H10
B51
C48
D47
B44
C44
A35
B37
B36
B34
C34
P27
N27
N24
C21
C23
F23
N23
G23
J20
C20
R24
L23
J23
E23
E20
K23
M20
M24
L32
N33
L35
G41
L39
L36
J36
N20
G36
BL3
BL2
BK1
BJ1
E1
A5
C51
B50
A50
A49
BK2
U21B
U21B
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
CRESTLINE_1p0
CRESTLINE_1p0
+3V
4
SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4
SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4
SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF_0
DDR MUXINGCLK
DDR MUXINGCLK
SM_VREF_1
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
PEG_CLK
PEG_CLK#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
CFGRSVD
CFGRSVD
PM
PM
NC
NC
R44 10K_4R44 10K_4
R39 10K_4R39 10K_4
R32 10K_4R32 10K_4
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI
DMI
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VR_EN
GRAPHICS VID
GRAPHICS VID
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
ME
ME
SDVO_CTRL_CLK
SDVO_CTRL_DATA
CLK_REQ#
ICH_SYNC#
MISC
MISC
TEST_1
TEST_2
CLK_MCH_OE#
PM_EXTTS#0
PM_EXTTS#1
4
AV29
BB23
BA25
AV23
AW30
BA23
AW25
AW23
BE29
AY32
BD39
BG37
BG20
BK16
BG16
BE13
BH18
BJ15
BJ14
BE16
BL15
BK14
BK31
BL31
AR49
AW4
B42
C42
H48
H47
K44
K45
DMI_TXN0
AN47
DMI_TXN1
AJ38
DMI_TXN2
AN42
DMI_TXN3
AN46
DMI_TXP0
AM47
DMI_TXP1
AJ39
DMI_TXP2
AN41
DMI_TXP3
AN45
DMI_RXN0
AJ46
DMI_RXN1
AJ41
DMI_RXN2
AM40
DMI_RXN3
AM44
DMI_RXP0
AJ47
DMI_RXP1
AJ42
DMI_RXP2
AM39
DMI_RXP3
AM43
E35
A39
C38
B39
E36
AM49
AK50
AT43
AN49
+1.25V_CL_VREF
AM50
H35
K36
CLK_MCH_OE#
G39
G40
GMCH_TEST1
A37
GMCH_TEST2
R32
M_RCOMP
M_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SMDDR_VREF_MCH
R107 *10K_6R107 *10K_6
R98 *10K_6R98 *10K_6
DREFCLK
DREFCLK#
DREFSSCLK
DREFSSCLK#
T16T16
T144T144
T133T133
T140T140
T143T143
M_CLK_DDR0 [13]
M_CLK_DDR1 [13]
M_CLK_DDR3 [13]
M_CLK_DDR4 [13]
M_CLK_DDR#0 [13]
M_CLK_DDR#1 [13]
M_CLK_DDR#3 [13]
M_CLK_DDR#4 [13]
M_CKE0 [12,13]
M_CKE1 [12,13]
M_CKE3 [12,13]
M_CKE4 [12,13]
M_CS#0 [12,13]
M_CS#1 [12,13]
M_CS#2 [12,13]
M_CS#3 [12,13]
M_ODT0 [12,13]
M_ODT1 [12,13]
M_ODT2 [12,13]
M_ODT3 [12,13]
DREFCLK [2]
DREFCLK# [2]
DREFSSCLK [2]
DREFSSCLK# [2]
CLK_PCIE_3GPLL [2]
CLK_PCIE_3GPLL# [2]
DMI_TXN[3:0] [15]
DMI_TXP[3:0] [15]
DMI_RXN[3:0] [15]
DMI_RXP[3:0] [15]
CL_CLK0 [16]
CL_DATA0 [16]
MPWROK [16]
CL_RST#0 [16]
T17T17
T24T24
CLK_MCH_OE# [2]
MCH_ICH_SYNC# [16]
R428 0_4R428 0_4
R70 20K_4R70 20K_4
SMDDR_VREF
R108 0_6R108 0_6
3
+1.8VSUS
R419 1.3K_6R419 1.3K_6
+1.25V_AXD
R84
R84
1K_4
1K_4
R83
R83
C67
C67
392_6
392_6
.1U_4
.1U_4
3
INT_LVDS_PWM[18]
INT_LVDS_BLON[18,26]
INT_LVDS_EDIDCLK[18]
INT_LVDS_EDIDDATA[18]
INT_LVDS_DIGON[18]
INT_TXLCLKOUT-[18]
INT_TXLCLKOUT+[18]
INT_TXLOUT0-[18]
INT_TXLOUT1-[18]
INT_TXLOUT2-[18]
INT_TXLOUT0+[18]
INT_TXLOUT1+[18]
INT_TXLOUT2+[18]
CRT_B[18]
CRT_G[18]
CRT_R[18]
DDCCLK[18]
DDCDAT[18]
HSYNC[18]
VSYNC[18]
R46 150_4R46 150_4
R52 150_4R52 150_4
R49 150_4R49 150_4
+1.8VSUS
+3V
R57 2.4K_4R57 2.4K_4
R34 *0_4R34 *0_4
R37 *0_4R37 *0_4
DDCCLK
DDCDAT
R41 30_4R41 30_4
R40 30_4R40 30_4
R106 1K_4R106 1K_4
R414 10K_4R414 10K_4
R429 10K_4R429 10K_4
LVDS_IBG
T25T25
CRT_B
CRT_G
CRT_R
HSYNC_A
CRTIREF
VSYNC_A
CRT_B
CRT_G
CRT_R
R104
R104
3.01K_4
3.01K_4
R103
R103
1K_4
1K_4
2
U21C
U21C
J40
L_BKLT_CTRL
H39
L_BKLT_EN
E39
L_CTRL_CLK
E40
L_CTRL_DATA
C37
L_DDC_CLK
D35
L_DDC_DATA
K40
L_VDD_EN
L41
LVDS_IBG
L43
LVDS_VBG
N41
LVDS_VREFH
N40
LVDS_VREFL
D46
LVDSA_CLK#
C45
LVDSA_CLK
D44
LVDSB_CLK#
E42
LVDSB_CLK
G51
LVDSA_DATA#_0
E51
LVDSA_DATA#_1
F49
LVDSA_DATA#_2
G50
LVDSA_DATA_0
E50
LVDSA_DATA_1
F48
LVDSA_DATA_2
G44
LVDSB_DATA#_0
B47
LVDSB_DATA#_1
B45
LVDSB_DATA#_2
E44
LVDSB_DATA_0
A47
LVDSB_DATA_1
A45
LVDSB_DATA_2
E27
TVA_DAC
G27
TVB_DAC
K27
TVC_DAC
F27
TVA_RTN
J27
TVB_RTN
L27
TVC_RTN
M35
TV_DCONSEL_0
P33
TV_DCONSEL_1
H32
CRT_BLUE
G32
CRT_BLUE#
K29
CRT_GREEN
J29
CRT_GREEN#
F29
CRT_RED
E29
CRT_RED#
K33
CRT_DDC_CLK
G35
CRT_DDC_DATA
F33
CRT_HSYNC
C32
CRT_TVO_IREF
E33
CRT_VSYNC
CRESTLINE_1p0
CRESTLINE_1p0
SM_RCOMP_VOH
C93
C93
.01U_4
.01U_4
SM_RCOMP_VOL
C97
C97
.01U_4
.01U_4
2
C95
C95
2.2U_6
2.2U_6
C98
C98
2.2U_6
2.2U_6
1
+VCC_PEG
EXP_A_COMPX
N43
PEG_COMPI
PEG_COMPO
LVDS
LVDS
TV VGA
TV VGA
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
GMCH DMI/VIDEO(2 of 7)
GMCH DMI/VIDEO(2 of 7)
GMCH DMI/VIDEO(2 of 7)
M43
J51
PEG_RX#_0
L51
PEG_RX#_1
N47
PEG_RX#_2
T45
PEG_RX#_3
T50
PEG_RX#_4
U40
PEG_RX#_5
Y44
PEG_RX#_6
Y40
PEG_RX#_7
AB51
PEG_RX#_8
W49
PEG_RX#_9
AD44
AD40
AG46
AH49
AG45
AG41
J50
PEG_RX_0
L50
PEG_RX_1
M47
PEG_RX_2
U44
PEG_RX_3
T49
PEG_RX_4
T41
PEG_RX_5
W45
PEG_RX_6
W41
PEG_RX_7
AB50
PEG_RX_8
Y48
PEG_RX_9
AC45
PEG_RX_10
AC41
PEG_RX_11
AH47
PEG_RX_12
AG49
PEG_RX_13
AH45
PEG_RX_14
AG42
PEG_RX_15
N45
PEG_TX#_0
U39
PEG_TX#_1
U47
PEG_TX#_2
N51
PEG_TX#_3
R50
PEG_TX#_4
T42
PEG_TX#_5
Y43
PEG_TX#_6
W46
PEG_TX#_7
W38
PEG_TX#_8
AD39
PEG_TX#_9
AC46
PEG_TX#_10
AC49
PEG_TX#_11
AC42
PEG_TX#_12
AH39
PEG_TX#_13
AE49
PEG_TX#_14
AH44
PEG_TX#_15
M45
PEG_TX_0
T38
PEG_TX_1
T46
PEG_TX_2
N50
PEG_TX_3
R51
PEG_TX_4
U43
PEG_TX_5
W42
PEG_TX_6
Y47
PEG_TX_7
Y39
PEG_TX_8
AC38
PEG_TX_9
AD47
PEG_TX_10
AC50
PEG_TX_11
AD43
PEG_TX_12
AG39
PEG_TX_13
AE50
PEG_TX_14
AH43
PEG_TX_15
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BU1 Santa Rosa
PROJECT : BU1 Santa Rosa
PROJECT : BU1 Santa Rosa
1
R67 24.9_4R67 24.9_4
633Monday, March 26, 2007
633Monday, March 26, 2007
633Monday, March 26, 2007
of
of
of
1A
1A
1A
5
NB(Memory controller)
4
3
2
1
M_A_DQ[63:0][13]
D D
C C
B B
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BF48
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BD8
AY9
BG10
AW9
BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8
AN10
AT9
AN9
AM9
AN11
U21D
U21D
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
CRESTLINE_1p0
CRESTLINE_1p0
BB19
SA_BS_0
BK19
SA_BS_1
BF29
SA_BS_2
BL17
SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_RAS#
SA_RCVEN#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_WE#
AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6
AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2
BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16
BE18
AY20
BA19
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
TP_SA_RCVEN#
M_A_BS#0 [12,13]
M_A_BS#1 [12,13]
M_A_BS#2 [12,13]
M_A_CAS# [12,13]
M_A_DM[7:0] [13]
M_A_DQS[7:0] [13]
M_A_DQS#[7:0] [13]
M_A_A[13:0] [12,13]
M_A_RAS# [12,13]
T43T43
M_A_WE# [12,13]
M_B_DQ[63:0][13]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BK5
BL5
BK9
BK10
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2
BL9
BJ8
BJ6
BJ2
U21E
U21E
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
CRESTLINE_1p0
CRESTLINE_1p0
AY17
SB_BS_0
BG18
SB_BS_1
BG36
SB_BS_2
BE17
SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_RAS#
SB_RCVEN#
SB_WE#
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2
AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3
BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
AV16
AY18
BC17
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
TP_SB_RCVEN#
M_B_BS#0 [12,13]
M_B_BS#1 [12,13]
M_B_BS#2 [12,13]
M_B_CAS# [12,13]
M_B_DM[7:0] [13]
M_B_DQS[7:0] [13]
M_B_DQS#[7:0] [13]
M_B_A[13:0] [12,13]
M_B_RAS# [12,13]
T42T42
M_B_WE# [12,13]
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BU1 Santa Rosa
PROJECT : BU1 Santa Rosa
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
PROJECT : BU1 Santa Rosa
MCH DDR(3 of 7)
MCH DDR(3 of 7)
MCH DDR(3 of 7)
1
1A
1A
1A
733Monday, March 26, 2007
733Monday, March 26, 2007
733Monday, March 26, 2007
of
of
of
5
NB(Power-1)
+1.05V
U21G
U21G
AT35
VCC_1
AT34
VCC_2
AH28
VCC_3
AC32
VCC_5
+1.8VSUS
+1.05V
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32
R30
AU32
AU33
AU35
AV33
AW33
AW35
AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33
AU30
R20
T14
W13
W14
Y12
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
CRESTLINE_1p0
CRESTLINE_1p0
D D
R69 0_4R69 0_4
+1.8VSUS
C89
C89
.1U_4
.1U_4
C C
B B
A A
5
+1.05V_VCC_GMCH_VCC13
C108
C108
C102
C102
22U_8
22U_8
22U_8
22U_8
4
VCC CORE
VCC CORE
POWER
POWER
VCC SMVCC GFX
VCC SMVCC GFX
4
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC GFX NCTF
VCC GFX NCTF
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC SM LF
VCC SM LF
T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31
AW45
BC39
BE39
BD17
BD4
AW8
AT6
+1.05V
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
3
R61 10_4R61 10_4
+1.05V
C82
C82
.1U_4
.1U_4
3
VCCGFPLLOW
ADD 10ohm
THEY ONLY USE IN UMA (GM OR GML)
+1.05V
330U_3528
330U_3528
+
+
C413
C413
330U_3528
330U_3528
C90
C90
C84
C84
.22U_4
.22U_4
.1U_4
.1U_4
D4 PDZ5.6BD4 PDZ5.6B
+
+
C423
C423
+
+
C417
C417
330U_3528
330U_3528
+1.05V
C88
C88
.22U_4
.22U_4
C74
C74
22U_8
22U_8
C81
C81
.47U_6
.47U_6
C66
C66
22U_8
22U_8
C59
C59
.22U_4
.22U_4
C61
C61
1U_6
1U_6
C92
C92
.47U_6
.47U_6
21
C70
C70
.22U_4
.22U_4
C73
C73
.22U_4
.22U_4
C57
C57
10U_8
10U_8
C86
C86
1U_6
1U_6
C71
C71
.22U_4
.22U_4
C63
C63
.1U_4
.1U_4
C58
C58
22U_8
22U_8
C85
C85
1U_6
1U_6
2
C62
C62
.1U_4
.1U_4
2
+1.05V+3V_VCCSYNC
U21F
U21F
AB33
VCC_NCTF_1
AB36
VCC_NCTF_2
AB37
VCC_NCTF_3
AC33
VCC_NCTF_4
AC35
VCC_NCTF_5
AC36
VCC_NCTF_6
AD35
VCC_NCTF_7
AD36
VCC_NCTF_8
AF33
VCC_NCTF_9
AF36
VCC_NCTF_10
AH33
VCC_NCTF_11
AH35
VCC_NCTF_12
AH36
VCC_NCTF_13
AH37
VCC_NCTF_14
AJ33
VCC_NCTF_15
AJ35
VCC_NCTF_16
AK33
VCC_NCTF_17
AK35
VCC_NCTF_18
AK36
VCC_NCTF_19
AK37
VCC_NCTF_20
AD33
VCC_NCTF_21
AJ36
VCC_NCTF_22
AM35
VCC_NCTF_23
AL33
C76
C76
.1U_4
.1U_4
C69
C69
.1U_4
.1U_4
C60
C60
.1U_4
.1U_4
C64
C64
.1U_4
.1U_4
VCC_NCTF_24
AL35
VCC_NCTF_25
AA33
VCC_NCTF_26
AA35
VCC_NCTF_27
AA36
VCC_NCTF_28
AP35
VCC_NCTF_29
AP36
VCC_NCTF_30
AR35
VCC_NCTF_31
AR36
VCC_NCTF_32
Y32
VCC_NCTF_33
Y33
VCC_NCTF_34
Y35
VCC_NCTF_35
Y36
VCC_NCTF_36
Y37
VCC_NCTF_37
T30
VCC_NCTF_38
T34
VCC_NCTF_39
T35
VCC_NCTF_40
U29
VCC_NCTF_41
U31
VCC_NCTF_42
U32
VCC_NCTF_43
U33
VCC_NCTF_44
U35
VCC_NCTF_45
U36
VCC_NCTF_46
V32
VCC_NCTF_47
V33
VCC_NCTF_48
V36
VCC_NCTF_49
V37
VCC_NCTF_50
AL24
VCC_AXM_NCTF_1
AL26
VCC_AXM_NCTF_2
AL28
VCC_AXM_NCTF_3
AM26
VCC_AXM_NCTF_4
AM28
VCC_AXM_NCTF_5
AM29
VCC_AXM_NCTF_6
AM31
VCC_AXM_NCTF_7
AM32
VCC_AXM_NCTF_8
AM33
VCC_AXM_NCTF_9
AP29
VCC_AXM_NCTF_10
AP31
VCC_AXM_NCTF_11
AP32
VCC_AXM_NCTF_12
AP33
VCC_AXM_NCTF_13
AL29
VCC_AXM_NCTF_14
AL31
VCC_AXM_NCTF_15
AL32
VCC_AXM_NCTF_16
AR31
VCC_AXM_NCTF_17
AR32
VCC_AXM_NCTF_18
AR33
VCC_AXM_NCTF_19
CRESTLINE_1p0
CRESTLINE_1p0
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
GMCH Power-1(4 of 7)
GMCH Power-1(4 of 7)
GMCH Power-1(4 of 7)
Date: Sheet
Date: Sheet
Date: Sheet
POWER
POWER
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BU1 Santa Rosa
PROJECT : BU1 Santa Rosa
PROJECT : BU1 Santa Rosa
1
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS NCTF
VSS NCTF
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VCC NCTF
VCC NCTF
VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6
VSS SCBVCC AXM
VSS SCBVCC AXM
VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7
VCC AXM NCTF
VCC AXM NCTF
1
T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28
A3
B2
C1
BL1
BL51
A51
+1.05V
R89
R89
0_6
0_6
AT33
AT31
AK29
AK24
AK23
AJ26
AJ23
1A
1A
833Thursday, February 01, 2007
833Thursday, February 01, 2007
833Thursday, February 01, 2007
1A
of
of
of
5
NB(Power-2)
'IND CHIP 10UH(20%,100MA,LB2012T100MR)'
'IND CHIP 10UH(20%,100MA,LB2012T100MR)'
L1 10UH_8
+1.25V
D D
+1.25V
+1.25V
C C
+3V
B B
+1.5V
A A
L1 10UH_8
+
+
C451
C451
470U_7343
470U_7343
L2 10UH_8L2 10UH_8
+
+
C452
C452
470U_7343
470U_7343
'EMI FILTER BKP1608HS181-T(180,1.5A)'
'EMI FILTER BKP1608HS181-T(180,1.5A)'
L28
L28
PBY160808T-301Y-N_6
PBY160808T-301Y-N_6
C445
C445
22U_8
22U_8
R30 0_6R30 0_6
L23 PBY160808T-301Y-N_6
L23 PBY160808T-301Y-N_6
L24 PBY160808T-301Y-N_6L24 PBY160808T-301Y-N_6
C409 22U_8C409 22U_8
+1.25V
C433
C433
.1U_4
.1U_4
C441
C441
.1U_4
.1U_4
C449
C449
10U_8
10U_8
C439
C439
.1U_4
.1U_4
R29 100/F_6R29 100/F_6
5
C39
C39
.1U_4
.1U_4
C44
C44
.1U_4
.1U_4
V1.25M_MPLL_RC
+3V_TV_DAC
C47
C47
.1U_4
.1U_4
C399
C399
+
+
100U_3528
100U_3528
C447
C447
22N_4
22N_4
C444
C444
22N_4
22N_4
C431
C431
22N_4
22N_4
C38
C38
22N_4
22N_4
C50
C50
.1U_4
.1U_4
R33 0_6R33 0_6
+3V
<FAE>
INT VGA disable
VCCSYNC connect to GND
L29 PBY160808T-301Y-N_6L29 PBY160808T-301Y-N_6
+3V
R110 0_6R110 0_6
R413
R413
*0_4
*0_4
R427
R427
*0_4
*0_4
R423
R423
*0_4
*0_4
C37
C37
22N_4
22N_4
R426 0_6R426 0_6
C72
C72
.1U_4
.1U_4
C75
C75
.1U_4
.1U_4
C49
C49
1U_6
1U_6
+3V_TV_DAC
C410
C410
22U_8
22U_8
R403
R403
0.5_6
0.5_6
R118 0_6R118 0_6
+1.25V
C103
C103
*22U_8
*22U_8
4
+3V_VCCSYNC
C45
C45
.1U_4
.1U_4
C430
C430
C446
C446
.1U_4
.1U_4
*22U_8
*22U_8
C429
C429
.1U_4
.1U_4
R53 0_8R53 0_8
+3V
C79
C79
4.7U_6
4.7U_6
C106
C106
C105
C105
*1U_6
*1U_6
*1U_6
*1U_6
R60 *0_4R60 *0_4
R31 0_6R31 0_6
R92 0_6R92 0_6
+1.25V
L3 PBY160808T-301Y-N_6L3 PBY160808T-301Y-N_6
+1.25V
+V1.25S_PEGPLL_FB
C40
C40
10U_8
10U_8
R420 0_6R420 0_6
+1.8VSUS
4
C110
C110
22U_8
22U_8
C107
C107
22U_8
22U_8
C448
C448
22N_4
22N_4
C438
C438
22N_4
22N_4
C80
C80
1U_6
1U_6
C87
C87
.1U_4
.1U_4
C435
C435
1000P_4
1000P_4
C48
C48
.1U_4
.1U_4
C78
C78
.1U_4
.1U_4
R43
R43
1_8
1_8
C46
C46
1U_6
1U_6
R421
R421
*0_4
*0_4
+3V_VCCA_CRT_DAC
R425
R425
*0_4
*0_4
+3V_VCCA_DAC_BG
+1.25V_VCCA_DPLLA
+1.25V_VCCA_DPLLB
+1.25VM_VCCA_HPLL
+1.25VM_VCCA_MPLL
+1.8VSUS_VCC_TX_LVDS
+3V_VCCA_PEG_BG
+1.25V_VCCD_PEG_PLL
+1.25VM_VCCA_SM
+1.25VM_VCCA_SM_CK
+1.5V_VCCD_CRT
+1.5V_VCCD_TVDAC
+1.5V_VCCD_QDAC
+1.25VM_MCH_VCCD_HPLL
+1.25V_VCCD_PEG_PLL
C55
C55
.1U_4
.1U_4
+1.8V_VCCD_LVDS
C440
C440
*10U_8
*10U_8
3
CRT/TV Disable/Enable guideline
EnableBall EnableDisable DisableBall
VCCA_CRT
3.3V GND
VCCD_CRT
VCCDQ_CRT
1.5V
VCCA_A_TVO
3.3V
VCCA_B_TVO VCC_SYNC
3.3V
AW18
AV19
AU19
AU18
AU17
AT22
AT21
AT19
AT18
AT17
AR17
AR16
BC29
BB29
C54
C54
.1U_4
.1U_4
GND
GND
GND
GND
U21H
U21H
J32
VCCSYNC
A33
VCCA_CRT_DAC_1
B33
VCCA_CRT_DAC_2
A30
VCCA_DAC_BG
B32
VSSA_DAC_BG
B49
VCCA_DPLLA
H49
VCCA_DPLLB
AL2
VCCA_HPLL
AM2
VCCA_MPLL
A41
VCCA_LVDS
B41
VSSA_LVDS
K50
VCCA_PEG_BG
K49
VSSA_PEG_BG
U51
VCCA_PEG_PLL
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2
VCCA_SM_CK_1
VCCA_SM_CK_2
C25
VCCA_TVA_DAC_1
B25
VCCA_TVA_DAC_2
C27
VCCA_TVB_DAC_1
B27
VCCA_TVB_DAC_2
B28
VCCA_TVC_DAC_1
A28
VCCA_TVC_DAC_2
M32
VCCD_CRT
L29
VCCD_TVDAC
N28
VCCD_QDAC
AN2
VCCD_HPLL
U48
VCCD_PEG_PLL
J41
VCCD_LVDS_1
H42
VCCD_LVDS_2
CRESTLINE_1p0
CRESTLINE_1p0
VCCA_C_TVO
VCCD_TVO
VCCABG_DAC
VSSABG_DAC
+1.05V
+3V
3
3.3V
1.5V1.5V
3.3V
GND
3.3V
CRTPLLA PEGA SMTV
CRTPLLA PEGA SMTV
POWER
POWER
A CK A LVDS
A CK A LVDS
D TV/CRTLVDS
D TV/CRTLVDS
D26 PDZ5.6BD26 PDZ5.6B
2 1
<CRB>
+1.25V AND +1.25M shall be
+1.5V for Calero Interposer
GND
1.5V
GND
GND
GND
AXD
AXD
VCC_AXD_NCTF
AXF
AXF
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
SM CK
SM CK
VCC_TX_LVDS
PEG
PEG
VCC_RXR_DMI_1
VCC_RXR_DMI_2
DMI
DMI
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT
VTT
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
VCC_DMI
VCC_HV_1
VCC_HV_2
HV
HV
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
VTTLF1
VTTLF2
VTTLF3
VTTLF
VTTLF
U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1
AT23
AU28
AU24
AT29
AT25
AT30
AR29
B23
B21
A21
AJ50
BK24
BK23
BJ24
BJ23
A43
C40
B40
AD51
W50
W51
V49
V50
AH50
AH51
A7
F2
AH1
+1.05V_SD
2
+1.05V
+1.25V_AXD
+1.25V_VCC_AXF
+1.25V_VCC_DMI
+1.8VSUS_VCC_SM_CK
+1.8VSUS_VCC_TX_LVDS
+3V_VCC_HV
C65
C65
C42
C42
.47U_4
.47U_4
.47U_4
.47U_4
R436
R436
10_4
10_4
R433 0_4R433 0_4
2
LVDS Disable/Enable guideline
External VGA with EV@part,Internal VGA with IV@ part
Signal
VCCD_LVDS
VCCA_LVDS
VCCTX_LVDS
C437
C437
.47U_4
.47U_4
C53
C53
4.7U_8
4.7U_8
C83
C83
1U_6
1U_6
C94
C94
.1U_4
.1U_4
+3V_VCC_HV
C453
C453
.1U_4
.1U_4
If SDVO Disable
LVDS Disable
GND
GND
EXTERNAL INTERNAL
C51
C51
4.7U_8
4.7U_8
R93 0_6R93 0_6
C77
C77
*22U_8
*22U_8
C443
C443
1U_6
1U_6
C68
C68
.1U_4
.1U_4
C96
C96
22U_8
22U_8
+VCC_PEG
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
If SDVO enable
LVDS Disable
1.8V
GND
GNDGND
C56
C56
C52
C52
.47U_6
.47U_6
2.2U_8
2.2U_8
R424 0_6R424 0_6
C442
C442
10U_8
10U_8
R91 0_6R91 0_6
L5 1UH_8L5 1UH_8
R109 1_6R109 1_6
+
+
C405
C405
10U_8
10U_8
330U_3528
330U_3528
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BU1 Santa Rosa
PROJECT : BU1 Santa Rosa
PROJECT : BU1 Santa Rosa
GMCH Power-2(5 of 7)
GMCH Power-2(5 of 7)
GMCH Power-2(5 of 7)
+
+
C421
C421
330U_3528
330U_3528
+1.25V
+V1.8_SMCK_RC
C434
C434
1000P_4
1000P_4
L22 91nHL22 91nH
C400
C400
1
If SDVO enable
LVDS enable
1.8V
1.8V
1.8V
+1.05V
+1.25V
+1.25V
+1.8VSUS
C119 22U_8C119 22U_8
L27 1UH_8L27 1UH_8
+
+
C450
C450
220U_7343
220U_7343
<FAE>
VCC_RXR_DMI and VCC_PEG
connect to+1.05V
1
+1.8VSUS
+1.05V
933Tuesday, February 06, 2007
933Tuesday, February 06, 2007
933Tuesday, February 06, 2007
of
of
of
1A
1A
1A
5
4
3
2
1
NB(Power-3)
U21I
U21I
A13
VSS_1
A15
VSS_2
A17
VSS_3
A24
VSS_4
AA21
VSS_5
AA24
VSS_6
AA29
VSS_7
AB20
D D
C C
B B
A A
5
AB23
AB26
AB28
AB31
AC10
AC13
AC3
AC39
AC43
AC47
AD1
AD21
AD26
AD29
AD3
AD41
AD45
AD49
AD5
AD50
AD8
AE10
AE14
AE6
AF20
AF23
AF24
AF31
AG2
AG38
AG43
AG47
AG50
AH3
AH40
AH41
AH7
AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AK31
AK51
AM11
AM13
AM3
AM4
AM41
AM45
AN1
AN38
AN39
AN43
AN5
AN7
AP4
AP48
AP50
AR11
AR2
AR39
AR44
AR47
AR7
AT10
AT14
AT41
AT49
AU1
AU23
AU29
AU3
AU36
AU49
AU51
AV39
AV48
AW1
AW12
AW16
AL1
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
CRESTLINE_1p0
CRESTLINE_1p0
VSS
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41
4
3
U21J
U21J
C46
VSS_199
C50
VSS_200
C7
VSS_201
D13
VSS_202
D24
VSS_203
D3
VSS_204
D32
VSS_205
D39
VSS_206
D45
VSS_207
D49
VSS_208
E10
VSS_209
E16
VSS_210
E24
VSS_211
E28
VSS_212
E32
VSS_213
E47
VSS_214
F19
VSS_215
F36
VSS_216
F4
VSS_217
F40
VSS_218
F50
VSS_219
G1
VSS_220
G13
VSS_221
G16
VSS_222
G19
VSS_223
G24
VSS_224
G28
VSS_225
G29
VSS_226
G33
VSS_227
G42
VSS_228
G45
VSS_229
G48
VSS_230
G8
VSS_231
H24
VSS_232
H28
VSS_233
H4
VSS_234
H45
VSS_235
J11
VSS_236
J16
VSS_237
J2
VSS_238
J24
VSS_239
J28
VSS_240
J33
VSS_241
J35
VSS_242
J39
VSS_243
K12
VSS_245
K47
VSS_246
K8
VSS_247
L1
VSS_248
L17
VSS_249
L20
VSS_250
L24
VSS_251
L28
VSS_252
L3
VSS_253
L33
VSS_254
L49
VSS_255
M28
VSS_256
M42
VSS_257
M46
VSS_258
M49
VSS_259
M5
VSS_260
M50
VSS_261
M9
VSS_262
N11
VSS_263
N14
VSS_264
N17
VSS_265
N29
VSS_266
N32
VSS_267
N36
VSS_268
N39
VSS_269
N44
VSS_270
N49
VSS_271
N7
VSS_272
P19
VSS_273
P2
VSS_274
P23
VSS_275
P3
VSS_276
P50
VSS_277
R49
VSS_278
T39
VSS_279
T43
VSS_280
T47
VSS_281
U41
VSS_282
U45
VSS_283
U50
VSS_284
V2
VSS_285
V3
VSS_286
CRESTLINE_1p0
CRESTLINE_1p0
VSS
VSS
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28
AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50
VSS_GMCH_T29
VSS_GMCH_T31
VSS_GMCH_T33
VSS_GMCH_R28
2
R35 0_4R35 0_4
R27 0_4R27 0_4
R28 0_4R28 0_4
R63 0_4R63 0_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BU1 Santa Rosa
PROJECT : BU1 Santa Rosa
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT : BU1 Santa Rosa
GMCH Power-3(6 of 7)
GMCH Power-3(6 of 7)
GMCH Power-3(6 of 7)
1
10 33Thursday, February 01, 2007
10 33Thursday, February 01, 2007
10 33Thursday, February 01, 2007
of
of
of
1A
1A
1A
5
4
3
2
1
Strap table
All strap are sampled with respect to the leading edge of the GMCH Power OK(PWROK) Signal
CFG[17:3] Have internal Pull-up
CFG[18:19] Have internal Pull-down
Any CFG signal strapping option not list below should be left NC Pin
Pin Name Strap description
D D
CFG[2:0]
CFG[4:3]
CFG5
CFG6
CFG7
CFG8
CFG9
CFG[11:10]
C C
CFG[13:12]
CFG[15:14]
CFG16
CFG[18:17]
SDVO_CTRLDATA
CFG19
CFG20
B B
DMI X2 Select
MCH_CFG_5 Low = DMIX2
High = IDMIX4(Default)
FSB Dynamic ODT
MCH_CFG_16 Low = ODT Disable
A A
MCH_CFG_16[6]
High = ODT Enable(Default)
5
FSB Frequency Select
Reserved
DMI X2 Select
Reserved
CPU Strap
Low power PCI Express
PCI Express Graphics Lane Reversal
Reserved
XOR/ALLZ
Reserved
FSB Dynamic ODT
Reserved
SDVO Present
DMI Lane Reversal
SDVO/PCIe concurrent
DMI Lane Reversal
MCH_CFG_19 Low = Normal operation(Default)
R51
R51
*4.02K_4
*4.02K_4
MCH_CFG_19[6]
SDVO/PCIE Concurrent operation
MCH_CFG_20
R58
R58
*4.02K_4
*4.02K_4
MCH_CFG_20[6]
High = Reverse Lane
+3V
R36
R36
*4.02K_4
*4.02K_4
Low = Only SDVO or PCIE X1 is
operational(Default)
High = SDVO andPCIE X1 are operating
simultaneously via the PEG port
+3V
R430
R430
*4.02K_4
*4.02K_4
4
Configuration
010 = FSB 800MHz
011 = FSB 667MHz
0 = DMI X2
1 = DMI X4(Default)
0 = Reserved
1 = Mobile CPU(Default)
0 = Normal mode
1 = Low Power mode
0 = Reverse Lanes
1 = Normal operation(Default)
00 = Reserved
01 = XOR Mode Enable
10 = All-Z Mode Enabled
11 = Normal operation(Default)
0 = Dynamic ODT disable
1 = Dynamic ODT Enable(Default)
0 = No SDVO Card present(Default)
1 = SDVO Card Present
0 = Normal operation(Default)
1 = Reverse Lanes
0 = Only SDVO or PCIE x1 is operation(Default)
1 = SDVO and PCIE x1 are operating simultaneously via the PEG port
XOR /ALLz /Clock Un-gating
MCH_CFG_12MCH_CFG_13 Configuration
0
0
1
1
MCH_CFG_12[6]
MCH_CFG_13[6]
0
1
0
1
Clock gating disable
XOR Mode Enable
ALL-z Mode Enable
Normal operation(Default)
3
R48
R48
*4.02K_4
*4.02K_4
PCI Express Graphics
MCH_CFG_9 Low = Reverse Lane
R54
R54
*4.02K_4
*4.02K_4
High = Normal operation(Default)
MCH_CFG_9[6]MCH_CFG_5[6]
2
R47
R47
*4.02K_4
*4.02K_4
SDVO Present
Strap define at External
DVI control page
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BU1 Santa Rosa
PROJECT : BU1 Santa Rosa
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT : BU1 Santa Rosa
GMCH Strap(7 of 7)
GMCH Strap(7 of 7)
GMCH Strap(7 of 7)
1
11 33Monday, March 26, 2007
11 33Monday, March 26, 2007
11 33Monday, March 26, 2007
of
of
of
1A
1A
1A
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