Quanta BL5S DABL5SMB6E0 Santa Rosa, Satellite A300 Schematic
1
2
3
4
5
6
7
8
PCB STACK UP
BL5S Block Diagram
LAYER 1 : TOP
LAYER 2 : SGND
LAYER 3 : IN1
A A
LAYER 4 : IN2
LAYER 5 : VCC
LAYER 6 : BOT
VCC_CORE
HDMI
Page 20
TV-OUT
Page 22
CRT
Page 18
LCD(WXGA+ 15.4W)
Page 18
Transmitter
Sil1392
Page 20
+1.5V
SATA - TWO HDD
+1.05V
B B
+1.25V
+1.8VSUS
+3VPCU
+3V_S5
+3VSUS
+3V
+5VPCU
+5V_S5
+5V
SMDDR_VTERM
SMDDR_VREF
C C
Page 22
IDE - ODD
Page 22
USB CONN 1
Page 19
USB CONN 2
Page 19
USB CONN3
Page 19
USB CONN 4
Page 19DAUGHTER BOARD
WLAN
Page 25
Finger Printer
Page 28
Bluetooth
Page 28
New Card
Page 28
Felica
Page 28
Camera
Page 18
Azalia
SATA X2
PATA
USB 2.0
SDVO
R.G.B
LVDS X2
Page 29
FAN Touch
Page 3,4
Page 5,7,8,9,10,11
Page 14,15,16,17
WPC8769LDG
WPCE775L
PAD Board
Intel
Merom
(35W)
FSB(667/800MHZ)
Crestline GM
DMI(x2/x4)
ICH8M
LPC
32.768KHz
Key FLASH
ROM
PCI-E X16
533/ 667 MHZ DDR II
PCI-Express
MINI CARD
WLAN
Page 25
Azalia
PCI Bus
CIR
Azalia
Card
Reader/1394
OZ129T
Page 23
5 IN 1
Page 2
Page 19
MINI CARD
Page 25
1394
CLOCK GENERATOR
CK505
ICS9LPR363
VGA CONNECTOR
DDRII-SODIMM1
DDRII-SODIMM2
Page 12,13
MINI CARD
Page 25
AUDIO CODEC
(CX20561)
Page 26
MODEM CONN
(CX20548)
Page 26
USB X2
RJ11
CRT
HDMI
LCD
TV-OUT
NEW CARD
Page 28 Page 24
Port-A
Port-B
DIB_PDIB_N
Port-C
Giga/100/10 LAN
Marvell_8040
8055
RJ45
SPK AMP
Page 26
HP(SPDIF)
Page 27
INT SPK
Page 26
INT MIC
Page 18,27
MIC JACK
Page 27
FM TUNER
Page 27
RJ11/USB DAUGHTER BOARD
D D
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
PROJECT : BL5S Santa Rosa
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
1
2
3
4
5
6
Date: Sheet
7
PROJECT : BL5S Santa Rosa
Block Diagram
Block Diagram
Block Diagram
1A
1A
137Tuesday, January 22, 2008
137Tuesday, January 22, 2008
137Tuesday, January 22, 2008
8
1A
of
of
of
Clock Generator
5
4
3
2
1
Clock Gen Differential IO
power
L21 PBY160808T-301Y-N_6L21 PBY160808T-301Y-N_6
+3V
C270
C270
10u/10V_8
D D
H=1.5mm
C272 27p_4C272 27p_4
CL=20p
C280 27p_4C280 27p_4
21
CG_XIN
Y2
Y2
14.318MHZ
14.318MHZ
CG_XOUT
10u/10V_8
10/26 REV_A1 Change Value
PCLK_DEBUG(25)
T49T49
PCLK_OZ129(23)
C C
PCLK_591(29)
PCLK_ICH(15)
CLKUSB_48(16)
14M_ICH(16)
+3V
+3V
+3V
CLK_BSEL0
CLK_BSEL1
CLK_BSEL2 FSC
C291 0.1u/10V_4C291 0.1u/10V_4
C299 0.1u/10V_4C299 0.1u/10V_4
C271 10u/10V_8C271 10u/10V_8
C253 0.1u/10V_4C253 0.1u/10V_4
C295 0.1u/10V_4C295 0.1u/10V_4
C259 0.1u/10V_4C259 0.1u/10V_4
C255 0.1u/10V_4C255 0.1u/10V_4
R277 10K_4R277 10K_4
R271 *10K_4R271 *10K_4
R278 *10K_4R278 *10K_4
R272 10K_4R272 10K_4
R279 *10K_4R279 *10K_4
R273 10K_4R273 10K_4
R275 2.2K_4R275 2.2K_4
R231 10K_4R231 10K_4
R228 33_4R228 33_4
+1.25V_VDD
R259 33_4R259 33_4
R264 33_4R264 33_4
R265 33_4R265 33_4
R266 10K_4R266 10K_4
R267 33_4R267 33_4
R268 33_4R268 33_4
R274 33_4R274 33_4
VDD_CK_VDD_48
VDD_CK_VDD_48
VDD_CK_VDD_48
VDD_CK_VDD_48
VDD_CK_VDD_48
VDD_CK_VDD_48
PCLK_DEBUG_R
PCLK_PCM_RPCLK_PCM
PCLK_R5C833_R
PCI_CLK_SIO_R
PCLK_591_R
PCLK_ICH_R
CG_XIN
CG_XOUT
FSA
FSA
H=1.2mm
U9
IC(64P) ICS9LPRS365BGLFT(TSSOP)
U9
IC(64P) ICS9LPRS365BGLFT(TSSOP)
2
VDD_PCI
9
VDD_48
16
VDD_PLL3
61
VDD_REF
CK505
39
55
12
20
26
45
36
49
1
3
4
5
6
7
60
59
10
57
62
8
11
15
19
52
23
29
42
58
CK505
VDD_SRC
VDD_CPU
VDD_96_IO
VDD_PLL3_IO
VDD_SRC_IO_1
VDD_SRC_IO_3
VDD_SRC_IO_2
VDD_CPU_IO
PCI0/CR#_A
PCI1/CR#_B
PCI2/TME
PCI3
PCI4/SRC5_EN
PCIF5/ITP_EN
XTAL_IN
XTAL_OUT
USB_48/FSA
FSB/TEST/MODE
REF0/FSC/TESTSEL
VSS_PCI
VSS_48
VSS_IO
VSS_PLL3
VSS_CPU
VSS_SRC1
VSS_SRC2
VSS_SRC3
VSS_REF
ICS9LPRS365BGLFT
IO_VOUT
SCLK
SDA
SRC5/PCI_STOP#
SRC5#/CPU_STOP#
CPU0
CPU0#
CPU1
CPU1#
SRC8/ITP
SRC8#/ITP#
SRC10#
SRC10
SRC11/CR#_H
SRC11#/CR#_G
SRC9
SRC9#
SRC7/CR#_F
SRC7#/CR#_E
SRC6
SRC6#
SRC4
SRC4#
SRC3/CR#_C
SRC3#/CR#_D
SRC2/SATA
SRC2#/SATA#
SRC1/SE1
SRC1#/SE2
SRC0/DOT96
SRC0#/DOT96#
CKPWRGD/PWRDWN#
ICS9LPRS365AGLFT/ SLG8SP512T
ICS9LPRS365AGLFT/ SLG8SP512T
48
CGCLK_SMB
64
CGDAT_SMB
63
38
37
CLK_CPU_BCLK_R
54
CLK_CPU_BCLK#_R
53
CLK_MCH_BCLK_R
51
CLK_MCH_BCLK#_R
50
CLK_PCIE_MINI3_R
47
CLK_PCIE_MINI3#_R
46
CLK_PCIE_3GPLL#_R
35
CLK_PCIE_3GPLL_R
34
CLK_MCH_OE#_R
33
NEW_CLKREQ#_R
32
CLK_PCIE_NEW_R
30
CLK_PCIE_NEW_R#
31
CLK_PCIE_MINI2_R
44
CLK_PCIE_MINI2#_R
43
CLK_PCIE_MINI_R
41
CLK_PCIE_MINI#_R
40
CLK_PCIE_LAN_R
27
CLK_PCIE_LAN#_R
28
CLK_PCIE_ICH_R
24
CLK_PCIE_ICH#_R
25
CLK_PCIE_SATA_R
21
CLK_PCIE_SATA#_R
22
DREFSSCLK_R
17
DREFSSCLK#_R
18
DREFCLK_R
13
DREFCLK#_R
14
56
C282
C282
C281
C281
10u/10V_8
10u/10V_8
*10u/10V_8
*10u/10V_8
CGCLK_SMB (13)
CGDAT_SMB (13)
RP32 0X2RP32 0X2
1
3
RP33 0X2RP33 0X2
1
3
RP34 0X2RP34 0X2
1
3
RP40 0X2RP40 0X2
1
3
R237 475_4R237 475_4
R262 475_4R262 475_4
RP46 0X2RP46 0X2
3
1
RP35 0X2RP35 0X2
1
3
RP36 0X2RP36 0X2
1
3
RP45 0X2RP45 0X2
3
1
RP44 0X2RP44 0X2
3
1
RP43 0X2RP43 0X2
3
1
RP41 IV@0X2RP41 IV@0X2
3
1
C257
C257
0.1u/10V_4
0.1u/10V_4
C260
C260
0.1u/10V_4
0.1u/10V_4
2
4
2
4
2
4
2
4
4
2
2
4
2
4
4
2
4
2
4
2
4
2
C297
C297
0.1u/10V_4
0.1u/10V_4
C256
C256
0.1u/10V_4
0.1u/10V_4
PM_STPPCI# (16)
PM_STPCPU# (16)
CLK_CPU_BCLK (3)
CLK_CPU_BCLK# (3)
CLK_MCH_BCLK (5)
CLK_MCH_BCLK# (5)
CLK_PCIE_MINI3 (25)
CLK_PCIE_MINI3# (25)
CLK_PCIE_3GPLL# (6)
CLK_PCIE_3GPLL (6)
CLK_MCH_OE# (6)
NEW_CLKREQ# (28)
CLK_PCIE_NEW (28)
CLK_PCIE_NEW# (28)
CLK_PCIE_MINI2 (25)
CLK_PCIE_MINI2# (25)
CLK_PCIE_MINI (25)
CLK_PCIE_MINI# (25)
CLK_PCIE_LAN (24)
CLK_PCIE_LAN# (24)
CLK_PCIE_ICH (15)
CLK_PCIE_ICH# (15)
CLK_PCIE_SATA (14)
CLK_PCIE_SATA# (14)
DREFCLK (6)
DREFCLK# (6)
CK_PWRGD (16)
+1.25V_VDD +1.25V
L22
L22
PBY160808T-301Y-N_6
PBY160808T-301Y-N_6
C300
C300
C296
C296
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
To SB
To CPU
To NB
To MINI3
To NB
To New Card
To MINI2
To WLAN
To LAN
To SB
To SB
To NB
ICS9LPRS365
(ALPRS365K13)
Pin 4
Pin 5
Pin 6
Pin 7
PCI2/TME
PCI-3
PCI-4/27M_SEL
PCIF-5/ITP_EN
B B
CPU Clock select
BSEL Frequency Select Table
FSC FSB FSA Frequency
0
0
0
1
0
A A
1
0
1
1
1
1
0
1
0
1
RTM875T-606
(AL000875K06)
PCI2/TME
internal PD
PCI-3/SRC5_EN
internal PD
PCI-4/27M_SEL
internal PD
PCIF-5/ITP_EN
internal PD
0
1
1
0
0
1
1
0
5
PIN37/38 IS SRC5
PIN 17/18 IS 27MHz
266Mhz0
133Mhz
166Mhz
200Mhz
400Mhz
Reserved
100Mhz
333Mhz
(default)
PULL DOWNPULL HIGH
NORMAL RUNNO OVERCLOCKING
PIN37/38 IS
PCI_STOP/CPU_STOP
PIN 17/18
IS SRC/DOT
PIN 46/47 IS SRC8PIN 46/47 IS CPUITP
+1.05V
+1.05V
+1.05V
10/31 REV_A1 Change Value
(default)
(default)
(default)
CPU_BSEL0(3)
CPU_BSEL1(3)
CPU_BSEL2(3) MCH_BSEL2 (6)
4
PCLK_PCM
PCLK_591
CLKUSB_48
14M_ICH
PCLK_ICH
PCLK_DEBUG
R282 0_4R282 0_4
R281 *56_4R281 *56_4
R280 *1K_4R280 *1K_4
R225 0_4R225 0_4
R227 *0_4R227 *0_4
R226 *1K_4R226 *1K_4
R233 0_4R233 0_4
R234 *0_4R234 *0_4
R232 *1K_4R232 *1K_4
CLK_BSEL0
CLK_BSEL1
CLK_BSEL2
C311 *33p_4C311 *33p_4
C312 *33p_4C312 *33p_4
C324 15p_4C324 15p_4
C258 *33p_4C258 *33p_4
C323 *33p_4C323 *33p_4
C304 *33p_4C304 *33p_4
MCH_BSEL0 (6)
MCH_BSEL1 (6)
3
FSA
FSB
FSC
DREFSSCLK#_R
DREFSSCLK_R
+3V
RP42 IV@0X2RP42 IV@0X2
RP47 EV@0X2RP47 EV@0X2
R261 10K_4R261 10K_4
2
2
1
4
3
4
3
2
1
Clock Gen
I2C
SDATA(16,21,25,28)
SCLK(16,21,25,28)
01/21 REV_3B Add for ESD
NEW_CLKREQ#_R
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
CLK. GEN./ CK505
CLK. GEN./ CK505
CLK. GEN./ CK505
Date: Sheet
Date: Sheet
Date: Sheet
DREFSSCLK# (6)
DREFSSCLK (6)
CLK_MXM (19)
CLK_MXM# (19)
To NB
To MXM
+3V
Q17
Q17
RHU002N06
RHU002N06
2
3
+3V
Q18
Q18
RHU002N06
RHU002N06
2
3
C685
C685
*0.1u/10V_4
*0.1u/10V_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
PROJECT : BL5S Santa Rosa
PROJECT : BL5S Santa Rosa
R242
R242
10K_4
10K_4
CGDAT_SMB
1
R250
R250
10K_4
10K_4
CGCLK_SMB
1
237Tuesday, January 22, 2008
237Tuesday, January 22, 2008
237Tuesday, January 22, 2008
1
1A
1A
1A
of
of
of
5
H_A#[16:3](5)
CPU(HOST)
D D
C C
B B
+1.05V
A A
R51
R51
1K/F_4
1K/F_4
R50
R50
2K/F_6
2K/F_6
T9T9
T73T73
T23T23
T8T8
H_ADSTB0#(5)
H_REQ#[4:0](5)
H_A#[35:17](5)
H_ADSTB1#(5)
H_IGNNE#(14)
H_STPCLK#(14)
H_D#[15:0](5)
H_DSTBN#0(5)
H_DSTBP#0(5)
H_DINV#0(5)
H_D#[31:16](5)
H_DSTBN#1(5)
H_DSTBP#1(5)
H_DINV#1(5)
CPU_BSEL0(2)
CPU_BSEL1(2)
CPU_BSEL2(2)
H_A20M#(14)
H_FERR#(14)
H_INTR(14)
H_NMI(14)
H_SMI#(14)
R45 *1K_4R45 *1K_4
R44 *1K_4R44 *1K_4
5
CPU_TEST4
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_GTLREF
CPU_TEST1
CPU_TEST2
CPU_TEST3
CPU_TEST5
CPU_TEST6
U22A
U22A
J4
A[3]#
L5
A[4]#
L4
A[5]#
K5
A[6]#
M3
A[7]#
N2
A[8]#
J1
A[9]#
N3
A[10]#
P5
A[11]#
P2
A[12]#
L2
A[13]#
P4
A[14]#
P1
A[15]#
R1
A[16]#
M1
ADSTB[0]#
K3
REQ[0]#
H2
REQ[1]#
K2
REQ[2]#
J3
REQ[3]#
L1
REQ[4]#
Y2
A[17]#
U5
A[18]#
R3
A[19]#
W6
A[20]#
U4
A[21]#
Y5
A[22]#
U1
A[23]#
R4
A[24]#
T5
A[25]#
T3
A[26]#
W2
A[27]#
W5
A[28]#
Y4
A[29]#
U2
A[30]#
V4
A[31]#
W3
A[32]#
AA4
A[33]#
AB2
A[34]#
AA3
A[35]#
V1
ADSTB[1]#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD[01]
N5
RSVD[02]
T2
RSVD[03]
V3
RSVD[04]
B2
RSVD[05]
C3
RSVD[06]
D2
RSVD[07]
D22
RSVD[08]
D3
RSVD[09]
F6
RSVD[10]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
U22B
U22B
E22
D[0]#
F24
D[1]#
E26
D[2]#
G22
D[3]#
F23
D[4]#
G25
D[5]#
E25
D[6]#
E23
D[7]#
K24
D[8]#
G24
D[9]#
J24
D[10]#
J23
D[11]#
H22
D[12]#
F26
D[13]#
K22
D[14]#
H23
D[15]#
J26
DSTBN[0]#
H26
DSTBP[0]#
H25
DINV[0]#
N22
D[16]#
K25
D[17]#
P26
D[18]#
R23
D[19]#
L23
D[20]#
M24
D[21]#
L22
D[22]#
M23
D[23]#
P25
D[24]#
P23
D[25]#
P22
D[26]#
T24
D[27]#
R24
D[28]#
L25
D[29]#
T25
D[30]#
N25
D[31]#
L26
DSTBN[1]#
M26
DSTBP[1]#
N24
DINV[1]#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
B22
BSEL[0]
B23
BSEL[1]
C21
BSEL[2]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
ADDR GROUP 0 ADDR GROUP 1
ADDR GROUP 0 ADDR GROUP 1
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
XDP/ITP SIGNALS
XDP/ITP SIGNALS
DBR#
THERMAL
THERMAL
PROCHOT#
THERMDA
THERMDC
ICH
ICH
THERMTRIP#
H CLK
H CLK
BCLK[0]
BCLK[1]
RESERVED
RESERVED
DATA GRP 0
DATA GRP 0
DATA GRP 2DATA GRP 3
DATA GRP 2DATA GRP 3
DSTBN[2]#
DSTBP[2]#
DINV[2]#
DATA GRP 1
DATA GRP 1
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
MISC
MISC
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
PWRGOOD
DPWR#
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
SLP#
PSI#
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
D21
A24
B25
C7
A22
A21
4
H_IERR#
XDP_TCK
XDP_TDI
XDP_TMS
XDP_TRST#
XDP_DBRESET#
H_PROCHOT_R#
H_THERMDA
H_THERMDC
THERMTRIP#_PWR
H_D#32
Y22
H_D#33
AB24
H_D#34
V24
H_D#35
V26
H_D#36
V23
H_D#37
T22
H_D#38
U25
H_D#39
U23
H_D#40
Y25
H_D#41
W22
H_D#42
Y23
H_D#43
W24
H_D#44
W25
H_D#45
AA23
H_D#46
AA24
H_D#47
AB25
Y26
AA26
U22
H_D#48
AE24
H_D#49
AD24
H_D#50
AA21
H_D#51
AB22
H_D#52
AB21
H_D#53
AC26
H_D#54
AD20
H_D#55
AE22
H_D#56
AF23
H_D#57
AC25
H_D#58
AE21
H_D#59
AD21
H_D#60
AC22
H_D#61
AD23
H_D#62
AF22
H_D#63
AC23
AE25
AF24
AC20
COMP0
R26
COMP1
U26
COMP2
AA1
COMP3
Y1
E5
B5
D24
D6
D7
AE6
4
R40 56.2_4R40 56.2_4
R43 0_4R43 0_4
R41 56.2_4R41 56.2_4
R42 *2.2K_4R42 *2.2K_4
CLK_CPU_BCLK (2)
CLK_CPU_BCLK# (2)
R49 27.4/F_6R49 27.4/F_6
R48 54.9/F_4R48 54.9/F_4
R170 27.4/F_6R170 27.4/F_6
R173 54.9/F_4R173 54.9/F_4
+1.05V
H_D#[47:32] (5)
H_DSTBN#2 (5)
H_DSTBP#2 (5)
H_DINV#2 (5)
H_D#[63:48] (5)
H_DSTBN#3 (5)
H_DSTBP#3 (5)
H_DINV#3 (5)
H_DPSLP# (14)
H_DPWR# (5)
H_CPUSLP# (5)
PSI# (32)
H_ADS# (5)
H_BNR# (5)
H_BPRI# (5)
H_DEFER# (5)
H_DRDY# (5)
H_DBSY# (5)
H_BREQ#0 (5)
H_INIT# (14)
H_LOCK# (5)
H_CPURST# (5)
H_RS#0 (5)
H_RS#1 (5)
H_RS#2 (5)
H_TRDY# (5)
H_HIT# (5)
H_HITM# (5)
T28T28
01/17 REV_3B Add C674
T25T25
T26T26
T27T27
T24T24
T29T29
T77T77
+1.05V
H_PROCHOT# (32)
12/06 REV_3A Add C666
H_CPURST#
C674
C674
0.1u/10V_4
0.1u/10V_4
ICH_DPRSTP# (6,14,32)
H_PWRGD (14)
3
SYS_RST# (16)
3
CPU Thermal monitor
01/17 REV_3B mount C666
C666
C666
0.1u/10V_4
0.1u/10V_4
2ND_MBCLK(29)
2ND_MBDATA(29)
THERM_ALERT#(16)
CPU FAN
SYSFANON#(19)
VFAN(29)
PU/PD (ITP700)
XDP_TMS
XDP_TDI
XDP_TCK
XDP_TRST#
R174 39_4R174 39_4
R175 150_4R175 150_4
R171 27_4R171 27_4
R172 680_4R172 680_4
+3V
+3V
+3V
2
3
+3V
2
3
R434 10K_4R434 10K_4
R435 *0_4R435 *0_4
R436 10K_4R436 10K_4
THER_SHD#
+5V
C433
C433
2.2u/6.3V_6
2.2u/6.3V_6
R415 0_4R415 0_4
+1.05V
2
THERM_ALERT#_R
Q37
Q37
RHU002N06
RHU002N06
1
Q38
Q38
RHU002N06
RHU002N06
1
THERM_MBCLK
THERM_MBDATA
THER_SHD#
THERM_MBCLK
THERM_MBDATA
8
7
6
4
U19
U19
SCLK
SDA
ALERT#
OVERT#
LM95245
LM95245
10/22 REV_A1 Mount R434
THERM_ALERT#_R
THER_SHD#
+3V
R431
R431
330_4
330_4
Q36
Q36
2
MMBT3904
MMBT3904
1 3
H=1.75mm
U17
U17
VIN2VO
GND
1
/FON
GND
GND
4
VSET
GND
G995
G995
SYS_SHDN# (31)
3
5
6
7
8
FANPWR = 1.6*VSET
Thermal Trip
DELAY_VR_PWRGOOD(6,16,32)
+1.05V
THERMTRIP#_PWR
2
1
LM86VCC
1
R440
R440
10K_4
10K_4
VCC
DXP
DXN
GND
R438
R438
10K_4
10K_4
2
3
5
8
7
6
4
H_THERMDA
H_THERMDC
+3V
R445
R445
200_6
200_6
H=1.75mm
U20
U20
VCC
SCLK
DXP
SDA
DXN
ALERT#
GND
OVERT#
*MAX6657
*MAX6657
ADDRESS:
98H
LM86VCC
1
2
3
5
C458
C458
0.1u/10V_4
0.1u/10V_4
C459
C459
2200p_4
2200p_4
H_THERMDA
H_THERMDC
10/29 REV_A1 Add for ESD
10/26 REV_A1 Add for ESD
FANSIG(29)
TH_FAN_POWER
C436
C436
10u/10V_8
10u/10V_8
C434
C434
0.01u_4
0.01u_4
D44
D44
VPORT_6
VPORT_6
2 1
21
VPORT_6
VPORT_6
D49
D49
C440
C440
*0.01u_4
*0.01u_4
+3V
R423
R423
10K_4
10K_4
CN17
CN17
1
2
345
PTI_CWY030-B0G1Z
PTI_CWY030-B0G1Z
21
*VPORT_6
*VPORT_6
D50
D50
12/04 REV_3A DNI C440
+1.05V
3
Q39
Q39
2
FDV301N
FDV301N
1
R613
R613
1K_4
R439
R439
56.2_4
56.2_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
1K_4
10/22 REV_A1 Add R613
Q40
Q40
2
MMBT3904
MMBT3904
1 3
R442 *0_4R442 *0_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
PROJECT : BL5S Santa Rosa
PROJECT : BL5S Santa Rosa
CPU(1 of 2)/FAN/Thermal
CPU(1 of 2)/FAN/Thermal
CPU(1 of 2)/FAN/Thermal
10/22 REV_A1 Del
C452,Add R614
D36
D36
R437
R437
*BAS316
*BAS316
*10K_4
*10K_4
SYS_SHDN# (31)
PM_THRMTRIP# (6,14)
1
337Tuesday, January 22, 2008
337Tuesday, January 22, 2008
337Tuesday, January 22, 2008
R614
R614
100K_6
100K_6
of
of
of
1A
1A
1A
5
CPU(Power)
VCC_CORE
C499
C133
C133
10u/6.3V_8
10u/6.3V_8
C185
C185
*10u/6.3V_8
*10u/6.3V_8
C485
C485
*10u/6.3V_8
*10u/6.3V_8
C173
C173
*10u/6.3V_8
*10u/6.3V_8
C499
10u/6.3V_8
10u/6.3V_8
C497
C497
10u/6.3V_8
10u/6.3V_8
C154
C154
*10u/6.3V_8
*10u/6.3V_8
C184
C184
*10u/6.3V_8
*10u/6.3V_8
C487
C174
C174
10u/6.3V_8
10u/6.3V_8
C498
C498
*10u/6.3V_8
*10u/6.3V_8
C483
C483
*10u/6.3V_8
*10u/6.3V_8
C155
C155
*10u/6.3V_8
*10u/6.3V_8
C487
10u/6.3V_8
10u/6.3V_8
C484
C484
*10u/6.3V_8
*10u/6.3V_8
C183
C183
*10u/6.3V_8
*10u/6.3V_8
C182
C182
*10u/6.3V_8
*10u/6.3V_8
C156
C172
C172
10u/6.3V_8
10u/6.3V_8
C134
C134
10u/6.3V_8
10u/6.3V_8
C131
C131
*10u/6.3V_8
*10u/6.3V_8
C132
C132
*10u/6.3V_8
*10u/6.3V_8
C156
10u/6.3V_8
10u/6.3V_8
C157
C157
*10u/6.3V_8
*10u/6.3V_8
C486
C486
*10u/6.3V_8
*10u/6.3V_8
C478
C478
*10u/6.3V_8
*10u/6.3V_8
+
+
C151
C151
330u/2.5V_7343
330u/2.5V_7343
C495
C495
10u/6.3V_8
10u/6.3V_8
D D
C477
C477
10u/6.3V_8
10u/6.3V_8
C191
C191
*10u/6.3V_8
*10u/6.3V_8
C C
C496
C496
*10u/6.3V_8
*10u/6.3V_8
+
+
C152
C152
330u/2.5V_7343
330u/2.5V_7343
12/04 REV_3A Mount C152,C151
B B
C171
C171
10u/6.3V_8
10u/6.3V_8
4
C488
C488
10u/6.3V_8
10u/6.3V_8
C494
C494
*10u/6.3V_8
*10u/6.3V_8
C479
C479
*10u/6.3V_8
*10u/6.3V_8
U22C
U22C
A7
VCC[001]
A9
VCC[002]
A10
VCC[003]
A12
VCC[004]
A13
VCC[005]
A15
VCC[006]
A17
VCC[007]
A18
VCC[008]
A20
VCC[009]
B7
VCC[010]
B9
VCC[011]
B10
VCC[012]
B12
VCC[013]
B14
VCC[014]
B15
VCC[015]
B17
VCC[016]
B18
VCC[017]
B20
VCC[018]
C9
VCC[019]
C10
VCC[020]
C12
VCC[021]
C13
VCC[022]
C15
VCC[023]
C17
VCC[024]
C18
VCC[025]
D9
VCC[026]
D10
VCC[027]
D12
VCC[028]
D14
VCC[029]
D15
VCC[030]
D17
VCC[031]
D18
VCC[032]
E7
VCC[033]
E9
VCC[034]
E10
VCC[035]
E12
VCC[036]
E13
VCC[037]
E15
VCC[038]
E17
VCC[039]
E18
VCC[040]
E20
VCC[041]
F7
VCC[042]
F9
VCC[043]
F10
VCC[044]
F12
VCC[045]
F14
VCC[046]
F15
VCC[047]
F17
VCC[048]
F18
VCC[049]
F20
VCC[050]
AA7
VCC[051]
AA9
VCC[052]
AA10
VCC[053]
AA12
VCC[054]
AA13
VCC[055]
AA15
VCC[056]
AA17
VCC[057]
AA18
VCC[058]
AA20
VCC[059]
AB9
VCC[060]
AC10
VCC[061]
AB10
VCC[062]
AB12
VCC[063]
AB14
VCC[064]
AB15
VCC[065]
AB17
VCC[066]
AB18
VCC[067]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
.
.
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
3
+VCCA_PROC
H_VID0 (32)
H_VID1 (32)
H_VID2 (32)
H_VID3 (32)
H_VID4 (32)
H_VID5 (32)
H_VID6 (32)
+1.05V
+
+
C475
C475
330u/2.5V_7343
330u/2.5V_7343
VCC_CORE
R134
R134
100/F_6
100/F_6
R133
R133
100/F_6
100/F_6
C192
C192
0.1u/16V_6
0.1u/16V_6
C56
C56
0.01u_4
0.01u_4
2
C53
C53
0.1u/16V_6
0.1u/16V_6
C52
C52
0.1u/16V_6
0.1u/16V_6
R39 0_6R39 0_6
C54
C54
10u/10V_8
10u/10V_8
VCCSENSE (32)
VSSSENSE (32)
C207
C207
0.1u/16V_6
0.1u/16V_6
+1.5V
C206
C206
0.1u/16V_6
0.1u/16V_6
C114
C114
0.1u/16V_6
0.1u/16V_6
1
U22D
U22D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080]
VSS[081]P3VSS[162]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[163]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
.
.
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
PROJECT : BL5S Santa Rosa
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
PROJECT : BL5S Santa Rosa
CPU(2 of 2)
CPU(2 of 2)
CPU(2 of 2)
1
1A
1A
1A
of
of
of
437Tuesday, January 22, 2008
437Tuesday, January 22, 2008
437Tuesday, January 22, 2008
5
4
3
2
1
NB(HOST)
U21A
M10
N12
P13
W10
W6
W9
W3
AD12
AE3
AD9
AC9
AC7
AC14
AD11
AC11
AB2
AD7
AB1
AC6
AE2
AC5
AG3
AJ9
AH8
AJ14
AE9
AE11
AH12
AJ5
AH5
AJ6
AE7
AJ7
AJ2
AE5
AJ3
AH2
AH13
W1
W2
E2
G2
G7
M6
H7
H3
G4
F3
N8
H2
N9
H5
K9
M2
Y8
V4
M3
J1
N5
N3
N2
Y7
Y9
P4
N1
Y3
B3
C2
B6
E5
B9
A9
U21A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
CRESTLINE_1p0
CRESTLINE_1p0
H_ADSTB#_0
H_ADSTB#_1
HOST
HOST
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19
G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7
K5
L2
AD13
AE13
M7
K3
AD2
AH11
L7
K2
AC2
AJ10
M14
E13
A11
H13
B12
E12
D7
D8
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_D#[63:0](3)
+1.05V
R430
+1.05V
+1.05V
R430
221/F_4
221/F_4
R429
R429
100/F_4
100/F_4
R428
R428
24.9/F_4
24.9/F_4
R30
R30
54.9/F_4
54.9/F_4
R29
R29
54.9/F_4
54.9/F_4
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
C447
C447
0.1u/10V_4
0.1u/10V_4
+1.05V
12/05 REV_3A Add L53 for ESD
C449
C449
0.1u/10V_4
0.1u/10V_4
H_CPURST#(3)
R432
R432
1K/F_4
1K/F_4
R433
R433
2K/F_4
2K/F_4
L53 BK1608LM252-T_6L53 BK1608LM252-T_6
D D
C C
B B
A A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
H_AVREF
965GM : AJSLA5T0T20
965PM : AJSLA5U0T25
960GL : AJSLA5V0T09
5
4
3
H_A#[35:3] (3)
H_ADS# (3)
H_ADSTB0# (3)
H_ADSTB1# (3)
H_BNR# (3)
H_BPRI# (3)
H_BREQ#0 (3)
H_DEFER# (3)
H_DBSY# (3)
CLK_MCH_BCLK (2)
CLK_MCH_BCLK# (2)
H_DPWR# (3)
H_DRDY# (3)
H_HIT# (3)
H_HITM# (3)
H_LOCK# (3)
H_TRDY# (3)
H_DINV#[3:0] (3)
H_DSTBN#[3:0] (3)
H_DSTBP#[3:0] (3)
H_REQ#[4:0] (3)
H_RS#[2:0] (3)H_CPUSLP#(3)
2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
PROJECT : BL5S Santa Rosa
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT : BL5S Santa Rosa
GMCH HOST(1 of 7)
GMCH HOST(1 of 7)
GMCH HOST(1 of 7)
1
of
of
of
537Tuesday, January 22, 2008
537Tuesday, January 22, 2008
537Tuesday, January 22, 2008
1A
1A
1A
5
)
D D
M_A_A14(12,13)
M_B_A14(12,13)
C C
MCH_BSEL0(2)
MCH_BSEL1(2)
MCH_BSEL2(2)
MCH_CFG_5(11)
MCH_CFG_9(11)
MCH_CFG_12(11)
MCH_CFG_13(11)
MCH_CFG_16(11)
MCH_CFG_19(11)
MCH_CFG_20(11)
B B
A A
DELAY_VR_PWRGOOD3,16,32
M_RCOMP#
M_RCOMP
PM_BMBUSY#(16)
ICH_DPRSTP#(3,14,32)
PM_EXTTS#0(13)
PM_EXTTS#1(13)
PLTRST#_NB(15)
PM_THRMTRIP#(3,14)
PM_DPRSLPVR(16,32)
+1.8VSUS
R36
R36
20/F_4
20/F_4
R46
R46
20/F_4
20/F_4
R61 100_4R61 100_4
R54 *0_4R54 *0_4
+3V
5
T74T74
T75T75
T16T16
T17T17
T11T11
T14T14
T18T18
T10T10
T15T15
T12T12
T21T21
MCH_CFG_3
MCH_CFG_4
MCH_CFG_6
MCH_CFG_7
MCH_CFG_8
MCH_CFG_10
MCH_CFG_11
MCH_CFG_14
MCH_CFG_15
MCH_CFG_17
MCH_CFG_18
PM_EXTTS#0
RST_IN#_MCH
PM_THRMTRIP#_GMCH
R123 10K_4R123 10K_4
R121 10K_4R121 10K_4
R122 10K_4R122 10K_4
+1.8VSUS
U21B
U21B
P36
RSVD1
P37
RSVD2
R35
RSVD3
N35
RSVD4
AR12
RSVD5
AR13
RSVD6
AM12
RSVD7
AN13
RSVD8
J12
RSVD9
AR37
RSVD10
AM36
RSVD11
AL36
RSVD12
AM37
RSVD13
D20
RSVD14
H10
RSVD20
B51
RSVD21
BJ20
RSVD22
BK22
RSVD23
BF19
RSVD24
BH20
RSVD25
BK18
RSVD26
BJ18
RSVD27
BF23
RSVD28
BG23
RSVD29
BC23
RSVD30
BD24
RSVD31
BJ29
RSVD32
BE24
RSVD33
BH39
RSVD34
AW20
RSVD35
BK20
RSVD36
C48
RSVD37
D47
RSVD38
B44
RSVD39
C44
RSVD40
A35
RSVD41
B37
RSVD42
B36
RSVD43
B34
RSVD44
C34
RSVD45
P27
CFG_0
N27
CFG_1
N24
CFG_2
C21
CFG_3
C23
CFG_4
F23
CFG_5
N23
CFG_6
G23
CFG_7
J20
CFG_8
C20
CFG_9
R24
CFG_10
L23
CFG_11
J23
CFG_12
E23
CFG_13
E20
CFG_14
K23
CFG_15
M20
CFG_16
M24
CFG_17
L32
CFG_18
N33
CFG_19
L35
CFG_20
G41
PM_BM_BUSY#
L39
PM_DPRSTP#
L36
PM_EXT_TS#_0
J36
PM_EXT_TS#_1
AW49
PWROK
AV20
RSTIN#
N20
THERMTRIP#
G36
DPRSLPVR
BJ51
NC_1
BK51
NC_2
BK50
NC_3
BL50
NC_4
BL49
NC_5
BL3
NC_6
BL2
NC_7
BK1
NC_8
BJ1
NC_9
E1
NC_10
A5
NC_11
C51
NC_12
B50
NC_13
A50
NC_14
A49
NC_15
BK2
NC_16
CRESTLINE_1p0
CRESTLINE_1p0
CLK_MCH_OE#
PM_EXTTS#0
PM_EXTTS#1
R113 1K/F_4R113 1K/F_4
CFGRSVD
CFGRSVD
PM
PM
NC
NC
R112
R112
3.01K/F_4
3.01K/F_4
R104
R104
1K/F_4
1K/F_4
4
AV29
SM_CK_0
BB23
SM_CK_1
BA25
SM_CK_3
AV23
SM_CK_4
AW30
SM_CK#_0
BA23
SM_CK#_1
AW25
SM_CK#_3
AW23
SM_CK#_4
BE29
SM_CKE_0
AY32
SM_CKE_1
BD39
SM_CKE_3
BG37
SM_CKE_4
BG20
SM_CS#_0
BK16
SM_CS#_1
BG16
SM_CS#_2
BE13
SM_CS#_3
BH18
SM_ODT_0
BJ15
SM_ODT_1
BJ14
SM_ODT_2
BE16
SM_ODT_3
BL15
SM_RCOMP
SM_VREF_0
SM_VREF_1
PEG_CLK
PEG_CLK#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VR_EN
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
CLK_REQ#
ICH_SYNC#
TEST_1
TEST_2
4
BK14
BK31
BL31
AR49
AW4
B42
C42
H48
H47
K44
K45
AN47
AJ38
AN42
AN46
AM47
AJ39
AN41
AN45
AJ46
AJ41
AM40
AM44
AJ47
AJ42
AM39
AM43
E35
A39
C38
B39
E36
AM49
AK50
AT43
AN49
AM50
H35
K36
G39
G40
A37
R32
C129
C129
2.2u/6.3V_6
2.2u/6.3V_6
C123
C123
2.2u/6.3V_6
2.2u/6.3V_6
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
DDR MUXINGCLK
DDR MUXINGCLK
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
DMI
DMI
GRAPHICS VID
GRAPHICS VID
ME
ME
SDVO_CTRL_CLK
SDVO_CTRL_DATA
MISC
MISC
SM_RCOMP_VOH
C120
C120
0.01u_4
0.01u_4
SM_RCOMP_VOL
C115
C115
0.01u_4
0.01u_4
M_RCOMP
M_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SMDDR_VREF_MCH
DREFCLK
DREFCLK#
DREFSSCLK
DREFSSCLK#
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
+1.25V_CL_VREF
CLK_MCH_OE#
GMCH_TEST1
GMCH_TEST2
M_CLK_DDR0 (13)
M_CLK_DDR1 (13)
M_CLK_DDR3 (13)
M_CLK_DDR4 (13)
M_CLK_DDR#0 (13)
M_CLK_DDR#1 (13)
M_CLK_DDR#3 (13)
M_CLK_DDR#4 (13)
M_CKE0 (12,13)
M_CKE1 (12,13)
M_CKE3 (12,13)
M_CKE4 (12,13)
M_CS#0 (12,13)
M_CS#1 (12,13)
M_CS#2 (12,13)
M_CS#3 (12,13)
M_ODT0 (12,13)
M_ODT1 (12,13)
M_ODT2 (12,13)
M_ODT3 (12,13)
R35 *10K_6R35 *10K_6
R31 *10K_6R31 *10K_6
R450 0_4R450 0_4
R88 20K_4R88 20K_4
R33 0_6R33 0_6
DREFCLK (2)
DREFCLK# (2)
DREFSSCLK (2)
DREFSSCLK# (2)
CLK_PCIE_3GPLL (2)
CLK_PCIE_3GPLL# (2)
DMI_TXN[3:0] (15)
DMI_TXP[3:0] (15)
DMI_RXN[3:0] (15)
DMI_RXP[3:0] (15)
CL_CLK0 (16)
CL_DATA0 (16)
MPWROK (16)
CL_RST#0 (16)
SDVO_CTRLCLK (20)
SDVO_CTRLDATA (20)
CLK_MCH_OE# (2)
MCH_ICH_SYNC# (16)
R126 EV@0_4R126 EV@0_4
R127 EV@0_4R127 EV@0_4
3
1
RP49 EV@0X2RP49 EV@0X2
RP53 EV@0X2RP53 EV@0X2
1
3
+SMDDR_VREF
+1.8VSUS
INT_CRT_DDCCLK(18)
INT_CRT_DDCDAT(18)
INT_HSYNC(18)
INT_VSYNC(18)
C506
C506
0.1u/10V_4
0.1u/10V_4
4
2
2
4
INT_LVDS_PWM(18)
INT_LVDS_BLON(18)
INT_LVDS_EDIDCLK(18)
INT_LVDS_EDIDDATA(18)
INT_LVDS_DIGON(18)
INT_CRT_BLU(18)
INT_CRT_GRN(18)
INT_CRT_RED(18)
+1.25V_AXD
R461
R461
1K/F_4
1K/F_4
R463
R463
392/F_6
392/F_6
INT_CRT_DDCCLK
INT_CRT_DDCDAT
DREFCLK
DREFCLK#
DREFSSCLK
DREFSSCLK#
3
R452 EV@0_4R452 EV@0_4
R456 EV@0_4R456 EV@0_4
+3V
R116 IV@2.4K_4R116 IV@2.4K_4
R124 IV@0_4R124 IV@0_4
INT_TXLCLKOUT-(18)
INT_TXLCLKOUT+(18)
INT_TXUCLKOUT-(18)
INT_TXUCLKOUT+(18)
INT_TXLOUT0-(18)
INT_TXLOUT1-(18)
INT_TXLOUT2-(18)
INT_TXLOUT0+(18)
INT_TXLOUT1+(18)
INT_TXLOUT2+(18)
INT_TXUOUT0-(18)
INT_TXUOUT1-(18)
INT_TXUOUT2-(18)
INT_TXUOUT0+(18)
INT_TXUOUT1+(18)
INT_TXUOUT2+(18)
INT_TV_Y/G(22)
INT_TV_C/R(22)
+3V
R117 IV@2.2K_4R117 IV@2.2K_4
R120 IV@2.2K_4R120 IV@2.2K_4
R119 EV@0_4R119 EV@0_4
R118 EV@0_4R118 EV@0_4
R106 IV@30/F_4R106 IV@30/F_4
R89 IV@30/F_4R89 IV@30/F_4
R108 EV@0_4R108 EV@0_4
R103 EV@0_4R103 EV@0_4
Close U3023
3
R451 IV@10K_4R451 IV@10K_4
R454 IV@10K_4R454 IV@10K_4
LVDS_IBG
T22T22
INT_TV_COMP
INT_TV_Y/G
INT_TV_C/R
INT_CRT_BLU
INT_CRT_GRN
INT_CRT_RED
INT_CRT_DDCCLK
INT_CRT_DDCDAT
HSYNC_A
CRTIREF
VSYNC_A
HSYNC_A
VSYNC_A
Close U3023
For EV@
CRT R/G/B
TV A/B/C
USE 0 ohm R
R90 150/F_4R90 150/F_4
R86 150/F_4R86 150/F_4
R91 150/F_4R91 150/F_4
R78 150/F_4R78 150/F_4
R75 150/F_4R75 150/F_4
R76 150/F_4R76 150/F_4
R448 1.3K_6R448 1.3K_6
For IV@ USE 1.3K ohm R
For EV@ USE 0 ohm R
CTCLK
CTDA
CTCLK
CTDA
U21C
U21C
J40
L_BKLT_CTRL
H39
L_BKLT_EN
E39
L_CTRL_CLK
E40
L_CTRL_DATA
C37
L_DDC_CLK
D35
L_DDC_DATA
K40
L_VDD_EN
L41
LVDS_IBG
L43
LVDS_VBG
N41
LVDS_VREFH
N40
LVDS_VREFL
D46
LVDSA_CLK#
C45
LVDSA_CLK
D44
LVDSB_CLK#
E42
LVDSB_CLK
G51
LVDSA_DATA#_0
E51
LVDSA_DATA#_1
F49
LVDSA_DATA#_2
G50
LVDSA_DATA_0
E50
LVDSA_DATA_1
F48
LVDSA_DATA_2
G44
LVDSB_DATA#_0
B47
LVDSB_DATA#_1
B45
LVDSB_DATA#_2
E44
LVDSB_DATA_0
A47
LVDSB_DATA_1
A45
LVDSB_DATA_2
E27
TVA_DAC
G27
TVB_DAC
K27
TVC_DAC
F27
TVA_RTN
J27
TVB_RTN
L27
TVC_RTN
M35
TV_DCONSEL_0
P33
TV_DCONSEL_1
H32
CRT_BLUE
G32
CRT_BLUE#
K29
CRT_GREEN
J29
CRT_GREEN#
F29
CRT_RED
E29
CRT_RED#
K33
CRT_DDC_CLK
G35
CRT_DDC_DATA
F33
CRT_HSYNC
C32
CRT_TVO_IREF
E33
CRT_VSYNC
CRESTLINE_1p0
CRESTLINE_1p0
For IV@
CRT R/G/B
TV A/B/C
USE 150 ohm R
INT_CRT_BLU
INT_CRT_GRN
INT_CRT_RED
INT_TV_COMP
INT_TV_Y/G
INT_TV_C/R
CRTIREF
2
EXP_A_COMPX
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
N43
M43
J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
PEG_RXN10
AD44
PEG_RXN11
AD40
PEG_RXN12
AG46
PEG_RXN13
AH49
PEG_RXN14
AG45
PEG_RXN15
AG41
PEG_RXP0
J50
PEG_RXP1_H
L50
PEG_RXP2
M47
PEG_RXP3
U44
PEG_RXP4
T49
PEG_RXP5
T41
PEG_RXP6
W45
PEG_RXP7
W41
PEG_RXP8
AB50
PEG_RXP9
Y48
PEG_RXP10
AC45
PEG_RXP11
AC41
PEG_RXP12
AH47
PEG_RXP13
AG49
PEG_RXP14
AH45
PEG_RXP15
AG42
N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44
M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43
C_PEG_TXN0_H
C_PEG_TXP0_H
C_PEG_TXN2_H
C_PEG_TXP2_H
C_PEG_TXN1_H
C_PEG_TXP1_H
C_PEG_TXN3_H
C_PEG_TXP3_H
PEG_RXN1_H
PEG_RXP1_H
PEG_COMPI
PEG_COMPO
LVDS
LVDS
TV VGA
TV VGA
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_TX#_10
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
2
R462 24.9/F_4R462 24.9/F_4
PEG_RXN0
PEG_RXN1_H
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
C_PEG_TXN0_H
C_PEG_TXN1_H
C_PEG_TXN2_H
C_PEG_TXN3_H
C_PEG_TXN4
C228 EV@0.1u/10V_4C228 EV@0.1u/10V_4
C_PEG_TXN5
C219 EV@0.1u/10V_4C219 EV@0.1u/10V_4
C_PEG_TXN6
C217 EV@0.1u/10V_4C217 EV@0.1u/10V_4
C_PEG_TXN7
C230 EV@0.1u/10V_4C230 EV@0.1u/10V_4
C_PEG_TXN8
C226 EV@0.1u/10V_4C226 EV@0.1u/10V_4
C_PEG_TXN9
C508 EV@0.1u/10V_4C508 EV@0.1u/10V_4
C_PEG_TXN10
C215 EV@0.1u/10V_4C215 EV@0.1u/10V_4
C_PEG_TXN11
C224 EV@0.1u/10V_4C224 EV@0.1u/10V_4
C_PEG_TXN12
C516 EV@0.1u/10V_4C516 EV@0.1u/10V_4
C_PEG_TXN13
C514 EV@0.1u/10V_4C514 EV@0.1u/10V_4
C_PEG_TXN14
C512 EV@0.1u/10V_4C512 EV@0.1u/10V_4
C_PEG_TXN15
C510 EV@0.1u/10V_4C510 EV@0.1u/10V_4
C_PEG_TXP0_H
C_PEG_TXP1_H
C_PEG_TXP2_H
C_PEG_TXP3_H
C_PEG_TXP4
C227 EV@0.1u/10V_4C227 EV@0.1u/10V_4
C_PEG_TXP5
C218 EV@0.1u/10V_4C218 EV@0.1u/10V_4
C_PEG_TXP6
C216 EV@0.1u/10V_4C216 EV@0.1u/10V_4
C_PEG_TXP7
C229 EV@0.1u/10V_4C229 EV@0.1u/10V_4
C_PEG_TXP8
C225 EV@0.1u/10V_4C225 EV@0.1u/10V_4
C_PEG_TXP9
C523 EV@0.1u/10V_4C523 EV@0.1u/10V_4
C_PEG_TXP10
C214 EV@0.1u/10V_4C214 EV@0.1u/10V_4
C_PEG_TXP11
C223 EV@0.1u/10V_4C223 EV@0.1u/10V_4
C_PEG_TXP12
C517 EV@0.1u/10V_4C517 EV@0.1u/10V_4
C_PEG_TXP13
C515 EV@0.1u/10V_4C515 EV@0.1u/10V_4
C_PEG_TXP14
C513 EV@0.1u/10V_4C513 EV@0.1u/10V_4
C_PEG_TXP15
C511 EV@0.1u/10V_4C511 EV@0.1u/10V_4
To HDMI
C209 IV@0.1u/10V_4C209 IV@0.1u/10V_4
C208 IV@0.1u/10V_4C208 IV@0.1u/10V_4
C213 IV@0.1u/10V_4C213 IV@0.1u/10V_4
C212 IV@0.1u/10V_4C212 IV@0.1u/10V_4
C211 IV@0.1u/10V_4C211 IV@0.1u/10V_4
C210 IV@0.1u/10V_4C210 IV@0.1u/10V_4
C204 IV@0.1u/10V_4C204 IV@0.1u/10V_4
C203 IV@0.1u/10V_4C203 IV@0.1u/10V_4
R191 EV@0_4R191 EV@0_4
R205 IV@0_4R205 IV@0_4
R190 EV@0_4R190 EV@0_4
R204 IV@0_4R204 IV@0_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
1
+VCC_PEG
PEG_RXN0 (19)
PEG_RXN2 (19)
PEG_RXN3 (19)
PEG_RXN4 (19)
PEG_RXN5 (19)
PEG_RXN6 (19)
PEG_RXN7 (19)
PEG_RXN8 (19)
PEG_RXN9 (19)
PEG_RXN10 (19)
PEG_RXN11 (19)
PEG_RXN12 (19)
PEG_RXN13 (19)
PEG_RXN14 (19)
PEG_RXN15 (19)
PEG_RXP0 (19)
PEG_RXP2 (19)
PEG_RXP3 (19)
PEG_RXP4 (19)
PEG_RXP5 (19)
PEG_RXP6 (19)
PEG_RXP7 (19)
PEG_RXP8 (19)
PEG_RXP9 (19)
PEG_RXP10 (19)
PEG_RXP11 (19)
PEG_RXP12 (19)
PEG_RXP13 (19)
PEG_RXP14 (19)PEG_RXP14 (19)
PEG_RXP15 (19)
C518 EV@0.1u/10V_4C518 EV@0.1u/10V_4
C509 EV@0.1u/10V_4C509 EV@0.1u/10V_4
C521 EV@0.1u/10V_4C521 EV@0.1u/10V_4
C519 EV@0.1u/10V_4C519 EV@0.1u/10V_4
C525 EV@0.1u/10V_4C525 EV@0.1u/10V_4
C524 EV@0.1u/10V_4C524 EV@0.1u/10V_4
C522 EV@0.1u/10V_4C522 EV@0.1u/10V_4
C520 EV@0.1u/10V_4C520 EV@0.1u/10V_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
PROJECT : BL5S Santa Rosa
PROJECT : BL5S Santa Rosa
GMCH DMI/VIDEO(2 of 7)
GMCH DMI/VIDEO(2 of 7)
GMCH DMI/VIDEO(2 of 7)
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
SDVOB_RED- (20)
SDVOB_RED+ (20)
SDVOB_BLUE- (20)
SDVOB_BLUE+ (20)
SDVOB_GREEN- (20)
SDVOB_GREEN+ (20)
SDVOB_CLK- (20)
SDVOB_CLK+ (20)
PEG_RXN1 (19)
SDVOB_INT- (20)
PEG_RXP1 (19)
SDVOB_INT+ (20)
1
PEG_TXN0 (19)
PEG_TXN1 (19)
PEG_TXN2 (19)
PEG_TXN3 (19)
PEG_TXN4 (19)
PEG_TXN5 (19)
PEG_TXN6 (19)
PEG_TXN7 (19)
PEG_TXN8 (19)
PEG_TXN9 (19)
PEG_TXN10 (19)
PEG_TXN11 (19)
PEG_TXN12 (19)
PEG_TXN13 (19)
PEG_TXN14 (19)
PEG_TXN15 (19)
PEG_TXP0 (19)
PEG_TXP1 (19)
PEG_TXP2 (19)
PEG_TXP3 (19)
PEG_TXP4 (19)
PEG_TXP5 (19)
PEG_TXP6 (19)
PEG_TXP7 (19)
PEG_TXP8 (19)
PEG_TXP9 (19)
PEG_TXP10 (19)
PEG_TXP11 (19)
PEG_TXP12 (19)
PEG_TXP13 (19)
PEG_TXP14 (19)
PEG_TXP15 (19)
637Tuesday, January 22, 2008
637Tuesday, January 22, 2008
637Tuesday, January 22, 2008
of
of
of
1A
1A
1A
5
NB(Memory controller)
4
3
2
1
M_A_DQ[63:0](13)
D D
C C
B B
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BF48
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BD8
AY9
BG10
AW9
BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8
AN10
AT9
AN9
AM9
AN11
U21D
U21D
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
CRESTLINE_1p0
CRESTLINE_1p0
BB19
SA_BS_0
BK19
SA_BS_1
BF29
SA_BS_2
BL17
SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_RAS#
SA_RCVEN#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_WE#
AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6
AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2
BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16
BE18
AY20
BA19
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
TP_SA_RCVEN#
M_A_BS#0 (12,13)
M_A_BS#1 (12,13)
M_A_BS#2 (12,13)
M_A_CAS# (12,13)
M_A_DM[7:0] (13)
M_A_DQS[7:0] (13)
M_A_DQS#[7:0] (13)
M_A_A[13:0] (12,13)
M_A_RAS# (12,13)
T20T20
M_A_WE# (12,13)
M_B_DQ[63:0](13)
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BK5
BK9
BK10
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2
BL9
BL5
BJ8
BJ6
U21E
U21E
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
CRESTLINE_1p0
CRESTLINE_1p0
AY17
SB_BS_0
BG18
SB_BS_1
BG36
SB_BS_2
BE17
SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_RAS#
SB_RCVEN#
SB_WE#
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2
AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3
BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
AV16
AY18
BC17
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
TP_SB_RCVEN#
M_B_BS#0 (12,13)
M_B_BS#1 (12,13)
M_B_BS#2 (12,13)
M_B_CAS# (12,13)
M_B_DM[7:0] (13)
M_B_DQS[7:0] (13)
M_B_DQS#[7:0] (13)
M_B_A[13:0] (12,13)
M_B_RAS# (12,13)
T13T13
M_B_WE# (12,13)
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
PROJECT : BL5S Santa Rosa
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
PROJECT : BL5S Santa Rosa
MCH DDR(3 of 7)
MCH DDR(3 of 7)
MCH DDR(3 of 7)
1
1A
1A
1A
of
of
of
737Tuesday, January 22, 2008
737Tuesday, January 22, 2008
737Tuesday, January 22, 2008
5
4
3
2
1
NB(Power-1)
+1.05V
U21G
U21G
AT35
VCC_1
AT34
VCC_2
AH28
VCC_3
AC32
VCC_5
+1.8VSUS
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32
R30
AU32
AU33
AU35
AV33
AW33
AW35
AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33
AU30
R20
T14
W13
W14
Y12
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
CRESTLINE_1p0
CRESTLINE_1p0
VCC CORE
VCC CORE
POWER
POWER
VCC SMVCC GFX
VCC SMVCC GFX
4
D D
+1.8VSUS
C145
C145
C144
C144
C136
C136
0.1u/10V_4
C C
B B
A A
0.1u/10V_4
+1.8VSUS
C457
C457
*0.1u/10V_4
*0.1u/10V_4
5
22u/10V_8
22u/10V_8
C464
C464
*0.1u/10V_4
*0.1u/10V_4
22u/10V_8
22u/10V_8
+1.05V_VCC_AXG_NCTF
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC GFX NCTF
VCC GFX NCTF
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC SM LF
VCC SM LF
T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31
AW45
BC39
BE39
BD17
BD4
AW8
AT6
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
C71
C71
IV@0.47u/10V_6
IV@0.47u/10V_6
C49
C49
0.1u/10V_4
0.1u/10V_4
+1.05V
+1.05V_VCC_AXG_NCTF
C64
C64
IV@1u/10V_6
IV@1u/10V_6
+1.05V
C87
C87
22u/10V_8
22u/10V_8
C48
C48
0.1u/10V_4
0.1u/10V_4
3
+
+
C442
C442
330u/2.5V_3528
330u/2.5V_3528
C65
C65
IV@10u/10V_8
IV@10u/10V_8
C46
C46
0.22u/6.3V_4
0.22u/6.3V_4
C84
C84
IV@22u/10V_8
IV@22u/10V_8
C112
C112
0.22u/6.3V_4
0.22u/6.3V_4
C139
C139
22u/10V_8
22u/10V_8
C118
C118
0.22u/6.3V_4
0.22u/6.3V_4
C62
C62
0.22u/6.3V_4
0.22u/6.3V_4
C128
C128
0.22u/6.3V_4
0.22u/6.3V_4
C63
C63
IV@0.1u/10V_4
IV@0.1u/10V_4
C124
C124
0.1u/10V_4
0.1u/10V_4
C150
C150
0.47u/10V_6
0.47u/10V_6
C143
C143
0.22u/6.3V_4
0.22u/6.3V_4
R82
R82
IV@0_8
IV@0_8
C70
C70
IV@0.1u/10V_4
IV@0.1u/10V_4
C104
C104
0.1u/10V_4
0.1u/10V_4
C146
C146
1u/10V_6
1u/10V_6
2
+1.05V
C167
C167
1u/10V_6
1u/10V_6
C117
C117
0.1u/10V_4
0.1u/10V_4
R81
R81
IV@0_8
IV@0_8
R74
R74
EV@0_4
EV@0_4
C142
C142
0.1u/10V_4
0.1u/10V_4
U21F
U21F
AB33
VCC_NCTF_1
AB36
VCC_NCTF_2
AB37
VCC_NCTF_3
AC33
VCC_NCTF_4
AC35
VCC_NCTF_5
AC36
VCC_NCTF_6
AD35
VCC_NCTF_7
AD36
VCC_NCTF_8
AF33
VCC_NCTF_9
AF36
VCC_NCTF_10
AH33
VCC_NCTF_11
AH35
VCC_NCTF_12
AH36
VCC_NCTF_13
AH37
VCC_NCTF_14
AJ33
VCC_NCTF_15
AJ35
VCC_NCTF_16
AK33
VCC_NCTF_17
AK35
VCC_NCTF_18
AK36
VCC_NCTF_19
AK37
VCC_NCTF_20
AD33
VCC_NCTF_21
AJ36
VCC_NCTF_22
AM35
VCC_NCTF_23
AL33
VCC_NCTF_24
AL35
VCC_NCTF_25
AA33
VCC_NCTF_26
AA35
VCC_NCTF_27
AA36
VCC_NCTF_28
AP35
VCC_NCTF_29
AP36
VCC_NCTF_30
AR35
VCC_NCTF_31
AR36
VCC_NCTF_32
Y32
VCC_NCTF_33
Y33
VCC_NCTF_34
Y35
VCC_NCTF_35
Y36
VCC_NCTF_36
Y37
VCC_NCTF_37
T30
VCC_NCTF_38
T34
VCC_NCTF_39
T35
VCC_NCTF_40
U29
VCC_NCTF_41
U31
VCC_NCTF_42
U32
VCC_NCTF_43
U33
VCC_NCTF_44
U35
VCC_NCTF_45
U36
VCC_NCTF_46
V32
VCC_NCTF_47
V33
VCC_NCTF_48
V36
VCC_NCTF_49
V37
VCC_NCTF_50
AL24
VCC_AXM_NCTF_1
AL26
VCC_AXM_NCTF_2
AL28
VCC_AXM_NCTF_3
AM26
VCC_AXM_NCTF_4
AM28
VCC_AXM_NCTF_5
AM29
VCC_AXM_NCTF_6
AM31
VCC_AXM_NCTF_7
AM32
VCC_AXM_NCTF_8
AM33
VCC_AXM_NCTF_9
AP29
VCC_AXM_NCTF_10
AP31
VCC_AXM_NCTF_11
AP32
VCC_AXM_NCTF_12
AP33
VCC_AXM_NCTF_13
AL29
VCC_AXM_NCTF_14
AL31
VCC_AXM_NCTF_15
AL32
VCC_AXM_NCTF_16
AR31
VCC_AXM_NCTF_17
AR32
VCC_AXM_NCTF_18
AR33
VCC_AXM_NCTF_19
CRESTLINE_1p0
CRESTLINE_1p0
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
GMCH Power-1(4 of 7)
GMCH Power-1(4 of 7)
GMCH Power-1(4 of 7)
Date: Sheet
Date: Sheet
Date: Sheet
VCC NCTF
VCC NCTF
POWER
POWER
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
PROJECT : BL5S Santa Rosa
PROJECT : BL5S Santa Rosa
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS NCTF
VSS NCTF
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS SCBVCC AXM
VSS SCBVCC AXM
VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7
VCC AXM NCTF
VCC AXM NCTF
1
VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6
T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28
A3
B2
C1
BL1
BL51
A51
+1.05V
AT33
AT31
AK29
AK24
AK23
AJ26
AJ23
of
of
of
837Tuesday, January 22, 2008
837Tuesday, January 22, 2008
837Tuesday, January 22, 2008
1A
1A
1A
5
NB(Power-2)
L13 IV@10uh_8L13 IV@10uh_8
+1.25V
D D
+1.25V
C C
IV@PBY160808T-301Y-N_6
IV@PBY160808T-301Y-N_6
+3V
B B
C500
C500
IV@220u/6.3V_7343
IV@220u/6.3V_7343
L15 IV@10uh_8L15 IV@10uh_8
C504
C504
IV@220u/6.3V_7343
IV@220u/6.3V_7343
R135 EV@0_4R135 EV@0_4
R140 EV@0_4R140 EV@0_4
L34
L34
C455
C455
IV@22u/10V_8
IV@22u/10V_8
+1.5V
+
+
+
+
+3V_TV_DAC
C456
C456
IV@10u/10V_8
IV@10u/10V_8
R68 0_6R68 0_6
C178
C178
IV@0.1u/10V_4
IV@0.1u/10V_4
C175
C175
IV@0.1u/10V_4
IV@0.1u/10V_4
+1.25V
C445 22u/10V_8C445 22u/10V_8
+1.25V_VCCA_DPLLA
+1.25V_VCCA_DPLLB
IV&EV Dis/Enable setting
C453
C453
IV@0.1u/10V_4
IV@0.1u/10V_4
C454
C454
IV@0.1u/10V_4
IV@0.1u/10V_4
C461
C461
IV@0.1u/10V_4
IV@0.1u/10V_4
R69 IV@100/F_6R69 IV@100/F_6
L33 PBY160808T-301Y-N_6L33 PBY160808T-301Y-N_6
V1.25M_MPLL_RC
C463
C463
IV@22n/16V_4
IV@22n/16V_4
C462
C462
IV@22n/16V_4
IV@22n/16V_4
C460
C460
IV@22n/16V_4
IV@22n/16V_4
C75
C75
IV@0.1u/10V_4
IV@0.1u/10V_4
IV&EV Dis/Enable setting
L35 IV@PBY160808T-301Y-N_6L35 IV@PBY160808T-301Y-N_6
+3V
+3V_TV_DAC
L32 PBY160808T-301Y-N_6L32 PBY160808T-301Y-N_6
+1.25V
C76
C76
IV@22n/16V_4
IV@22n/16V_4
R427
R427
0.5_6
0.5_6
C444
C444
+
+
100u/6.3V_3528
100u/6.3V_3528
+1.25V
R443
R443
EV@0_4
EV@0_4
<FAE>
INT VGA disable
VCCD_TVDAC still
+1.5V
C443
C443
22u/10V_8
22u/10V_8
C40
C40
0.1u/10V_4
0.1u/10V_4
R37 0_6R37 0_6
R71 0_6R71 0_6
C97
C97
0.1u/10V_4
0.1u/10V_4
C77
C77
IV@1u/10V_6
IV@1u/10V_6
R107 IV@0_6R107 IV@0_6
+3V
C470
C470
IV@22u/10V_8
IV@22u/10V_8
R444 IV@0_6R444 IV@0_6
C45
C45
0.1u/10V_4
0.1u/10V_4
C103
C103
22n/16V_4
22n/16V_4
R77
R77
4
EV@0_4
EV@0_4
+3V_VCCSYNC
C122
C122
IV@0.1u/10V_4
IV@0.1u/10V_4
C472
C472
IV@0.1u/10V_4
IV@0.1u/10V_4
C468
C468
C467
C467
IV@22n/16V_4
IV@22n/16V_4
IV@0.1u/10V_4
IV@0.1u/10V_4
IV&EV Dis/Enable setting
R145 0_8R145 0_8
+3V
C188 0.1u/10V_4C188 0.1u/10V_4
C58
C58
*22u/10V_8
*22u/10V_8
C99
C99
C98
C98
*1u/16V_6
*1u/16V_6
*1u/16V_6
*1u/16V_6
R87 EV@0_4R87 EV@0_4
R84 IV@0_6R84 IV@0_6
R27 0_6R27 0_6
+1.25V
L17 PBY160808T-301Y-N_6L17 PBY160808T-301Y-N_6
+1.25V
+V1.25S_PEGPLL_FB
C197
C197
10u/10V_8
10u/10V_8
R457 IV@0_6R457 IV@0_6
+1.8VSUS
C473
C473
IV@22n/16V_4
IV@22n/16V_4
C61
C61
4.7u/10V_6
4.7u/10V_6
C100
C100
22u/10V_8
22u/10V_8
R105
R105
EV@0_4
EV@0_4
R449
R449
EV@0_4
EV@0_4
R447
R447
EV@0_4
EV@0_4
C491
C491
IV@1000p_4
IV@1000p_4
C193 0.1u/10V_4C193 0.1u/10V_4
C59
C59
22u/10V_8
22u/10V_8
C102
C102
0.1u/10V_4
0.1u/10V_4
+1.25VM_MCH_VCCD_HPLL
C43
C43
0.1u/10V_4
0.1u/10V_4
R149
R149
1_8
1_8
C153
C153
IV@1u/10V_6
IV@1u/10V_6
3
CRT/TV Disable/Enable guideline
EnableBall EnableDisable DisableBall
3.3V GND
VCCA_CRT
VCCD_CRT
1.5V
VCCDQ_CRT
3.3V
VCCA_A_TVO
3.3V
VCCA_B_TVO VCC_SYNC
+3V_VCCA_CRT_DAC
+3V_VCCA_DAC_BG
+1.25V_VCCA_DPLLA
+1.25V_VCCA_DPLLB
+1.25VM_VCCA_HPLL
+1.25VM_VCCA_MPLL
+1.8VSUS_VCC_TX_LVDS
+3V_VCCA_PEG_BG
+1.25V_VCCD_PEG_PLL
+1.25VM_VCCA_SM
C69
C69
1u/10V_6
1u/10V_6
+1.25VM_VCCA_SM_CK
+1.5V_VCCD_CRT
+1.5V_VCCD_TVDAC
+1.5V_VCCD_QDAC
+1.25V_VCCD_PEG_PLL
C180
C180
0.1u/10V_4
0.1u/10V_4
+1.8V_VCCD_LVDS
C482
C482
R455
R455
IV@10u/10V_8
IV@10u/10V_8
EV@0_4
EV@0_4
AW18
AV19
AU19
AU18
AU17
AT22
AT21
AT19
AT18
AT17
AR17
AR16
BC29
BB29
GND
GND
GND
GND
J32
A33
B33
A30
B32
B49
H49
AL2
AM2
A41
B41
K50
K49
U51
C25
B25
C27
B27
B28
A28
M32
L29
N28
AN2
U48
J41
H42
VCCA_C_TVO
VCCD_TVO
VCCABG_DAC
VSSABG_DAC
U21H
U21H
VCCSYNC
VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
VCCA_DAC_BG
VSSA_DAC_BG
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCA_LVDS
VSSA_LVDS
VCCA_PEG_BG
VSSA_PEG_BG
VCCA_PEG_PLL
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2
VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2
VCCD_CRT
VCCD_TVDAC
VCCD_QDAC
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS_1
VCCD_LVDS_2
CRESTLINE_1p0
CRESTLINE_1p0
3.3V
1.5V1.5V
3.3V
GND
3.3V
CRTPLLA PEGA SMTV
CRTPLLA PEGA SMTV
POWER
POWER
A CK A LVDS
A CK A LVDS
D TV/CRTLVDS
D TV/CRTLVDS
D37 PDZ5.6BD37 PDZ5.6B
+1.05V
+3V
GND
1.5V
GND
GND
GND
2 1
VTT
VTT
VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
AXD
AXD
VCC_AXD_6
VCC_AXD_NCTF
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
AXF
AXF
VCC_DMI
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
SM CK
SM CK
VCC_TX_LVDS
VCC_HV_1
VCC_HV_2
HV
HV
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
PEG
PEG
VCC_PEG_5
VCC_RXR_DMI_1
VCC_RXR_DMI_2
DMI
DMI
VTTLF
VTTLF
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTTLF1
VTTLF2
VTTLF3
+1.05V_SD
+1.05V
U13
U12
U11
U9
U8
U7
U5
U3
+1.25V_AXD
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1
AT23
AU28
AU24
AT29
AT25
AT30
AR29
+1.25V_VCC_AXF
B23
B21
A21
+1.25V_VCC_DMI
AJ50
+1.8VSUS_VCC_SM_CK
BK24
BK23
BJ24
BJ23
+1.8VSUS_VCC_TX_LVDS
A43
C40
B40
AD51
W50
W51
V49
V50
AH50
AH51
A7
F2
AH1
C42
C42
0.47u/6.3V_4
0.47u/6.3V_4
R446
R446
10_4
10_4
R453 0_4R453 0_4
2
LVDS Disable/Enable guideline
External VGA with EV@part,Internal VGA with IV@ part
+3V_VCC_HV
C446
C446
0.47u/6.3V_4
0.47u/6.3V_4
Signal
VCCD_LVDS
VCCA_LVDS
VCCTX_LVDS
C47
C47
4.7u/10V_8
4.7u/10V_8
C90
C90
1u/10V_6
1u/10V_6
C82
C82
0.1u/10V_4
0.1u/10V_4
+3V_VCC_HV
If SDVO Disable
LVDS Disable
GND
GND
EXTERNAL INTERNAL
C39
C39
4.7u/10V_8
4.7u/10V_8
R92 0_6R92 0_6
C88
C88
*22u/10V_8
*22u/10V_8
C450
C450
1u/10V_6
1u/10V_6
+VCC_PEG
C448
C448
0.47u/6.3V_4
0.47u/6.3V_4
C480
C480
0.1u/10V_4
0.1u/10V_4
C505
C505
0.1u/10V_4
0.1u/10V_4
C83
C83
22u/10V_8
22u/10V_8
If SDVO enable
LVDS Disable
1.8V
GND
GNDGND
C55
C55
2.2u/10V_8
2.2u/10V_8
R441 0_6R441 0_6
C451
C451
10u/10V_8
10u/10V_8
R467 0_6R467 0_6
R67 1_6R67 1_6
R130
R130
EV@0_4
EV@0_4
C503
C503
10u/10V_8
10u/10V_8
1
If SDVO enable
LVDS enable
1.8V
1.8V
1.8V
C44
C44
0.47u/10V_6
0.47u/10V_6
+1.25V
+1.25V
+1.25V
L7 1uh_8L7 1uh_8
+V1.8_SMCK_RC
IV&EV Dis/Enable setting
L36 IV@1uh_8L36 IV@1uh_8
+
+
C489
C489
C492
C492
IV@220u/6.3V_7343
IV@220u/6.3V_7343
IV@1000p_4
IV@1000p_4
L37 91nHL37 91nH
+
+
C501
C501
220u/6.3V_7343
220u/6.3V_7343
+1.05V
+1.8VSUS
C68 22u/10V_8C68 22u/10V_8
+1.8VSUS
+1.05V
A A
VCCGFPLLOW
R109 IV@10_4R109 IV@10_4
5
4
3
D8 IV@PDZ5.6BD8 IV@PDZ5.6B
21
2
+1.05V+3V_VCCSYNC
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
PROJECT : BL5S Santa Rosa
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT : BL5S Santa Rosa
GMCH Power-2(5 of 7)
GMCH Power-2(5 of 7)
GMCH Power-2(5 of 7)
1
1A
1A
937Tuesday, January 22, 2008
937Tuesday, January 22, 2008
937Tuesday, January 22, 2008
1A
of
of
of
5
4
3
2
1
NB(Power-3)
U21I
U21I
A13
VSS_1
A15
VSS_2
A17
VSS_3
A24
VSS_4
AA21
VSS_5
AA24
VSS_6
AA29
VSS_7
AB20
D D
C C
B B
A A
5
AB23
AB26
AB28
AB31
AC10
AC13
AC3
AC39
AC43
AC47
AD1
AD21
AD26
AD29
AD3
AD41
AD45
AD49
AD5
AD50
AD8
AE10
AE14
AE6
AF20
AF23
AF24
AF31
AG2
AG38
AG43
AG47
AG50
AH3
AH40
AH41
AH7
AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AK31
AK51
AM11
AM13
AM3
AM4
AM41
AM45
AN1
AN38
AN39
AN43
AN5
AN7
AP4
AP48
AP50
AR11
AR2
AR39
AR44
AR47
AR7
AT10
AT14
AT41
AT49
AU1
AU23
AU29
AU3
AU36
AU49
AU51
AV39
AV48
AW1
AW12
AW16
AL1
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
CRESTLINE_1p0
CRESTLINE_1p0
VSS
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41
4
3
U21J
U21J
C46
VSS_199
C50
VSS_200
C7
VSS_201
D13
VSS_202
D24
VSS_203
D3
VSS_204
D32
VSS_205
D39
VSS_206
D45
VSS_207
D49
VSS_208
E10
VSS_209
E16
VSS_210
E24
VSS_211
E28
VSS_212
E32
VSS_213
E47
VSS_214
F19
VSS_215
F36
VSS_216
F4
VSS_217
F40
VSS_218
F50
VSS_219
G1
VSS_220
G13
VSS_221
G16
VSS_222
G19
VSS_223
G24
VSS_224
G28
VSS_225
G29
VSS_226
G33
VSS_227
G42
VSS_228
G45
VSS_229
G48
VSS_230
G8
VSS_231
H24
VSS_232
H28
VSS_233
H4
VSS_234
H45
VSS_235
J11
VSS_236
J16
VSS_237
J2
VSS_238
J24
VSS_239
J28
VSS_240
J33
VSS_241
J35
VSS_242
J39
VSS_243
K12
VSS_245
K47
VSS_246
K8
VSS_247
L1
VSS_248
L17
VSS_249
L20
VSS_250
L24
VSS_251
L28
VSS_252
L3
VSS_253
L33
VSS_254
L49
VSS_255
M28
VSS_256
M42
VSS_257
M46
VSS_258
M49
VSS_259
M5
VSS_260
M50
VSS_261
M9
VSS_262
N11
VSS_263
N14
VSS_264
N17
VSS_265
N29
VSS_266
N32
VSS_267
N36
VSS_268
N39
VSS_269
N44
VSS_270
N49
VSS_271
N7
VSS_272
P19
VSS_273
P2
VSS_274
P23
VSS_275
P3
VSS_276
P50
VSS_277
R49
VSS_278
T39
VSS_279
T43
VSS_280
T47
VSS_281
U41
VSS_282
U45
VSS_283
U50
VSS_284
V2
VSS_285
V3
VSS_286
CRESTLINE_1p0
CRESTLINE_1p0
VSS
VSS
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28
AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
PROJECT : BL5S Santa Rosa
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
PROJECT : BL5S Santa Rosa
GMCH Power-3(6 of 7)
GMCH Power-3(6 of 7)
GMCH Power-3(6 of 7)
1
1A
1A
1A
of
of
of
10 37Tuesday, January 22, 2008
10 37Tuesday, January 22, 2008
10 37Tuesday, January 22, 2008
5
4
3
2
1
Strap table
All strap are sampled with respect to the leading edge of the GMCH Power OK(PWROK) Signal
CFG[17:3] Have internal Pull-up
CFG[18:19] Have internal Pull-down
Any CFG signal strapping option not list below should be left NC Pin
Pin Name Strap description
D D
CFG[2:0]
CFG[4:3]
CFG5
CFG6
CFG7
CFG8
CFG9
CFG[11:10]
C C
CFG[13:12]
CFG[15:14]
CFG16
CFG[18:17]
SDVO_CTRLDATA
CFG19
CFG20
B B
DMI X2 Select
MCH_CFG_5 Low = DMIX2
High = IDMIX4(Default)
FSB Dynamic ODT
MCH_CFG_16 Low = ODT Disable
A A
MCH_CFG_16(6)
High = ODT Enable(Default)
5
FSB Frequency Select
Reserved
DMI X2 Select
Reserved
CPU Strap
Low power PCI Express
PCI Express Graphics Lane Reversal
Reserved
XOR/ALLZ
Reserved
FSB Dynamic ODT
Reserved
SDVO Present
DMI Lane Reversal
SDVO/PCIe concurrent
DMI Lane Reversal
MCH_CFG_19 Low = Normal operation(Default)
R59
R59
*4.02K_4
*4.02K_4
MCH_CFG_19(6)
SDVO/PCIE Concurrent operation
MCH_CFG_20
R53
R53
*4.02K_4
*4.02K_4
MCH_CFG_20(6)
High = Reverse Lane
+3V
R115
R115
*4.02K_4
*4.02K_4
Low = Only SDVO or PCIE X1 is
operational(Default)
High = SDVO andPCIE X1 are operating
simultaneously via the PEG port
+3V
R114
R114
*4.02K_4
*4.02K_4
4
Configuration
010 = FSB 800MHz
011 = FSB 667MHz
0 = DMI X2
1 = DMI X4(Default)
0 = Reserved
1 = Mobile CPU(Default)
0 = Normal mode
1 = Low Power mode
0 = Reverse Lanes
1 = Normal operation(Default)
00 = Reserved
01 = XOR Mode Enable
10 = All-Z Mode Enabled
11 = Normal operation(Default)
0 = Dynamic ODT disable
1 = Dynamic ODT Enable(Default)
0 = No SDVO Card present(Default)
1 = SDVO Card Present
0 = Normal operation(Default)
1 = Reverse Lanes
0 = Only SDVO or PCIE x1 is operation(Default)
1 = SDVO and PCIE x1 are operating simultaneously via the PEG port
XOR /ALLz /Clock Un-gating
MCH_CFG_12MCH_CFG_13 Configuration
0
0
1
1
MCH_CFG_12(6)
MCH_CFG_13(6)
0
1
0
1
3
Clock gating disable
XOR Mode Enable
ALL-z Mode Enable
Normal operation(Default)
R58
R58
*4.02K_4
*4.02K_4
PCI Express Graphics
MCH_CFG_9 Low = Reverse Lane
R60
R60
*4.02K_4
*4.02K_4
High = Normal operation(Default)
MCH_CFG_9(6)MCH_CFG_5(6)
2
R62
R62
*4.02K_4
*4.02K_4
SDVO Present
Strap define at External
DVI control page
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
PROJECT : BL5S Santa Rosa
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT : BL5S Santa Rosa
GMCH Strap(7 of 7)
GMCH Strap(7 of 7)
GMCH Strap(7 of 7)
1
of
of
of
11 37Tuesday, January 22, 2008
11 37Tuesday, January 22, 2008
11 37Tuesday, January 22, 2008
1A
1A
1A
1
DDR2 Dual channel A/B PU
2
3
4
5
6
7
8
A A
DDRII A CHANNEL DDRII B CHANNEL
+SMDDR_VTERM +SMDDR_VTERM
C176
C176
C186
C85
C85
0.1u/10V_4
0.1u/10V_4
B B
C C
D D
C148
C148
0.1u/10V_4
0.1u/10V_4
M_A_BS#2(7,13)
M_A_RAS#(7,13)
M_A_BS#1(7,13)
M_B_BS#0(7,13)
M_B_BS#1(7,13)
C93
C93
0.1u/10V_4
0.1u/10V_4
M_CKE1(6,13)
M_CKE0(6,13)
C189
C189
0.1u/10V_4
0.1u/10V_4
M_A_A3
M_A_A1
M_A_A9
M_A_A5
M_A_A4
M_A_A2
M_A_A11
M_A_A8
M_A_A12
M_B_A10
M_B_A5
M_B_A3
M_B_A0
M_B_A7
M_B_A11
M_B_A8
M_B_A1
M_B_A4
M_B_A2
M_B_A9
M_B_A12
C141
C141
C164
C164
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
RP17 56X2RP17 56X2
1
3
RP22 56X2RP22 56X2
1
3
RP20 56X2RP20 56X2
1
3
RP28 56X2RP28 56X2
1
3
RP25 56X2RP25 56X2
1
3
RP29 56X2RP29 56X2
1
3
RP15 56X2RP15 56X2
1
3
RP14 56X2RP14 56X2
1
3
RP19 56X2RP19 56X2
1
3
RP13 56X2RP13 56X2
1
3
RP21 56X2RP21 56X2
1
3
RP24 56X2RP24 56X2
1
3
RP18 56X2RP18 56X2
1
3
RP26 56X2RP26 56X2
1
3
C89
C89
0.1u/10V_4
0.1u/10V_4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
C96
C96
0.1u/10V_4
0.1u/10V_4
C186
0.1u/10V_4
0.1u/10V_4
+SMDDR_VTERM
+SMDDR_VTERM
0.1u/10V_4
0.1u/10V_4
M_A_A[13..0]
M_B_A[13..0]
C86
C86
0.1u/10V_4
0.1u/10V_4
C177
C177
0.1u/10V_4
0.1u/10V_4
M_A_A[13..0] (7,13)
M_B_A[13..0] (7,13)
C91
C91
0.1u/10V_4
0.1u/10V_4
C190
C160
C160
C92
C92
C111
C187
C187
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
M_A_A7
M_A_A6
M_CKE3(6,13)
M_B_BS#2(7,13)
M_CS#1(6,13)
M_ODT1(6,13)
M_ODT3(6,13)
M_B_CAS#(7,13)
M_A_BS#0(7,13)
M_A_WE#(7,13)
M_A_CAS#(7,13)
M_CS#0(6,13)
M_B_WE#(7,13)
M_CS#3(6,13)
M_CKE4(6,13)
M_ODT2(6,13)
M_B_RAS#(7,13)
M_ODT0(6,13)
M_CS#2(6,13)
M_A_A10
M_A_A0
M_B_A6
M_A_A13
M_B_A13
C111
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
RP23 56X2RP23 56X2
RP30 56X2RP30 56X2
RP6 56X2RP6 56X2
RP7 56X2RP7 56X2
RP16 56X2RP16 56X2
RP12 56X2RP12 56X2
RP11 56X2RP11 56X2
RP10 56X2RP10 56X2
RP27 56X2RP27 56X2
RP9 56X2RP9 56X2
RP5 56X2RP5 56X2
RP8 56X2RP8 56X2
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
C95
C95
0.1u/10V_4
0.1u/10V_4
C166
C166
0.1u/10V_4
0.1u/10V_4
C181
C181
0.1u/10V_4
0.1u/10V_4
+SMDDR_VTERM
C190
0.1u/10V_4
0.1u/10V_4
C140
C140
0.1u/10V_4
0.1u/10V_4
C110
C110
0.1u/10V_4
0.1u/10V_4
C161
C161
0.1u/10V_4
0.1u/10V_4
C179
C179
0.1u/10V_4
0.1u/10V_4
C138
C138
0.1u/10V_4
0.1u/10V_4
Quanta Computer Inc.
Quanta Computer Inc.
M_A_A14(6,13)
M_B_A14(6,13)
1
R128 56_4R128 56_4
R125 56_4R125 56_4
2
+SMDDR_VTERM
3
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
4
5
6
Date: Sheet
Quanta Computer Inc.
PROJECT : BL5S Santa Rosa
PROJECT : BL5S Santa Rosa
PROJECT : BL5S Santa Rosa
DDR RES. ARRAY
DDR RES. ARRAY
DDR RES. ARRAY
7
1A
1A
1A
of
of
of
12 37Tuesday, January 22, 2008
12 37Tuesday, January 22, 2008
12 37Tuesday, January 22, 2008
8
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