5
4
3
2
1
PCB STACK UP
LAYER 1 : TOP
LAYER 2 : GND
LAYER 3 : IN1
LAYER 4 : SVCC
LAYER 5 : IN2
D D
LAYER 6 : IN3
LAYER 7 : GND
LAYER 8 : BOT
Transformer
Page 26
RJ45
Page 26
DDRIII-SODIMM1
DDRIII-SODIMM2
Page 10,11
X'TAL
25MHz
Atheros
10/100M
AR8162B
Page 26
WLAN Con.
Page 28
BD9 FT3 Kabini Block Diagram
Single Channel DDR III
800~1866 MHZ
PCIe-0
PCIe-1
PCI-Express
APU
Kabini APU 25W/15W
SoC
Port 0
RTD2136R
For support PRD 1600x900
Port 1
Page 24
LVDS CONN
LVDS Panel
LVDS CONN
eDP Panel
HDMI CONN
Page 30
Page 30
Page 25
01
24.5mm X 24.5mm
C C
Card Reader Con.
B B
SATA - HDD Con.
SATA - ODD Con.
Support zero power ODD
USB/B
Page 23
USB/B
Page 23
Genesys Logic
GL834L
Page 29Page 29
CCD
Page 30
WLAN
Page 28
Page 31
Page 31
USB2_0
USB2_1
USB2_5
USB2_6
USB2_7
SATA 0
SATA 1
USB 2.0 (Port 0 ~ 9)
BATTERY
Azalia
Conexant
Audio Codec
CX20756-11Z
Port-B
Page 27 Page 27 Page 27
A A
Port-A
HP SPK Con.MIC JACK
Page 27
BGA 769 pin
SATA
USB2.0
+1.5V_RTC
IHDA
USB3.0
LPC
HALL Sensor
PCI-E x4
GFX
USB 3.0 (Port 0 ~ 1)
X'TAL
32.768KHz
X'TAL
48 MHz
SPI
Nuvoton
EC NPCE985L
LED
SPI
Page 8
SPI
K/B Con.FAN
dGPU
Mars/Sun
Pro
29mm X 29mm
Page 12~19,22
USB3_0
USB2_8
USB3_1
USB2_9
Touch Pad /B
Con.
VRAM DDR3-256MB*4
VRAM DDR3-512MB*4
X'TAL
27.0MHz
USB3.0 w/ S&C
USB3.0 w/o S&C
Page 23
Page 23
Page 33
Power /B
Con.
Page 32Page 32Page 32Page 29Page 30Page 7
VRAM DDRIII
Page 20, 21
POWER SYSTEM
ISL88732
TPS51123A
TPS51216RUKR
TPS51211DSCR
ISL62771
Discharge
ISL62881CHRTZ-T
G9661-25ADJF12U
CHARGER
+15V
+3VPCU
+3V_S5
+3V
+5VPCU
+5V_S5
+5V
+SMDDR_VTERM
+SMDDR_VREF
+1.5VSUS
+1.5V_S5
+1.5V
+0.95V_DUAL
+0.95V
+1.8V_S5
+1.8V
+VDD_CORE
+VDDNB_CORE
DISCHARGE
+VGPU_CORE
+1.8V_GPU
+1.5V_GPU
+0.95V_GPU
P34
P35
P36
P37
P38
P39
P40
P41
P34
P35
P36
P37
P38
P39
P40
P41
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
5
4
3
2
Tuesday, December 25, 2012
PROJECT :
Block Diagram
Block Diagram
Block Diagram
BD9
BD9
BD9
1 41
1 41
1
1 41
A1A
A1A
A1A
5
4
3
2
1
02
Table of Contents
D D
C C
PAGE DESCRIPTION
Schematic Block Diagram
1
Power Stage
2
Processor
3 - 8
9
Straps
10
SO-DIMM 1 DDR
11
SO-DIMM 2
12 - 19
Mars/Sun Pro(M2) VGA
20 - 21
VRAM - DDR3 VGA
22
PX5 VGA
23
USB U3B/USB
24
eDP to LVDS(RTD2136R) LDS
HDMI/Touch Screen
25
LAN(1AR8162B) LAN
26
Codec (CX20756-11Z)
27
MINI CARD (WLAN)
28
29
CARD READER(GL834L)/LED MMC/LED
30
LDS/CRT/CCD
HDD/ODD
31
32
KB/TouchPad
33
EC 985L
Charger (ISL88731CHRTZ-T)
34
System 5V/3V
35
DDR 1.5V
36
+0.95V_DUAL
37
+VCC_CORE
38
Discharge
39
40
GPU_CORE
41
+0.95V_GPU/+1.8V_GPU/+1.5V_GPU/+3V_GPU
GND PLANE PAGE
B B
GND_SIGNAL
8769GND
BOI-FUNCTION
CPU
CPU
DDR
HDM/TSN
ADO
MNW
LDS/CRT/CCD
HDD/ODD
KBC/TPD
KBC
CHR
PWM
PWM
PWM
PWM
PWM
PWM
PWM
POWER PLANE
VIN
+VCCRTC
+3V
+3V_S5
+3VPCU
+5V
+5V_S5
+5VPCU
+WIMAX_P
+1.5VSUS
+1.5V
VOLTAGE
10V~+19V
+1.5V
+3.3V
+3.3V
+3.3V
+5V
+5V
+5V
+3.3V
+1.5V SUSON
+1.5V
MAIND
S5_ON
MAIND S0
S5_ON S0~S5
AC/DC Insert enable
IOAC_EN
MAIND
CONTROL
SIGNAL
Power States
+1.8V_S5 +1.8V PE_PWRGD ^ PE_GPIO1 S0~S5
+0.95V_DUAL
+0.95V +0.95V_DUAL_EN
+0.95V+0.95V MAIND
+VDD_CORE
~
VRON
+VDDNB_CORE ~ VRON S0
+VGPU_CORE
+1.8V_GPU
+1.8V
+0.95V_GPU +0.95V
+3V_GPU
+1.5V_GPU
+3.3V
+1.5V GPU_MAIND
GPU_MAINON ^ PE_GPIO1
GPU_MAIND
GPU_MAINON ^ PE_GPIO1
GPU_MAIND S0
ACTIVE IN
S0~S5
S0~S5
S0
S0~S5
S0~S5AC/DC Insert enable
S0~S5
S0
S0~S3
S0
S0~S5
S0
S0
S0
S0
S0
S0
GND ALL
ADOGND
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
POWER STAGE & BOI-FUNCTION
POWER STAGE & BOI-FUNCTION
POWER STAGE & BOI-FUNCTION
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
5
4
3
2
Tuesday, December 25, 2012
PROJECT :
1
BD9
BD9
BD9
2 41
2 41
2 41
A1A
A1A
A1A
5
4
3
2
1
Coupling Caps Note:
U22B
D D
PCIe-LAN
PCIe-WLAN
PCIE_RXP_LAN[26]
PCIE_RXN_LAN[26]
PCIE_RXP_WLAN[28]
PCIE_RXN_WLAN[28]
+0.95V +0.95V
R109 1.69K/F_4
PCIE_RXP_LAN
PCIE_RXN_LAN
PCIE_RXP_WLAN
PCIE_RXN_WLAN
P_TX_ZVDD P_RX_ZVDD
R10
N10
R8
R5
R4
N5
N4
N8
W8
P_GPP_RXP0
P_GPP_RXN0
P_GPP_RXP1
P_GPP_RXN1
P_GPP_RXP2
P_GPP_RXN2
P_GPP_RXP3
P_GPP_RXN3
P_TX_ZVDD_095
PCIE
L2
P_GPP_TXP0
P_GPP_TXN0
P_GPP_TXP1
P_GPP_TXN1
P_GPP_TXP2
P_GPP_TXN2
P_GPP_TXP3
P_GPP_TXN3
P_RX_ZVDD_095
PCIE_TXP_LAN_C
L1
PCIE_TXN_LAN_C
K2
PCIE_TXP_WLAN_C
K1
PCIE_TXN_WLAN_C
J2
J1
H2
H1
W7
X5R is required.
C624 LAN@0.1U/10V_4X
C622 0.1U/10V_4X
R104 1K/F_4
C621 LAN@0.1U/10V_4X
C620 0.1U/10V_4X
PCIE_TXP_LAN
PCIE_TXN_LAN
PCIE_TXP_WLAN
PCIE_TXN_WLAN
PCIE_TXP_LAN [26]
PCIE_TXN_LAN [26]
PCIE_TXP_WLAN [28]
PCIE_TXN_WLAN [28]
PCIe-LAN
PCIe-WLAN
03
PEG_RXP0[12]
PEG_RXN0[12]
PEG_RXP1[12]
PEG_RXN1[12]
PEG_RXP2[12]
PEG_RXN2[12]
C C
APU_TRST#[5]
B B
PEG_RXP3[12]
PEG_RXN3[12]
PEG_RXP0
PEG_RXN0
PEG_RXP1
PEG_RXN1
PEG_RXP2
PEG_RXN2
PEG_RXP3
PEG_RXN3
+1.8V
R41
*DEBUG@1K_4
R47 DEBUG@0_4
R53 DEBUG@10K_4
R55 DEBUG@10K_4
R62 DEBUG@10K_4
L5
P_GFX_RXP0
L4
P_GFX_RXN0
J5
P_GFX_RXP1
J4
P_GFX_RXN1
G5
P_GFX_RXP2
G4
P_GFX_RXN2
D7
P_GFX_RXP3
E7
P_GFX_RXN3
FT3 REV 0.53
HDT+ Connector
+1.8V
SPEC X with CHECK LIST
J1
1
CPU_VDDIO1
3
GND1
5
GND2
7
GND3
9
CPU_TRST_L
11
CPU_DBRDY3
13
CPU_DBRDY2
15
CPU_DBRDY1
17
GND4
19
CPU_VDDIO2
*DEBUG@HDT+ HEADER
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TDO
CPU_PWROK_BUF
CPU_RST_L_BUF
CPU_DBRDY0
CPU_DBREQ_L
CPU_PLLTEST0
CPU_PLLTEST1
P_GFX_TXP0
P_GFX_TXN0
P_GFX_TXP1
P_GFX_TXN1
P_GFX_TXP2
P_GFX_TXN2
P_GFX_TXP3
P_GFX_TXN3
FT3
G2
PEG_TXP0_C
G1
PEG_TXN0_C
F2
PEG_TXP1_C
F1
PEG_TXN1_C
E2
PEG_TXP2_C
E1
PEG_TXN2_C
D2
PEG_TXP3_C
D1
2
APU_TCK
4
APU_TMS
6
APU_TDI
8
APU_TDO
10
APU_PWROK_BUFAPU_TRST#
12
APU_RST_L_BUF
14
APU_DBRDY
16
DBREQ#
18
APU_TEST19_PLLTEST0
20
APU_TEST18_PLLTEST1
C619 EV@0.1U/10V_4X
C618 EV@0.1U/10V_4X
C615 EV@0.1U/10V_4X
C614 EV@0.1U/10V_4X
R64 *DEBUG/EVB@0_4
C617 EV@0.1U/10V_4X
C616 EV@0.1U/10V_4X
C613 EV@0.1U/10V_4X
C612 EV@0.1U/10V_4X
APU_TCK [5]
APU_TMS [5]
APU_TDI [5]
APU_TDO [5]
APU_DBRDY [5]
APU_DBREQ#
APU_TEST19_PLLTEST0 [5]
APU_TEST18_PLLTEST1 [5]
PEG_TXP0
PEG_TXN0
PEG_TXP1
PEG_TXN1
PEG_TXP2
PEG_TXN2
PEG_TXP3
PEG_TXN3PEG_TXN3_C
APU_DBREQ# [5]
PEG_TXP0 [12]
PEG_TXN0 [12]
PEG_TXP1 [12]
PEG_TXN1 [12]
PEG_TXP2 [12]
PEG_TXN2 [12]
PEG_TXP3 [12]
PEG_TXN3 [12]
PEG X 4
Debug only
R600 *0_4
Debug only
U3
APU_RST#[5]
APU_PWRGD[5]
A A
APU_PWRGD
C21
*DEBUG@0.1U/10V_4X
1
A1
2
GND
3
A2
*DEBUG@74LVC2G07
R601 *0_4
VCC
6
Y1
5
4
Y2
C26 *E@1000P/50V_4X
APU_RST_L_BUFAPU_RST#
+1.8V
APU_PWROK_BUF
C23
*DEBUG@0.1U/10V_4X
R28 *DEBUG@1K_4
R25 *DEBUG@1K_4
C20
*E@1000P/50V_4X
+1.8V
RevB 1221 Add 0 ohm for debug
5
4
3
2
Close by HDT+ Conector
APU_TDI
APU_TCK
APU_TMS
APU_DBREQ#
C44
*DEBUG@0.1U/10V_4X
R387 *DEBUG@1K_4
R389 *DEBUG@1K_4
R388 *DEBUG@1K_4
R69 *DEBUG@1K_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
Tuesday, December 25, 2012
PROJECT :
APU 1/6(PCIE/GPP)
APU 1/6(PCIE/GPP)
APU 1/6(PCIE/GPP)
+1.8V
1
BD9
BD9
BD9
3 41
3 41
3 41
A1A
A1A
A1A
5
4
3
2
1
04
D D
M_A_A[15:0][10,11]
M_A_BS#[2..0][10,11]
M_A_DM[7..0][10,11]
C C
+1.5VSUS
R113
1K/F_4
B B
M_A_EVENT#[10,11]
+1.5VSUS
R459
1K/F_4
+MEMVREF_CPU
+APU_M_VREFDQ_SUS
R460
1K/F_4
A A
C630
0.47U/6.3V_4X
C631
0.1U/10V_4X
C628
1U/6.3V_4X
C775
39P/50V_4N
RevB 1221 Add cap
M_A_A[15:0]
M_A_BS#[2:0]
M_A_DM[7:0]
M_A_DQSP0[10,11]
M_A_DQSN0[10,11]
M_A_DQSP1[10,11]
M_A_DQSN1[10,11]
M_A_DQSP2[10,11]
M_A_DQSN2[10,11]
M_A_DQSP3[10,11]
M_A_DQSN3[10,11]
M_A_DQSP4[10,11]
M_A_DQSN4[10,11]
M_A_DQSP5[10,11]
M_A_DQSN5[10,11]
M_A_DQSP6[10,11]
M_A_DQSN6[10,11]
M_A_DQSP7[10,11]
M_A_DQSN7[10,11]
+MEMVREF_CPU
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_BS#0
M_A_BS#1
M_A_BS#2
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
TP40
M_A_DQSP0
M_A_DQSN0
M_A_DQSP1
M_A_DQSN1
M_A_DQSP2
M_A_DQSN2
M_A_DQSP3
M_A_DQSN3
M_A_DQSP4
M_A_DQSN4
M_A_DQSP5
M_A_DQSN5
M_A_DQSP6
M_A_DQSN6
M_A_DQSP7
M_A_DQSN7
M_A_CLKP0[10]
M_A_CLKN0[10]
M_A_CLKP1[10]
M_A_CLKN1[10]
M_A_CLKP2[11]
M_A_CLKN2[11]
M_A_CLKP3[11]
M_A_CLKN3[11]
M_A_RST#[10,11]
M_A_CKE0[10]
M_A_CKE1[10]
M_A_CKE2[11]
M_A_CKE3[11]
M_A_ODT0[10]
M_A_ODT1[10]
M_A_ODT2[11]
M_A_ODT3[11]
M_A_CS#0[10]
M_A_CS#1[10]
M_A_CS#2[11]
M_A_CS#3[11]
M_A_RAS#[10,11]
M_A_CAS#[10,11]
M_A_WE#[10,11]
M_A_CLKP0
M_A_CLKN0
M_A_CLKP1
M_A_CLKN1
M_A_CLKP2
M_A_CLKN2
M_A_CLKP3
M_A_CLKN3
M_A_RST#
M_A_EVENT#
M_A_CKE0
M_A_CKE1
M_A_CKE2
M_A_CKE3
M_A_ODT0
M_A_ODT1
M_A_ODT2
M_A_ODT3
M_A_CS#0
M_A_CS#1
M_A_CS#2
M_A_CS#3
M_A_RAS#
M_A_CAS#
M_A_WE#
C625
*1U/10V_4X
AG38
W35
W38
W34
U38
U37
U34
R35
R38
N38
AG34
R34
N37
AN34
L38
L35
AJ38
AG35
N34
B32
B38
G40
N41
AG40
AN41
AY40
AY34
Y40
B33
A33
B40
A40
H41
H40
P41
P40
AH41
AH40
AP41
AP40
BA40
AY41
AY33
BA34
AA40
Y41
AC35
AC34
AA34
AA32
AE38
AE37
AA37
AA38
G38
AE34
L34
J38
J37
J34
AN38
AU38
AN37
AR37
AJ34
AR38
AL38
AN35
AJ37
AL34
AL35
AD40
AC38
C626
*100P/50V_4N
U22A
M_ADD0
M_ADD1
M_ADD2
M_ADD3
M_ADD4
M_ADD5
M_ADD6
M_ADD7
M_ADD8
M_ADD9
M_ADD10
M_ADD11
M_ADD12
M_ADD13
M_ADD14
M_ADD15
M_BANK0
M_BANK1
M_BANK2
M_DM0
M_DM1
M_DM2
M_DM3
M_DM4
M_DM5
M_DM6
M_DM7
M_DM8
M_DQS_H0
M_DQS_L0
M_DQS_H1
M_DQS_L1
M_DQS_H2
M_DQS_L2
M_DQS_H3
M_DQS_L3
M_DQS_H4
M_DQS_L4
M_DQS_H5
M_DQS_L5
M_DQS_H6
M_DQS_L6
M_DQS_H7
M_DQS_L7
M_DQS_H8
M_DQS_L8
M_CLK_H0
M_CLK_L0
M_CLK_H1
M_CLK_L1
M_CLK_H2
M_CLK_L2
M_CLK_H3
M_CLK_L3
M_RESET_L
M_EVENT_L
M0_CKE0
M0_CKE1
M1_CKE0
M1_CKE1
M0_ODT0
M0_ODT1
M1_ODT0
M1_ODT1
M0_CS_L0
M0_CS_L1
M1_CS_L0
M1_CS_L1
M_RAS_L
M_CAS_L
M_WE_L
M_VREF
M_VREFDQ
MEMORY
FT3 REV 0.53
M_DATA0
M_DATA1
M_DATA2
M_DATA3
M_DATA4
M_DATA5
M_DATA6
M_DATA7
M_DATA8
M_DATA9
M_DATA10
M_DATA11
M_DATA12
M_DATA13
M_DATA14
M_DATA15
M_DATA16
M_DATA17
M_DATA18
M_DATA19
M_DATA20
M_DATA21
M_DATA22
M_DATA23
M_DATA24
M_DATA25
M_DATA26
M_DATA27
M_DATA28
M_DATA29
M_DATA30
M_DATA31
M_DATA32
M_DATA33
M_DATA34
M_DATA35
M_DATA36
M_DATA37
M_DATA38
M_DATA39
M_DATA40
M_DATA41
M_DATA42
M_DATA43
M_DATA44
M_DATA45
M_DATA46
M_DATA47
M_DATA48
M_DATA49
M_DATA50
M_DATA51
M_DATA52
M_DATA53
M_DATA54
M_DATA55
M_DATA56
M_DATA57
M_DATA58
M_DATA59
M_DATA60
M_DATA61
M_DATA62
M_DATA63
M_CHECK0
M_CHECK1
M_CHECK2
M_CHECK3
M_CHECK4
M_CHECK5
M_CHECK6
M_CHECK7
M_ZVDDIO_MEM_S
B30
M_A_DQ0
A32
M_A_DQ1
B35
M_A_DQ2
A36
M_A_DQ3
B29
M_A_DQ4
A30
M_A_DQ5
A34
M_A_DQ6
B34
M_A_DQ7
B37
M_A_DQ8
A38
M_A_DQ9
D40
M_A_DQ10
D41
M_A_DQ11
B36
M_A_DQ12
A37
M_A_DQ13
B41
M_A_DQ14
C40
M_A_DQ15
F40
M_A_DQ16
F41
M_A_DQ17
K40
M_A_DQ18
K41
M_A_DQ19
E40
M_A_DQ20
E41
M_A_DQ21
J40
M_A_DQ22
J41
M_A_DQ23
M41
M_A_DQ24
N40
M_A_DQ25
T41
M_A_DQ26
U40
M_A_DQ27
L40
M_A_DQ28
M40
M_A_DQ29
R40
M_A_DQ30
T40
M_A_DQ31
AF40
M_A_DQ32
AF41
M_A_DQ33
AK40
M_A_DQ34
AK41
M_A_DQ35
AE40
M_A_DQ36
AE41
M_A_DQ37
AJ40
M_A_DQ38
AJ41
M_A_DQ39
AM41
M_A_DQ40
AN40
M_A_DQ41
AT41
M_A_DQ42
AU40
M_A_DQ43
AL40
M_A_DQ44
AM40
M_A_DQ45
AR40
M_A_DQ46
AT40
M_A_DQ47
AV41
M_A_DQ48
AW40
M_A_DQ49
BA38
M_A_DQ50
AY37
M_A_DQ51
AU41
M_A_DQ52
AV40
M_A_DQ53
AY39
M_A_DQ54
AY38
M_A_DQ55
BA36
M_A_DQ56
AY35
M_A_DQ57
BA32
M_A_DQ58
AY31
M_A_DQ59
BA37
M_A_DQ60
AY36
M_A_DQ61
BA33
M_A_DQ62
AY32
M_A_DQ63
V41
W40
AB40
AC40
U41
V40
AA41
AB41
AD41
+M_ZVDDIO
Place close to APU within 1"
FT3
M_A_DQ[63:0]
+1.5VSUS
R45839.2/F_4
M_A_DQ[63:0] [10,11]
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
5
4
3
2
Tuesday, December 25, 2012
PROJECT :
APU 2/6(DDR3 MEM)
APU 2/6(DDR3 MEM)
APU 2/6(DDR3 MEM)
BD9
BD9
BD9
A1A
A1A
4 41
4 41
1
4 41
A1A
5
4
3
2
1
U22C
DISPLAY/SVI2/JTAG/TEST
TDP1_TXP0
TDP1_TXN0
TDP1_TXP1
TDP1_TXN1
TDP1_TXP2
TDP1_TXN2
TDP1_TXP3
TDP1_TXN3
LTDP0_TXP0
LTDP0_TXN0
LTDP0_TXP1
LTDP0_TXN1
LTDP0_TXP2
LTDP0_TXN2
LTDP0_TXP3
LTDP0_TXN3
DISP_CLKIN_H
DISP_CLKIN_L
+1.8V
SVT
+1.8V
SVC
+1.8V
SVD
+3V
SIC
+3V
SID
APU_RST_L
LDT_RST_L
APU_PWROK
LDT_PWROK
+3V
PROCHOT_L
+3V
ALERT_L
+1.8V
TDI
+1.8V
TDO
+1.8V
TCK
+1.8V
TMS
+1.8V
TRST_L
+1.8V
DBRDY
+1.8V
DBREQ_L
VDDCR_NB_SENSE
VDDCR_CPU_SENSE
VDDIO_MEM_S_SENSE
VSS_SENSE
VDD_095_FB_H
VDD_095_FB_L
FT3 REV 0.53
Read APU Temperature
+3V
5
Q25B 2N7002KDW_115MA
3 4
R412 *0_4
Q25A
2
6
R406 *0_4
DP_150_ZVSS
DP_2K_ZVSS
+3V
DP_BLON
+3V
DP_DIGON
+3V
DP_VARY_BL
+3V
TDP1_AUXP
+3V
TDP1_AUXN
+3V
TDP1_HPD
+3V
LTDP0_AUXP
+3V
LTDP0_AUXN
+3V
LTDP0_HPD
DAC_RED
DAC_GREEN
DAC_BLUE
+3V
DAC_HSYNC
+3V
DAC_VSYNC
+3V
DAC_SCL
+3V
DAC_SDA
DAC_ZVSS
TEST4
TEST5
TEST6
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST31
RSVD
TEST36
TEST37
TEST42
TEST43
TEST39
TEST40
TEST41
DP_STEREOSYNC
FT3
APU_SIC2ND_MBCLK
2N7002KDW _115MA
1
B16
DP_150_ZVSS
A21
DP_2K_ZVSS
B17
APU_BLON
A17
APU_DIGON
A18
APU_VARY_BL
D17
INT_HDMI_AUXP
E17
INT_HDMI_AUXN
H19
INT_HDMI_HPD
D15
INT_LVDS_AUXP_C
E15
INT_LVDS_AUXN_C
H17
INT_LVDS_HPD_Q
B14
APU_CRT_RED
A14
APU_CRT_GRE
B15
APU_CRT_BLU
G19
APU_CRT_HSYNC
E19
APU_CRT_VSYNC
D19
APU_DDCCLK
D21
APU_DDCDAT
A16
DAC_ZVSS
H27
APU_TEST4
H29
APU_TEST5
D25
APU_TEST6
A27
APU_TEST14
B27
APU_TEST15
A26
APU_TEST16
B26
APU_TEST17
B28
APU_TEST18_PLLTEST1
A28
APU_TEST19_PLLTEST0
B24
APU_TEST25_H
A24
APU_TEST25_L
AV35
APU_TEST28_H
AU35
APU_TEST28_L
E33
APU_TEST31
A29
APU_TEST34
H21
APU_TEST36
H25
APU_TEST37
AJ10
APU_TEST42
AJ8
APU_TEST43
R32
APU_TEST39
N32
APU_TEST40
AP29
APU_TEST41
E21
DP_STEREOSYNC
+3V
R410
1K_4
R409
1K_4
3
R442 150/F_4
1 2
R434 2K/F_4
C42 0.1U/10V_4X
C43 0.1U/10V_4X
R433 499/F_4
R63 1K_4
APU_BL_EN [30]
APU_DIGON [30]
APU_VARY_BL [24,30]
INT_HDMI_AUXP [25]
INT_HDMI_AUXN [25]
INT_HDMI_HPD [25]
INT_LVDS_AUXP
INT_LVDS_AUXN
APU_CRT_RED [30]
APU_CRT_GRE [30]
APU_CRT_BLU [30]
APU_CRT_HSYNC [30]
APU_CRT_VSYNC [30]
APU_DDCCLK [30]
APU_DDCDAT [30]
TP10
TP13
TP8
TP4
TP7
TP5
TP1
APU_TEST18_PLLTEST1 [3]
APU_TEST19_PLLTEST0 [3]
TP3
TP2
TP32
TP29
TP9
TP6
TP12
TP14
TP22
TP21
TP16
TP15
TP31
APU_PWRGD CPU_PWRGD_SVID_REG
SVC SVD BOOT VOLTAGE
000
1
0
111
R42
*1K_4
1.1
1.0
0.9
0.8
LVDS Back Light Control
HDMI AUX
INT_LVDS_AUXP [24]
INT_LVDS_AUXN [24]
layout trace
reference GND
+1.8V
R48
R49
*1K_4
*1K_4
R36 0_4
R44 0_4
Re
R43 0_4
Rf
R424 0_4
Rg
2
EDID PU 4.7K +3.3V @ Conn
eDP to LVDS Translator
R place close to APU
APU_CRT_RED
APU_CRT_GRE
APU_CRT_BLU
INT_LVDS_HPD_Q
Note:
To override VID,Remove Rd,Re, Rf, Rg, install Rc
set VID via SVC & SVD option RES Ra, Rb
Ra RbRdRc
R38
*220_4
R441 150/F_4
R440 150/F_4
R439 150/F_4
+3V
R401
LDS@1K_4
34
LDS@2N7002KDW_115MA
5
Q22B
APU_TEST14
APU_TEST16
APU_TEST17
APU_TEST18_PLLTEST1
APU_TEST19_PLLTEST0
APU_TEST25_H
APU_TEST36
APU_TEST25_L
APU_TEST37
APU_SVTSVT
APU_SVCSVC
APU_SVDSVD
R423
R37
*220_4
*220_4
+5V
R394
LDS@10K_4
6
LDS@2N7002KDW_115MA
2
Q21A
1
R392 eDP@0_4
R60 *1K_4
R59 *1K_4
R50 *1K_4
R79 1K_4
R78 1K_4
R58 510/F_4
R57 *1K_4
R56 *1K_4
R46 510/F_4
R95 *1K_4
R103 *1K_4
C586
*0.1U/10V_4X
INT_LVDS_HPD
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
Tuesday, December 25, 2012
INT_HDMI_AUXP
INT_HDMI_AUXN
INT_LVDS_AUXP_C
INT_LVDS_AUXN_C
INT_LVDS_AUXP_C
INT_LVDS_AUXN_C
R94 *1.8K_4
R96 *1.8K_4
R65 1.8K_4
R70 1.8K_4
R66 *eDP@100K_4
R71 *eDP@100K_4
For eDP Panel
INT_LVDS_HPD [24,30]
R396
100K_4
RevB 1219 Change HDMI strap setting
from PD to PU for HDMI No display issue
+1.8V
APU_CRT_HSYNC
APU_SVT [38]
APU_SVC [38]
APU_SVD [38]
CPU_PWRGD_SVID_REG [38]
APU 3/6(DP/SVI2/JTAG/Test)
APU 3/6(DP/SVI2/JTAG/Test)
APU 3/6(DP/SVI2/JTAG/Test)
+3V
R52
1K_4
R54
*1K_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
AV33
AU33
A9
B9
A10
B10
A11
B11
A12
B12
A4
B4
A5
B5
A6
B6
A7
B7
K15
H15
G31
D27
E29
B22
B21
B20
A20
B19
A19
A22
B18
D29
D31
D35
D33
G27
B25
A25
D23
G23
E25
E23
INT_HDMI_TXDP2[25]
INT_HDMI_TXDN2[25]
INT_HDMI_TXDP1[25]
R427
300_4
C598
150P/50V_4N
INT_HDMI_TXDN1[25]
INT_HDMI_TXDP0[25]
INT_HDMI_TXDN0[25]
INT_HDMI_TXCP[25]
INT_HDMI_TXCN[25]
INT_LVDS_TXP0[24]
INT_LVDS_TXN0[24]
INT_LVDS_TXP1[24]
INT_LVDS_TXN1[24]
INT_LVDS_TXP2[30]
INT_LVDS_TXN2[30]
INT_LVDS_TXP3[30]
INT_LVDS_TXN3[30]
+1.8V +1.8V
R428
300_4
C596
150P/50V_4N
APU_VDDNB_RUN_FB_H[38]
APU_VDD_RUN_FB_H[38]
APU_VDDIO_RUN_FB_H
APU_VDD_RUN_FB_L[38]
D D
LVDS
HDMI
C C
APU_RST#[3]
APU_PWRGD[3]
INT_HDMI_TXDP2
INT_HDMI_TXDN2
INT_HDMI_TXDP1
INT_HDMI_TXDN1
INT_HDMI_TXDP0
INT_HDMI_TXDN0
INT_HDMI_TXCP
INT_HDMI_TXCN
INT_LVDS_TXP0
INT_LVDS_TXN0
INT_LVDS_TXP1
INT_LVDS_TXN1 INT_LVDS_TXN1_C
INT_LVDS_TXP2
INT_LVDS_TXN2
INT_LVDS_TXP3
INT_LVDS_TXN3
C595
*E@0.1U/10V_4X
VDD_095_FB_H
VDD_095_FB_L
C603 HM@0.1U/10V_4X
C602 HM@0.1U/10V_4X
C594 HM@0.1U/10V_4X
C593 HM@0.1U/10V_4X
C601 HM@0.1U/10V_4X
C600 HM@0.1U/10V_4X
C592 HM@0.1U/10V_4X
C591 HM@0.1U/10V_4X
C609 0.1U/10V_4X
C608 0.1U/10V_4X
C607 0.1U/10V_4X
C606 0.1U/10V_4X
C605 eDP@0.1U/10V_4X
C604 eDP@0.1U/10V_4X
C599 eDP@0.1U/10V_4X
C597 eDP@0.1U/10V_4X
R51 1K_4
+3V
R432 1K_4
APU_TDI[3]
APU_TDO[3]
APU_TCK[3]
APU_TMS[3]
APU_TRST#[3]
APU_DBRDY[3]
APU_DBREQ#[3]
APU_VDDNB_RUN_FB_H
APU_VDD_RUN_FB_H
APU_VDDIO_RUN_FB_H
APU_VDD_RUN_FB_L VSS_SENSE
VDD_095_FB_H
VDD_095_FB_L
INT_HDMI_TXDP2_C
INT_HDMI_TXDN2_C
INT_HDMI_TXDP1_C
INT_HDMI_TXDN1_C
INT_HDMI_TXDP0_C
INT_HDMI_TXDN0_C
INT_HDMI_TXCP_C
INT_HDMI_TXCN_C
INT_LVDS_TXP0_C
INT_LVDS_TXN0_C
INT_LVDS_TXP1_C
INT_LVDS_TXP2_C
INT_LVDS_TXN2_C
INT_LVDS_TXP3_C
INT_LVDS_TXN3_C
Reserved for external clock Gen,
leave unconnected.
SVT
SVC
SVD
APU_SIC
APU_SID
APU_RST#
APU_PWRGD
R61 0_4
APU_RST#_R
APU_PWRGD_R
H_PROCHOT
APU_ALERT#
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#
R444 0_4
R435 0_4
1.5V & 0.95V SENSE PIN
TP11
B B
TP33
TP24
APU_VDDIO_RUN_FB_H
VDD_095_FB_H
VDD_095_FB_L
PROC HOT
+3V
H_PROCHOT_EC#[33]
+3V_S5
R34 10K_4
R35 10K_4
2
3
Q7
2N7002K_300MA
1
H_PROCHOT
+3V
2ND_MBCLK[23,33]
2ND_MBDATA[23,33]
2ND_MBDATA APU_SID
2
3
Q6
2N7002K_300MA
5
1
4
+3VPCU
A A
CORE_PWM_PROCHOT#[38]
BD9
BD9
BD9
5 41
5 41
5 41
05
+3V
A1A
A1A
A1A
5
4
3
2
1
06
+1.5VSUS
C103
D D
10U/6.3V_6X
C144
10U/6.3V_6X
C162
180P/50V_4N
+1.5V_S5
R483 0_8
C656
C C
RevB 1219 Change from short pad to mount 0805
+1.8V_S5
1U/6.3V_4X
R82 0_8
C47
*180P/50V_4N
C66
1U/6.3V_4X
C67
1U/6.3V_4X
RevB 1219 Change from short pad to mount 0805
B B
+3VPCU
+VCCRTC_2
R456
10K_4
+BAT
20MIL
12
+0.95V_DUAL
D31
BAT54C-7-F_200MA
CN15
20MIL
20MIL
RTC_VIN
180pF: COG, NP0
Others: X5R
C116
10U/6.3V_6X
C678
1U/10V_4X
C146
180P/50V_4N
C179
C92
0.1U/10V_4X
0.1U/10V_4X
C71
C128
0.1U/10V_4X
0.1U/10V_4X
+APU_VDDIO_AZ_S
C649
1U/6.3V_4X
C655
180P/50V_4N
+APU_VDD18V_S
C56
1U/6.3V_4X
C65
1U/6.3V_4X
C69
1U/6.3V_4X
C68
1U/6.3V_4X
R505 U3@0_8
R108 0_8
+1.5V_RTC_R
NCP698SQ15T1G
1
GND
4
EN
3
VIN2VOUT
U29
R514 1K_4
1.5V level
need a LDO from 3V to 1.5V
W31
W32
W37
AA31
AA35
AC32
AC37
AE31
AE35
AG32
AG37
AJ35
AL32
AL37
AR35
J35
L32
L37
N35
R31
R37
U32
U35
U22F
VDDIO_MEM_S_1
VDDIO_MEM_S_2
VDDIO_MEM_S_3
VDDIO_MEM_S_4
VDDIO_MEM_S_5
VDDIO_MEM_S_6
VDDIO_MEM_S_7
VDDIO_MEM_S_8
VDDIO_MEM_S_9
VDDIO_MEM_S_10
VDDIO_MEM_S_11
VDDIO_MEM_S_12
VDDIO_MEM_S_13
VDDIO_MEM_S_14
VDDIO_MEM_S_15
VDDIO_MEM_S_16
VDDIO_MEM_S_17
VDDIO_MEM_S_18
VDDIO_MEM_S_19
VDDIO_MEM_S_20
VDDIO_MEM_S_21
VDDIO_MEM_S_22
VDDIO_MEM_S_23
C125
180P/50V_4N
C153
0.1U/10V_4X
C139
0.1U/10V_4X
3 A
C165
180P/50V_4N
C109
0.1U/10V_4X
C196
0.1U/10V_4X
0.1 A
C648
C650
1U/6.3V_4X
4.7U/6.3V_6X
0.5 A
C55
4.7U/6.3V_6X
C57
180P/50V_4N
+APU_3V_S
1 A
+VDD_095_USB3_S
0.5 A
+VDD_095_PHY_S
+1.5V_RTC
R140 10K_4
C195
0.22U/10V_4X
RevB 1210 Change P/N to AL000698000
0.2 A
AL10
AL11
AL13
AM13
AR5
AU4
AW5
AE11
AE13
AJ11
AJ13
20MIL
AN4
12
G1
*SHORT_PAD
VDDIO_AZ_ALW_1
VDDIO_AZ_ALW_2
B1
VDD_18_ALW_1
B2
VDD_18_ALW_2
VDD_33_ALW_1
VDD_33_ALW_2
VDD_095_USB3_DUAL_1
VDD_095_USB3_DUAL_2
AV7
VDD_095_USB3_DUAL_3
VDD_095_USB3_DUAL_4
VDD_095_ALW_1
VDD_095_ALW_2
VDD_095_ALW_3
VDD_095_ALW_4
VDDBT_RTC_G
+1.5V_S5
FT3 REV 0.53
POWER
VDDCR_CPU_1
VDDCR_CPU_2
VDDCR_CPU_3
VDDCR_CPU_4
VDDCR_CPU_5
VDDCR_CPU_6
VDDCR_CPU_7
VDDCR_CPU_8
VDDCR_CPU_9
VDDCR_CPU_10
VDDCR_CPU_11
VDDCR_CPU_12
VDDCR_CPU_13
VDDCR_CPU_14
VDDCR_CPU_15
VDDCR_CPU_16
VDDCR_CPU_17
VDDCR_CPU_18
VDDCR_CPU_19
VDDCR_CPU_20
VDDCR_CPU_21
VDDCR_CPU_22
VDDCR_CPU_23
VDDCR_CPU_24
VDDCR_CPU_25
VDDCR_CPU_26
VDDCR_NB_1
VDDCR_NB_2
VDDCR_NB_3
VDDCR_NB_4
VDDCR_NB_5
VDDCR_NB_6
VDDCR_NB_7
VDDCR_NB_8
VDDCR_NB_9
VDDCR_NB_10
VDDCR_NB_11
VDDCR_NB_12
VDDCR_NB_13
VDDCR_NB_14
VDDCR_NB_15
VDDCR_NB_16
VDDCR_NB_17
VDDCR_NB_18
VDDCR_NB_19
VDDCR_NB_20
VDDCR_NB_21
VDD_18_1
VDD_18_2
VDD_18_3
VDD_18_4
VDD_33_1
VDD_33_2
VDD_095_1
VDD_095_2
VDD_095_3
VDD_095_4
VDD_095_5
VDD_095_6
VDD_095_7
VDD_095_8
VDD_095_9
VDD_095_GFX_1
VDD_095_GFX_2
VDD_095_GFX_3
FT3
21 A
L21
L23
L25
L27
L29
N21
N23
N27
R21
R23
R27
U21
U23
U27
W21
W23
W27
AA21
AA23
AA27
AC21
AC23
AC27
AE21
AE23
AE27
17 A
L13
L17
N11
N13
N17
R11
R13
R17
U13
U17
W13
W17
AA13
AA17
AC13
AC17
AE15
AE17
AE19
AG17
AG21
A2
A3
B3
C3
AM15
AM17
AG23
AG27
AJ21
AJ27
AL21
AL23
AL27
AM23
AM25
U10
W10
AA10
1.5 A
0.2 A
+VDDIO_3V
5 A
+VDD_095_GPP
0.6 A
+VDD_095_GFX
C118
EV@1U/6.3V_4X
+VDDIO_18V
RevB 1221 Change EV@
C188
180P/50V_4N
C177
1U/6.3V_4X
C89
C99
10U/6.3V_6X
10U/6.3V_6X
10U/6.3V_6X
C121
C131
1U/6.3V_4X
1U/6.3V_4X
C152
C148
1U/6.3V_4X
1U/6.3V_4X
C95
C104
10U/6.3V_6X
10U/6.3V_6X
C130
1U/6.3V_4X
C168
1U/6.3V_4X
C29
10U/6.3V_6X
C38
1U/6.3V_4X
10U/6.3V_6X
C120
1U/6.3V_4X
C141
1U/6.3V_4X
C36
1U/6.3V_4X
C35
1U/6.3V_4X
RevB 1219 Change from short pad to mount 0805
C94
R117 EV@0_8
C140
+0.95V
C132
1U/6.3V_4X
C115
1U/6.3V_4X
C85
C107
180P/50V_4N
C147
1U/6.3V_4X
C151
1U/6.3V_4X
C79
10U/6.3V_6X
C149
1U/6.3V_4X
C113
1U/6.3V_4X
C39
1U/6.3V_4X
C41
1U/6.3V_4X
C181
1U/6.3V_4X
C155
180P/50V_4N
C169
1U/6.3V_4X
C90
1U/6.3V_4X
+VDDIO_3V
EV@10U/6.3V_6X
+VDD_095_GPP
C174
C658
10U/6.3V_6X
C659
10U/6.3V_6X
1U/6.3V_4X
C178
1U/6.3V_4X
AAA-BAT-054-K01
A A
+3V_S5
+APU_3V_S
+VDD_095_USB3_S
+VDD_095_PHY_S
R488 0_8
C184
1U/6.3V_4X
C176
1U/6.3V_4X
C651
180P/50V_4N
C186
1U/6.3V_4X
C654
1U/6.3V_4X
C197
1U/6.3V_4X
C661
10U/6.3V_6X
C667
10U/6.3V_6X
C105
*10U/6.3V_6X
RevB 1219 Change from short pad to mount 0805
5
4
3
C126
1U/6.3V_4X
C117
1U/6.3V_4X
+VDDNB_CORE
C34
1U/6.3V_4X
C33
180P/50V_4N
C183
1U/6.3V_4X
C163
1U/6.3V_4X
RevB 1219 Change for EODRevB 1219 Change for EOD
+VDD_CORE
C110
1U/6.3V_4X
C170
1U/6.3V_4X
L1
HCB1608KF-181T15_1.5A
C40
1U/6.3V_4X
R473 0_8
C182
180P/50V_4N
C154
1U/6.3V_4X
C156
1U/6.3V_4X
+1.8V
+3V
L29
HCB1608KF-181T15_1.5A
L28
HCB1608KF-181T15_1.5A
C158
1U/6.3V_4X
C172
1U/6.3V_4X
C173
1U/6.3V_4X
2
A8
A13
A23
A31
A35
A39
B8
B13
B23
B31
B39
C1
C2
C5
C7
C9
C11
C13
C15
C17
C19
C21
C23
C25
C27
C29
C31
C33
C35
C37
C39
C41
D9
D11
D13
E3
E4
E9
E11
E13
E27
E31
E35
E38
E39
G3
G7
G11
G13
G15
G17
G21
G25
G29
G35
G37
G39
G41
H11
H13
H23
H31
+0.95V
C157
1U/6.3V_4X
U22G
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
GND
FT3 REV 0.53
U22H
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
J3
J7
J8
J39
K11
K13
K17
K19
K21
K23
K25
K27
K29
K31
L3
L7
L8
L10
L11
L15
L19
L31
L39
L41
M1
M2
N3
N7
N15
N19
N25
N29
N31
N39
P1
P2
R3
R7
R15
R19
R25
R29
R39
R41
U1
U2
U3
U7
U8
U11
U15
U19
U25
U29
U31
U39
W3
W5
W11
W15
W19
W25
W29
W39
W41
AA11
AA15
AA19
AA25
AA29
AA39
AC3
AC7
AC11
AC15
AC19
AC25
AC29
AC31
AC39
AC41
AE25
AE29
AE32
AE39
AG3
AG5
AG10
AG11
AG13
AG15
AG19
AG25
AG29
AG31
AG39
AG41
AH1
AH2
AJ15
AJ17
AJ19
AJ23
AJ25
AJ29
AJ31
AJ32
AJ39
AL15
AL17
AL19
AL25
AL29
Y1
Y2
AA3
AA7
AA8
AE3
AE7
AJ3
AJ7
AL3
AL8
FT3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, December 27, 2012
Date: Sheet of
Thursday, December 27, 2012
Date: Sheet of
Thursday, December 27, 2012
PROJECT :
APU 4/6(POWER/GND/GND)
APU 4/6(POWER/GND/GND)
APU 4/6(POWER/GND/GND)
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
FT3 REV 0.53
1
GND
BD9
BD9
BD9
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSSBG_DAC
VSS_243
VSS_244
FT3
6 41
6 41
6 41
AL39
AL41
AM11
AM27
AM31
AN3
AN7
AN39
AP31
AR3
AR13
AR17
AR21
AR25
AR29
AR39
AR41
AU1
AU2
AU3
AU15
AU19
AU23
AU27
AU39
AV9
AW3
AW7
AW13
AW15
AW17
AW19
AW21
AW23
AW25
AW27
AW31
AW33
AW35
AW37
AW39
AW41
AY13
AY15
AY18
AY30
BA2
BA7
BA13
BA15
BA18
BA21
BA25
BA31
BA35
BA39
A15
AL31
AM29
A1A
A1A
A1A
5
4
3
2
1
+3V_S5
+3V_S5
To PCIE device
LAN, WLAN, Cardreader, GPU
APU_PCIE_RST#[22,26,28]
D D
D7 RB500V-40_100MA
RSMRST_GATE#[33]
C C
+3V_S5
+3V
B B
+3V_S5
RSMRST_GATE#
+1.8V_S5
R218 47K_4
+3V_S5
R508
10K_4
SYS_RST#
12
G3
*SHORT_PAD
R216 *1K_4
R215 *1K_4
R214 *1K_4
NEED TO CHANGE P/N
Debug Only
R189 10K_4
R188 10K_4
R472 10K_4
R203 10K_4
R202 ZRP@10K_4
APU_TEST2
APU_TEST1
APU_TEST0
PCIE_CLKREQ#_LAN
PCIE_CLKREQ#_W LAN
PCIE_CLKREQ#_GPU_R
CLK_REQ3 #
APU_ODD_EN
RevA 1025 Add 10K PU to +3V
R490 10K_4
R180 10K_4
R497 10K_4
R470 10K_4
R468 10K_4
R212 10K_4
R602 10K_4
PWR_BTN#
PCIE_W AKE#
USB_NORMA L_OC#
USB_SC_O C#
ODD_PRSNT#
ODD_MD#
USB_DB_O C#
21
RSMRST#
1U/6.3V_4X
R195 *15K_4
R194 *15K_4
R193 *15K_4
APU_PCIE_RST#
C280
U28
R210 E@0_4
C281
*E@0.1U/10V_4X
R498 *4.7K_4
2
4
1
3 5
*TC7SH08FU(F)
R496 0_4
RSMRST#_R
PCIE_CLKREQ#_GPU[13 ]
USB_NORMA L_OC#[23,33 ]
USB_SC_O C#[23,33]
ODD_PRSNT#[31]
USB_DB_O C#[23,33]
RevA 1025 Add USB_DB_OC#
CLK Source GPP_Clk
GFX_CLKP/N
GFX
GPP_CLK0P/N
Lan
GPP_CLK1P/N
WLan
RevB 1224 Add USB/B OC# Pin PU
D22
D2
2 1
2 1
<THM>
40 MIL
40 MIL
40 MIL40 MIL
C54 2.2U/6.3V_4X
VFAN1[33]
FANSIG1
*VPORT 060 3 220K-V05
+5V_FAN
*VPORT 060 3 220K-V05
+5V
FANPWR = 1.6*VSET
1
4
APE8872 M
5
U5
VIN2VO
/FON
VSET
40 MIL
40 MIL
40 MIL40 MIL
3
+5V_FAN
5
GND
6
GND
7
GND
8
GND
C49
2.2U/10V_6X
FANSIG1[33]
+3V
C53
0.01U/25V_4X
RevB 1222 Change for EOD
FAN Control
A A
C652 15 0P/50V_4N
PLTRST#[28,29,33]
C660 15 0P/50V_4N
DNBSWON#[33]
FCH_PWRGD[9]
PCIE_W AKE#[26,28]
EC_KBRST#[33]
EC_A20GATE[33]
EC_EXT_SCI #[3 3]
PCIE_CLKREQ#_LAN[26]
PCIE_CLKREQ#_W LAN[28]
HDaudio
interface
are
+3V_S5
Clk_Req GPIO
Clk_Req0
Clk_Req1
R422 *10K_4
FANSIG1
C589
*0.01U/25 V_4X
PLTRST#
R479 33_4
PCIE_RST#
R477 33_4
DNBSWON#
FCH_PWRGD
SYS_RST#[9]
SYS_RST#
PCIE_W AKE#
SLP_S3#[2 2,33]
SLP_S5#[33]
SLP_S3#
SLP_S5#
EC_KBRST#
EC_A20GATE
EC_EXT_SCI #
PCIE_CLKREQ#_LAN
PCIE_CLKREQ#_W LAN
R474 EV@0_4
R489 0_4
R469 0_4
R471 0_4
5 6
3
2
1
R462 *10KX8
C632
15P/50V_4C
USE GROUND GUARD FOR 32K_X1 AND 32K_X2
GPIO65Clk_ReqG
GPIO60
GPIO61
CN11
1
2
3
85205-03 00L
4
A_RST#
PCIE_RST#_ R
RSMRST#_R
R478 0_4
APU_TEST0
APU_TEST1
APU_TEST2
GEVENT23#
TP23
BOARD_ID5
PCIE_CLKREQ#_GPU_RPCIE_CLKREQ#_GPU
USB_NORMA L_OC#_RUSB_NORMA L_OC#
USB_SC_O C#_RUSB_SC_O C#
ODD_PRSNT#
USB_DB_O C#_RUSB_DB_O C#
74
8
9
10
R461 20M_4
41
2 3
Y4
32.768KHZ_10
Azalia
Local Temp
AY4
AY9
AY5
BA8
PWR_BTN#
AM19
AY7
AW11
AY3
BA5
AU13
AY10
AY6
AR23
AR31
AN5
AL7
AP15
AV13
BA9
BA10
AV15
AU29
AW29
AR27
AV27
CLK_REQ3 #
AY29
AY8
AW1
AV1
AY1
ACZ_BCLK_R
ACZ_SDOUT_R
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
ACZ_SDIN3
ACZ_SYNC_R
ACZ_RST#_R
AN2
AN1
AK2
AK1
AM1
AL2
AM2
AL1
AJ2
32K_X1
AJ1
32K_X2
AMD recomanded 15pF
C633
15P/50V_4C
<ADO>
ACZ_SDOUT_R
ACZ_SYNC_R
ACZ_BCLK_R
ACZ_RST#_R
ACZ_SDIN0
+5V_FAN
U22D
LPC_RST_L
PCIE_RST_L
RSMRST_L
PWR_BTN_L
PWR_GOOD
SYS_RESET_L/GEVENT19_L
WAKE_L/GEVENT8_L
SLP_S3_L
SLP_S5_L
+3V_S5
TEST0
+3V_S5
TEST1/TMS
+3V_S5
TEST2
+3V
KBRST_L
GA20IN/GEVENT0_L
LPC_PME_L/GEVENT3_L
LPC_SMI_L/GEVENT23_L
AC_PRES/IR_RX0/GEVENT16_L
IR_TX0/GEVENT21_L
IR_TX1/GEVENT6_L
IR_RX1/GEVENT20_L
IR_LED_L/LLB_L/GPIO184
CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60
CLK_REQ1_L/GPIO61
CLK_REQ2_L/GPIO62
CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63
CLK_REQG_L/GPIO65/OSCIN
USB_OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L
USB_OC1_L/TDI/GEVENT13_L
USB_OC2_L/TCK/GEVENT14_L
USB_OC3_L/TDO/GEVENT15_L
AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST_L
X32K_X1
X32K_X2
+3V_S5
+1.8V_S5
+1.8V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V
+3V_S5
+3V_S5
+3V_S5
+3V
+3V
+3V_S5
+3V
+3V_S5
+3V_S5
+3V_S5
ACPI/SD/AZ/GPIO/RTC/MISC
+3V
+3V
+3V_S5
FT3 REV 0.53
+3V_S5
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V_S5
+3V_S5
+3V
+3V
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V
+3V
+3V
+3V
SD_DATA0/GPIO77
SD_DATA1/GPIO78
SD_DATA2/GPIO79
SD_DATA3/GPIO80
+3V
+3V
+3V
DEVSLP[0]/GPIO55
+3V
+3V
DEVSLP[1]/GPIO59
+3V
+3V
+3V
+3V
+3V
+3V
BLINK/GEVENT18_L
GENINT1_L/GPIO32
GENINT2_L/GPIO33
FANOUT0/GPIO52
SD_PWR_CTRL
SD_CLK/GPIO73
SD_CMD/GPIO74
SD_CD/GPIO75
SD_WP/GPIO76
SD_LED/GPIO45
SCL0/GPIO43
SDA0/GPIO47
SCL1/GPIO227
SDA1/GPIO228
SPKR/GPIO66
GPIO174
GEVENT2_L
GEVENT4_L
GEVENT7_L
GEVENT10_L
GEVENT11_L
GEVENT17_L
GEVENT22_L
FANIN0/GPIO56
BA23
AY22
AY23
AY20
Without SD,
BA20
Left Unconnected.
BA22
AY21
AY24
BA24
AY25
AU25
SMB_RUN_CL K
AV25
SMB_RUN_DA T
AY11
SMB_LAN_ CLK
BA11
SMB_LAN_ DAT
AP27
GPIO49
AY28
BOARD_ID8
GPIO50
BA28
BOARD_ID3
GPIO51
AV23
AP21
APU_ODD_EN
GPIO57
BA26
BOARD_ID4
GPIO58
AV19
BOARD_ID9
AY27
GPIO64
BA27
PCBEEP
AU21
GPIO68
AY26
BOARD_ID6
GPIO69
AV21
BOARD_ID7
GPIO70
AM21
BOARD_ID1 0
GPIO71
BA3
BOARD_ID1 1
AV17
GEVENT2#
BA4
AR15
GEVENT7#
AP17
AP11
GEVENT11#
AN8
ODD_MD#
AU17
GEVENT18#
BA6
RevA 1023 ODD_MD# CRB assign GEVENT17
BA29
PASSW DCLR
AP23
AV31
BOARD_ID1
AU31
BOARD_ID2
AV11
RTCCLK
FT3
To Azalia
R159 33_4
R156 33_4
R158 33 _4
C235
R157 33_4
*22P/50V _4N
ACZ_SDOUT [27]
ACZ_SYNC [27]
ACZ_BITCLK [27]
ACZ_RST# [27]
ACZ_SDIN0 [27]
<THM>
+5V VIN +5VP CU
U32
2
Q28
1 3
*MMBT2222A _600MA
R531 *100K_4
R532
*100K_4
R533
*162K/F_4
1
1 OUT
2
1 IN-
3
VFAN1
3
1 IN+
GND42 IN+
*LM358
2 OUT
2 IN-
8
VCC
7
6
5
SMB_RUN_CL K [10 ,11]
SMB_RUN_DA T [10,1 1]
SMB_LAN_ CLK [24,28,32]
SMB_LAN_ DAT [24,28,32 ]
TP34
APU_ODD_EN [31]
PE_GPIO0 [22]
PCBEEP [27]
PE_GPIO1 [22]
GEVENT2# [9]
TP28
TP30
TP27
R200 0_4
Local Temp
R484 15 0_4
+3VPCU
R549
*IV@NTC_470 K_4
R546
*48.7K/F_ 4
ODD_MD# [31]
PE_PW RGD [33,40,41]
RTC_CLK [9,33]
<THM>
HYST=VCC for 10
degree Hys.
HYST=GND for 30
degree Hys.
R552
*EV@NTC_470 K_4
+3VPCU_HW _SD
C664
0.1U/16V_4Y
2
+3V
R548
*499K/F_4
R545
*499K/F_4
SMB_RUN_CL K
SMB_RUN_DA T
SMB_LAN_ CLK
SMB_LAN_ DAT
R481
10K_4
12
G2
*SHORT_PAD
BOARD_ID[1:11]
U26
5
VCC
4
HYST
G708T1U
34
Q30B
5
*2N7002K DW_115MA
6
Q30A
2
*2N7002K DW_115MA
1
+3V
R4932.2K_4
R4942.2K_4
+3V_S5
R4752.2K_4
R4762.2K_4
BOARD_ID[1:11] [8,27,32]
GPIONet I/O Power Well DOS
Function
I +3.3V
O
O +3.3V
GPIO64
GPIO68
DGPU_PWRGD
DGPU_RST#
PE_PWRGD
PE_GPIO0 "0->1"
PE_GPIO1
Rset(Kohm)=0.0012T*T-0.9308T+96.147
R513 EV@2 4.9K/F_4
1
R507 IV@24.9K/F_4
SET
2
GND
3
S5_ON
R556
*IV@1M_4
OT#
R553
*EV@1M_4
R511 *470K_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Docu ment Number Rev
Size Docu ment Number Rev
Size Docu ment Number Rev
Date: S heet of
Tuesday, December 25, 2012
Date: S heet of
Tuesday, December 25, 2012
Date: S heet of
Tuesday, December 25, 2012
PROJECT :
APU 5/6(ACPI/SD/AZ/GPIO/RTC/MISC)
APU 5/6(ACPI/SD/AZ/GPIO/RTC/MISC)
APU 5/6(ACPI/SD/AZ/GPIO/RTC/MISC)
1
+3.3V
+3VPCU
"0->1"GPIO33
"0->1"DGPU_PWREN
S5_ON [13,3 3,35]
BD9
BD9
BD9
7 41
7 41
7 41
07
A1A
A1A
A1A
5
SATA_TXP0[31]
SATA HDD
SATA ODD
D D
CLK_PCIE_VGAP[12]
Reference GND
Do not change layer
and cross plane
CLK_PCIE_VGAN[12]
CLK_PCIE_LANP[26]
CLK_PCIE_LANN[26]
CLK_PCIE_WLANP[28]
CLK_PCIE_WLANN[28]
SATA_TXN0[31]
SATA_RXN0[31]
SATA_RXP0[31]
SATA_TXP1[31]
SATA_TXN1[31]
SATA_RXN1[31]
SATA_RXP1[31]
+0.95V
RP1 0X2
RP2 0X2
RP3 0X2
C627 15P/50V_4C
RevB 1222 Change cap value for vendor suggestion
PCLK_DEBUG[28]
PCLK_591[ 33]
C C
For EMI
PCLK_DEBUG
PCLK_591
C251 * 15P/50V_4C
C248 * 15P/50V_4C
LPC_CLK0[9]
LPC_CLK1[9]
LFRAME#[9,28,33]
SERIRQ[33] FCH_SPI_SO[33]
CLKRUN#[33]
LPCPD#[33]
C623 15P/50V_4C
LPC_CLK0
LPC_CLK1
LAD0[28,33]
LAD1[28,33]
LAD2[28,33]
LAD3[28,33]
LAD0
LAD1
LAD2
LAD3
LFRAME#
SERIRQ
CLKRUN#
LPCPD#
R170 1K/F_4
R169 1K/F_4
TP41
241
241
241
Y3
48MHZ_15
R178 0_4
R164 22_4
R172 22_4
R167 22_4
R495 10K_4
+3V_S5
4
Integrated Clock Mode:
Leave unconnected.
INT_CLK_PCIE_VGAPCLK_PCIE_VGAP
3
INT_CLK_PCIE_VGANCLK_PCIE_VGAN
INT_CLK_PCIE_LANPCLK_PCIE_LANP
3
INT_CLK_PCIE_LANNCLK_PCIE_LANN
INT_CLK_PCIE_WLANPCLK_PCIE_WLANP
3
INT_CLK_PCIE_WLANNCLK_PCIE_WLANN
Integrated Clock Mode:
Leave unconnected.
Cardreader pass through PCIE
Leave unconnected.
2
R457
1M_4
1 3
4
TP25
SATA_CALRN
SATA_CALRP
SATA_LED#
48M_X1
48M_X2
LPC_CLK0_R
LPC_CLK1_R
U22E
BA14
SATA_TX0P
AY14
SATA_TX0N
BA16
SATA_RX0N
AY16
SATA_RX0P
AY19
SATA_TX1P
BA19
SATA_TX1N
AY17
SATA_RX1N
BA17
SATA_RX1P
AR19
SATA_ZVSS
AP19
SATA_ZVDD_095
BA30
SATA_ACT_L/GPIO67
AY12
SATA_X1
BA12
SATA_X2
U4
GFX_CLKP
U5
GFX_CLKN
AC8
GPP_CLK0P
AC10
GPP_CLK0N
AE4
GPP_CLK1P
AE5
GPP_CLK1N
AC4
GPP_CLK2P
AC5
GPP_CLK2N
AA5
GPP_CLK3P
AA4
GPP_CLK3N
AP13
X14M_25M_48M_OSC
N2
X48M_X1
N1
X48M_X2
AY2
LPCCLK0
AW2
LPCCLK1
AT2
+3V_S5
LAD0
AT1
+3V_S5
LAD1
AR2
+3V_S5
LAD2
AR1
+3V_S5
LAD3
AP2
LFRAME_L
AP1
LDRQ0_L
AV29
SERIRQ/GPIO48
AP25
LPC_CLKRUN_L
AV2
LPC_PD_L/GEVENT5_L/SPI_TPM_CS_L
+3V
+3V
+3V_S5
+3V_S5
+3V
+3V
+3V
CLK/SATA/USB/SPI/LPC
+3V_S5
FT3 REV 0.53
USBCLK/14M_25M_48M_OSC
USB_SS_ZVDD_095_USB3_DUAL
+3V
+3V
+3V
+3V_S5
+3V_S5
+3V_S5
+3V_S5
USB_ZVSS
USB_HSD0P
USB_HSD0N
USB_HSD1P
USB_HSD1N
USB_HSD2P
USB_HSD2N
USB_HSD3P
USB_HSD3N
USB_HSD4P
USB_HSD4N
USB_HSD5P
USB_HSD5N
USB_HSD6P
USB_HSD6N
USB_HSD7P
USB_HSD7N
USB_HSD8P
USB_HSD8N
USB_HSD9P
USB_HSD9N
USB_SS_ZVSS
USB_SS_0TXP
USB_SS_0TXN
USB_SS_0RXP
USB_SS_0RXN
USB_SS_1TXP
USB_SS_1TXN
USB_SS_1RXP
USB_SS_1RXN
SPI_CLK/GPIO162
SPI_CS1_L/GPIO165
SPI_CS2_L/GPIO166
SPI_DO/GPIO163
SPI_DI/GPIO164
SPI_HOLD_L/GEVENT9_L
SPI_WP_L/GPIO161
3
W4
AG4
USB_ZVSS
AL4
USBP0+
AL5
USBP0-
AJ4
USBP1+
AJ5
USBP1-
AG7
RevA 1023 Add USBP1 for BD9
AG8
AG1
AG2
AF1
USBP4+
AF2
USBP4-
AE1
USBP5+
AE2
USBP5-
AD1
USBP6+_CCD
AD2
USBP6-_CCD
AC1
USBP7+
AC2
USBP7-
AB1
USBP8+
AB2
USBP8-
AA1
USBP9+
AA2
USBP9-
AE10
USBSS_CALRN
AE8
USBSS_CALRP
T2
USB3_TXP0
T1
USB3_TXN0
V2
USB3_RXP0
V1
USB3_RXN0
R1
USB3_TXP1
R2
USB3_TXN1
W1
USB3_RXP1
W2
USB3_RXN1
AU7
FCH_SPI_CLK_R
FCH_SPI_CS0#_R
FCH_SPI_SO_R
double check
R190 33_4
R197 0_4
R199 0_4
AW9
AR4
AR11
AR7
AU11
AU9
FT3
TP17
R131 11. 8K/F_6
USBP0+ [23]
USBP0- [23]
USBP1+ [23]
USBP1- [23]
USBP4+ [25]
USBP4- [25]
USBP5+ [29]
USBP5- [29]
USBP6+_CCD [30]
USBP6-_CCD [30]
USBP7+ [28]
USBP7- [28]
USBP8+ [23]
USBP8- [23]
USBP9+ [23]
USBP9- [23]
R124 1K/F_4
R125 1K/F_4
USB3_TXP0 [23]
USB3_TXN0 [23]
USB3_RXP0 [23]
USB3_RXN0 [23]
USB3_TXP1 [23]
USB3_TXN1 [23]
USB3_RXP1 [23]
USB3_RXN1 [23]
FCH_SPI_CLK
FCH_SPI_CS0#
FCH_SPI_SO
FCH_SPI_SI
SPI_HOLD#
FCH_SPI_WP
To USB 2.0 Daughter/B
To USB 2.0 Daughter/B
Touch Screen
Card Reader
CCD on LVDS
WLAN
USB3.0/2.0 S&C
USB2.0/3.0 w/o S&C
+0.95V_DUAL
USB3.0 S&C
USB3.0 Port 2
TP26
2
1
08
HUB1
HUB2
HUB3
W25Q32BVSSIG:AKE391P0N00
W25Q64FVSSIQ:AKE3EFP0N07
R517 10K_4
U30
FCH_SPI_CS0#[33]
FCH_SPI_CLK[33]
FCH_SPI_SI[33]
FCH_SPI_CS0#
FCH_SPI_CLK
FCH_SPI_SO
FCH_SPI_SI SPI_HOLD#FCH_SPI_SI_R
R519 0_4
+3V_S5
R524 10K_4
FCH_SPI_WP
1
6
5
2
3
C687
*22P/50V_4N
RevB 1225 Change from 8M to 4M
CE#
VDD
SCK
SI
SO
HOLD#
WP#
VSS
W25Q32BVSSIG
8
7
4
+3V_S5
C684
0.1U/10V_4X
R520
10K_4
BOARD_ID[1:11][7,27,32]
BOARD ID SETTING
ID7
ID9ID8ID1 ID2Board ID ID3
ID10
ID11
ID12 ID13
H
H
L
H
L
H
L
H
L
4
ID5
ID6
B B
RevB 1221 Modify Board ID
Always PU
Always PU
RevC 0130 Change Board ID setting
Reserve PD
A A
5
UMA SKU
PX SKU
VRAM 1GHz
VRAM 900M
USB3.0
USB2.0
14" MTN
17" BD9
W/O S&C
W S&C
N-METAL (W/O KBLED)
METAL (W/ KBLED)
N-Brand
Brand (ONKYO) L
W/O HDMI
W HDMI
N-Brand
Brand(Harman/Kardon)
Metal/IMR
TEXTURE
RSVD
RSVD
H
L
ID4
H
L
H
L
H
L
H
L
H
L
+3V
+3V_S5
BOARD_ID[1:11]
R165 UMA@10K_4
R163 *10K_4
R510 U3@10K_4
R491 *MTN@10K_4
R492 KBLED@10K_4
R187 N-Brand@10K_4
R509 NHM@10K_4
R198 10K_4
R186 Metal@10K_4
R487 *10K_4
R192 NS&C@10K_4
3
BOARD_ID1
R171 EV@10K_4
BOARD_ID2
R160 10K_4
BOARD_ID3
R501 U2@10K_4
BOARD_ID4
R485 BD9@10K_4
BOARD_ID6
R486 *NKBLED@10K_4
BOARD_ID7
R168 *ONKYO@10K_4
BOARD_ID8
R500 HM@10K_4
BOARD_ID9
R184 *10K_4
BOARD_ID10
R201 Texture@10K_4
BOARD_ID11
R480 10K_4
BOARD_ID5
R179 S&C@10K_4
RevC 0130 Change Board ID 9 for Harman-Kardon
Stuff R198, Remove R184
2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, January 30, 2013
Date: Sheet of
Wednesday, January 30, 2013
Date: Sheet of
Wednesday, January 30, 2013
PROJECT :
APU 6/7(CLK/SATA/USB/SPI)
APU 6/7(CLK/SATA/USB/SPI)
APU 6/7(CLK/SATA/USB/SPI)
1
BD9
BD9
BD9
8 41
8 41
8 41
A1A
A1A
A1A
5
4
3
2
1
STRAPS PINS
D D
+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5
R162
R217
R166
R182
*10K_4
LPC_CLK0[8]
LPC_CLK1[8]
LFRAME#[8,28,33]
RTC_CLK[7,33]
C C
B B
GEVENT2#[7]
LPC_CLK0
LPC_CLK1
LFRAME#
RTC_CLK
GEVENT2#
REQUIRED
STRAPS
PULL
HIGH
PULL
LOW
R183
2K/F_4
LPC_CLK0 LFRAME#
LPC_CLK1
Internal
BOOT
Fail Timer
ENABLE
BOOT
Fail Timer
DISABLE
DEFAULT
SPI
CLKGEN
ROM
ENABLED
DEFAULT DEFAULT DEFAULT
Internal
LPC
CLKGEN
ROM
DISABLED
10K_4
R173
*2K/F_4
RTC_CLK
Normal
Power Timing
ENABLE
Normal
Power Timing
DISABLE
10K_4
R161
*2K/F_4
10K_4
*2.2K_4
GEVENT2#
SPI
Voltage
1.8V
SPI
Voltage
3.3V
DEFAULT
R213
*10K_4
R191
2.2K_4
+1.8V_S5 +1.8V_S5
R512
1U/10V_6X
10K_4
C677
U27
2 4
3 5
R506 0_4
C674
*0.1U/10V_4X
R502 *0_4
*SN74LVC1G17DCKR
FCH_PWRGDVRM_PWRGD
FCH_PWRGD [7]
MPWROK
D29 *1SS355_100MA
D32 1SS355_100MAR196
D28 1SS355_100MA
D30 *1SS355_100MA
SYS_RST#[7]
VRM_PWRGD[38]
MPWROK[33]
MAINON[33,39]
PWRGD CIRCUIT
09
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
5
4
3
2
Tuesday, December 25, 2012
PROJECT :
APU 7/7(STRAP & PWRGD)
APU 7/7(STRAP & PWRGD)
APU 7/7(STRAP & PWRGD)
1
BD9
BD9
BD9
9 41
9 41
9 41
A1A
A1A
A1A
5
4
3
2
1
DDR_STD(DDR)
JDIM2A
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12/BC#
119
A13
80
A14
78
A15
109
BA0
108
BA1
79
BA2
114
S0#
121
S1#
101
CK0
103
CK0#
102
CK1
104
CK1#
73
CKE0
74
CKE1
115
CAS#
110
RAS#
113
WE#
197
SA0
201
SA1
202
SCL
200
SDA
116
ODT0
120
ODT1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
10
DQS#0
27
DQS#1
45
DQS#2
62
DQS#3
135
DQS#4
152
DQS#5
169
DQS#6
186
DQS#7
DDRSK-20401-TP8D
C72
1U/10V_4X
C261
*10U/6.3V_6X
PC2100 DDR3 SDRAM SO-DIMM
C91
1U/10V_4X
+1.5VSUS
4
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
C93
1U/10V_4X
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
(204P)
C137
1U/10V_4X
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
RevB 1219 Change for EOD
EMI Suggestion
C76
ESD@39P/50V_4N
C75
ESD@39P/50V_4N
C127
10U/6.3V_6X
+0.75V_VREF_CA
C123
10U/6.3V_6X
C51
ESD@39P/50V_4N
M_A_DQ[0..63]
M_A_DQ[0..63] [4,11]
+0.75V_VREF_DQ
+0.75V_VREF_CA
C5329 placed between JDIM1 and JDIM2
+1.5VSUS
R111
1K/F_4
R122 0_6
+0.75V_VREF_DQ
C13
0.1U/10V_4X
C52
ESD@39P/50V_4N
MEM_VREFCA_SUS
R112
1K/F_4
+APU_M_VREFDQ_SUS
C14
1000P/50V_4X
C74
ESD@39P/50V_4N
3
C70
ESD@39P/50V_4N
M_A_EVENT#[4,11]
M_A_RST#[4,11]
R123 *0_6
C150
0.47U/6.3V_4X
R21
1K/F_4
R20 *0_6
R23
1K/F_4
2.48A
+3V
C27 *E@0.1U/10V_4X
+SMDDR_VREF
+1.5VSUS
C83
ESD@39P/50V_4N
+1.5VSUS
DQ_OP-
DQ_OP+
C19
0.47U/6.3V_4X
+0.75V_VREF_CA
U2
4
-
3
+
C159
0.1U/10V_4X
2
JDIM2B
75
VDD1
76
VDD2
81
VDD3
82
VDD4
87
VDD5
88
VDD6
93
VDD7
94
VDD8
99
VDD9
100
VDD10
105
VDD11
106
VDD12
111
VDD13
112
VDD14
117
VDD15
118
VDD16
123
VDD17
124
VDD18
199
VDDSPD
77
NC1
122
NC2
125
NCTEST
198
EVENT#
30
RESET#
1
VREF_DQ
126
VREF_CA
2
VSS1
3
VSS2
8
VSS3
9
VSS4
13
VSS5
14
VSS6
19
VSS7
20
VSS8
25
VSS9
26
VSS10
31
VSS11
32
VSS12
37
VSS13
38
VSS14
43
VSS15
DDRSK-20401-TP8D
R27 *0_4
R30 *0_4
+3V_S5
2
*0.1U/10V_4X
V+
V-
*MCP6001RT-E/OT
5
C160
1000P/50V_4X
(204P)
PC2100 DDR3 SDRAM SO-DIMM
C18
1
OP_OUT
R19 0_6
44
VSS16
48
VSS17
49
VSS18
54
VSS19
55
VSS20
60
VSS21
61
VSS22
65
VSS23
66
VSS24
71
VSS25
72
VSS26
127
VSS27
128
VSS28
133
VSS29
134
VSS30
138
VSS31
139
VSS32
144
VSS33
145
VSS34
150
VSS35
151
VSS36
155
VSS37
156
VSS38
161
VSS39
162
VSS40
167
VSS41
168
VSS42
172
VSS43
173
VSS44
178
VSS45
179
VSS46
184
VSS47
185
VSS48
189
VSS49
190
VSS50
195
VSS51
196
VSS52
203
VTT1
204
VTT2
205
GND
206
GND
R18 *0_6
C22*0.1U/10V_4X
+SMDDR_VTERM
+APU_M_VREFDQ_SUS
R17
*0_4
+0.75V_VREF_DQ
R24 *0_6
C16
0.1U/10V_4X
R26
*10K_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
DDR3 DIMM-0
DDR3 DIMM-0
DDR3 DIMM-0
Tuesday, December 25, 2012
Tuesday, December 25, 2012
Tuesday, December 25, 2012
C17
0.1U/10V_4X
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
BD9
BD9
BD9
1
10
+SMDDR_VREF
10 41
10 41
10 41
A1A
A1A
A1A
C269
1U/6.3V_4X
M_A_A[15:0]
M_A_BS#[2:0]
M_A_CS#0[4]
M_A_CS#1[4]
M_A_CLKP0[4]
M_A_CLKN0[4]
M_A_CLKP1[4]
M_A_CLKN1[4]
M_A_CKE0[4]
M_A_CKE1[4]
M_A_CAS#[4,11]
M_A_RAS#[4,11]
M_A_WE#[4,11]
SMB_RUN_CLK[7,11]
SMB_RUN_DAT[7,11]
M_A_ODT0[4]
M_A_ODT1[4]
C88
10U/6.3V_6X
C263
1U/6.3V_4X
M_A_DM[7:0]
M_A_DQSP[7:0]
M_A_DQSN[7:0]
C102
10U/6.3V_6X
C264
1U/6.3V_4X
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_BS#0
M_A_BS#1
M_A_BS#2
M_A_CS#0
M_A_CS#1
M_A_CLKP0
M_A_CLKN0
M_A_CLKP1
M_A_CLKN1
M_A_CKE0
M_A_CKE1
M_A_CAS#
M_A_RAS#
M_A_WE#
DIMM0_SA0
DIMM0_SA1
SMB_RUN_CLK
SMB_RUN_DAT
M_A_ODT0
M_A_ODT1
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7
M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7
C87
10U/6.3V_6X
C270
1U/6.3V_4X
C61
*10U/6.3V_6X
C274
10U/6.3V_6X
M_A_A[15:0][4,11]
D D
M_A_BS#[2..0][4,11]
R499 10K_4
R504 10K_4
C C
B B
A A
Reserve ICT test point
+1.5VSUS
C78
C62
10U/6.3V_6X
10U/6.3V_6X
+3V
C238
2.2U/10V_6X
C242
0.1U/10V_4X
M_A_DM[7..0][4,11]
M_A_DQSP[7:0][4,11]
M_A_DQSN[7:0][4,11]
Place these Caps near So-Dimm0.
C119
10U/6.3V_6X
+SMDDR_VTERM
RevB 1222 Change for EOD
5
5
4
3
2
1
DDR_STD(DDR)
JDIM1A
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12/BC#
119
A13
80
A14
78
A15
109
BA0
108
BA1
79
BA2
114
S0#
121
S1#
101
CK0
103
CK0#
102
CK1
104
CK1#
73
CKE0
74
CKE1
115
CAS#
110
RAS#
113
WE#
197
SA0
201
SA1
202
SCL
200
SDA
116
ODT0
120
ODT1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
10
DQS#0
27
DQS#1
45
DQS#2
62
DQS#3
135
DQS#4
152
DQS#5
169
DQS#6
186
DQS#7
DDRSK-20401-TP4B
5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
(204P)
PC2100 DDR3 SDRAM SO-DIMM
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
M_A_DQ0
7
M_A_DQ1
15
M_A_DQ2
17
M_A_DQ3
4
M_A_DQ4
6
M_A_DQ5
16
M_A_DQ6
18
M_A_DQ7
21
M_A_DQ8
23
M_A_DQ9
33
M_A_DQ10
35
M_A_DQ11
22
M_A_DQ12
24
M_A_DQ13
34
M_A_DQ14
36
M_A_DQ15
39
M_A_DQ16
41
M_A_DQ17
51
M_A_DQ18
53
M_A_DQ19
40
M_A_DQ20
42
M_A_DQ21
50
M_A_DQ22
52
M_A_DQ23
57
M_A_DQ24
59
M_A_DQ25
67
M_A_DQ26
69
M_A_DQ27
56
M_A_DQ28
58
M_A_DQ29
68
M_A_DQ30
70
M_A_DQ31
129
M_A_DQ32
131
M_A_DQ33
141
M_A_DQ34
143
M_A_DQ35
130
M_A_DQ36
132
M_A_DQ37
140
M_A_DQ38
142
M_A_DQ39
147
M_A_DQ40
149
M_A_DQ41
157
M_A_DQ42
159
M_A_DQ43
146
M_A_DQ44
148
M_A_DQ45
158
M_A_DQ46
160
M_A_DQ47
163
M_A_DQ48
165
M_A_DQ49
175
M_A_DQ50
177
M_A_DQ51
164
M_A_DQ52
166
M_A_DQ53
174
M_A_DQ54
176
M_A_DQ55
181
M_A_DQ56
183
M_A_DQ57
191
M_A_DQ58
193
M_A_DQ59
180
M_A_DQ60
182
M_A_DQ61
192
M_A_DQ62
194
M_A_DQ63
M_A_DQ[0..63]
M_A_DQ[0..63] [4,10]
M_A_EVENT#[4,10]
M_A_RST#[4,10]
+0.75V_VREF_DQ
+0.75V_VREF_CA
2.48A
+3V
+1.5VSUS
JDIM1B
75
VDD1
76
VDD2
81
VDD3
82
VDD4
87
VDD5
88
VDD6
93
VDD7
94
VDD8
99
VDD9
100
VDD10
105
VDD11
106
VDD12
111
VDD13
112
VDD14
117
VDD15
118
VDD16
123
VDD17
124
VDD18
199
VDDSPD
77
NC1
122
NC2
125
NCTEST
198
EVENT#
30
RESET#
1
VREF_DQ
126
VREF_CA
2
VSS1
3
VSS2
8
VSS3
9
VSS4
13
VSS5
14
VSS6
19
VSS7
20
VSS8
25
VSS9
26
VSS10
31
VSS11
32
VSS12
37
VSS13
38
VSS14
43
VSS15
DDRSK-20401-TP4B
44
VSS16
48
VSS17
49
VSS18
54
VSS19
55
VSS20
60
VSS21
61
VSS22
65
VSS23
66
VSS24
71
VSS25
72
VSS26
127
VSS27
128
VSS28
133
VSS29
134
VSS30
138
VSS31
139
VSS32
144
VSS33
145
VSS34
150
VSS35
151
VSS36
155
VSS37
156
VSS38
161
VSS39
162
VSS40
167
VSS41
168
VSS42
172
VSS43
173
VSS44
178
VSS45
179
VSS46
184
VSS47
185
VSS48
189
VSS49
190
VSS50
195
VSS51
196
VSS52
(204P)
PC2100 DDR3 SDRAM SO-DIMM
VTT1
VTT2
GND
GND
203
204
205
206
+SMDDR_VTERM
11
M_A_CS#2[4]
M_A_CS#3[4]
M_A_CLKP2[4]
M_A_CLKN2[4]
M_A_CLKP3[4]
M_A_CLKN3[4]
M_A_CKE2[4]
M_A_CKE3[4]
M_A_CAS#[4,10]
M_A_RAS#[4,10]
M_A_WE#[4,10]
SMB_RUN_CLK[7,10]
SMB_RUN_DAT[7,10]
M_A_ODT2[4]
M_A_ODT3[4]
M_A_A[15:0]
M_A_BS#[2:0]
M_A_DM[7:0]
M_A_DQSP[7:0]
M_A_DQSN[7:0]
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_BS#0
M_A_BS#1
M_A_BS#2
M_A_CS#2
M_A_CS#3
M_A_CLKP2
M_A_CLKN2
M_A_CLKP3
M_A_CLKN3
M_A_CKE2
M_A_CKE3
M_A_CAS#
M_A_RAS#
M_A_WE#
DIMM1_SA0
DIMM1_SA1
SMB_RUN_CLK
SMB_RUN_DAT
M_A_ODT2
M_A_ODT3
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7
M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7
M_A_A[15:0][4,10]
D D
M_A_BS#[2..0][4,10]
R176 10K_4
+3V
R177 10K_4
C C
B B
Reserve ICT test point
M_A_DM[7..0][4,10]
M_A_DQSP[7:0][4,10]
M_A_DQSN[7:0][4,10]
+1.5VSUS
C106
10U/6.3V_6X
Place these Caps near So-Dimm0.
C98
10U/6.3V_6X
C60
10U/6.3V_6X
C64
10U/6.3V_6X
C77
10U/6.3V_6X
C96
10U/6.3V_6X
C80
*10U/6.3V_6X
C100
1U/10V_4X
C58
1U/10V_4X
C112
1U/10V_4X
C97
1U/10V_4X
C142
10U/6.3V_6X
C50
10U/6.3V_6X
+0.75V_VREF_DQ
C12
0.1U/10V_4X
C15
1000P/50V_4X
RevB 1219 Change for EOD
RevB 1219 Change for EOD
C108
ESD@39P/50V_4N
4
EMI Suggestion
C143
ESD@39P/50V_4N
C63
ESD@39P/50V_4N
C84
ESD@39P/50V_4N
C59
ESD@39P/50V_4N
3
C129
ESD@39P/50V_4N
C73
ESD@39P/50V_4N
+0.75V_VREF_CA
C167
0.1U/10V_4X
C161
1000P/50V_4X
2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
Tuesday, December 25, 2012
PROJECT :
DDR3 DIMM-1
DDR3 DIMM-1
DDR3 DIMM-1
BD9
BD9
BD9
11 41
11 41
1
11 41
A1A
A1A
A1A
+3V
A A
C246
2.2U/10V_6X
C252
0.1U/10V_4X
+SMDDR_VTERM
C275
1U/6.3V_4X
C266
1U/6.3V_4X
C276
1U/6.3V_4X
C265
1U/6.3V_4X
C279
10U/6.3V_6X
+1.5VSUS
C262
*10U/6.3V_6X
RevB 1222 Change for EOD
5
<VGA>
PART 1 0F 9
U33A
12
PEG_TXP0[3]
PEG_TXN0[3]
PEG_TXP1[3]
PEG_TXN1[3]
PEG_TXP2[3]
PEG_TXN2[3]
PEG_TXP3[3]
PEG_TXN3[3]
CLK_PCIE_VGAP[8]
CLK_PCIE_VGAN[8]
R301 EV@10K_4
PERST#_BUF[22]
PERST#_BUF
R249 EV@0_4
C403
*E@0.1U/10V_4X
PEG_TXP0
PEG_TXN0
PEG_TXP1
PEG_TXN1
PEG_TXP2
PEG_TXN2
PEG_TXP3
PEG_TXN3
PERST#_BUF_R
AA38
W36
W38
M37
M35
G36
G38
AB35
AA36
AH16
AA30
Y37
Y35
V37
V35
U36
U38
T37
T35
R36
R38
P37
P35
N36
N38
L36
L38
K37
K35
H37
H35
F37
F35
E37
J36
J38
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
NC_PCIE_RX8P
NC_PCIE_RX8N
NC_PCIE_RX9P
NC_PCIE_RX9N
NC_PCIE_RX10P
NC_PCIE_RX10N
NC_PCIE_RX11P
NC_PCIE_RX11N
NC_PCIE_RX12P
NC_PCIE_RX12N
NC_PCIE_RX13P
NC_PCIE_RX13N
NC_PCIE_RX14P
NC_PCIE_RX14N
NC_PCIE_RX15P
NC_PCIE_RX15N
CLOCK
PCIE_REFCLKP
PCIE_REFCLKN
TEST_PG
PERSTB
PCI EXPRESS INTERFACE
EV@Mars_M2
PCIE_TX0P C329 EV@0.1U/10V_4X
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
NC_PCIE_TX8P
NC_PCIE_TX8N
NC_PCIE_TX9P
NC_PCIE_TX9N
NC_PCIE_TX10P
NC_PCIE_TX10N
NC_PCIE_TX11P
NC_PCIE_TX11N
NC_PCIE_TX12P
NC_PCIE_TX12N
NC_PCIE_TX13P
NC_PCIE_TX13N
NC_PCIE_TX14P
NC_PCIE_TX14N
NC_PCIE_TX15P
NC_PCIE_TX15N
CALIBRATION
PCIE_CALR_TX
PCIE_CALR_RX
Y33
Y32
W33
W32
U33
U32
U30
U29
T33
T32
T30
T29
P33
P32
P30
P29
N33
N32
N30
N29
L33
L32
L30
L29
K33
K32
J33
J32
K30
K29
H33
H32
Y30
Y29
CPEG_RXP0
CPEG_RXN0
CPEG_RXP1
CPEG_RXN1
CPEG_RXP2
CPEG_RXN2
CPEG_RXP3
CPEG_RXN3
C337 EV@0.1U/10V_4X
C327 EV@0.1U/10V_4X
C331 EV@0.1U/10V_4X
C321 EV@0.1U/10V_4X
C320 EV@0.1U/10V_4X
C322 EV@0.1U/10V_4X
C323 EV@0.1U/10V_4X
R251 *EV@1.27K/F_4
R250 EV@1.69K/F_4
R265 EV@1K/F_4
+5VRUN/+3VRUN/VDDR3
RUNPWROK
MVDDQ/VDDC/VDDCI
1.8V_IO/PCIE_VDDC
PWRGOOD
PCIE_RST#(PERSTB)
PCIE Clock
+0.95V_GPU
PEG_RXP0 [3]
PEG_RXN0 [3]
PEG_RXP1 [3]
PEG_RXN1 [3]
PEG_RXP2 [3]
PEG_RXN2 [3]
PEG_RXP3 [3]
PEG_RXN3 [3]
Mars Power-on sequence
1 => +3V_GPU
2 => +VDDC,+VDDCI,+1.5V_GPU,+0.95V_GPU
3 => +1.8V_GPU
PEG
Intel platform: Lane0 ~ Lane15
Brazos platform: Lane12 ~ Lane15
Comal and Sabine platform: Lane8 ~Lane15
Richland and Kabini platform: Lane0 ~ Lane7
Power Up Reset Sequence
20ms max
100ms min 100ms min
100us min
Asic in Reset Hardware Reset Sequence DFG Space Ready
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
100ms max
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Mars_M2/ PEG*8
Mars_M2/ PEG*8
Mars_M2/ PEG*8
BD9
BD9
BD9
A1A
A1A
A1A
12 41Tuesday, December 25, 2012
12 41Tuesday, December 25, 2012
12 41Tuesday, December 25, 2012
<VGA>
Q17A EV@2N7002KDW_115MA
3ND_MBCLK[24,33]
3ND_MBDATA[24,33]
S5_ON[7,33,35]
On Mars only HPD1 and GPIO_14_HPD2
are available for display hot-plug detection
+1.8V_GPU
6
2
5
3 4
Q17B EV@2N7002KDW_115MA
3
Q34
2
*ME2N7002E_200MA
1
+1.8V_GPU
R310
EV@499/F_4
R311
EV@249/F_4
1.8V@8mA
EV@BLM15BD121SN1D_300MAL8
on-die thermal sensor power
1
R312
EV@10K/F_4
+3V_GPU
R315
EV@10K/F_4
+3V_GPU
R573 EV@10K_4
GPIO_19_CTF
R577
*EV@100K_4
Place close to Chip
C448
EV@0.1U/10V_4X
PU:Disable MLPS
PD:Enable MLPS
C429
EV@10U/6.3V_6X
GENIL_CLK[15]
GENIL_VSYNC[15]
GPU_SMBCLK
1.8V GPIO
GPU_SMBDAT
Tempeature function: Connect to EC
R307 EV@4.7K_4
R292 EV@4.7K_4
GPU_GPIO0[15,40]
GPU_GPIO1[15]
GPU_GPIO2[15]
GPU_GPIO8[15]
GPU_GPIO9[15]
GPU_GPIO10[15]
GPU_GPIO11[15]
GPU_GPIO12[15]
GPU_GPIO13[15]
GFX_CORE_CNTRL1[40]
GFX_CORE_CNTRL5[40]
GFX_CORE_CNTRL2[40]
GPU_GPIO21[15]
GPU_GPIO22[15]
PCIE_CLKREQ#_GPU[7]
GFX_CORE_CNTRL3[40]
GFX_CORE_CNTRL4[40]
GPU_GENERICC[15]
GPU_VREFG
+3V_GPU
+3V_GPU
C428
EV@1U/6.3V_4X
GPU_SMBCLK
GPU_SMBDAT
GPU_SCL
GPU_SDA
T7
T6
T5
T26
T3
T8
T11
T23
R260 *EV@4.7K_4
R256 EV@1K_4
R255 *EV@5.11K/F_4
R290 *EV@10K/F_4
R291 EV@10K/F_4
TSVDD
C427
EV@0.1U/10V_4X
T29
T25
T28
T24
T27
T16
T18
AD29
AC29
AJ21
AK21
AW8
AW3
AW5
AW6
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12
AJ23
AH23
AK26
AJ26
AH20
AH18
AN16
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13
AG32
AG33
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24
AC30
AK24
AH13
AL21
AD28
AM23
AN23
AK23
AL24
AM24
AF29
AG29
AK32
AL31
AJ32
AJ33
AR8
AU8
AP8
AR3
AR1
AU1
AU3
AP6
AU5
AR6
AU6
AT7
AV7
AN7
AV9
AT9
PART 2 0F 9
MUTI GFX
GENLK_CLK
GENLK_VSYNC
SWAPLOCKA
SWAPLOCKB
NC_DVPCNTL_MVP_0
NC_DVPCNTL_MVP_1
DBG_CNTL0
NC_DVPCNTL_1
NC_DVPCNTL_2
NC_DVPCLK
DBG_DATA0
DBG_DATA1
DBG_DATA2
DBG_DATA3
DBG_DATA4
DBG_DATA5
DBG_DATA6
DBG_DATA7
DBG_DATA8
DBG_DATA9
DBG_DATA10
DBG_DATA11
DBG_DATA12
DBG_DATA13
DBG_DATA14
DBG_DATA15
DBG_DATA16
DBG_DATA17
DBG_DATA18
DBG_DATA19
DBG_DATA20
DBG_DATA21
DBG_DATA22
DBG_DATA23
SMBCLK
SMBus
SMBDATA
SCL
I2C
SDA
GENERAL PURPOSE I/O
GPIO_0
GPIO_1
GPIO_2
GPIO_5_AC_BATT
GPIO_6_TACH
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21
GPIO_22_ROMCSB
CLKREQB
GPIO_29
GPIO_30
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE
GENERICF
GENERICG
CEC_1
HPD1
DBG_VREFG
BACO
PX_EN
DEBUG
TESTEN
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
THERMAL
DPLUS
DMINUS
GPIO_28_FDO
TS_A
TSVDD
TSVSS
U33B
NC_TXCAP_DPA3P
NC_TXCAM_DPA3N
NC_TX0P_DPA2P
NC_TX0M_DPA2N
DPA
NC_TX1P_DPA1P
NC_TX1M_DPA1N
NC_TX2P_DPA0P
NC_TX2M_DPA0N
NC_TXCBP_DPB3P
NC_TXCBM_DPB3N
NC_TX3P_DPB2P
NC_TX3M_DPB2N
DPB
NC_TX4P_DPB1P
NC_TX4M_DPB1N
NC_TX5P_DPB0P
NC_TX5M_DPB0N
NC_TXCCP_DPC3P
NC_TXCCM_DPC3N
NC_TX0P_DPC2P
NC_TX0M_DPC2N
DPC
NC_TX1P_DPC1P
NC_TX1M_DPC1N
NC_TX2P_DPC0P
NC_TX2M_DPC0N
NC_TXCDP_DPD3P
NC_TXCDM_DPD3N
NC_TX3P_DPD2P
NC_TX3M_DPD2N
DPD
NC_TX4P_DPD1P
NC_TX4M_DPD1N
NC_TX5P_DPD0P
NC_TX5M_DPD0N
DAC1
MLPS
DDC/AUX
NC_DDCCLK_AUX3P
NC_DDCDATA_AUX3N
NC_DDCCLK_AUX4P
NC_DDCDATA_AUX4N
NC_DDCCLK_AUX5P
NC_DDCDATA_AUX5N
NC_DDCCLK_AUX6P
NC_DDCDATA_AUX6N
EV@Mars_M2
AVSSN#1
AVSSN#2
AVSSN#3
HSYNC
VSYNC
RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
NC_SVI2
NC_SVI2
NC_SVI2
NC_TSVSSQ
DDC1CLK
DDC1DATA
DDC2CLK
DDC2DATA
DDCVGACLK
DDCVGADATA
AU24
AV23
AT25
AR24
AU26
AV25
AT27
AR26
AR30
AT29
AV31
AU30
AR32
AT31
AT33
AU32
AU14
AV13
AT15
AR14
AU16
AV15
AT17
AR16
AU20
AT19
AT21
AR20
AU22
AV21
AT23
AR22
AD39
R
AD37
AE36
G
AD35
AF37
B
AE38
AC36
AC38
AB34
AD34
AE34
AC33
AC34
V13
NC#1
U13
NC#2
AC31
AD30
AC32
NC#5
AD32
AF32
NC#7
AA29
NC#8
AG21
NC#9
NC_TSVSSQ should be tied
to GND on Thames/Whistler/Seymour
AF33
PS_0 should be tied to GND on
Thames/Whistler/Seymour
AM34
PS_0
AD31
PS_1
AG31
PS_2
AD33
PS_3
PS_1,PS_2, PS_3 are NC on
Thames/Whistler/Seymour
AM26
AN26
AM27
AUX1P
AL27
AUX1N
AM19
AL19
AN20
AUX2P
AM20
AUX2N
AL30
AM30
AL29
AM29
AN21
AM21
AK30
AK29
AJ30
AJ31
T20
T22
T21
GPU_HSYNC [15]
GPU_VSYNC [15]
R252 EV@499/F_4
AVDD
VDD1DI
T2
T1
T13
T14
T15
T19
T17
T12
T4
PS_0
PS_1
PS_2
PS_3
PS_3 [15]
DAC1 Analog Power
AVDD
C715
Mars@0.1U/10V_4X
VDD1DI
C714
Mars@0.1U/10V_4X
Close to ASIC
11001 11000 00000 for Mars
PS_0 PS_1 PS_2
C420
*EV@0.1U/10V_4X
VDDC_CT VDDC_CT VDDC_CT
R285
EV@8.45K/F_4
R_pu
R286
R_pdCa
EV@2K/F_4
C412
*EV@0.1U/10V_4X
R_pu
R_pdCa
C716
Mars@1U/6.3V_4X
C713
Mars@1U/6.3V_4X
R266
*EV@8.45K/F_4
R267
EV@4.75K/F_4
1.8V@18mA
C717
Mars@4.7U/6.3V_6X
DAC1 Digital Power
1.8V@117mA
C712
Mars@4.7U/6.3V_6X
Mars@BLM15BD121SN1D_300MAL35
Mars@BLM15BD121SN1D_300MAL34
01000 for Sun
PS_2
C774
Mars@0.68U/6.3V_4X
RevB 1221 Add for Mars
System Memory Aperture size
PS0[3:1]
ROMIDCFG[2:0]
128M
256M
64M
000
001
010
011Reserved
MLPS
R_pu R_pd
4.75K
NC
2K
8.45K
2K
4.53K
4.99K
6.98K
4.99K
4.53K
5.62K
3.24K
3.4K
10K
NC
Ca Bits [5:4]
680nF
82nF
10nF
NC
00
01
10
11
Bits [3:1]
000
001
010
011
100
101
110
1114.75K
P/N
CH4681K9B00 X5R
CH4681JEB00 X6S
CH3823K1B00
CH31003KB11
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Mars_M2/ GPIO_DP_CRT_I2C
Mars_M2/ GPIO_DP_CRT_I2C
Mars_M2/ GPIO_DP_CRT_I2C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Ra P/N
2K
3.24K
3.4K
4.53K
4.75K
4.99K
5.62K
6.98K
8.45K
10K
MLPS Bit Bits [5:1]
PS_0
PS_1
PS_2
PS_3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
+1.8V_GPU
R_pu
R_pdCa
C419
EV@0.082U/16V_4X
CS22002FB19
CS23242FB09
CS23402FB08
CS24532FB08
CS24752FB12
CS24992FB26
CS25622FB18
CS26982FB01
CS28452FB12
CS31002FB26
11001
11000
01000
11XXX
BD9
BD9
BD9
13 41Wednesday, January 30, 2013
13 41Wednesday, January 30, 2013
13 41Wednesday, January 30, 2013
13
R283
*EV@10K/F_4
R284
EV@4.75K/F_4
A1A
A1A
A1A
<VGA>
0.95V@16mA for Sun
0.95V@330mA for Mars
+0.95V_GPU
1.8V@90mA for Sun
1.8V@130mA for Mars
1002 AMD FAE suggest 220ohm
+1.8V_GPU
1.8V@75mA for Sun
1.8V@75mA for Mars
+1.8V_GPU
0.95V@100mA for Sun
0.95V@100mA for Mars
+0.95V_GPU
1002 AMD FAE suggest 120ohm
EV@PBY160808T-501Y-N_1.2AL11
C434
EV@10U/6.3V_6X
Memory phase-locked loop power.
Dedicated analog power pin for the memory PLLs.
EV@FCM1608KF-221T05_500MAL38
C735
EV@10U/6.3V_6X
Engine phase-locked loop power.
Dedicated analog power pin for the engine and UVD PLLs.
EV@BLM15BD121SN1D_300MAL12
C445
EV@10U/6.3V_6X
Engine phase-locked loop power.
Dedicated digital power pin for the engine and UVD PLLs.
EV@BLM15BD121SN1D_300MAL14
C451
EV@10U/6.3V_6X
C431
EV@1U/6.3V_4X
C732
EV@1U/6.3V_4X
C443
EV@1U/6.3V_4X
C449
EV@1U/6.3V_4X
DPEF_VDD18
1.8V@20mA for Sun
DPLL_VDDC
DPLL_VDDC
C430
EV@0.1U/10V_4X
MPLL_PVDD
C728
EV@0.1U/10V_4X
SPLL_PVDD
C444
EV@0.1U/10V_4X
SPLL_VDDC
C450
EV@0.1U/10V_4X
R278 *EV@0_4
R277 *EV@0_4
DPEF_VDD18
AM32
AN31
AN32
AM10
AN10
AF30
AF31
H7
H8
AN9
DP_VDDR
DP_VDDC
DP_VSSR
MPLL_PVDD
MPLL_PVDD
SPLL_PVDD
SPLL_VDDC
SPLL_PVSS
NC_XTAL_PVDD
NC_XTAL_PVSS
PART 9 0F 9
PLLS/XTAL
EV@Mars_M2
14
DPE/DPF/LVDS
U33I
AV33
GPU_XTALIN
XTALIN
XTALOUT
XO_IN
XO_IN2
CLKTESTA
CLKTESTB
AU34
AW34
AW35
AK10
AL10
GPU_XTALOUT
CLKTESTA
CLKTESTB
*EV@0.1U/10V_4X
R289
EV@1M/F_4
R288 EV@0_4
T31
T30
C447
R314
*EV@51.1/F_4
C433 EV@27P/50V_4N
23
Y2
EV@27MHZ_10
4 1
C432 EV@27P/50V_4N
C446
*EV@0.1U/10V_4X
R313
*EV@51.1/F_4
PART 7 0F 9
LVDS CONTROL
LVTMDP
U33G
TXCBP_DPB3P
TXCBM_DPB3N
TX3P_DPB2P
TX3M_DPB2N
TX4P_DPB1P
TX4M_DPB1N
TX5P_DPB0P
TX5M_DPB0N
NC_TXOUT_U3P
NC_TXOUT_U3N
TXCAP_DPA3P
TXCAM_DPA3N
TX0P_DPA2P
TX0M_DPA2N
TX1P_DPA1P
TX1M_DPA1N
TX2P_DPA0P
TX2M_DPA0N
NC_TXOUT_L3P
NC_TXOUT_L3N
EV@Mars_M2
RSVD
RSVD
AK27
AJ27
AK35
AL36
AJ38
AK37
AH35
AJ36
AG38
AH37
AF35
AG36
AP34
AR34
AW37
AU35
AR37
AU39
AP35
AR35
AN36
AP37
R259 *EV@10K/F_4
R258 *EV@10K/F_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROJECT :
Mars_M2/ XTAL_LVDS
Mars_M2/ XTAL_LVDS
Mars_M2/ XTAL_LVDS
BD9
BD9
BD9
14 41Tuesday, December 25, 2012
14 41Tuesday, December 25, 2012
14 41Tuesday, December 25, 2012
A1A
A1A
A1A
<VGA>
Close to ASIC
10XXX for Mars
11XXX for Sun
PS_3[13]
RevB 1221 Add for Mars
MLPS
R_pu R_pd Bits [3:1]
NC
8.45K
4.53K
6.98K
4.53K
3.24K
3.4K
GPU_GENERICC[13]
GPU_GPIO11[13]
GPU_GPIO12[13]
GPU_GPIO13[13]
GPU_GPIO22[13]
GENIL_VSYNC[13]
GPU_HSYNC[13]
GPU_VSYNC[13]
GENIL_CLK[13]
GPU_GPIO21[13]
GPU_GPIO10[13]
PS_3
GPU_GPIO0[13,40]
GPU_GPIO1[13]
GPU_GPIO2[13]
GPU_GPIO9[13]
GPU_GPIO8[13]
4.75K
4.99K
4.99K
5.62K
2K
2K
10K
NC
R293 *EV@10K/F_4
R294 EV@10K/F_4
R303 *EV@10K/F_4
R302 *EV@10K/F_4
R296 EV@10K/F_4
R297 *EV@10K/F_4
R298 *EV@10K/F_4
R306 *EV@10K/F_4
R253 *EV@10K/F_4
R555 *EV@10K/F_4
R551 *EV@10K/F_4
R254 *EV@10K/F_4
R305 *EV@10K/F_4
R304 *EV@10K/F_4
R300 *EV@10K/F_4
R295 *EV@10K/F_4
R_pu
R_pdCa
C410
Mars@0.01U/25V_4X
000
001
010
011
100
101
110
1114.75K
VDDC_CT
R274
H2G@4.75K/F_4
R264
H1G@4.75K/F_4
+3V_GPU
R275
S1G@8.45K/F_4
R262
SAM@2K/F_4
Ca Bits [5:4]
680nF
82nF
10nF
NC
R272
S2G@4.53K/F_4
R263
MICRON@4.99K/F_4
00
01
10
11
R276
M1G@6.98K/F_4
R596
H1GG@5.62K/F_4
P/N
CH4681K9B00
CH3823K1B00
CH31003KB11
RevB 1221 Add for 1GHz VRAM
R273
M2G@4.53K/F_4
R597
S1GG@10K/F_4
R598
H1GG@3.24K/F_4
R599
S1GG@3.4K/F_4
CONFIGURATION STRAPS -- SEE EACH DATABOOK FOR STRAP DETAILS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
STRAPS
MLPS_DISABLE
STRAP_TX_CFG_DRV_FULL_SWING
STRAP_TX_DEEMPH_EN
STRAP_BIF_GEN3_EN_A
STRAP_BIF_VGA_DIS
ROM_CONFIG[2:0]
STRAP_BIOS_ROM_EN
AUD[1]
AUD[0]
N/A
N/A
STRAP_BIF_CLK_PM_EN
RESERVED
RESERVED
AUD_PORT_CONN_PINSTRAP[2]
AUD_PORT_CONN_PINSTRAP[1]
AUD_PORT_CONN_PINSTRAP[0]
MLPS GPIO PIN
NA
GPIO_28_FDO
PS_1[4]
PS_1[5]
PS_1[1]
PS_2[4]
PS_0[3..1]
PS_2[3]
HSYNC
NA
VSYNC
NA
PS_0[4]
PS_1[3]
GENLK_CLK
PS_1[2]
GPIO8
GPIO21
NA
NA
GENERICC
PS_3[5]
PS_3[4]
PS_0[5]
DESCRIPTION OF DEFAULT SETTINGS
Enable MLPS, NA for Thames/Whistler/Seymour 0
0: Enable MLPS, disable GPIO PINSTRAP
1: Disable MLPS, enable GPIO PINSTRAP
Control the transmitter full-/half- swing mode
0: 50% Tx output swing
1: Full Tx output swing
PCIe transmitter, de-emphasis enable
0: Tx de-emphasis disabled
1: Tx de-emphasis enabled
PCIe GEN3 Capability
0: GEN3 not supported at power-on
1: GEN3 supported at power-on
VGA disable determines whether or not the card will be recognized as the system's
VGA controler (through the SUBCLASS field in the PCI configuration space)
0: VGA controller capacity enabled
1: The device will not be recognized as the system's VGA controller
Serial ROM type or Memory Aperture Size Select
If GPIO22 = 0, defines memory aperture size
If GPIO22 = 1, defines ROM type
100 - 512Kbit M25P05A (ST)
101 - 1Mbit M25P10A (ST)
101 - 2Mbit M25P20 (ST)
101 - 4Mbit M25P40 (ST)
101 - 8Mbit M25P80 (ST)
100 - 512Kbit Pm25LV512 (Chingis)
101 - 1Mbit Pm25LV010 (Chingis)
Enable external BIOS ROM device
0: Disabled
1: Enabled
00 - No audio function
01 - Audio for DP only
10 - Audio for DP and HDMI if dongle is detected
11 - Audio for both DP and HDMI
HDMI must only be enabled on systems that are legally entitled. It is the
responsibility of the system designer to ensure that the system is entitled to
support this feature.
Reserved for internal use only. Must be 1 at reset
Reserved
PCIe reference clock power management capability is reported in the PCI
0: The CLKREQB power management capability is disabled
1: The CLKREQB power management capability is enabled
Reserved
Reserved (for Thames/Whistler/Seymour only)
NA
NA
NA
STRAPS TO INDICATE THE NUMBER OF AUDIO CAPABLE DISPLAY OUTPUTS
111 = 0 usable endpoints
110 = 1 usable endpoints
101 = 2 usable endpoints
100 = 3 usable endpoints
011 = 4 usable endpoints
010 = 5 usable endpoints
001 = 6 usable endpoints
000 = all endpoints are usable
Power Up Reset Sequence
Default Setting
1
1
0 for Kabini
0
XXX
0
XX
1
0
0
0
0
XXX
15
Ra P/N
CS22002FB19
2K
CS23242FB09
3.24K
CS23402FB08
3.4K
CS24532FB08
4.53K
CS24752FB12
4.75K
CS24992FB26
4.99K
CS25622FB18
5.62K
CS26982FB01
6.98K
CS28452FB12
8.45K
CS31002FB26
10K
DDR3 Memory TYPE
Vendor P/N B/S P/N (QCI P/N)
H5TQ2G63DFR-11C
(128M*16)
Hynix
H5TC4G63AFR-11C
(256M*16)
MT41J128M16JT-107G:K
(128M*16)
Micron
MT41K256M16HA-107G:E
(256M*16)
K4W2G1646E-BC11
(128M*16)
Samsung
K4W4G1646B-HC11
(256M*16)
SizeVendor
AKD5MGWTW16 * 4 1GB
AKD5PGWTW05 * 4
AKD5DGSTL00 * 4
AKD5PGSTL00 * 4
2GB
1GB
2GB
1GB
2GB
MLPS
000
111
011
100
001
010
+5VRUN/+3VRUN/VDDR3
RUNPWROK
MVDDQ/VDDC/VDDCI
1.8V_IO/PCIE_VDDC
PWRGOOD
PCIE_RST#(PERSTB)
PCIE Clock
20ms max
100ms min 100ms min
100us min
Asic in Reset Har dware Reset Sequ ence DFG Spac e Ready
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
100ms max
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Mars_M2/ STRAPS_Thermal
Mars_M2/ STRAPS_Thermal
Mars_M2/ STRAPS_Thermal
BD9
BD9
BD9
A1A
A1A
15 41Tuesday, December 25, 2012
15 41Tuesday, December 25, 2012
15 41Tuesday, December 25, 2012
A1A
+1.5V_GPU
<VGA>
C343
EV@10U/6.3V_6X
C332
EV@2.2U/6.3V_4X
C407
*EV@0.1U/10V_4X
C385
*EV@0.1U/10V_4X
C657
EV@10U/6.3V_6X
C333
EV@2.2U/6.3V_4X
C646
*EV@0.1U/10V_4X
C375
*EV@0.1U/10V_4X
(3.3V@25mA for Sun, Mars)
(1.8V@300mA for Mars; NC for Sun)
(1.5V@930mA/ Sun DDR3)
(1.5V@1.5A/Mars DDR3 128bits)
(1.5V@1.0A Mars DDR3 64bits)
C408
EV@10U/6.3V_6X
C330
EV@2.2U/6.3V_4X
+1.8V_GPU
+3V_GPU
+1.8V_GPU
C353
*EV@4.7U/6.3V_6X
C336
EV@2.2U/6.3V_4X
C645
*EV@0.1U/10V_4X
C401
*EV@0.1U/10V_4X
Level translation between core and I/O,
excluding memory receivers.
C386
*EV@0.1U/10V_4X
C363
*EV@0.1U/10V_4X
(1.8V@13mA for Sun, Mars)
EV@BLM15BD121SN1D_300MAL9
I/O power for 3.3-V pins, such as GPIOs.
1002 AMD FAE suggest 120ohm
EV@BLM15BD121SN1D_300MAL10
Power for all DVP pins; DVPDATA_[23:0]—DVO or GPIO.
1002 AMD FAE suggest 120ohm
Mars@FCM1608KF-121T04_400MAL37
C739
*EV@10U/6.3V_6X
C350
*EV@2.2U/6.3V_4X
+
C642
EV@100U/6.3V_3528P_E45b
C438
EV@10U/6.3V_6X
C743
Mars@10U/6.3V_6X
VGPU_CORE_VCCSSENSE[40]
VCORE_SEN/RTN route a differtial pair.
VGPU_CORE_VSSSENSE[40]
C733
*EV@10U/6.3V_6X
C394
*EV@2.2U/6.3V_4X
VDDC_CT
C441
EV@10U/6.3V_6X
C436
EV@1U/6.3V_4X
C740
Mars@1U/6.3V_4X
C341
EV@2.2U/6.3V_4X
C439
EV@1U/6.3V_4X
VDDR3
C426
EV@1U/6.3V_4X
VDDR4
C741
Mars@0.1U/10V_4X
R279 EV@0_4
R280 EV@0_4
VDDC_CT
C440
EV@0.1U/10V_4X
C409
EV@1U/6.3V_4X
AD11
AG10
AF26
AF27
AG26
AG27
AF23
AF24
AG23
AG24
AD12
AF11
AF12
AF13
AF15
AG11
AG13
AG15
AF28
AG28
AH29
AC7
AF7
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
K11
K13
L12
L16
L21
L23
L26
M11
N11
R11
U11
Y11
J7
J9
K8
L7
P7
U7
Y7
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDD_CT
VDD_CT
VDD_CT
VDD_CT
VDDR3
VDDR3
VDDR3
VDDR3
VDDR4
VDDR4
VDDR4
VDDR4
VDDR4
VDDR4
VDDR4
VDDR4
FB_VDDC
FB_VDDCI
FB_GND
MEM I/O
LEVEL
TRANSLATION
I/O
DVP
VOLTAGE
SENESE
PART 5 0F 9
U33E
EV@Mars_M2
NC_PCIE_VDDR
NC_PCIE_VDDR
NC_PCIE_VDDR
NC_PCIE_VDDR
NC_PCIE_VDDR
NC_PCIE_VDDR
NC_BIF_VDDC
NC_BIF_VDDC
PCIE_PVDD
PCIE
BACO
CORE
ISOLATED
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
BIF_VDDC
BIF_VDDC
CORE I/O
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
On Mars except for AB37, all other balls can be NC
AA31
AA32
AA33
AA34
W30
Y31
V28
W29
AB37
G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28
N27
T27
AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AH22
AH27
AH28
M26
N24
R18
R21
R23
R26
T17
T20
T22
T24
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28
AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13
PCIE_VDDR
C372
EV@0.01U/25V_4X
C325
EV@1U/6.3V_4X
(0.95V@1.4A for Sun, Mars)
C335
EV@1U/6.3V_4X
C360
EV@1U/6.3V_4X
C366
EV@1U/6.3V_4X
C373
EV@1U/6.3V_4X
VDDCI
C309
*EV@1U/6.3V_4X
C334
*EV@10U/6.3V_6X
C388
EV@1U/6.3V_4X
C369
EV@1U/6.3V_4X
C406
EV@1U/6.3V_4X
C364
EV@0.1U/10V_4X
C324
EV@1U/6.3V_4X
C351
EV@10U/6.3V_6X
C383
EV@1U/6.3V_4X
C338
*EV@10U/6.3V_6X
C359
EV@1U/6.3V_4X
C326
EV@1U/6.3V_4X
+0.95V_GPU
C355
EV@1U/6.3V_4X
C397
EV@1U/6.3V_4X
C757
EV@1U/6.3V_4X
C405
EV@1U/6.3V_4X
C354
*EV@1U/6.3V_4X
PCIe digital power supply.
(0.95V@2.5A for Sun, Mars)
C340
EV@1U/6.3V_4X
C293
EV@1U/6.3V_4X
Dedicated core power, provides power to the internal logic.
C346
EV@1U/6.3V_4X
C389
EV@1U/6.3V_4X
C750
EV@1U/6.3V_4X
C368
EV@1U/6.3V_4X
Isolated (clean) core power for the l/O logic.
(0.775V~1.125V@5A/Sun)
C356
*EV@1U/6.3V_4X
C371
EV@10U/6.3V_6X
PCIe IO power.
(1.8V@100mA for Sun, Mars)
L7 EV@HCB1608KF-181T15_1.5A
C377
EV@10U/6.3V_6X
+0.95V_GPU
C345
EV@1U/6.3V_4X
Always connect to PCIE_VDDC for
both BACO & non-BACO designs.
C302
EV@1U/6.3V_4X
(0.775~1.125V@30A)
C348
EV@1U/6.3V_4X
C390
EV@1U/6.3V_4X
C358
EV@10U/6.3V_6X
C367
EV@1U/6.3V_4X
L6 EV@HCB1608KF-121T30_3A
L5 EV@HCB1608KF-121T30_3A
C349
*EV@1U/6.3V_4X
C376
EV@1U/6.3V_4X
C370
EV@1U/6.3V_4X
C347
EV@1U/6.3V_4X
C395
EV@1U/6.3V_4X
C380
EV@10U/6.3V_6X
C391
EV@1U/6.3V_4X
C298
EV@1U/6.3V_4X
+VGPU_CORE
C339
*EV@1U/6.3V_4X
+1.8V_GPU
C287
EV@10U/6.3V_6X
C396
EV@1U/6.3V_4X
C398
EV@1U/6.3V_4X
C756
EV@1U/6.3V_4X
C379
EV@1U/6.3V_4X
+VGPU_CORE
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
C308
EV@10U/6.3V_6X
C362
EV@1U/6.3V_4X
C745
EV@1U/6.3V_4X
C344
EV@1U/6.3V_4X
Mars_M2/ MainPower
Mars_M2/ MainPower
Mars_M2/ MainPower
C402
EV@1U/6.3V_4X
C381
EV@10U/6.3V_6X
C404
EV@1U/6.3V_4X
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
16
C393
EV@1U/6.3V_4X
C357
EV@10U/6.3V_6X
BD9
BD9
BD9
16 41Tuesday, December 25, 2012
16 41Tuesday, December 25, 2012
16 41Tuesday, December 25, 2012
A1A
A1A
A1A
<VGA>
+1.8V_GPU
EV@PBY160808T-501Y-N_1.2AL36
C723
EV@10U/6.3V_6X
DPEF_VDD18
DPEF_VDD18
C721
EV@1U/6.3V_4X
DPEF_VDD18_MARS
R563
MARS@0_6
C722
EV@0.1U/10V_4X
Reserve for Mars
R570 *EV@150/F_4
R572 *EV@150/F_4
R567 EV@150/F_4
DP_VDDR DP_VDDC
AN24
NC
AP24
NC
AP25
NC
AP26
NC
AU28
NC
AV29
NC
AP20
NC
AP21
NC
AP22
NC
AP23
NC
AU18
NC
AV19
NC
AH34
DP_VDDR
AJ34
DP_VDDR
AF34
DP_VDDR
AG34
DP_VDDR
AM37
DP_VDDR
AL38
DP_VDDR
CALIBRATION
AW28
NC_DPAB_CALR
AW18
NC_DPCD_CALR
AM39
DP_CALR
PART 8 0F 9
U33H
DP GND
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
17
AP31
AP32
AN33
AP33
AP13
NC
AT13
NC
AP14
NC
AP15
NC
AL33
AM33
AK33
AK34
AN27
AP27
AP28
AW24
AW26
AN29
AP29
AP30
AW30
AW32
AN17
AP16
AP17
AW14
AW16
AN19
AP18
AP19
AW20
AW22
AN34
AP39
AR39
AU37
AF39
AH39
AK39
AL34
AV27
AR28
AV17
AR18
AN38
AM35
C729
Mars@10U/6.3V_6X
C744
Mars@10U/6.3V_6X
C727
Mars@1U/6.3V_4X
C736
Mars@1U/6.3V_4X
For ESD
+0.95V_GPU
(0.95V@280mA/link for Mars)
C726
Mars@0.1U/10V_4X
DPLL_VDDC_MARS
C737
Mars@0.1U/10V_4X
(0.95V@280mA/link for Mars)(1.8V@237mA/link for Mars)
C411
EV@39P/50V_4N
R571 MARS@0_6
C310
EV@39P/50V_4N
DPLL_VDDC
EV@Mars_M2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROJECT :
Mars_M2/ DP_Powers
Mars_M2/ DP_Powers
Mars_M2/ DP_Powers
BD9
BD9
BD9
17 41Tuesday, December 25, 2012
17 41Tuesday, December 25, 2012
17 41Tuesday, December 25, 2012
A1A
A1A
A1A
<VGA>
AB39
W31
W34
U33F
PART 6 0F 9
PCIE_VSS
E39
PCIE_VSS
F34
PCIE_VSS
F39
PCIE_VSS
G33
PCIE_VSS
G34
PCIE_VSS
H31
PCIE_VSS
H34
PCIE_VSS
H39
PCIE_VSS
J31
PCIE_VSS
J34
PCIE_VSS
K31
PCIE_VSS
K34
PCIE_VSS
K39
PCIE_VSS
L31
PCIE_VSS
L34
PCIE_VSS
M34
PCIE_VSS
M39
PCIE_VSS
N31
PCIE_VSS
N34
PCIE_VSS
P31
PCIE_VSS
P34
PCIE_VSS
P39
PCIE_VSS
R34
PCIE_VSS
T31
PCIE_VSS
T34
PCIE_VSS
T39
PCIE_VSS
U31
PCIE_VSS
U34
PCIE_VSS
V34
PCIE_VSS
V39
PCIE_VSS
PCIE_VSS
PCIE_VSS
Y34
PCIE_VSS
Y39
PCIE_VSS
F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
EV@Mars_M2
NC_EVDDQ2
VSS_MECH
VSS_MECH
VSS_MECH
A3
GND
A37
GND
AA16
GND
AA18
GND
AA2
GND
AA21
GND
AA23
GND
AA26
GND
AA28
GND
AA6
GND
AB12
GND
AB15
GND
AB17
GND
AB20
GND
AB22
GND
AB24
GND
AB27
GND
AC11
GND
AC13
GND
AC16
GND
AC18
GND
AC2
GND
AC21
GND
AC23
GND
AC26
GND
AC28
GND
AC6
GND
AD15
GND
AD17
GND
AD20
GND
AD22
GND
AD24
GND
AD27
GND
AD9
GND
AE2
GND
AE6
GND
AF10
GND
AF16
GND
AF18
GND
AF21
GND
AG17
GND
AG2
GND
AG20
GND
AG22
AG6
GND
AG9
GND
AH21
GND
AJ10
GND
AJ11
GND
AJ2
GND
AJ28
GND
AJ6
GND
AK11
GND
AK31
GND
AK7
GND
AL11
GND
AL14
GND
AL17
GND
AL2
GND
AL20
GND
AL23
GND
AL26
GND
AL32
GND
AL6
GND
AL8
GND
AM11
GND
AM31
GND
AM9
GND
AN11
GND
AN2
GND
AN30
GND
AN6
GND
AN8
GND
AP11
GND
AP7
GND
AP9
GND
AR5
GND
B11
GND
B13
GND
B15
GND
B17
GND
B19
GND
B21
GND
B23
GND
B25
GND
B27
GND
B29
GND
B31
GND
B33
GND
B7
GND
B9
GND
C1
GND
C39
GND
E35
GND
E5
GND
F11
GND
F13
GND
A39
AW1
AW39
Mars AG22 NC
18
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROJECT :
Mars_M2/ GND
Mars_M2/ GND
Mars_M2/ GND
BD9
BD9
BD9
18 41Tuesday, December 25, 2012
18 41Tuesday, December 25, 2012
18 41Tuesday, December 25, 2012
A1A
A1A
A1A
<VGA>
VMA_RDQS[7..0][20]
VMA_WDQS[7..0][20]
Place MVREF dividers and Caps close to ASIC
+1.5V_GPU
R515
Ra
EV@40.2/F_4
R518
Rb
EV@100/F_4
+1.5V_GPU
R219
Ra
EV@40.2/F_4
VMA_DQ[63..0][20]
VMA_DM[7..0][20]
VMA_MA[14..0][20]
VMA_BA0[20]
VMA_BA1[20]
VMA_BA2[20]
(0.7*VDDR1)
C680
EV@1U/6.3V_4X
(0.7*VDDR1)
VMA_DQ[63..0]
VMA_DM[7..0]
VMA_RDQS[7..0]
VMA_WDQS[7..0]
VMA_MA[14..0]
VMA_BA0
VMA_BA1
VMA_BA2
VMA_DQ0
VMA_DQ1
VMA_DQ2
VMA_DQ3
VMA_DQ4
VMA_DQ5
VMA_DQ6
VMA_DQ7
VMA_DQ8
VMA_DQ9
VMA_DQ10
VMA_DQ11
VMA_DQ12
VMA_DQ13
VMA_DQ14
VMA_DQ15
VMA_DQ16
VMA_DQ17
VMA_DQ18
VMA_DQ19
VMA_DQ20
VMA_DQ21
VMA_DQ22
VMA_DQ23
VMA_DQ24
VMA_DQ25
VMA_DQ26
VMA_DQ27
VMA_DQ28
VMA_DQ29
VMA_DQ30
VMA_DQ31
VMA_DQ32
VMA_DQ33
VMA_DQ34
VMA_DQ35
VMA_DQ36
VMA_DQ37
VMA_DQ38
VMA_DQ39
VMA_DQ40
VMA_DQ41
VMA_DQ42
VMA_DQ43
VMA_DQ44
VMA_DQ45
VMA_DQ46
VMA_DQ47
VMA_DQ48
VMA_DQ49
VMA_DQ50
VMA_DQ51
VMA_DQ52
VMA_DQ53
VMA_DQ54
VMA_DQ55
VMA_DQ56
VMA_DQ57
VMA_DQ58
VMA_DQ59
VMA_DQ60
VMA_DQ61
VMA_DQ62
VMA_DQ63
MVREFDA
MVREFSA
R240 EV@120/F_4
R299 *EV@120/F_4
AG12
AH12
C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5
L18
L20
L27
N12
M12
M27
DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31
MVREFDA
MVREFSA
NC_MEM_CALRN0
NC_MEM_CALRN1
NC_MEM_CALRN2
NC_MEM_CALRP1
MEM_CALRP0
NC_MEM_CALRP2
PART 3 0F 9
GDDR5/DDR3
MEMORY INTERFACE A
U33C
MAA1_5/MAA_BA2
MAA1_6/MAA_BA0
MAA1_7/MAA_BA1
WCKA0_0/DQMA_0
WCKA0B_0/DQMA_1
WCKA0_1/DQMA_2
WCKA0B_1/DQMA_3
WCKA1_0/DQMA_4
WCKA1B_0/DQMA_5
WCKA1_1/DQMA_6
WCKA1B_1/DQMA_7
EDCA0_0/QSA_0
EDCA0_1/QSA_1
EDCA0_2/QSA_2
EDCA0_3/QSA_3
EDCA1_0/QSA_4
EDCA1_1/QSA_5
EDCA1_2/QSA_6
EDCA1_3/QSA_7
DDBIA0_0/QSA_0B
DDBIA0_1/QSA_1B
DDBIA0_2/QSA_2B
DDBIA0_3/QSA_3B
DDBIA1_0/QSA_4B
DDBIA1_1/QSA_5B
DDBIA1_2/QSA_6B
DDBIA1_3/QSA_7B
EV@Mars_M2
MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
ADBIA0/ODTA0
ADBIA1/ODTA1
CLKA0
CLKA0B
CLKA1
CLKA1B
RASA0B
RASA1B
CASA0B
CASA1B
CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1
CKEA0
CKEA1
WEA0B
WEA1B
MAA0_8/MAA_13
MAA1_8/MAA_14
MAA0_9/MAA_15
MAA1_9/RSVD
G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17
A32
C32
D23
E22
C14
A14
E10
D9
C34
D29
D25
E20
E16
E12
J10
D7
A34
E30
E26
C20
C16
C12
J11
F8
J21
G19
H27
G27
J14
H14
K23
K19
K20
K17
K24
K27
M13
K16
K21
J20
K26
L15
H23
J19
M21
M20
VMA_MA0
VMA_MA1
VMA_MA2
VMA_MA3
VMA_MA4
VMA_MA5
VMA_MA6
VMA_MA7
VMA_MA8
VMA_MA9
VMA_MA10
VMA_MA11
VMA_MA12
VMA_BA2
VMA_BA0
VMA_BA1
VMA_DM0
VMA_DM1
VMA_DM2
VMA_DM3
VMA_DM4
VMA_DM5
VMA_DM6
VMA_DM7
VMA_RDQS0
VMA_RDQS1
VMA_RDQS2
VMA_RDQS3
VMA_RDQS4
VMA_RDQS5
VMA_RDQS6
VMA_RDQS7
VMA_WDQS0
VMA_WDQS1
VMA_WDQS2
VMA_WDQS3
VMA_WDQS4
VMA_WDQS5
VMA_WDQS6
VMA_WDQS7
VMA_CLK0
VMA_CLK0#
VMA_CLK1
VMA_CLK1#
VMA_RAS0#
VMA_RAS1#
VMA_CAS0#
VMA_CAS1#
VMA_CS0#
VMA_CS1#
VMA_CKE0
VMA_CKE1
VMA_WE0#
VMA_WE1#
VMA_MA13
VMA_MA14
VMA_ODT0 [20]
VMA_ODT1 [20]
VMA_CLK0 [20]
VMA_CLK0# [20]
VMA_CLK1 [20]
VMA_CLK1# [20]
VMA_RAS0# [20]
VMA_RAS1# [20]
VMA_CAS0# [20]
VMA_CAS1# [20]
VMA_CS0# [20]
VMA_CS1# [20]
VMA_CKE0 [20]
VMA_CKE1 [20]
VMA_WE0# [20]
VMA_WE1# [20]
VMB_DQ[63..0][21]
VMB_DM[7..0][21]
VMB_RDQS[7..0][21]
VMB_WDQS[7..0][21]
VMB_MA[14..0][21]
VMB_BA0[21]
VMB_BA1[21]
VMB_BA2[21]
Place MVREF dividers and Caps close to ASIC
+1.5V_GPU
(0.7*VDDR1)
R575
Ra
EV@40.2/F_4
Rb
+1.5V_GPU
Ra
R576
EV@100/F_4
R580
EV@40.2/F_4
C731
EV@1U/6.3V_4X
(0.7*VDDR1)
VMB_DQ[63..0]
VMB_DM[7..0]
VMB_RDQS[7..0]
VMB_WDQS[7..0]
VMB_MA[14..0]
VMB_BA0
VMB_BA1
VMB_BA2
VMB_DQ0
VMB_DQ1
VMB_DQ2
VMB_DQ3
VMB_DQ4
VMB_DQ5
VMB_DQ6
VMB_DQ7
VMB_DQ8
VMB_DQ9
VMB_DQ10
VMB_DQ11
VMB_DQ12
VMB_DQ13
VMB_DQ14
VMB_DQ15
VMB_DQ16
VMB_DQ17
VMB_DQ18
VMB_DQ19
VMB_DQ20
VMB_DQ21
VMB_DQ22
VMB_DQ23
VMB_DQ24
VMB_DQ25
VMB_DQ26
VMB_DQ27
VMB_DQ28
VMB_DQ29
VMB_DQ30
VMB_DQ31
VMB_DQ32
VMB_DQ33
VMB_DQ34
VMB_DQ35
VMB_DQ36
VMB_DQ37
VMB_DQ38
VMB_DQ39
VMB_DQ40
VMB_DQ41
VMB_DQ42
VMB_DQ43
VMB_DQ44
VMB_DQ45
VMB_DQ46
VMB_DQ47
VMB_DQ48
VMB_DQ49
VMB_DQ50
VMB_DQ51
VMB_DQ52
VMB_DQ53
VMB_DQ54
VMB_DQ55
VMB_DQ56
VMB_DQ57
VMB_DQ58
VMB_DQ59
VMB_DQ60
VMB_DQ61
VMB_DQ62
VMB_DQ63
MVREFDB
MVREFSB
AA12
19
U33D
PART 4 0F 9
DQB0_0
DQB0_1
DQB0_2
DQB0_3
DQB0_4
DQB0_5
DQB0_6
DQB0_7
DQB0_8
DQB0_9
DQB0_10
DQB0_11
DQB0_12
DQB0_13
DQB0_14
DQB0_15
DQB0_16
DQB0_17
DQB0_18
DQB0_19
DQB0_20
DQB0_21
DQB0_22
DQB0_23
DQB0_24
DQB0_25
DQB0_26
DQB0_27
DQB0_28
DQB0_29
DQB0_30
DQB0_31
DQB1_0
DQB1_1
DQB1_2
DQB1_3
DQB1_4
DQB1_5
DQB1_6
DQB1_7
DQB1_8
DQB1_9
DQB1_10
DQB1_11
DQB1_12
DQB1_13
DQB1_14
DQB1_15
DQB1_16
DQB1_17
DQB1_18
DQB1_19
DQB1_20
DQB1_21
DQB1_22
DQB1_23
DQB1_24
DQB1_25
DQB1_26
DQB1_27
DQB1_28
DQB1_29
DQB1_30
DQB1_31
MVREFDB
MVREFSB
GDDR5/DDR3
MEMORY INTERFACE B
MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
WCKB0_0/DQMB_0
WCKB0B_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0B_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1B_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1B_1/DQMB_7
EDCB0_0/QSB_0
EDCB0_1/QSB_1
EDCB0_2/QSB_2
EDCB0_3/QSB_3
EDCB1_0/QSB_4
EDCB1_1/QSB_5
EDCB1_2/QSB_6
EDCB1_3/QSB_7
DDBIB0_0/QSB_0B
DDBIB0_1/QSB_1B
DDBIB0_2/QSB_2B
DDBIB0_3/QSB_3B
DDBIB1_0/QSB_4B
DDBIB1_1/QSB_5B
DDBIB1_2/QSB_6B
DDBIB1_3/QSB_7B
ADBIB0/ODTB0
ADBIB1/ODTB1
MAB0_8/MAB_13
MAB1_8/MAB_14
MAB0_9/MAB_15
EV@Mars_M2
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1
CLKB0
CLKB0B
CLKB1
CLKB1B
RASB0B
RASB1B
CASB0B
CASB1B
CSB0B_0
CSB0B_1
CSB1B_0
CSB1B_1
CKEB0
CKEB1
WEB0B
WEB1B
MAB1_9/RSVD
DRAM_RST
P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9
H3
H1
T3
T5
AE4
AF5
AK6
AK5
F6
K3
P3
V5
AB5
AH1
AJ9
AM5
G7
K1
P1
W4
AC4
AH3
AJ8
AM3
T7
W7
L9
L8
AD8
AD7
T10
Y10
W10
AA10
P10
L10
AD10
AC10
U10
AA11
N10
AB11
T8
W8
U12
V12
AH11
VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_BA2
VMB_BA0
VMB_BA1
VMB_DM0
VMB_DM1
VMB_DM2
VMB_DM3
VMB_DM4
VMB_DM5
VMB_DM6
VMB_DM7
VMB_RDQS0
VMB_RDQS1
VMB_RDQS2
VMB_RDQS3
VMB_RDQS4
VMB_RDQS5
VMB_RDQS6
VMB_RDQS7
VMB_WDQS0
VMB_WDQS1
VMB_WDQS2
VMB_WDQS3
VMB_WDQS4
VMB_WDQS5
VMB_WDQS6
VMB_WDQS7
VMB_CLK0
VMB_CLK0#
VMB_CLK1
VMB_CLK1#
VMB_RAS0#
VMB_RAS1#
VMB_CAS0#
VMB_CAS1#
VMB_CS0#
VMB_CS1#
VMB_CKE0
VMB_CKE1
VMB_WE0#
VMB_WE1#
VMB_MA13
VMB_MA14
GPU_DRAM_RST
QSB[7..0]
QSB#[7..0]
VMB_ODT0 [21]
VMB_ODT1 [21]
VMB_CLK0 [21]
VMB_CLK0# [21]
VMB_CLK1 [21]
VMB_CLK1# [21]
VMB_RAS0# [21]
VMB_RAS1# [21]
VMB_CAS0# [21]
VMB_CAS1# [21]
VMB_CS0# [21]
VMB_CS1# [21]
VMB_CKE0 [21]
VMB_CKE1 [21]
VMB_WE0# [21]
VMB_WE1# [21]
C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5
Y12
Rb
R222
EV@100/F_4
C288
EV@1U/6.3V_4X
MEM_CALRN0
MEM_CALRN1
MEM_CALRN2
MEM_CALRP0
MEM_CALRP1
MEM_CALRP2
243R
X
243R
243R
X
243R
SeymourThamesBall Name
X
243R
X
X
243R
X
Mars
X
X
X
120R
X
X
Rb
R579
EV@100/F_4
C742
EV@1U/6.3V_4X
25mm (max) 5mm (max) 25mm (max)
GPU_DRAM_RST
Place all these componets very close to GPU (within 25mm)
and keep all components close to each other
** This basic topology should be used for DRAM_RAT for DDR3/GDDR5
These Capacitors and Resistor values arre an example only
The series R and || cap values will depend on the DRAM loads
and will have to be calculated for differrent Memory, DRAM loads and board
to pass Reset Signal Spec
R578 EV@10/F_4
R574
EV@4.99K/F_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
C746
EV@120P/50V_4N
R581 EV@51/F_4
MEM_RST# [20,21]
C747
*E@0.1U/10V_4X
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Mars_M2/ MEM Interface
Mars_M2/ MEM Interface
Mars_M2/ MEM Interface
BD9
BD9
BD9
19 41Tuesday, December 25, 2012
19 41Tuesday, December 25, 2012
19 41Tuesday, December 25, 2012
A1A
A1A
A1A
5
VMA_DQ[63..0][19]
VMA_DM[7..0][19]
VMA_RDQS[7..0][19]
VMA_WDQS[7..0][19]
D D
C C
VMA_DQ[63..0]
VMA_DM[7..0]
VMA_RDQS[7..0]
VMA_WDQS[7..0]
VMA_MA10[19]
VMA_MA11[19]
VMA_MA12[19]
VMA_MA13[19]
VMA_MA14[19]
VMA_CLK0#[19]
VMA_CKE0[19]
VMA_ODT0[19]
VMA_RAS0#[19]
VMA_CAS0#[19]
VMA_WE0#[19]
QSA[7..0]
QSA#[7..0]
VMA_MA0[19]
VMA_MA1[19]
VMA_MA2[19]
VMA_MA3[19]
VMA_MA4[19]
VMA_MA5[19]
VMA_MA6[19]
VMA_MA7[19]
VMA_MA8[19]
VMA_MA9[19]
VMA_BA0[19]
VMA_BA1[19]
VMA_BA2[19]
VMA_CLK0[19]
VMA_CS0#[19]
MEM_RST#[19,21]
U7
M8
VREFC_VMA1
VREFD_VMA1
VMA_MA0
VMA_MA1
VMA_MA2
VMA_MA3
VMA_MA4
VMA_MA5
VMA_MA6
VMA_MA7
VMA_MA8
VMA_MA9
VMA_MA10
VMA_MA11
VMA_MA12
VMA_MA13 VMA_MA13
VMA_MA14 VMA_MA14
VMA_BA0
VMA_BA1
VMA_BA2
VMA_CLK0
VMA_CLK0#
VMA_CKE0
VMA_ODT0
VMA_CS0#
VMA_RAS0#
VMA_CAS0#
VMA_WE0#
VMA_RDQS0
VMA_RDQS3
VMA_DM0
VMA_DM3
VMA_WDQS0
VMA_WDQS3
MEM_RST#
VMA_ZQ1
R145
Mars@243/F_4
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC
T3
A13
T7
A14
M7
A15
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE
K1
ODT
L2
CS
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ
J1
NC#J1
L1
NC#L1
J9
NC#J9
L9
NC#L9
Mars@VRAM _DDR3
100-BALL
SDRAM DDR3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
E3
VMA_DQ5
DQL0
F7
VMA_DQ0
DQL1
F2
VMA_DQ6
DQL2
F8
VMA_DQ1
DQL3
H3
VMA_DQ4
DQL4
H8
VMA_DQ3
DQL5
G2
VMA_DQ7
DQL6
H7
VMA_DQ2
DQL7
D7
VMA_DQ24
C3
VMA_DQ31
C8
VMA_DQ27
C2
VMA_DQ28
A7
VMA_DQ25
A2
VMA_DQ29
B8
VMA_DQ26
A3
VMA_DQ30
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
+1.5V_GPU
+1.5V_GPU
TOP Left TOP Right
B B
R146
Mars@4.99K/F_4
VREFC_VMA1
R147
Mars@4.99K/F_4
C204
Mars@0.1U/10V_4X
R205
Mars@4.99K/F_4
VREFD_VMA1
R204
Mars@4.99K/F_4
C285
Mars@0.1U/10V_4X
+1.5V_GPU +1.5V_GPU+1.5V_GPU +1.5V_GPU
4
U24
M8
VREFC_VMA2
VREFD_VMA2
VMA_MA0
VMA_MA1
VMA_MA2
VMA_MA3
VMA_MA4
VMA_MA5
VMA_MA6
VMA_MA7
VMA_MA8
VMA_MA9
VMA_MA10
VMA_MA11
VMA_MA12
VMA_BA0
VMA_BA1
VMA_BA2
VMA_CLK0
VMA_CLK0#
VMA_CKE0
VMA_ODT0
VMA_CS0#
VMA_RAS0#
VMA_CAS0#
VMA_WE0#
VMA_RDQS1
VMA_RDQS2
VMA_DM1
VMA_DM2
VMA_WDQS1
VMA_WDQS2
MEM_RST#
VMA_ZQ2
R206
Mars@243/F_4
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3
J7
K7
K9
K1
L2
J3
K3
L3
F3
C7
E7
D3
G3
B7
T2
L8
J1
L1
J9
L9
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
BA0
BA1
BA2
CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ
NC#J1
NC#L1
NC#J9
NC#L9
100-BALL
SDRAM DDR3
Mars@VRAM _DDR3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
BOT Left
R148
Mars@4.99K/F_4
VREFC_VMA2 VREFD_VMA2
R149
Mars@4.99K/F_4
C206
Mars@0.1U/10V_4X
R142
Mars@4.99K/F_4
R154
Mars@4.99K/F_4
3
CHANNEL A: 1024MB DDR3 (128M*16*4pcs)
E3
VMA_DQ12
F7
VMA_DQ14
F2
VMA_DQ8
F8
VMA_DQ11
H3
VMA_DQ10
H8
VMA_DQ15
G2
VMA_DQ9
H7
VMA_DQ13
D7
VMA_DQ20
C3
VMA_DQ19
C8
VMA_DQ23
C2
VMA_DQ17
A7
VMA_DQ22
A2
VMA_DQ16
B8
VMA_DQ21
A3
VMA_DQ18
+1.5V_GPU
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5V_GPU
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
VMA_CLK1[19]
VMA_CLK1#[19]
VMA_CKE1[19]
VMA_ODT1[19]
VMA_CS1#[19]
VMA_RAS1#[19]
VMA_CAS1#[19]
VMA_WE1#[19]
Group-A1 VREFGroup-A0 VREF
C220
Mars@0.1U/10V_4X
VREFC_VMA3
VREFD_VMA3
VMA_MA0
VMA_MA1
VMA_MA2
VMA_MA3
VMA_MA4
VMA_MA5
VMA_MA6
VMA_MA7
VMA_MA8
VMA_MA9
VMA_MA10
VMA_MA11
VMA_MA12
VMA_MA13 VMA_MA13
VMA_MA14 VMA_MA14
VMA_BA0
VMA_BA1
VMA_BA2
VMA_CLK1
VMA_CLK1#
VMA_CKE1
VMA_ODT1
VMA_CS1#
VMA_RAS1#
VMA_CAS1#
VMA_WE1#
VMA_RDQS6
VMA_RDQS4
VMA_DM6
VMA_DM4
VMA_WDQS6
VMA_WDQS4
MEM_RST#
VMA_ZQ3 VMA_ZQ4
R209
Mars@243/F_4
R207
Mars@4.99K/F_4
VREFC_VMA3 VREFD_VMA3
R208
Mars@4.99K/F_4
C286
Mars@0.1U/10V_4X
<VGA>
U8
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC
T3
A13
T7
A14
M7
A15
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE
K1
ODT
L2
CS
J3
RAS
VDDQ#C1
K3
CAS
VDDQ#C9
L3
WE
VDDQ#D2
F3
DQSL
VDDQ#H2
C7
DQSU
VDDQ#H9
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ
J1
NC#J1
L1
NC#L1
J9
NC#J9
L9
NC#L9
100-BALL
SDRAM DDR3
Mars@VRAM _DDR3
BOT Right
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#E9
VDDQ#F1
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
R153
Mars@4.99K/F_4
R152
Mars@4.99K/F_4
2
1
20
E3
VMA_DQ54
F7
VMA_DQ50
F2
VMA_DQ53
F8
VMA_DQ49
H3
VMA_DQ52
H8
VMA_DQ51
G2
VMA_DQ55
H7
VMA_DQ48
D7
VMA_DQ32
C3
VMA_DQ36
C8
VMA_DQ33
C2
VMA_DQ37
A7
VMA_DQ34
A2
VMA_DQ39
B8
VMA_DQ35
A3
VMA_DQ38
+1.5V_GPU
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5V_GPU
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
C219
Mars@0.1U/10V_4X
VREFC_VMA4
VREFD_VMA4
VMA_MA0
VMA_MA1
VMA_MA2
VMA_MA3
VMA_MA4
VMA_MA5
VMA_MA6
VMA_MA7
VMA_MA8
VMA_MA9
VMA_MA10
VMA_MA11
VMA_MA12
VMA_BA0
VMA_BA1
VMA_BA2
VMA_CLK1
VMA_CLK1#
VMA_CKE1
VMA_ODT1
VMA_CS1#
VMA_RAS1#
VMA_CAS1#
VMA_WE1#
VMA_RDQS5
VMA_RDQS7
VMA_DM5
VMA_DM7
VMA_WDQS5
VMA_WDQS7
MEM_RST#
U25
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC
T3
A13
T7
A14
M7
A15
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE
K1
ODT
L2
CS
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ
R467
Mars@243/F_4
J1
NC#J1
L1
NC#L1
J9
NC#J9
L9
NC#L9
100-BALL
SDRAM DDR3
Mars@VRAM _DDR3
R465
Mars@4.99K/F_4
VREFC_VMA4 VREFD_VMA4
R466
Mars@4.99K/F_4
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
C637
Mars@0.1U/10V_4X
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
VMA_DQ46
VMA_DQ45
VMA_DQ44
VMA_DQ40
VMA_DQ41
VMA_DQ42
VMA_DQ43
VMA_DQ47
VMA_DQ61
VMA_DQ58
VMA_DQ63
VMA_DQ56
VMA_DQ60
VMA_DQ59
VMA_DQ62
VMA_DQ57
+1.5V_GPU+1.5V_GPU+1.5V_GPU +1.5V_GPU
R464
Mars@4.99K/F_4
R463
Mars@4.99K/F_4
+1.5V_GPU
+1.5V_GPU
C636
Mars@0.1U/10V_4X
MEM_A0 CLK
VMA_CLK0
VMA_CLK0#
R144
Mars@40.2/F_4
A A
R143
Mars@40.2/F_4
C202
Mars@0.01U/25V_4X
Group-A0 decoupling CAP
+1.5V_GPU
C250
Mars@1U/6.3V_4X
+1.5V_GPU
Mars@1U/6.3V_4X
+1.5V_GPU
C641
Mars@4.7U/6.3V_6X
5
C247
Mars@1U/6.3V_4X
C253
Mars@1U/6.3V_4X
C644
Mars@4.7U/6.3V_6X
C239
Mars@1U/6.3V_4X
C234
Mars@1U/6.3V_4X
C229
Mars@4.7U/6.3V_6X
C236
Mars@1U/6.3V_4X
C207
Mars@1U/6.3V_4X
C653
Mars@4.7U/6.3V_6X
C232
Mars@1U/6.3V_4X
C203
Mars@1U/6.3V_4X
4
C668
Mars@4.7U/6.3V_6X
Mars@1U/6.3V_4X
C205
Mars@1U/6.3V_4X
C240
Mars@1U/6.3V_4X
C231
Mars@1U/6.3V_4X
C237
Mars@1U/6.3V_4X
C260
Mars@1U/6.3V_4X
Group-A1 decoupling CAP
+1.5V_GPU
C212
Mars@1U/6.3V_4X
+1.5V_GPU
C218
Mars@1U/6.3V_4X
+1.5V_GPU
C696
Mars@4.7U/6.3V_6X
3
C639
Mars@1U/6.3V_4X
C640
Mars@1U/6.3V_4X
C711
Mars@4.7U/6.3V_6X
C638
Mars@1U/6.3V_4X
C213
Mars@1U/6.3V_4XC243
C698
Mars@4.7U/6.3V_6X
C215
Mars@1U/6.3V_4XC244
C223
Mars@1U/6.3V_4X
C198
Mars@4.7U/6.3V_6X
C208
Mars@1U/6.3V_4X
C226
Mars@1U/6.3V_4X
C199
Mars@4.7U/6.3V_6X
2
C209
Mars@1U/6.3V_4X
C228
Mars@1U/6.3V_4X
C210
Mars@1U/6.3V_4X
C217
Mars@1U/6.3V_4X
C211
Mars@1U/6.3V_4X
C216
Mars@1U/6.3V_4X
MEM_A1 CLK
VMA_CLK1
VMA_CLK1#
R150
Mars@40.2/F_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROJECT :
VRAM_A: DDR3*4PCS
VRAM_A: DDR3*4PCS
VRAM_A: DDR3*4PCS
1
R151
Mars@40.2/F_4
C214
Mars@0.01U/25V_4X
BD9
BD9
BD9
20 41Tuesday, December 25, 2012
20 41Tuesday, December 25, 2012
20 41Tuesday, December 25, 2012
A1A
A1A
A1A
5
VMB_MA0[19]
VMB_MA1[19]
VMB_MA2[19]
VMB_MA3[19]
VMB_MA4[19]
VMB_MA5[19]
VMB_MA6[19]
VMB_MA7[19]
VMB_MA8[19]
VMB_MA9[19]
VMB_MA10[19]
VMB_MA11[19]
VMB_MA12[19]
VMB_MA13[19]
VMB_MA14[19]
VMB_BA0[19]
VMB_BA1[19]
VMB_BA2[19]
VMB_CLK0[19]
VMB_CLK0#[19]
VMB_CKE0[19]
VMB_ODT0[19]
VMB_CS0#[19]
VMB_RAS0#[19]
VMB_CAS0#[19]
VMB_WE0#[19]
MEM_RST#[19,20]
VMB_DQ[63..0]
VMB_DM[7..0]
VMB_RDQS[7..0]
VMB_WDQS[7..0]
QSA[7..0]
QSA#[7..0]
VREFC_VMB1
VREFD_VMB1
VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_MA13 VMB_MA13 VMB_MA13 VMB_MA13
VMB_MA14 VMB_MA14 VMB_MA14 VMB_MA14
VMB_BA0
VMB_BA1
VMB_BA2
VMB_CLK0
VMB_CLK0#
VMB_CKE0
VMB_ODT0
VMB_CS0#
VMB_RAS0#
VMB_CAS0#
VMB_WE0#
VMB_RDQS2
VMB_RDQS3
VMB_DM2
VMB_DM3
VMB_WDQS2 VMB_WDQS0
VMB_WDQS3
MEM_RST#
VMB_ZQ1
EV@243/F_4
U12
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC
T3
A13
T7
A14
M7
A15
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE
K1
ODT
L2
CS
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ
R238
J1
NC#J1
L1
NC#L1
J9
NC#J9
L9
NC#L9
100-BALL
SDRAM DDR3
EV@VRAM _DDR3
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
E3
VMB_DQ23
F7
VMB_DQ16
F2
VMB_DQ21
F8
VMB_DQ17
H3
VMB_DQ22
H8
VMB_DQ19
G2
VMB_DQ20
H7
VMB_DQ18
D7
VMB_DQ26
C3
VMB_DQ30
C8
VMB_DQ28
C2
VMB_DQ31
A7
VMB_DQ24
A2
VMB_DQ27
B8
VMB_DQ25
A3
VMB_DQ29
+1.5V_GPU
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5V_GPU
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
VMB_DQ[63..0][19]
VMB_DM[7..0][19]
VMB_RDQS[7..0][19]
VMB_WDQS[7..0][19]
D D
C C
BOT Down
4
CHANNEL B: 1024MB DDR3 (128M*16*4pcs)
VREFC_VMB2
VREFD_VMB2
VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_BA0
VMB_BA1
VMB_BA2
VMB_CLK0
VMB_CLK0#
VMB_CKE0
VMB_ODT0
VMB_CS0#
VMB_RAS0#
VMB_CAS0#
VMB_WE0#
VMB_RDQS0
VMB_RDQS1
VMB_DM0
VMB_DM1
VMB_WDQS1
MEM_RST#
VMB_ZQ2 VMB_ZQ3 VMB_ZQ4
R534
EV@243/F_4
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC
T3
A13
T7
A14
M7
A15
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE
K1
ODT
L2
CS
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ
J1
NC#J1
L1
NC#L1
J9
NC#J9
L9
NC#L9
EV@VRAM _DDR3
100-BALL
SDRAM DDR3
U31
M8
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
E3
VMB_DQ1
F7
VMB_DQ4
F2
VMB_DQ2
F8
VMB_DQ5
H3
VMB_DQ0
H8
VMB_DQ7
G2
VMB_DQ3
H7
VMB_DQ6
D7
VMB_DQ15
C3
VMB_DQ10
C8
VMB_DQ14
C2
VMB_DQ8
A7
VMB_DQ12
A2
VMB_DQ9
B8
VMB_DQ13
A3
VMB_DQ11
+1.5V_GPU
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5V_GPU +1.5V_GPU
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
3
2
<VGA>
U14
R247
EV@243/F_4
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC
T3
A13
T7
A14
M7
A15
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE
K1
ODT
L2
CS
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ
J1
NC#J1
L1
NC#L1
J9
NC#J9
L9
NC#L9
EV@VRAM _DDR3
100-BALL
SDRAM DDR3
VREFC_VMB3
VREFD_VMB3
VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_BA0
VMB_BA1
VMB_BA2
VMB_CLK1[19]
VMB_CLK1#[19]
VMB_CKE1[19]
VMB_ODT1[19]
VMB_CS1#[19]
VMB_RAS1#[19]
VMB_CAS1#[19]
VMB_WE1#[19]
VMB_CLK1
VMB_CLK1#
VMB_CKE1
VMB_ODT1
VMB_CS1#
VMB_RAS1#
VMB_CAS1#
VMB_WE1#
VMB_RDQS6
VMB_RDQS5
VMB_DM6
VMB_DM5
VMB_WDQS6
VMB_WDQS5
MEM_RST#
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
E3
VMB_DQ55
F7
VMB_DQ51
F2
VMB_DQ54
F8
VMB_DQ50
H3
VMB_DQ52
H8
VMB_DQ49
G2
VMB_DQ53
H7
VMB_DQ48
D7
VMB_DQ41
C3
VMB_DQ47
C8
VMB_DQ40
C2
VMB_DQ46
A7
VMB_DQ44
A2
VMB_DQ45
B8
VMB_DQ43
A3
VMB_DQ42
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5V_GPU
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
TOP Down TOP Up
VREFC_VMB4
VREFD_VMB4
VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_BA0
VMB_BA1
VMB_BA2
VMB_CLK1
VMB_CLK1#
VMB_CKE1
VMB_ODT1
VMB_CS1#
VMB_RAS1#
VMB_CAS1#
VMB_WE1#
VMB_RDQS7
VMB_RDQS4
VMB_DM7
VMB_DM4
VMB_WDQS7
VMB_WDQS4
MEM_RST#
R564
EV@243/F_4
U34
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC
T3
A13
T7
A14
M7
A15
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE
K1
ODT
L2
CS
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ
J1
NC#J1
L1
NC#L1
J9
NC#J9
L9
NC#L9
EV@VRAM _DDR3
BOT Up
100-BALL
SDRAM DDR3
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
1
21
E3
VMB_DQ62
F7
VMB_DQ61
F2
VMB_DQ63
F8
VMB_DQ60
H3
VMB_DQ59
H8
VMB_DQ58
G2
VMB_DQ57
H7
VMB_DQ56
D7
VMB_DQ38
C3
VMB_DQ32
C8
VMB_DQ36
C2
VMB_DQ33
A7
VMB_DQ37
A2
VMB_DQ35
B8
VMB_DQ39
A3
VMB_DQ34
+1.5V_GPU+1.5V_GPU
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
Group-B0 VREF Group-B1 VREF
B B
R529
EV@4.99K/F_4
R530
EV@4.99K/F_4
C707
EV@1U/6.3V_4X
C291
EV@1U/6.3V_4X
C695
EV@0.1U/10V_4X
C421
EV@1U/6.3V_4X
C290
EV@1U/6.3V_4X
C361
EV@1U/6.3V_4X
3
Group-B1 decoupling CAPGroup-B0 decoupling CAP
+1.5V_GPU
C423
EV@1U/6.3V_4X
+1.5V_GPU
C365
EV@1U/6.3V_4X
+1.5V_GPU
C665
EV@4.7U/6.3V_6X
C387
EV@1U/6.3V_4X
C705
EV@1U/6.3V_4X
C437
EV@4.7U/6.3V_6X
R244
EV@4.99K/F_4
R245
EV@4.99K/F_4
C730
EV@1U/6.3V_4X
C392
EV@1U/6.3V_4X
C382
EV@0.1U/10V_4X
C435
EV@1U/6.3V_4X
C342
EV@1U/6.3V_4X
C724
EV@4.7U/6.3V_6X
+1.5V_GPU
C710
EV@1U/6.3V_4X
+1.5V_GPU
C292
EV@1U/6.3V_4X
+1.5V_GPU
C442
EV@4.7U/6.3V_6X
R243
EV@4.99K/F_4
R242
EV@4.99K/F_4
C352
EV@0.1U/10V_4X
C709
EV@1U/6.3V_4X
C689
EV@1U/6.3V_4X
C635
EV@4.7U/6.3V_6X
R241
EV@4.99K/F_4
VREFC_VMB1 VREFD_VMB1 VREFC_VMB3 VREFD_VMB3
R239
EV@4.99K/F_4
C328
EV@0.1U/10V_4X
MEM_B0 CLK MEM_B1 CLK
VMB_CLK0
VMB_CLK0#
R236
EV@40.2/F_4
A A
R237
EV@40.2/F_4
C319
EV@0.01U/25V_4X
5
C700
EV@1U/6.3V_4X
C706
EV@1U/6.3V_4X
C201
EV@4.7U/6.3V_6X
R540
EV@4.99K/F_4
R536
EV@4.99K/F_4
C701
EV@1U/6.3V_4X
C694
EV@1U/6.3V_4X
C227
EV@4.7U/6.3V_6X
4
C697
EV@0.1U/10V_4X
C702
EV@1U/6.3V_4X
C693
EV@1U/6.3V_4X
C662
EV@4.7U/6.3V_6X
R282
EV@4.99K/F_4
R281
EV@4.99K/F_4
C425
EV@1U/6.3V_4X
C384
EV@1U/6.3V_4X
C313
EV@4.7U/6.3V_6X
2
C415
EV@0.1U/10V_4X
C725
EV@1U/6.3V_4X
C378
EV@1U/6.3V_4X
C318
EV@4.7U/6.3V_6X
R560
EV@4.99K/F_4
VREFC_VMB4 VREFD_VMB4VREFC_VMB2 VREFD_VMB2
R562
EV@4.99K/F_4
C703
EV@1U/6.3V_4X
C374
EV@1U/6.3V_4X
C719
EV@0.1U/10V_4X
C400
EV@1U/6.3V_4X
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
+1.5V_GPU+1.5V_GPU+1.5V_GPU+1.5V_GPU+1.5V_GPU+1.5V_GPU+1.5V_GPU+1.5V_GPU
R541
EV@4.99K/F_4
R542
EV@4.99K/F_4
VMB_CLK1
VMB_CLK1#
VRAM_B: DDR3*4PCS
VRAM_B: DDR3*4PCS
VRAM_B: DDR3*4PCS
C704
EV@0.1U/10V_4X
R268
EV@40.2/F_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
BD9
BD9
BD9
1
R270
EV@40.2/F_4
C414
EV@0.01U/25V_4X
21 41Tuesday, December 25, 2012
21 41Tuesday, December 25, 2012
21 41Tuesday, December 25, 2012
A1A
A1A
A1A
5
4
3
2
1
<VGA>
D D
SLP_S3#[7,33]
PE_GPIO1[7]
SLP_S3#
21
D34 *EV@RB500V-40_100MA
R584 EV@0_4
R585
*EV@200K_4
+5V_S5
R583
EV@100K_4
C755
EV@4700P/25V_4X
C758
EV@0.1U/10V_4X
31
2
EV@ME2N7002E_200MA
Q36
2
+3V
1
Q35
EV@ME1303_3A
3
C752
EV@10U/6.3V_6X
There is no restriction on
VDDR3 relative to other rails
+3V_GPU
GPU +3V power
0.5A
C753
EV@1U/6.3V_4X
R535 EV@0_4
C754
EV@0.1U/10V_4X
22
GPU_MAINON [40,41]
RevB 1219 Change for EOD
C C
+3V
C399 EV@0.1U/10V_4X
U13
PE_GPIO0[7]
APU_PCIE_RST#[7,26,28]
2
1
4
EV@TC7SH08FU(F)
3 5
PERST#_BUF
PERST#_BUF [12]
B B
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
BD9
BD9
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
PROJECT :
Mars_M2/ PX5
Mars_M2/ PX5
Mars_M2/ PX5
BD9
A1A
A1A
22 41Tuesday, December 25, 2012
22 41Tuesday, December 25, 2012
22 41Tuesday, December 25, 2012
1
A1A
5
USB 3.0 Power
switch
USB_SC_EN#[33]
D D
URL@10K_4
+3V_S5
R339
USB 3.0 CONN
USB3_TXN0[8]
USB3_TXP0[8]
RevB 1220 Add C.M Choke for EMI suggestion
Delete RP5, Add L15
C C
L15
2
USB_S&C#_R
USB_S&C_R USB_S&C_R1
2
3
URL@MCM2012B900GBE
<USB> <U3B>
+5V_S5
U17
2
8
7
6
5
OC#
USB3_TXN0_R
USB3_TXP0_R
USB3_TXP0_R
+5VSUS_USBP0
USB_S&C#_R1
USB3_RXP0_R
+5VSUS_USBP0
C468
*URL@470P/50V_4X
USB_SC_OC#
D35 *URL-3@AZ5125-01J
RP5 URL@0X2
241
USB3_RXN0_R
USB3_RXP0_R
C465 URL-3@0.1U/10V_4X
C466 URL-3@0.1U/10V_4X
ESD5
1
2
3
4
*URL-3@AZ1065-06F
USB_SC_EN#
C470
URL@1U/16V_6X
<USB>
<U3B>
C760 *URL-3@15P/50V_4C R588 *URL-3@300_4
USB3_RXN0[8]
USB3_RXP0[8]
USB3_TXN0 USB3_TXN0_C
1
USB_S&C#_R1
1
443
EN#
1
GND
9
GND-C
URL@UP7534BRA8-15
<EMI>
R324 URL-3@0_4
USB3_RXN0
R327 URL-3@0_4
USB3_RXP0
R334 URL-3@0_4
R338 URL-3@0_4
USB_S&C#_R
USB_S&C_R
IN1
OUT3
IN23OUT2
OUT1
4
3
1
VDD
NC
4
556
4
C469
*URL@0.1U/10V_4X
USB_SC_OC# [7,33]
+5VSUS_USBP0
USB_S&C#_R1
USB_S&C_R1
USB3_TXP0_CUSB3_TXP0
10
10
9
GND
8
NC1
7
7
6
1015 change Caps to 220uF
C761
+
URL@220U/6.3V_105CS_E18e
RevB 1219 Change for EOD
Right-Low Side
USB3.0 Support S&C
CN23
1
VBUS
1
2
D-
2
3
D+
3
4
4
GND
5
SSRX-
5
6
6
SSRX+
7
7
GND
8
8
SSTX-
9
SSTX+
9
11111010131312
URL-3@C19066-90905-L
12
USB3_TXN0_R
USB_S&C_R1
USB3_RXN0_R
C467
*URL@10U/6.3V_6X
C471
*URL@100U/6.3V_1206
Q20
URL@ME2N7002E_200MA
3
USB w S&C MAXIM solution
R346
URL@470/F_4
3
2
1
USB_BUS_SW3[33]
USB_BUS_SW2[33]
SC_SDA
+5V_S5
C463
S&C@0.1U/10V_4X
R7
R336 *S&C@10K_4
R1
R335 *S&C@0_4
R328 S&C@0_4
R2
R322 *S&C@0_4
R3
CB1_CEN#_CB2
CB0_SDA
2
<SLC>
14566/14600/14617
R1 R2 R3
14566
14600
14617(no CB2)
14641/14642/14644
14640/14651 V
U16
5
1
8
9
VCC
CB1/CEN#/CB2/INT#
CB0/SDA
GND/CB1/SCL
GND
S&C@MAX14641ETA+T
TDP
TDM
DP
DM
V V
1015 Close to U2501
6
R586 NS&C@0_4
USBP8+
7
R587 NS&C@0_4
USBP8-
3
2
R4
4
R325 S&C@0_4
GND_CB1
R5
R321 *S&C@0_4
R6
R326 *S&C@0_4
1
23
R4
R5
R6
V
V
V
V
V
V V
V
V
USB_S&C_R
USB_S&C#_R
USB_BUS_SW3
SC_SCL
USBP8+[8]
USBP8-[8]
R7
USBP8+
USBP8-
RevC 0130 update S&C table
+5V_S5
+5V_S5
R319
*S&C@10K_4
Q19A
2ND_MBCLK[5,33]
2ND_MBDATA[5,33]
B B
126
*S&C@2N7002KDW_115MA
+5V_S5
5
Q19B
34
*S&C@2N7002KDW_115MA
USB 3.0 CONN
USB3_RXN1[8]
USB3_RXP1[8]
USB3_TXN1[8]
USB3_TXP1[8]
RevB 1220 Add C.M Choke for EMI suggestion
Delete RP4, Add L13
L13
1
2
USBP9ÂUSBP9+ USBP9+_R
1
2
3
443
URU@MCM2012B900GBE
USB 2.0 CONN (USB/B)
CN12
1
2
3
4
A A
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
88511-200N
1005 Update FP
+5V_S5
USBP1+_R
USBP1-_R
USBP0+_R
USBP0-_R
R443 10K_4
RevB 1130 Change R443 PU from USB_DB_OC# to USB_DB_EN#
5
SC_SCL
+5V_S5
R320
*S&C@10K_4
SC_SDA
<EMI>
<U2B><U3B>
USBP9-_R
C751 *URU-3@15P/50V_4C
USB3_RXN1
USB3_RXP1
USB3_TXN1
USB3_TXP1
<EMI><U2B>
RevB 1220 Add C.M Choke for EMI suggestion
Delete RP24,RP25, Add L26,L27
L27
3
USBP1+_R
USBP1-_R USBP1-
USBP0+_R
USBP0-_R USBP0-
443
2
1
2
MCM2012B900GBE
L26
3
443
2
1
2
MCM2012B900GBE
RP25 *0X2
RP24 *0X2
241
241
+3V_S5
3
3
USB_DB_OC# [7,33]
USB_DB_EN# [33]
Co-Lay USB 2.0 CONN
+5VSUS_USBP0
D13
*URL-2@AZ5125-01J
R582 *URU-3@300_4
USBP9-[8]
USBP9+[8]
R308 URU-3@0_4
R309 URU-3@0_4
R316 URU-3@0_4 C454
R317 URU-3@0_4
USB3_TXP1_R USB3_TXN1_R
+5VSUS_USBP1
USB3_RXP1_R USB3_RXN1_R
USBP1+
1
USBP0+
1
USBP9ÂUSBP9+
USB3_RXN1_R
USB3_RXP1_R
USB3_TXN1_R
USB3_TXP1_R
ESD4
1
1
2
VDD
3
NC
4
4
556
*URU-3@AZ1065-06F
USBP1+ [8]
USBP1- [8]
USBP0+ [8]
USBP0- [8]
C452 URU-3@0.1U/10V_4X
C453 URU-3@0.1U/10V_4X
10
10
9
GND
8
NC1
7
7
6
4
<USB>
<EMI>
CN22
1
VBUS
1
USB_S&C#_R1
USB_S&C_R1
USB3_RXN0_R
USB3_RXP0_R
USB3_TXN0_C
USB3_TXP0_C
RP4 *URU@0X2
241
2
D-
2
3
D+
3
4
4
GND
5
SSRX-
5
6
6
SSRX+
7
7
GND
8
8
SSTX-
9
SSTX+
9
11111010131312
12
URL-2@UARC8-4K1986
Right-Up Side
USB3.0/USB2.0 Co-lay
+5VSUS_USBP1
USBP9-_R
3
USBP9+_R
USB3_TXN1_C
USB3_TXP1_C
USBP9+_RUSBP9-_R
Co-Lay USB 2.0 CONN
+5VSUS_USBP1
USBP9-_R
D33
*URU-2@AZ5125-01J
USBP9+_R
USB3_RXN1_R
USB3_RXP1_R
USB3_TXN1_C
USB3_TXP1_C
CN19
1
VBUS
1
2
D-
2
3
D+
3
4
4
GND
5
SSRX-
5
6
6
SSRX+
7
7
GND
8
8
SSTX-
9
SSTX+
9
11111010131312
12
<USB> <EMI>
CN20
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
URU-3@C19066-90905-L
SSRX-
VBUS
DÂD+
GND
SSRX+
GND
SSTXÂSSTX+
11111010131312
12
URU-2@UARC8-4K1986
CB0 CB10Status
0
0 1
1 0
1
SW2 SW3
CB0 CB10Status
0
0 1
1 0
1
USB_NORMAL_EN#[33]
3
14600
Auto mode
Force dedicated charger mode
Pass-Through(USB) mode
pass-through(USB) with CDP
1
Emulation
14644
2A Auto mode for Apple device
Force dedicated charger mode
Pass-Through(USB) mode
pass-through(USB) with CDP
1
Emulation
R318
URU@10K_4
+5V_S5+3V_S5
USB_NORMAL_EN#
URU@1U/16V_6X
Charger , AM
Charger , FM
USB , PM
USB , CM
Charger , AM2
Charger , FM
USB , PM
USB , CM
U15
2
IN1
OUT3
IN23OUT2
OUT1
4
EN#
1
GND
9
OC#
GND-C
URU@UP7534BRA8-15
SW2 SW3SW3SW2
CB0 CB10Status
0
0 1
1 0
1
SW2 SW3
CB0 CB10Status
1 0
1
8
+5VSUS_USBP1
7
6
C456
5
*URU@470P/50V_4X
USB_NORMAL_OC#
2
14641
2A Auto mode for Apple device
Force 1A for Apple device
Pass-Through(USB) mode
pass-through(USB) with CDP
1
Emulation
14642
2A Auto mode for Apple device
X
Pass-Through(USB) mode
pass-through(USB) with CDP
1
Emulation
1015 change Caps to 220uF
C457
C759
+
*URU@0.1U/10V_4X
URU@220U/6.3V_105CS_E18e
USB_NORMAL_OC# [7,33]
Size Document Numbe r Rev
Size Document Numbe r Rev
Size Document Numbe r Rev
Date: Shee t of
Wednesday, January 30, 2013
Date: Shee t of
Wednesday, January 30, 2013
Date: Shee t of
Wednesday, January 30, 2013
Charger , AM2
Charger , AP1
USB , PM
USB , CM
Charger , AM2
USB , PM
USB , CM
C455
C459
*URU@10U/6.3V_6X
*URU@100U/6.3V_1206
RevB 1219 Change for EOD
URU@ME2N7002E_200MA
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
USB2.0/USB3.0
USB2.0/USB3.0
USB2.0/USB3.0
1
Q18
2
BD9
BD9
BD9
3
1
23 41
23 41
23 41
R323
URU@470/F_4
A1A
A1A
A1A
5
4
3
2
1
+3V
40mils
L25 LDS@HCB1608KF-221T20_2A
+3V
D D
C C
B B
A A
80mils
L23 LDS@HCB1608KF-221T20_2A
INT_LVDS_AUXN[5]
INT_LVDS_AUXP[5]
INT_LVDS_TXP0[5]
INT_LVDS_TXN0[5]
INT_LVDS_TXP1[5]
INT_LVDS_TXN1[5]
CIICSCL
+3V
CIICSDA
C590
LDS@10U/6.3V_6X
C575
LDS@0.1U/10V_4X
R430 *LDS@0_4
1
Q26A *LDS@2N7002KDW_115MA
R446
LDS@4.7K_4
R438
LDS@4.7K_4
Q26B *LDS@2N7002KDW_115MA
R429 *LDS@0_4
MODE_CFG1(PIN48)
R408 *LDS@4.7K_4
+3V
R411 LDS@4.7K_4
+3V
5
AVCC33
C587
LDS@0.1U/10V_4X
C572
LDS@10U/6.3V_6X
INT_LVDS_HPD[5,30]
R419 LDS@0_4
R418 LDS@0_4
R417 LDS@0_4
R416 LDS@0_4
R415 LDS@0_4
R414 LDS@0_4
2
RP23 eDP@0X2
4
2
RP22 eDP@0X2
4
2
RP21 eDP@0X2
4
Close to U2600
6
2
1018 FAE suggest connect to FCH and EC
5
34
0 1
0
1
MODE_CFG0
MODE_CFG1
Close to chip
DVCC33
C573
LDS@22U/6.3V_6X
PD at APU side
R421 LDS@1K_4
1
3
1
3
1
3
1010 Reserve 0_4
R437 *LDS@0_4
R450 *LDS@0_4
R449 *LDS@0_4
R436 *LDS@0_4
1010 Reserve 0_4
MODE_CFG0(PIN47)
EEPROM MODEROM ONLY MODE
R404 LDS@4.7K_4
R407 *LDS@4.7K_4
C585
LDS@0.1U/10V_4X
C577
LDS@0.1U/10V_4X
R420 LDS@100K_4
AUX_CH_N
AUX_CH_P
LANE0_P
LANE0_N
LANE1_P
LANE1_N
VCCK_V12
C584
LDS@0.1U/10V_4X
INT_LVDS_AUXN_R [30]
INT_LVDS_AUXP_R [30]
INT_LVDS_TXP0_R [30]
INT_LVDS_TXN0_R [30]
INT_LVDS_TXP1_R [30]
INT_LVDS_TXN1_R [30]
3ND_MBCLK [13,33]
SMB_LAN_CLK [7,28,32]
SMB_LAN_DAT [7,28,32]
3ND_MBDATA [13,33]
EP MODEX
C30
LDS@0.1U/10V_4X
INT_LVDS_HPD_R
TEST_MODE
AVCC33
R413
LDS@12K/F_4
APU_VARY_BL[5,30]
4
1
2
3
4
5
6
7
8
9
10
11
12
U20
DP_HPD
TEST_MODE
AUX_CH_N
AUX_CH_P
DP_V33
DP_GND
LANE0_P
LANE0_N
LANE1_P
LANE1_N
DP_V12
DP_REXT
MODE_CFG1
MODE_CFG0
MIICSCL
VCCK_V12
TRAVIS_BL_EN
MIICSDA
47
46
45
44
43
49
EPAD_GND
MIICSCL
MODE_CFG148MODE_CFG0
42
VCCK
BL_EN
MIICSDA
RTD2136R
CIICSCL13CIICSDA14SWR_VCCK/LDO_VCCK15GND16SWR_LX/LDO_FB17SWR_VDD/LDO_VDD18PWMOUT19PANEL_VCC20PWMIN21PVCC22TXE3+23TXE3-
CIICSCL
CIICSDA
VCCK_V12
PIN17
DVCC33
TRAVIS_VARY_BL
R391 LDS@0_4
R390
LDS@100K_4
C578 LDS@0.1U/10V_4X
41
40
39
38
TXO0-
TXO1-
TXO2-
TXO0+
TXO1+
DVCC33=80mils
PANEL_VCC
PWM_IN
DVCC33
3
24
INT_LCD_TXLOUT0- [30]
INT_LCD_TXLOUT0+ [30]
INT_LCD_TXLOUT1- [30]
INT_LCD_TXLOUT1+ [30]
INT_LCD_TXLOUT2- [30]
INT_LCD_TXLOUT2+ [30]
37
TXO2+
36
TXOC-
35
TXOC+
34
TXO3-
33
TXO3+
32
TXE0-
31
TXE0+
30
TXE1-
29
TXE1+
28
TXE2-
27
TXE2+
26
TXEC-
25
TXEC+
24
INT_LCD_TXLCLKOUT- [30]
INT_LCD_TXLCLKOUT+ [30]
INT_LCD_TXUOUT0- [30]
INT_LCD_TXUOUT0+ [30]
INT_LCD_TXUOUT1- [30]
INT_LCD_TXUOUT1+ [30]
INT_LCD_TXUOUT2- [30]
INT_LCD_TXUOUT2+ [30]
INT_LCD_TXUCLKOUT- [30]
INT_LCD_TXUCLKOUT+ [30]
MIICSCL
MIICSDA
R399 LDS@100K_4
R395 LDS@100K_4
R29 *LDS@1K_4
C24 *LDS@4.7U/6.3V_6X
1018 FAE suggest
EEPROM Mode
RTD2136R
RTD2136S
0918 FAE suggest reserve
SMbus connect to FCH
MIICSDA
MIICSCL
MODE_CFG0
MODE_CFG1
R453 *LDS@0_4
R454 *LDS@0_4
R447 *LDS@0_4
R448 *LDS@0_4
1- EEPROM with a size 8K-Byte
L24 *LDS@TLPC3010C-4R7M
R45 LDS@0_6
0918 FAE suggest
C2611 used 22uF X5R
L2602 used TLPC3010C-4R7M
60mils
2.2-uH(L2602) 0 Olm(R2618)
SWR
LDO
+3V
R402
LDS@4.7K_4
+3V
R398
LDS@4.7K_4
TRAVIS_BL_EN
TRAVIS_VARY_BL
PANEL_VCC
R31 LDS@0_1206
U21
8
VCC
5
SDA
6
SCL
4
GND
*LDS@M24C64
R405 LDS@0_4
R403 LDS@0_4
80mils
7
WP
3
A2
2
A1
1
A0
I2C address=0xA8
Connect NC
NC Connect
C610 *LDS@0.1U/10V_4X
2- EEPROM device should be 2-byte addressing device
3- Slave address should configure as 0xA8
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
TRAVIS RTD2136R
TRAVIS RTD2136R
TRAVIS RTD2136R
Tuesday, December 25, 2012
Tuesday, December 25, 2012
Tuesday, December 25, 2012
Close to PIN17
VCCK_V12PIN17
C37
LDS@22U/6.3V_6X
C583
LDS@0.1U/10V_4X
INT_LCD_EDIDCLK [30]
INT_LCD_EDIDDATA [30]
TRAVIS_BL_EN [30]
TRAVIS_VARY_BL [30]
PANEL_VCC_R [30]
For RTD2136S
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
BD9
BD9
BD9
24 41
24 41
1
24 41
A1A
A1A
A1A
5
HDMI
D D
INT_HDMI_TXDN0[5]
INT_HDMI_TXDP0[5]
INT_HDMI_TXDN1[5]
INT_HDMI_TXDP1[5]
INT_HDMI_TXDN2[5]
INT_HDMI_TXDP2[5]
INT_HDMI_TXCN[5]
INT_HDMI_TXCP[5]
R246 *HM@100_4
INT_HDMI_TXDN2 INT_HDMI_TXDP2
INT_HDMI_TXDN1
R248 *HM@100_4
INT_HDMI_TXDN0
R257 *HM@100_4
R261 *HM@100_4
INT_HDMI_TXCN INT_HDMI_TXCP
HDMI_SCL
HDMI_SDA
DDC5V
C422
*HM@0.1U/10V_4X *HM@0.1U/16V_4Y
INT_HDMI_TXDP1
INT_HDMI_TXDP0
C718
*HM@56P/50V_4N
INT_HDMI_TXDN0
INT_HDMI_TXDP0
INT_HDMI_TXDN1
INT_HDMI_TXDP1
INT_HDMI_TXDN2
INT_HDMI_TXDP2
INT_HDMI_TXCN
INT_HDMI_TXCP
C720
*HM@56P/50V_4N
R287 HM@0_6
+5V
4
0922 del HDMI_CON_CEC
1015 Change to correct diode (BC000220Z01)
12
Q16
3
IN
HM@AP2337SA-7
+5V_HDM
1
OUT
2
GND
F2 *HM@SMD1206P110TFT
C418
2 1
D11 *HM@B220LFA-13-F
C424
*HM@0.1U/16V_4Y
INT_HDMI_TXDP2
INT_HDMI_TXDN2
INT_HDMI_TXDP1
INT_HDMI_TXDN1
INT_HDMI_TXDP0
INT_HDMI_TXDN0
INT_HDMI_TXCP
INT_HDMI_TXCN
DDC5V
HDMI_HPD_L
D10
*HM@AZ5125-01J
HDMI_SCL
HDMI_SDA
C416
HM@0.1U/10V_4X
3
CN18
SHELL1
1
D2+
2
D2 Shield
3
D2-
4
D1+
5
D1 Shield
6
D1-
7
D0+
8
D0 Shield
9
D0-
10
CK+
11
CK Shield
12
CK-
13
CE Remote
14
NC
15
DDC CLK
16
DDC DATA
17
GND
18
+5V
19
HP DET
SHELL2
HM@2HE1655-000111F
1022 change FP
2
20
23
GND
22
GND
21
HDMI Hot-plug
INT_HDMI_HPD[5]
+3V
R568
HM@1K_4
34
Q33B
5
HM@2N7002KDW_115MA
+5V
R569
HM@10K_4
6
HM@2N7002KDW_115MA
2
Q33A
1
HDMI_HPD_L
R565
HM@100K_4
1
25
RevA 1113 Change P/N & need to stuff
RevA 1122 Reserve C5601/C5602
ESD3
1
2
3
DDC5V
C C
Touch Screen
<TSN>
1113 add touch screen function
B B
CN13
1
2
3
4
5
6
TSN@50273-0060N-001
INT_HDMI_TXDN0 INT_HDMI_TXDN0
INT_HDMI_TXCP INT_HDMI_TXCP
INT_HDMI_TXCN INT_HDMI_TXCN
INT_HDMI_TXDN1
INT_HDMI_TXDP1
INT_HDMI_TXDN2
INT_HDMI_TXDP2
+5V +3V
R452
*TSN5V@0_4
1
2
USBP4-_R
3
USBP4+_R
4
5
6
nRST
R604 *TSN5V@0_4
R605 *TSN5V@0_4
4
1
2
3
4
1
2
3
4
R451
*TSN3V@0_4
RP26 *TSN@0X2
241
1
2
GND_3/8
4
556
*HM@RClamp0524P
ESD2
1
2
GND_3/8
4
556
*HM@RClamp0524P
ESD1
1
2
GND_3/8
4
556
*HM@RClamp0524P
R455 *TSN@300_4
3
10
10
9
9
7
7
6
10
10
9
9
7
7
6
10
10
9
9
7
7
6
PLTRST# [8,30,31,35]
HDMI_SDAHDMI_SDA
HDMI_SCLHDMI_SCL
DDC5V
HDMI_HPD_LHDMI_HPD_L
INT_HDMI_TXDP0INT_HDMI_TXDP0
INT_HDMI_TXDN1
INT_HDMI_TXDP1
INT_HDMI_TXDN2
INT_HDMI_TXDP2
C611 *TSN@15P/50V_4C
USBP4- [8]
USBP4+ [8]
RevB 1220 Co-lay L41 & RP26 for EMI
L41
1
USBP4-_R
USBP4+_R
2
1
2
3
443
*E@MCM2012B900GBE
USBP4ÂUSBP4+
INT_HDMI_AUXN[5]
INT_HDMI_AUXP[5]
+3V
R561
HM@2.2K_4
INT_HDMI_AUXN
INT_HDMI_AUXP HDMI_SCL
1
Q31 HM@FDV301N_200MA
+3V
R566
HM@2.2K_4
1
Q32 HM@FDV301N_200MA
+5V
1015 add Diode for leakage
D8
HM@RB500V-40_100MA
+3V
2
+3V
2
R269
HM@2.2K_4
3
HDMI_SDA
+5V
1015 add Diode for leakage
D9
HM@RB500V-40_100MA
R271
HM@2.2K_4
3
+3V +5V
R537
*HM@0_4
R538
HM@0_4
Q29
2
HM@FDV301N_200MA
R539 HM@100K_4
C699 HM@0.1U/10V_4X
R316,R311,R335,R330,R343,R339,R327 and R321
need to close to HDMI connector
R554 HM@604/F_4
3
R557 HM@604/F_4
R547 HM@604/F_4
R550 HM@604/F_4
R543 HM@604/F_4
1
R544 HM@604/F_4
R558 HM@604/F_4
R559 HM@604/F_4
INT_HDMI_TXDP0
INT_HDMI_TXDN0
INT_HDMI_TXDP1
INT_HDMI_TXDN1
INT_HDMI_TXDP2
INT_HDMI_TXDN2
INT_HDMI_TXCP
INT_HDMI_TXCN
RevC 0130 Change Pin define & FP & P/N
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, January 30, 2013
Date: Sheet of
Wednesday, January 30, 2013
Date: Sheet of
5
4
3
2
Wednesday, January 30, 2013
PROJECT :
HDMI/CEC
HDMI/CEC
HDMI/CEC
1
BD9
BD9
BD9
25 41
25 41
25 41
A1A
A1A
A1A
5
Atheros Lan
<LAN> <LNG>
Power Sequence
VDD33
D D
C301
LAN@10U/6.3V_6X
Close to Pin1
C307
LAN@10U/6.3V_6X
APU_PCIE_RST#[7,22,28]
LAN@12P/50V_4CC278
LAN@12P/50V_4CC277
+LAN_VDD33
23
0.163A(30mils)
+LAN_VDD33
PERSTn(20mils)
AVDDL 20mil
C673
C679
LAN@0.1U/16V_4Y
LAN@1U/6.3V_4X
C C
RevB 1222 Change cap value for vendor suggestion
=100ms
PERSTn
AVDDH 20mil
C675
LAN@1U/6.3V_4X
C289
LAN@0.1U/16V_4Y
C297
LAN@1U/6.3V_4X
R220 LAN@0_4
PCIE_WAKE#_LAN PCIE_WAKE#_LAN_R
R211 LAN@30K/F_4
C676
LAN@0.1U/16V_4Y
Y1
LAN@25MHZ_30
4 1
C295
*LAN@1000P/50V_4X
For EMI
TX0P
E@6.8P/50V_4NC257
E@6.8P/50V_4NC256
TX0N
E@6.8P/50V_4NC255
TX1P
E@6.8P/50V_4NC254
TX1N
PLACE NEAR LAN IC SIDE
B B
0920 FAE suggest remove 49.9K, 0.1u and 1000p
A A
<LAN> <LNG>
5
TRANSFORMER CONN
For ESD
1
TX0P
CH1
2
GND
TX0N
CH23CH3
LAN@TVLST2304AD0
RevC 0130 Stuff U9
U9
4
CKREQ_G#
AVDDL
LAN_XTLO
LAN_XTLI
AVDDH
10
RBIAS
R181
LAN@2.37K/F_4
Individual to GND
25mil
6
TX1P
CH4
5
VDD
4
TX1N
4
U10
1
VDD33
2
PERSTn
3
WAKEn
4
CLKREQn
5
ISOLATn
6
AVDDL_REG
7
XTLO
8
XTLI
9
AVDDH_REG
RBIAS
+LAN_VDD33
LAN@AR8162-B
41
10/100:AR8162B
50
GND
GND142GND243GND344GND445GND546GND647GND748GND849GND9
GIGA:AR8161B
<LAN> <LNG>
AVDD_CEN_R
C634
LAN@0.1U/16V_4Y
*LAN@GT1206200ASMD
LAN_LINKLED#
LAN_ACTLED
32
REFCLK_P
31
AVDDL
REFCLK_N
C304 LAN@1U/6.3V_4X
DVDDL
AVDDVCO
AVDDL
LAN@0.1U/16V_4YC303
LAN@0.1U/16V_4YC305
LAN@0.1U/16V_4YC296
40
38
LX
LED139LED0
DVDDL 20mil
37
36
35
34
33
RX_P
RX_N
AVDDL
DVDDL_REG
Atheros
AR8161/8162
TRXP011TRXN012AVDDL13TRXP114TRXN115AVDD3316TRXP217TRXN218AVDDL19TRXP3
20
TX1P
TX0P
TX1N
TX0N
AVDDH_C 30mil
AVDDH_C
AVDDL
AVDDL 20mil
U23
8
TX0N
TX0P
TX1N
TX1P
C643
*LAN@1000P/50V_4X
1
1
1
1
2
2
D5
2
*LAN@GT1206200ASMD
2
D4
RevA 1114 Add Gas Tube for Surge issue
RevC 0130 Un-stuff D4,D5
9
TD-
TX-
7
10
TD+
TX+
6
11
CT
CT
5
12
NC
NC
4
13
NC
NC
3
14
CT
CT
2
15
RD-
RX-
16
RD+1RX+
LAN@NS681610
LAN@0.01U/100V_6X
C200
*LAN@0.1U/10V_4X
C629 LAN@220P/3KV_1808X
3
3
LAN@0.1U/16V_4YC672
X-TX0N
X-TX0P
TERM0
TERM1
X-TX1N
X-TX1P
C221
TERM2
R155
LAN@75/F_8
TESTMODE
SMDATA
SMCLK
AVDDH
TRXN3
PCIE_TXN_LAN [3]
PCIE_TXP_LAN [3]
CLK_PCIE_LANP [8]
CLK_PCIE_LANN [8]
30
TX_P
29
TX_N
28
NC
27
26
25
24
PPS
23
LED2
22
21
C685
LAN@4.7U/6.3V_6X
PCIE_RXP_LAN_C
PCIE_RXN_LAN_C
AVDDH
C671 LAN@1U/6.3V_4X
LAN@0.1U/16V_4YC670
R503 LAN@0_6
C192
LAN@0.01U/100V_6X
TERM3
C180
R129
*LAN@0.1U/10V_4X
LAN@75/F_8
L30
C686
LAN@1U/6.3V_4X
LAN@0.1U/10V_4XC282
LAN@0.1U/10V_4XC283
LAN@0.1U/16V_4YC284
+LAN_VDD33
LAN@HCB1608KF-601T10_1A
AVDDLAVDDVCO
PCIE_RXP_LAN [3]
PCIE_RXN_LAN [3]
RJ45
X-TX1N
X-TX1P
X-TX0N
X-TX0P
2
CLK_REQ#
LAN-Wake up function
Wake on LAN function
<LAN> <LNG> <LN1>
CN14
2
8
NC4/3-
7
NC/3+
6
RX-/1-
5
NC2/2-
4
NC1/2+
3
RX+/1+
2
TX-/0-
1
TX+/0+
LAN@2RJ3057-008211F
1005 Update FP
TERM0
TERM0
TERM0
TERM0
<LAN>
Pull UP 10K to +3V in APU
PCIE_CLKREQ#_LAN[7]
Pull UP 10K to +3V_S5 in APU
PCIE_WAKE#[7,28]
+3V_S5
C300
LAN@0.01U/25V_4X
9
R482 *SHORT_6
GND
10
GND
<LAN>
+LAN_VDD33
R226 *LAN@0_6
3
1
Q14 LAN@ME1303_3A
2
LED0 = LAN_ACTLED
LED1 = LAN_LINKLED#
LED2
1
+3V
5
34
Q27B LAN@2N7002KDW_115MA
R522 *LAN@0_4
+LAN_VDD33
R523
LAN@10K_4
<LAN>
+LAN_VDD33
2
1
6
Q27A LAN@2N7002KDW_115MA
R525 *LAN@0_4
C299
*LAN@0.01U/25V_4X
R228 LAN@3.01K/F_4
1
0
1
0
1
0
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
+LAN_VDD33
R221
LAN@10K_4
PCIE_WAKE#_LAN
+3V_S5
R227
2
LAN@4.7K_4
High core voltage(default=1)
Low core voltage
Switch mode regulator (SWR) select
Linear regulator (LDO) select
25 MHz external clock input
48 MHz external clock input
Q15
LAN@LTC044EUBFS8TL_30MA
13
Power on Strapping pin
R521 *LAN@5.1K/F_6
LAN_ACTLED
R516 LAN@5.1K/F_6
LAN_LINKLED#
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
ATHEROS LAN (AR8152B)
ATHEROS LAN (AR8152B)
ATHEROS LAN (AR8152B)
Wednesday, January 30, 2013
Wednesday, January 30, 2013
Wednesday, January 30, 2013
1
CKREQ_G#
LAN_P [33]
BD9
BD9
BD9
26
26 41
26 41
26 41
A1A
A1A
A1A
5
Codec (CX20756-11Z)
<ADO> <EMI>
4
3
2
1
29
D D
R371 0_6
+3V
R364 0_6
RevB 1219 Change for EOD
RevB 1219 Change for EOD
C C
C515 0.1U/16V_4Y
ACZ_RST#[7]
ACZ_BITCLK[7]
ACZ_SYNC[7]
ACZ_SDIN0[7]
ACZ_SDOUT[7]
Low Active
AMP_MUTE#[33]
R368 33_4
PCBEEP[7]
R369 *10K_4
DMIC_DATA[ 30]
DMIC_CLK[30]
B B
1.2mA(20mils)
C524
C503
4.7U/6.3V_6X
0.1U/16V_4Y
C506
C505
*10U/6.3V_6X
0.1U/16V_4Y
Determining HDA use +1.5V/+3V
48.7mA(20mils)
C487
C485
0.1U/16V_4Y
*10U/6.3V_6X
R360 0_4
R361 33_4
AMP_MUTE#
C516 0.1U/16V_4Y
PCBEEP_R PCBEEP_C
R354 33_4
Place close to audio codec.
1019 FAE suggest change to 33ohm
DMIC
DMIC_DATA
C484
*0.47U/6.3V_4X
C483
*0.47U/6.3V_4X
ACZ_BITCLK_R
SDATA_IN
Output
C491
4.7U/6.3V_6X
DMIC_DATA
DMIC
TP35
TP36
Output
C488
C486
0.1U/16V_4Y
1U/10V_6Y
ADOGND ADOGND
+3AVDD
C522
0.1U/16V_4Y
Near chip
+1.5AVDD_S5
+3AVDD
FILT_1.8V
C492
0.1U/16V_4Y
2
3
U18
9
RESET#
FILT_1.8V
5
BIT_CLK
8
SYNC
6
SDATA_IN
4
SDATA_OUT
39
SPKR_MUTE#
10
PCBEEP
1
DMIC_DAT/GPIO1
40
DMIC_CLK/MUSIC_REQ/GPIO0
37
GPIO1/PORTC_R_MIC
36
MUSIC_REQ/GPIO0/PORTC_L_MIC
For EMI
ACZ_BITCLK
C498
*10P/50V_4C
A A
ACZ_SDOUT
C495
*10P/50V_4C
ACZ_RST#
C509
*10P/50V_4C
FILT_1.65V
7
18
VDD_IO
DVDD33
VDDO33
LEFT+
12
24
29
AVDD_HP
CX20756-11Z
LEFT-14RIGHT-
15
FILT_1.65V
Output
27
28
AVDD_3.3V
RIGHT+
17
AVDD_3.3
C493
4.7U/6.3V_6X
+5AVDD
RevB 1219 Change for EOD
C517
0.1U/16V_4Y
13
16
11
AVDD_5V
LPWR_5.0
RPWR_5.0
CLASS-D_REF
38
JSENSE
35
MICBIASC
34
MICBIASB
33
PORTB_R_LINE
32
PORTB_L_LINE
26
HGNDB
25
HGNDA
31
PORTD_B_MIC
30
PORTD_A_MIC
23
PORTA_R
22
PORTA_L
21
AVEE
20
FLY_N
19
FLY_P
EP_GND
41
C762 0.1U/16V_4Y
C531 0.1U/16V_4Y
C763 *0.1U/16V_4Y
C767 *0.1U/16V_4Y
<ADO> <EMC>
C494
0.1U/16V_4Y
1A(100mils)0.061mA(15mils)
C766
*10U/6.3V_6X
(40mils)
C518
0.1U/16V_4Y
SENSE_A
TP37
MIC1-VREFO_B MIC1-VREFO
MIC1-RR MIC1_R1
TP38
TP39 C478
AVEE
FLY_N
C519 1U/10V_6Y
FLY_P
ADOGND
SPK_R+
SPK_RÂSPK_LÂSPK_L+
RevB 1224 Change from bead to resistor
R603 0_6
C765
Layout Note: Path from +5V_IC to LPWR_5.0 and
0.1U/16V_4Y
RPWR_5.0 must be very low resistance ( <0.01 ohms).
Place bypass caps very close to device.
RevB 1219 Change for EOD
C525
0.1U/16V_4Y
R353 0_4
C479 2.2U/10V_6X
C480 2.2U/10V_6X
10U/6.3V_6X
10U/6.3V_6X
MIC1_L1MIC1-LL
C527
C526
RevB 1222 Change for EOD
ADOGND
HPOUT-R
HPOUT-L
C512
0.1U/16V_4Y
C521
4.7U/6.3V_6X
+5V+1.5V_S5
R350 0_4
SENSE_A_R
R351
5.11K/F_4
R356 39.2K/F_4
R355 20K/F_4
MIC1-LL
MIC1-RR
SENSE PIN A
C481
*0.47U/6.3V_4X
+3AVDD
Port_A#
Port_B#
C482
*0.47U/6.3V_4X
HP
HPOUT-L HPOUT-L3
R367 5.1/F_6
External MIC
MIC1_L1 MIC1_L3
HPOUT-L2
R366 5.1/F_6
HPOUT-R2
D18 *VPORT 0603 220K-V05
D17 *VPORT 0603 220K-V05
<ADO> <EMC>
MIC1-VREFO
R589
3.3K/F_4
R357 100/F_6
R352 100/F_6
MIC1_L2
MIC1_R2
2 1
D15 *VPORT 0603 220K-V05
2 1
D14 *VPORT 0603 220K-V05
L19 HCB1608KF-121T20_2A
L18 HCB1608KF-121T20_2A
Internal Speaker
<ADO> <EMC>
BOARD_ID7[7,8]
BOARD_ID9[7,8]
INSPKL-N
INSPKL+N
INSPKR-N
INSPKR+N
D26
VPORT 0603 220K-V05
*100P/50V_4N
HPOUT-L3
HPOUT-R3
C764
R590
*4.7U/6.3V_6X
3.3K/F_4
ADOGND
L17 HCB1608KF-121T20_2A
L16 HCB1608KF-121T20_2A
100P/50V_4N
100P/50V_4N
MIC1_L3
MIC1_R3
R121 PBY160808T-501Y-N_1.2A
R120 PBY160808T-501Y-N_1.2A
R119 PBY160808T-501Y-N_1.2A
R118 PBY160808T-501Y-N_1.2A
Close to CN2902
C136
E@2200P/50V_4X
INSPKL+N INSPKL-NINSPKR-NINSPKR+N
D25
VPORT 0603 220K-V05
RevC 0204 Change Audio Jack
HPOUT-R3HPOUT-R
Port_A#
C504C507
C528
*0.1U/25V_6X
*100P/50V_4N
ADOGND
RevC 0204 Change Audio Jack
MIC1_R3MIC1_R1
Port_B#
C489
C476
*0.1U/25V_6X
ADOGND
INSPKR+NSPK_R+
INSPKR-NSPK_RÂINSPKL-NSPK_LÂINSPKL+NSPK_L+
RevC 0130 Change to 8 pin connector
C135
C133
E@2200P/50V_4X
E@2200P/50V_4X
D23
VPORT 0603 220K-V05
CN8
1
2
6
3
4
5
2SJ3013-018311F
Normal Open Jack
Port_A#
1
CN7
2
6
3
4
5
2SJ3013-018311F
Normal Open Jack
Port_B#
CN4
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
88266-080L
C134
E@2200P/50V_4X
D24
VPORT 0603 220K-V05
7
8
9
D16
*VPORT 0603 220K-V05
7
8
9
D12
*VPORT 0603 220K-V05
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Monday, February 04, 2013
Date: Sheet of
Monday, February 04, 2013
Date: Sheet of
5
4
3
2
Monday, February 04, 2013
PROJECT :
AUDIO CODEC (CX20756-11Z)
AUDIO CODEC (CX20756-11Z)
AUDIO CODEC (CX20756-11Z)
1
BD9
BD9
BD9
27 41
27 41
27 41
A1A
A1A
A1A
5
MINI Card Slot#1
(WiFi)
D D
C C
Pull UP 10K to +3V in APU
PCIE_CLKREQ#_WLAN[7]
B B
Pull UP 10K to +3V_S5 in APU
PCIE_WAKE#[7,26]
<MNW>
+WIMAX_P
2
3
1
Q3 *IOIC@ME2N7002E_200MA
R22 NIOIC@0_4
2
3
Q1 *IOIC@ME2N7002E_200MA
1
R11 *IOIC@0_4
PCLK_DEBUG[8]
+WIMAX_P+WIMAX_P
PLTRST#[7,29,33]
+WIMAX_P
R10
10K_4
PLTRST# PLTRST#_debug
R13
*IOIC@10K_4
CLKREQ#
WLAN_WAKE#
4
R431 NMP@0_4
R445 NMP@0_4
PCIE_TXP_WLAN[3]
PCIE_TXN_WLAN[3]
PCIE_RXP_WLAN[3]
PCIE_RXN_WLAN[3]
CLK_PCIE_WLANP[8]
CLK_PCIE_WLANN[8]
BT_RFCTRL[33]
CLKREQ#
BT_RFCTRL_BT
WLAN_WAKE#
Before RAMP must to remove
debug card component
C576
E@0.01U/25V_4X
CN10
BT_RFCTRL_BT
PCLK__debug_R
R14 *0_4
51
NC
49
C-Link_RST
47
C-Link_DAT
45
C-Link_CLK
43
GND
41
NC
39
NC
37
GND
35
GND
33
PETp0
31
PETn0
29
GND
27
GND
25
PERp0
23
PERn0
21
GND
19
NC
17
NC
15
GND
13
REFCLK+
11
REFCLK-
9
GND
7
CLKREQ#
5
BT_CHCLK
3
BT_DATA
1
WAKE#
AAA-PCI-052-P01
1018 change to 7H
2
1 3
Q4 LTC044EUBFS8TL_30MA
C571
E@0.1U/16V_4Y
+WIMAX_P
C582
*10U/6.3V_6X
52
+3.3V
50
GND
48
+1.5V
46
LED_WP AN#
44
LED_WL AN#
42
NC
40
NC
38
USB_D+
36
USB_D-
34
GND
32
SMB_DATA
30
SMB_CLK
28
+1.5V
26
GND
24
+3.3Vaux
22
PERST#
20
W_DISA BLE#
18
GND
16
NC
14
NC
12
NC
10
NC
8
NC
6
+1.5V
4
GND
2
+3.3V
R16 10K_4
3
+1.5V +WIMAX_P
C32
E@0.1U/16V_4Y
BT_RFCTRL_BT
2
RevB 1219 Change for EODRevB 1219 Change for EOD
C25
C10
*C@0.1U/16V_4Y
0.1U/16V_4Y
USBP7+
USBP7-
WLCGDAT_SMB
WLCGCLK_SMB
RF_EN
LFRAME#_PCIE
LAD3_PCIE
LAD2_PCIE
LAD1_PCIE
LAD0_PCIE
2
RN2 NMP@0X2
4
2
RN1 NMP@0X2
4
R386 NMP@0_4
+3V +WIMAX_P
+3V_S5
C579
*IOIC@0.01U/25V_4X R397
C31
*C@0.1U/16V_4Y
R393 *300_4
C574 *150P/50V_4N
1
3
1
3
R426 NIOIC@0_8
R425 NIOIC@0_8
1
Q24 *IOIC@ME1303_3A
C580 *15P/50V_4C
APU_PCIE_RST# [7,22, 26]
RF_EN [33]
LFRAME# [8,9,33]
LAD3 [8,33]
LAD2 [8,33]
LAD1 [8,33]
LAD0 [8,33]
3
2
*IOIC@0.01U/25V_4X
C588
*C@10U/6.3V_6X
C581
USBP7+ [8]
USBP7- [8]
R400 *IOIC@3.01K/F_4
SMB_LAN_CLK[7,24,32]
SMB_LAN_DAT[ 7,24,32]
+3V_S5
*IOIC@4.7K_4
Q23
2
*IOIC@LTC044EUBFS8TL_30MA
1 3
SMBus(WLAN)
R39 *0_4
Q5B 2N7002KDW_115MA
3 4
5
2
6
Q5A 2N7002KDW_115MA
R32 *0_4
WLAN_P [33]
1
28
WLCGCLK_SMB
R33
4.7K_4
+WIMAX_P
R40
4.7K_4
1
WLCGDAT_SMB
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
5
4
3
2
Tuesday, December 25, 2012
PROJECT :
MINI CARD
MINI CARD
MINI CARD
1
BD9
BD9
BD9
28 41
28 41
28 41
A1A
A1A
A1A
5
BATERRY
BATERRY
BATERRYBATERRY
+5VPCU
2
-BATLED0
-BATLED1
R372 2.2K_4
R373 1.2K/F_4
1
2
3
D19
*PJMBZ5V6
D D
1
LED1
12-12Z/S2ST3D-C31/2C(QN)
3
-BATLED0
-BATLED1
BAT_SAT0# [33]
BAT_SAT1# [33]
4
POWER
POWER
POWERPOWER
+5VPCU
RevB 1130 Change back to Dual LED FP & P/N
1
LED2
12-11Z/T3D-CP2Q2B12Y/2C(QN)
2
3
SUSLED SUSLED_EC#
3
R377 1.2K/F_4
SUSLED
2
RF LED
RF LED
RF LEDRF LED
1
29
3
1 2
LED3 12-21/S2C-AQ2R2B/2C
RF_LED_R
R375 1.2K/F_4
1
3
2
D20
*PJMBZ5V6
RF_LED_R
1
3
2
D21
*PJMBZ5V6
+5V
RF_LED# [33]SUSLED_EC# [33]
2 IN 1 CARD READER (Type: MS/SD)
Card Reader (GL834L QFN24-3.3V)
C C
+3V_CARD
B B
+3V_CARD
C508
4.7U/6.3V_6X
R370 0_8
RevB 1220 Co-lay L40 & RP27 for EMI
L40
USBP5+[8]
USBP5-[8]
A A
USBP5+
USBP5-
5
2
3
*E@MCM2012B900GBE
2
RP27 0X2
4
C514 *15P/50V_4C
C511
0.1U/16V_4Y
2.2U/10V_6X
RevB 1222 Change for EOD
1
USBP5+_C
1
2
443
1
3
R365 *300_4
USBP5-_C
USBP5+_C
USBP5-_C
<MMC>
FAE suggestion
near PIN 24 9/20
USBP5-_C
USBP5+_C
C520C523
0.1U/16V_4Y
C496
4.7U/6.3V_6X
R363 0_8
C502
C497
0.1U/10V_4X
C513
1U/6.3V_4X
PLTRST#
C500
0.1U/16V_4Y
4.7U/6.3V_6X
SB0:SD_D7/MS_CLK
SB1:SD_D6/MS_D3
SB3:SD_D5/MS_D2
SB4:SD_D4/MS_D0
SB5:SD_WP/MS_D1
SB8:SD_D1/MS_D7
SB9:SD_D0/MS_D6
SB12:SD_D3/MS_D4
SB13:SD_D2/MS_D5
+3V_CARD
R358
*1K_4
R359
*100K_4
3
+3V_CARD
C499
0.1U/16V_4Y
0.1U/16V_4YC501
VCC_SD
SD_GPIO0
+3V_CARD
SD_DETECT#
PLTRST#
20
21
22
23
24
RSTZ
PMOS
DVDD33
SD_CDZ
GL834L
QFN24-3.3V
SB17SB38SB49SB510MS_BS11SB8
SD_WP
19
GPIO0
DVDD33
12
SD_DATA1
VDD18
SB13
SB12
SD_CMD
SD_CLK
SB9
GL834L-OGY03
18
+1.8V_CARD
17
SD_DATA2
16
SD_DATA3
15
SD_CMD
14
SD_CLK
13
SD_DATA0
PLTRST#[7,28,33]
U19
1
DVDD33
2
DM
3
DP
4
AVDD33
5
MS_INS
6
SB0
G1
25
4
+3V+3V_CARD
VCC_SD
SD_DATA2 SD_DATA2_R
SD_DATA1 SD_DATA1_R
SD_DATA0 SD_DATA0_R
SD_CLK SD_CLK_R
SD_CMD SD_CMD_R
SD_DATA3 SD_DATA3_R
SD_DATA0_R
SD_DATA1_R
SD_DATA2_R
SD_DATA3_R
SD_CLK_R
SD_GPIO0
R3116
NC
Power Saving Mode (default)
10K Normal Mode
800mA 40mils
C474
C473
C472
0.1U/16V_4Y
Close to connector
R342 E@BLM15BD121SN1D_300MA
R343 E@BLM15BD121SN1D_300MA
R344 E@BLM15BD121SN1D_300MA
R347 E@BLM15BD121SN1D_300MA
R340 E@0_4
R341 E@BLM15BD121SN1D_300MA
RevB 1130 Add EMI suggestion
C769 *E@12P/50V_4C
C768 *E@12P/50V_4C
C770 *E@12P/50V_4C
C771 *E@12P/50V_4C
C772 *E@4.7P/50V_4C
R362 *10K_4
*0.1U/16V_4Y
*0.1U/16V_4Y
SD_WP
RevA 1120 remove for power saving mode
2
R376 E@0_4
R349 33_4
VCC_SD
SD_WP_R
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
SD_DETECT#_RSD_DETECT#
CN24
10
W/P(GND)
9
DATA2
8
DATA1
7
DATA0
6
VSS2
5
CLK
3
VSS1
2
CMD
1
DATA3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
CARD READER/LED
CARD READER/LED
CARD READER/LED
Tuesday, December 25, 2012
Tuesday, December 25, 2012
Tuesday, December 25, 2012
1016 update CONN
11WP12
4
PSDBT0-09GLBS1N14H1
C/D
VDD
GND4
GND3
GND113GND2
14
1
16
15
BD9
BD9
BD9
29 41
29 41
29 41
A1A
A1A
A1A
[CCD]
CCD HALL SENSOR&BACK LIGHT
USBP6+_CCD
USBP6-_CCD
USBP6+_CCD
USBP6-_CCD
D D
+3V
R384 Hud son@300_4
0924 Bolton without R+C
F1 SMD1206P110TFT
12
R7 *0_8
1015 Exchange
5
RevB 1220 Add C.M Chock for EMI
L22
1
2
3
E@MCM2012B900GBE
1
2
443
USBP6+_CCD [8]
USBP6-_CCD [8]
C568 Hud son@15P/50V_4C
C5 10U/6.3V_6X
USBP6+_CCD_C
USBP6-_CCD_C
CCD_POWER
+
RevB 1219 Change for EOD
C567 *4.7P/50V_4C
C542 *4.7P/50V_4C
USBP6+_CCD
USBP6-_CCD
Close LVDS Connector
LCD POWER
SWITCH
4
1017 3D eDP panel VDD=5V
C533
eDP@1U/10V_6X
R1 eDP@0_1206
APU_DIGON[5]
PANEL_VCC_R[24]
R2 LDS@0_1206
3
<LDS> <HSR>
+5V
+3V
2A
R379
eDP@0_1206
R380
LDS@0_1206
R3
100K_4
U1
6
IN
4
IN
3
ON/OFF
AP2821KTR-G1
C534
LDS@1U/10V_6X
OUT
GND
GND
LCDVCC
1
2
C1
5
0.1U/16V_4Y
SWITCH
2
R378 100K_4
+3VPCU
2
1
LID591#
MR1
C532
APX9132H AI-TRG
3
0.1U/10V_4X
R84 LDS@0_4
R87 eDP@0_4
R91
100K_4
DISPON
D1
LCP0G050M0R2R
R4 1.2K/F_4
LID591# [ 33]
EC_FPBACK# [33]
TRAVIS_BL_EN [24]DISPON_I[33]
APU_BL_EN [5]
1
30
CN9
G_1
1
2
3
4
5
6
7
8
9
10
G_2
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
G_3
31
32
33
34
35
36
37
38
39
40
G_4
7300L40-000000-G4
RevB 1224 Change FP & P/N
111
12
CRTDDAT
13
CRTHSYNC
14
CRTVSYNC
15
CN17
CRT@10256-00011
1020 Update CRT CONN
CRTDCLK
RevA 1115 Change P/N & FP
CRTHSYNC
C317
CRT@10P/50V_4C
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
LVDS/CCD/DRT
LVDS/CCD/DRT
LVDS/CCD/DRT
1
BD9
BD9
BD9
30 41
30 41
30 41
A1A
A1A
A1A
LCD_EDIDDATA
LCD_EDIDCLK
[LDS]
VIN
LVDS Enable
TRAVIS_VARY_BL[24]
C7 E@2200P/50V_4X
C6 E@2200P/50V_4X
APU_CRT_RED
APU_CRT_GRE
APU_CRT_BLU
APU_CRT_HSYNC
APU_CRT_VSYNC
APU_DDCDAT
APU_DDCCLK
5
R381 0_8
+3V
APU_VARY_BL[5,24]
LCD_BK_POWER
C536
1000P/50V_4X
R9 4.7K_4
R8 4.7K_4
R5 eDP@0_4
R6 LDS@0_4
C3 0.1U/10V_4X
APU_CRT_RED
APU_CRT_GRE
C537
0.1U/25V_6X
LCD_EDIDCLK
LCD_EDIDDATA
LVDS_VADJ
+3VPCU +3VPCU
C569
0.1U/10V_4X
R528
CRT@150/F_4
R527
CRT@150/F_4
C570
0.1U/10V_4X
L33 CRT@BLM18BA470SN1D_300MA
L32 CRT@BLM18BA470SN1D_300MA
L31 CRT@BLM18BA470SN1D_300MA
R526
CRT@150/F_4
C692
CRT@10P/50V_4C
C691
CRT@10P/50V_4C
C690
CRT@10P/50V_4C
RevB 1220 Change from 6.8P to 10P for EMI suggestion
4
INT_LCD_TXLCLKOUT-[24]
INT_LCD_TXLCLKOUT+[24]
INT_LCD_TXLOUT0-[24]
INT_LCD_TXLOUT0+[24]
INT_LCD_TXLOUT1-[24]
INT_LCD_TXLOUT1+[24]
INT_LCD_TXLOUT2-[24]
INT_LCD_TXLOUT2+[24]
INT_LCD_TXUOUT0-[24]
INT_LCD_TXUOUT0+[24]
INT_LVDS_TXN0_R[24]
INT_LVDS_TXP0_R[24]
INT_LVDS_TXN1_R[24]
INT_LVDS_TXP1_R[24]
INT_LVDS_TXN2[5]
INT_LVDS_TXP2[5]
INT_LVDS_TXN3[5]
INT_LVDS_TXP3[5]
INT_LVDS_AUXN_R[24]
INT_LVDS_AUXP_R[24]
C267
CRT@0.1U/25V_6X
C683
CRT@10P/50V_4C
+3V+5V
CRT@0.1U/25V_6X
C268
RP8 LDS@0X2
241
RP11 LDS@0X2
241
RP13 LDS@0X2
241
RP15 LDS@0X2
241
RP17 LDS@0X2
241
RP7 eDP@0X2
241
RP9 eDP@0X2
241
RP12 eDP@0X2
241
RP14 eDP@0X2
241
RP16 eDP@0X2
241
C681
CRT@10P/50V_4C
Close to CN3200
3
3
3
3
3
3
3
3
3
3
CRT_RED_L
CRT_GRE_L
CRT_BLU_LAPU_CRT_BLU
C682
CRT@10P/50V_4C
+5V
+3V
3
LCD_TXLOUT0ÂLCD_TXLOUT0+
LCD_TXLOUT1ÂLCD_TXLOUT1+
LCD_TXLOUT2ÂLCD_TXLOUT2+
LCD_TXLCLKOUTÂLCD_TXLCLKOUT+
LCD_TXUOUT0ÂLCD_TXUOUT0+
+5V
C272
CRT@0.1U/16V_4Y
+3V
C271 CRT@0.22U/10V_4X
+3V
C273
CRT@0.1U/16V_4Y
R234 CRT@4.7K_4
R231 CRT@4.7K_4
5V_CRT2
CRT_RED_L
CRT_GRE_L
CRT_BLU_L
INT_LVDS_HPD[5,24]
+5V
APU_DDCDAT
APU_DDCCLK
U11
1
VCC_SYNC
7
VCC_DDC
8
BYP
2
VCC_VIDEO
3
VIDEO_1
4
VIDEO_2
5
VIDEO_3
6
GND
CRT@CM2009-02QR
+3V
C539 *47P/50V_4N
INT_LCD_EDIDCLK[24]
INT_LCD_EDIDDATA[24]
INT_LCD_TXUOUT1-[24]
INT_LCD_TXUOUT1+[24]
INT_LCD_TXUOUT2-[24]
INT_LCD_TXUOUT2+[24]
INT_LCD_TXUCLKOUT-[24]
INT_LCD_TXUCLKOUT+[24]
2 1
D27 CRT@SS14L_1A
16
SYNC_OUT2
14
SYNC_OUT1
15
SYNC_IN2
13
SYNC_IN1
10
DDC_IN1
11
DDC_IN2
9
DDC_OUT1
12
DDC_OUT2
LCD_BK_POWER
C538 *10U/6.3V_4X
R383 eDP@0_4
R382 LDS@0_4
C540 22P/50V_4N
DMIC_DATA[27]
DMIC_CLK[27]
VSYNC1 CRTVSYNC
HSYNC1
APU_CRT_VSYNC 5V_CRT2
APU_CRT_HSYNC
APU_DDCCLK
APU_DDCDAT
CRTDCLK
CRTDDAT
2
L20 FCM1005KF-221T03_300MA
L21 FCM1005KF-221T03_300MA
C541 22P/50V_4N
F3 CRT@SMD1206P110TFT
LCDVCC
3
241
RP6 LDS@0X2
RP18 LDS@0X2
RP19 LDS@0X2
RP20 LDS@0X2
12
3
241
3
241
3
241
Close to CN3200
C688 CRT@0.1U/16V_4Y
5V_CRT2
CRT_RED_L
CRT_GRE_L
CRT_BLU_L
R232 CRT@39/F_4
R229 CRT@39/F_4
R230
CRT@2.7K_4
R235
CRT@2.7K_4
C311
CRT@10P/50V_4C
LCDVCC
CCD_POWER
DMIC_DATA_R
DMIC_CLK_R
LVDS_VADJ
DISPON
LCD_EDIDCLK
LCD_EDIDDATA
USBP6-_CCD_C
USBP6+_CCD_C
LCD_TXLOUT0ÂLCD_TXLOUT0+
LCD_TXLOUT1ÂLCD_TXLOUT1+
LCD_TXLOUT2ÂLCD_TXLOUT2+
LCD_TXLCLKOUTÂLCD_TXLCLKOUT+
LCD_TXUOUT0ÂLCD_TXUOUT0+
LCD_TXUOUT1ÂLCD_TXUOUT1+
LCD_TXUOUT2ÂLCD_TXUOUT2+
LCD_TXUCLKOUTÂLCD_TXUCLKOUT+
1617
6
7
2
8
3
9
4
10
5
C316
CRT@10P/50V_4C
C312
CRT@10P/50V_4C
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, December 26, 2012
Date: Sheet of
Wednesday, December 26, 2012
Date: Sheet of
Wednesday, December 26, 2012
LCD Panel Module
C C
B B
[CRT]
CRT
APU_CRT_RED[5]
APU_CRT_GRE[5]
APU_CRT_BLU[5]
APU_CRT_HSYNC[5]
APU_CRT_VSYNC[5]
APU_DDCDAT[ 5]
APU_DDCCLK[5]
A A
5
4
3
2
1
SATA ODD
CN16
D D
GND14
GND1
RXP
RXN
GND2
TXN
TXP
GND3
DP
+5V
+5V
RSVD
GND
GND
GND15
10300-00001
1020 update CONN
RevA 1115 Change P/N & FP
C C
B B
[ODD]
+5V
14
1
2
SATA_TXP1_C
3
SATA_TXN1_C
4
5
SATA_RXN1_C
6
SATA_RXP1_C
7
8
ODD_DP
9
10
11
ODD_MD#_Q
12
13
15
ODD_MD#_Q
C230 0.01U/25V_4X
C233 0.01U/25V_4X
C241 0.01U/25V_4X
C245 0.01U/25V_4X
R174 NZRP@1K/F_4
R175 ZRP@0_4
+5V_ODD
R223
ZRP@10K_4
1
Q12 ZRP@ME2N7002E_200MA
ODD_PRSNT#
+3V
2
3
SATA_TXP1 [8]
SATA_TXN1 [8]
SATA_RXN1 [8]
SATA_RXP1 [8]
ODD_PRSNT# [7]
C669
0.1U/10V_4X
C666
0.1U/10V_4X
ODD_MD# [7]
C663
10U/6.3V_6X
+5V_ODD
+
C647
*100U/6.3V_3528P_E45b
1
C294
ZRP@0.01U/25V_4X
3D-u-micro P<GSR>
<GSR>3D-LDO Power
<OZP>ODD Zero power
L4 NZRP@HCB1608KF-121T30_3A
3
Q10
2
ZRP@ME1303_3A
C306
*ZRP@0.01U/25V_4X
R224 ZRP@3.01K/F_4
+5V_ODD
3
1
+5V_ODD
R233
ZRP@22_8
2
Q13
ZRP@ME2N7002E_200MA
+5V
R225
ZRP@4.7K_4
2
Q11
1 3
ZRP@LTC044EUBFS8TL_30MA
APU_ODD_EN [7]
SATA
[HDD]
HDD
CN21
23
GND23
1
GND1
2
SATA_TXP0_C
RXP
3
SATA_TXN0_C
RXN
4
GND2
5
SATA_RXN0_C
TXN
6
SATA_RXP0_C
TXP
7
GND3
8
3.3V
9
3.3V
10
3.3V
11
GND
12
GND
13
GND
14
5V
15
5V
16
5V
GND
RSVD
GND
12V
12V
12V
GND24
6030H-22G05
1018 update HDD CONN
RevA 1115 Need to update correct FP
+5V_HDD1
17
18
19
C460
20
21
0.1U/16V_4Y
22
24
C734 0.01U/25V_4X
C738 0.01U/25V_4X
C748 0.01U/25V_4X
C749 0.01U/25V_4X
C462
C461
10U/6.3V_6X
0.1U/16V_4Y
RevB 1219 Change for EOD
SATA_TXP0 [8]
SATA_TXN0 [8]
SATA_RXN0 [8]
SATA_RXP0 [8]
+
C464
*100U/6.3V_3528P_E45b
R337 0_8
33
+5V
3D-SMBus
A A
<GSR>
3D-Sensor IC
5
4
<GSR>
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, December 27, 2012
Date: Sheet of
Thursday, December 27, 2012
Date: Sheet of
3
2
Thursday, December 27, 2012
PROJECT :
HDD/ODD
HDD/ODD
HDD/ODD
1
BD9
BD9
BD9
31 41
31 41
31 41
A1A
A1A
A1A
5
4
3
2
1
KEY BOARD Connector
INT KeyBoard
D D
C C
C557 ESD@39P/50V_4N
C558 ESD@39P/50V_4N
C559 ESD@39P/50V_4N
C560 ESD@39P/50V_4N
C561 ESD@39P/50V_4N
C562 ESD@39P/50V_4N
C563 ESD@39P/50V_4N
C564 ESD@39P/50V_4N
C553 ESD@39P/50V_4N
C554 ESD@39P/50V_4N
C555 ESD@39P/50V_4N
C556 ESD@39P/50V_4N
C549 ESD@39P/50V_4N
C550 ESD@39P/50V_4N
C551 ESD@39P/50V_4N
C552 ESD@39P/50V_4N
C545 ESD@39P/50V_4N
C546 ESD@39P/50V_4N
C547 ESD@39P/50V_4N
C548 ESD@39P/50V_4N
C543 ESD@39P/50V_4N
C544 ESD@39P/50V_4N
ESD Issue
K_LED_P
CAPSLED
C565
220P/50V_4X
C566
220P/50V_4X
KEY BOARD LED
<KBP> <EMI>
B B
EMI PAD
VIN VIN VIN VIN VIN VIN VIN VIN
C185
E@0.1U/25V_4X
<EMI>
C9
*0.1U/25V_4X HOLE9
+3V
C28
*0.1U/25V_4X
MX7
MX2
MX3
MX4
MX0
MX5
MX6
MX1
MY7
MY13
MY12
MY15
MY3
MY5
MY14
MY6
MY2
MY1
MY0
MY4
MY16
MY17
NUMLED
R385 150_4
BOARD_ID6[7,8]
1010 Reserve
KB_LED[33]
C4
E@1U/25V_6X
<KBC> <EMI>
C187
220P/50V_4X
K_LED_P
0.35A(20mils)
+5V
C314
E@0.1U/25V_6X
CN1
36
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
91504-340N
RevA 1115 Change P/N
MX1 MX2
MX6
MX5 MX4
MX0
For EMI
C2 *E@0.1U/10V_4X
R15 *Metal@0_4
R12 Metal@300_4
*Metal@1U/6.3V_4X
C458
E@0.1U/25V_6X
K_LED_P
MY16
MY17
MY2
MY1
MY0
MY4
MY3
MY5
MY14
MY6
MY7
MY13
MY8
MY9
MY10
MY11
MY12
MY15
MX7
MX2
MX3
MX4
MX0
MX5
MX6
MX1
K_LED_P
CAPSLED
NUMLED
+3VPCU
10
RP10
9
8
7 4
MY16 [33]
MY17 [33]
MY2 [33]
MY1 [33]
MY0 [33]
MY4 [33]
MY3 [33]
MY5 [33]
MY14 [33]
MY6 [33]
MY7 [33]
MY13 [33]
MY8 [33]
MY9 [33]
MY10 [33]
MY11 [33]
MY12 [33]
MY15 [33]
MX7 [33]
MX2 [33]
MX3 [33]
MX4 [33]
MX0 [33]
MX5 [33]
MX6 [33]
MX1 [33]
CAPSLED [33]
NUMLED [33]
1
10KX8
2
3
56
MX7
MX3
RevC 0130 Change FP & P/N
CN2
1
2
3
6
4 5
Metal@88513-0401
2
Q2
Metal@MMBT2222A_600MA
C8
1 3
RevB 1219 Change for EOD
C490
*E@10U/6.3V_6X
C529
*E@10U/6.3V_6X
TOUCH PAD BOARD
BOM option
R139 METAL@0_4
+3V
R141 TEX@0_4
+5V
ID_Detect default
Metal
TEXTURE
Power Board (UIF)
NBSWON#[33]
PWRLED[33]
ME2N7002E_200MA
RevA 1114 Add Q3402 for PWRLED
HOLE
+3.3V
+5V
NBSWON#
Q9
2
<OTH>
HOLE17
<PSW>
PWRLED#_Q
1008 Reserve for ESD
3
D6
ESD@LCP0G050M0R2R
1
HOLE1
67
5
8
4
9
123
*HG-C315D118P2
HOLE14
67
5
8
4
9
123
*HG-C315D118P2
+TP_PWR
C222
4.7U/6.3V_6X
+5V
R185 0_4
HOLE3
<TPD> <EMI>
TPDATA[33]
TPCLK[33]
C225
E@0.1U/16V_4X
5
1
PWRLED#_R
C259
220P/50V_4X
RevA 1026 Add EMI suggestion
HOLE6
67
5
8
4
9
123
*HG-C315D118P2
HOLE10
67
5
8
4
9
123
*HG-C315D118P2
HOLE15
2
3
4
C258
E@220P/50V_4X
8
9
8
9
6
RevA 1026 Add EMI suggestion
R136 E@0_6
R137 E@0_6
C190
*10P/50V_4C
TP board <TPD>
CN6
5
6
50503-0040N-001
123
123
HOLE11
HOLE8
67
5
4
*HG-C315D118P2
HOLE16
67
5
4
*HG-C315D118P2
8
9
8
9
HOLE2
123
*HG-C315D118P2
HOLE5
123
*HG-C315D118P2
SMB_LAN_DAT[7,24,28]
SMB_LAN_CLK[7,24,28]
67
5
4
67
5
4
C224
*10P/50V_4C
6
5
4
3
2
1
50503-0060N-001
TPDATA_R
TPCLK_R
SMB_LAN_CLK_Q
SMB_LAN_DAT_Q
C191
*10P/50V_4C
+TP_PWR
C189
*10P/50V_4C
1010 For EMI
3 4
Q8B 2N7002KDW _115MA
Q8A 2N7002KDW _115MA
6
RevB 1130 Add 4.7K PURevB 1204 Change power rail from +5VPCU to +5V
5
2
1
RevB 1224 Remove Hole & Add PAD for ME
HOLE13
1
*spad-bd9-np
1
*spad-bd9-np
PAD3
PAD4
8
9
123
HOLE7
CN5
6
5
4
3
2
1
SMB_LAN_DAT_Q
R591
4.7K_4
R592
4.7K_4
SMB_LAN_CLK_Q
HOLE12
67
5
4
*HG-C315D118P2
32
+3V
34
+1.5VSUS+5V +5V +5V +5V +5V +5V
C708
A A
*0.1U/10V_4X
+3V +3V +3V +3V +3V
C249
*0.1U/10V_4X
C477
*0.1U/10V_4X
C417
*0.1U/10V_4X
C510
*0.1U/10V_4X
C530
*0.1U/10V_4X
5
C11
*0.1U/10V_4X
C111
*0.1U/10V_4X
C315
*0.1U/10V_4X
C535
*0.1U/10V_4X
C413
*0.1U/10V_4X
+5V_S5 +5V_S5
C475
E@0.1U/25V_4X
C101
E@680P/50V_4X
C773
E@2200P/50V_4X
RevB 1220 EMI solutioon
4
R374 *0_4
R348 *0_4
R345 *0_4
ADOGND
1
H-TC236BC161D161PT
HOLE18
1
*h-tc131bc236d91p2
1
*H-C91D91N
HOLE19
1
*h-tc131bc236d91p2
RevB 1224 Add Hole & PAD for ME
3
1
*H-C91D91N
HOLE20
1
*h-tc131bc236d91p2
1
*h-tc276bc150d150p2
HOLE21
1
*h-tc131bc236d91p2
1
*h-tc276bc150d150p2
PAD1
1
*spad-bd9-np
2
1
*spad-bd9-np
1
*h-tc276bc150d150p2
PAD2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
KBC/TP/FP CONN.
KBC/TP/FP CONN.
KBC/TP/FP CONN.
Wednesday, January 30, 2013
Wednesday, January 30, 2013
Wednesday, January 30, 2013
*INTEL-CPU-BKT2
1 2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
BD9
BD9
BD9
32 41
32 41
1
32 41
A1A
A1A
A1A
EC
<KBC>
5
4
3
2
1
35
+3VPCU
R138
2.2_6
D D
C C
B B
AC SET_EC
C171
C124
0.1U/10V_4X
10U/6.3V_6X
Battery
APU, S&C IC
GPU, eDP to LVDS IC
C194
*10U/6.3V_6X
8769AGND
C86
0.1U/10V_4X
ICMNT
USB_NORMAL_EN#[23]
USB_NORMAL_OC#[7,23]
8769AGND
C46
0.1U/10V_4X
EC_A20GATE[7]
EC_KBRST#[7]
EC_EXT_SCI#[7]
2ND_MBCLK[5,23]
2ND_MBDATA[5,23]
3ND_MBCLK[13,24]
3ND_MBDATA[13,24]
PE_PWRGD[7,40,41 ]
USB_SC_EN#[23]
RTC_CLK[7,9]
C193
*10U/6.3V_6X
C81
0.1U/10V_4X
LFRAME#[8,9,28]
LAD0[8,28]
LAD1[8,28]
LAD2[8,28]
LAD3[8,28]
PCLK_591[8]
CLKRUN#[8]
LPCPD#[8]
PLTRST#[7,28,29 ]
SERIRQ[8]
MX0[32]
MX1[32]
MX2[32]
MX3[32]
MX4[32]
MX5[32]
MX6[32]
MX7[32]
MY0[32]
MY1[32]
MY2[32]
MY3[32]
MY4[32]
MY5[32]
MY6[32]
MY7[32]
MY8[32]
MY9[32]
MY10[32]
MY11[32]
MY12[32]
MY13[32]
MY14[32]
MY15[32]
MY16[32]
MY17[32]
MBCLK[34]
MBDATA[34]
2ND_MBCLK
2ND_MBDATA
3ND_MBCLK
3ND_MBDATA
TPCLK[32]
TPDATA[32]
RevB 1219 Change for EOD
SKU_STRAP_1(GPIO56) SKU_STRAP_2(GPIO02) SKU_STRAP_3(GPIO41) SKU
0
A A
0
0 1
1
1
0
0
1 10
0
0
5
0
14" Kabini UMA
1
14" Kabini DIS
0
Richland UMA
Richland DIS
17" Kabini UMA
0
17" Kabini DIS
1
L2 HCB1608KF- 601T10_1A
C82
C114
0.1U/10V_4X
ESD@39P/50V_4N
126
127
128
CLKRUN#
EC_EXT_SCI#
SERIRQ
121
122
124
123
125
119
120
RevB 1220 Change symbol
PCLK_591
R126
*22_4
C166
*10P/50V_4C
+3V
SKU strap
pin
R99
DIS@10K_4
R97
UMA@10K_4
19
U6
3
LFRAME/GPIOF6
LAD0/GPIOF1
LAD1/GPIOF2
LAD2/GPIOF3
1
LAD3/GPIOF4
2
LCLK/GPIOF5
8
GPIO11/CLKRUN
GPIO85/GA20
KBRST/GPIO86
29
ECSCI/GPIO54
GPIO10/LPCPD
7
LREST/GPIOF7
GPIO67/N2TMS
SERIRQ/GPIOF0
9
GPIO65/SMI
54
KBSIN0/GPIOA0/N2TCK
55
KBSIN1/GPIOA1/N2TMS
56
KBSIN2/GPIOA2
57
KBSIN3/GPIOA3
58
KBSIN4/GPIOA4
59
KBSIN5/GPIOA5
60
KBSIN6/GPIOA6
61
KBSIN7/GPIOA7
53
KBSOUT0/GPIOB0/SOUT_CR/JENK
52
KBSOUT1/GPIOB1/TCK
51
KBSOUT2/GPIOB2/TMS
50
KBSOUT3/GPIOB3/TDI
49
KBSOUT4/GPIOB4/JENO
48
KBSOUT5/GPIOB5/TDO
47
KBSOUT6/GPIOB6/RDY
43
KBSOUT7/GPIOB7
42
KBSOUT8/GPIOC0
41
KBSOUT9/GPIOC1/SDP_VIS
40
KBSOUT10&P80_CLK/GPIOC2
39
KBSOUT11&P80_DAT/GPIOC3
38
KBSOUT12/GPO64/TEST
37
KBSOUT13/GPIO63/TRIST
36
KBSOUT14/GPIO62/XORTR
35
KBSOUT15/GPIO61/XOR_OUT
34
GPIO60/KBSOUT16
33
GPIO57/KBSOUT17
70
GPIO17/SCL1/N2TCK
69
GPIO22/SDA1/N2TMS
67
GPIO73/SCL2/N2TCK
68
GPIO74/SDA2/N2TMS
GPIO23/SCL3/N2TCK
GPIO31/SDA3/N2TMS
72
GPIO37/PSCLK1
71
GPIO35/PSDAT1
10
GPIO26/PSCLK2
11
GPIO27PSDAT2
77
GPIO00/EXTCLK/F_SDIO3
12
VTT
13
PECI
NPCE985LA0DX
R134 *10K_4
R106 10K_4
+A3VPCU
C164
0.1U/10V_4X
8769AGND
46
76
88
102
115
H=1.6mm
VCC1
VCC2
VCC3
VCC4
VCC5
AVCC
LPC
KB
TIMER
TIMER
SMB
PS/2
GND1
GND2
GND3
GND4
GND5
GND6
5
18
45
78
89
116
L3 0_6
RevB 1220 Change to unstuff
SERIRQ
CLKRUN#
For BD9 Strap pin setting:
+3VPCU+3VPCU
4
Pull Hi SKU_STRAP_3 For Disctete
Pull Down SKU_STRAP_3 For UMA
SKU_STRAP_1=Hi
R85
SKU_STRAP_2=Low
10K_4
SKU_STRAP_1
SKU_STRAP_3
SKU_STRAP_2
R98
10K_4
A/D
D/A
GPIO
GPO82/IOX_LDSH/VD_OUT1
GPO84/IOX_SCLK/VD_OUT2
GPIO20/TA2/IOX_DIN_DIO
IR
FIU
GPIO55/CLKOUT/IOX_DIN_DIO
AGND
103
8769AGND
C175
10U/6.3V_6X
GPIO90/AD0
GPIO91/AD1
GPIO92/AD2
GPIO93/AD3
GPIO05/AD4
GPIO04/AD5
GPIO03/AD6
GPIO07/AD7/VD_IN2
GPIO94/DA0
GPIO95/DA1
GPIO96/DA2
GPIO24
GPIO01/TB2
GPIO02/SPI_CS
GPIO06/IOX_DOUT
GPIO16
GPIO30/F_WP
GPIO36
GPIO41/F_WP
GPIO42/TCK
GPIO43/TMS
GPIO44/TDI
GPO47/SCL4/N2TCK
GPIO50/PSCLK3/TDO
GPIO51/N2TCK
GPIO52/PSDAT3/RDY
GPIO53/SDA4/N2TMS
GPIO70
GPIO71
GPIO72
GPIO75/SPI_SCK
GPO76/SPI_MOSI
GPIO77/SPI_MISO
GPIO81/FW_P/F_SDIO2
GPIO97/DA3
GPIO56/TA1
GPIO14/TB1
GPIO15/A_PWM
GPIO21/B_PWM
GPIO13/C_PWM
GPIO32/D_PWM
GPIO45/E_PWM
GPIO40/F_PWM/1_WIRE
GPIO66/G_PWM
GPO33/H_PWM/VD1_EN
GPIO34
GPIO87/SIN_CR
GPIO46/TRST
GPIO83/SOUT_CR
F_SDI&F_SDIO1
F_SDIO&F_SDIO0
F_CS0
F_SCK
EST_RST
GPIO80/VD_IN1
VCORF
44
VCORF_uR
C45
1U/10V_6X
+3V_S5
R88 *1 0K_4
+3V_VDD_EC
4
VDD
NPCE791LA0DX: AJ007910F00 (w/o CIR)
R110 2.2_6
C138
C122
10U/6.3V_6X
0.1U/10V_4X
R128 *100K/F_4
97
98
ICMNT
99
AC SET_EC
100
USB_BUS_SW4
108
96
95
NBSWON#_R
94
101
105
106
6
64
79
SKU_STRAP_2
93
114
USB_DB_EN#
109
PWRLED
15
80
SKU_STRAP_3
17
H_PROCHOT_EC#
20
21
24
USB_BUS_SW3
25
26
27
DISPON_I_R
28
HWPG
73
74
MPWROK
75
RSMRST_GATE#
82
USB_BUS_SW2
83
RF_EN
84
91
DNBSWON#_uR
110
NUMLED
112
107
RevA 1026 Remove pin 107 +1.1V_EN_EC
31
SKU_STRAP_1
117
63
32
RF_LED#
118
62
65
22
16
81
66
14
113
TP_ON_OFF
23
111
EC_Debug
86
SPI_SDI_uR
87
SPI_SDO_uR
90
SPI_CS0#_uR
92
SPI_SCK_uR
30
R100 4.7K_4
85
VCC_POR#
104
R595 *0_4
RevB 1221 Add R595 & unstuff
EC_EXT_SCI#
+3V
+3VPCU
TEMP_MBAT [34]
ICMNT [34]
AC SET_EC [34]
R127 1.2K/F_4
R92 0_4
R115 0_4
TP18
R105 0_4
R102 *100K/F_4
R107 33_4
R114 33_4
R116 33_4
Make sure that the rise time of VCC_POR is less than 10?sec.
Power Button
DNBSWON#_uR
NBSWON#_R
USB_SC_OC# [7,23]
NBSWON# [32]
SLP_S3# [7,22]
USB_DB_OC# [7,23]
VFAN1 [7]
WLAN_P [28]
EC_FPBACK# [30]
ACIN [34]
LID591# [30]
USB_DB_EN# [23]
PWRLED [32 ]
VRON [38]
H_PROCHOT_EC# [5]
AMP_MUTE# [27]
ID [34]
USB_BUS_SW3 [23]
D/C# [34]
S5_ON [7,13,35]
DISPON_I [30]
SLP_S5# [7]
MPWROK [9]
RSMRST_GATE# [7]
USB_BUS_SW2 [23]
RF_EN [28]
DNBSWON# [7]
FANSIG1 [7]
RF_LED# [29]
SUSLED_EC# [29]
BAT_SAT0# [29]
BAT_SAT1# [29]
SUSON [36]
MAINON [9,39]
BT_RFCTRL [28]
LAN_P [26]
+3VPCU
+A3VPCU
<KBC><KBC>
C145 *0.1U/10V_4X
SW1 *SHORT_ PAD
D3
*LCP0G050M0R2R
3
RevA 1026 Add VRON
RevB 1204 Swap KB_LED & CAPSLED pin define
FCH_SPI_SI [8]
FCH_SPI_SO [8]
FCH_SPI_CS0# [8]
FCH_SPI_CLK [8 ]
TP20
TP19
For Daughter Board USB2.0
For Daughter Board USB2.0
NUMLED [32]
KB_LED [32]
CAPSLED [32]
R594 *10K_4
RevB 1220 Add net EC_DUAL_EN to enable
+1.8V_S5/+0.95V_DUAL/+1.5V_S5
+3VPCU
EC_DUAL_EN [37,39]
TP_ON_OFF
EC_Debug
TP interface
PU
LED
PU/PD
RevB 1204 Change power rail from +5VPCU to +5V
+TP_PWR
1015 add for Metal ID
<LED>
PWRLED
RF_LED#
SUSLED_EC#
BAT_SAT0#
BAT_SAT1#
R93 METAL @10K_4
R90 METAL @10K_4
R130 10K_4
R76 1 0K_4
R77 *IOIC@10 K_4
R135 10K_4
R75 1 0K_4
R74 1 0K_4
CN3
1
2
3
*DEBUG@50273-0037L-00 1
<KBC>
TPCLK
TPDATA
+5V
+5V_S5
+5VPCU
2
+3VPCU
R101 10K_4
6
5
7
SMBUS Table
SMBUS
1
2
3
U4
SCL
SDA
WP
M24C08-WMN6TP
SM BUS
PU
MBCLK
MBDATA
2ND_MBCLK
2ND_MBDATA
3ND_MBCLK
3ND_MBDATA
Strap
<KBC>
ID EEPROM
<KBC>
RF_EN
<KBC>
R89 4.7K_4
R86 4.7K_4
R81 4.7K_4
R83 4.7K_4
R132 4.7K_4
R133 4.7K_4
SHBM
2ND_MBCLK
2ND_MBDATA
ADDRESS: A0H
SPI
<KBC>
FLASH
INTERNAL KEYBOARD
STRIP SET
<KBC>
HWPG circuit
AMD
1.8V_S5_PG[37]
HWPG_1.5V[36]
RT8223P_PG[35]
<KBC>
MY0
R72 0_4
R67 0_4
R593 0_4
R73 10K_4
RevB 1219 Add R593 for 3V/5V Power Good pull high
Size Document Numbe r Rev
Size Document Numbe r Rev
Size Document Numbe r Rev
Date: Shee t of
Tuesday, December 25, 2012
Date: Shee t of
Tuesday, December 25, 2012
Date: Shee t of
Tuesday, December 25, 2012
Battery
PCH SML1
3D Sensor
EC EEPROM
VGA Board Thermal Sensor
Touch Sensor
HDMI CEC
Light Sensor 52H
SHBM=0: Enable shared memory with host BIOS
Disabled ('1') if using FWH device on LPC.
Enabled ('0') if using SPI flash for both system BIOS and EC firmware
1
A0
2
A1
3
A2
8
VCC
4
GND
+3VPCU
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
EC NPCE795CA0DX
EC NPCE795CA0DX
EC NPCE795CA0DX
1
AddressDevices
32H
A0H
98H
58H
34H
+3VPCU
0.003A(20mils)
C48
0.1U/10V_4X
+3VPCU
R68
10K_4
BD9
BD9
BD9
+3V
R80
*10K_6
HWPG
33 41
33 41
33 41
A1A
A1A
A1A
5
4
3
2
1
50302-00641-001
PF2
PC100
E@0.1U/50V_6X
PC110
PR71
F1206HA15V024TM
1 2
10U/10V_8X
PD3
TVLST2304AD0
1
CH1
2
VN
CH23CH3
PC83
47P/50V_4N
MBDATA
MBCLK
1000P/50V_4X
PR117
82.5K/F_6
PR116
10K/F_4
CH4
VP
1K_4
PR67
VA0
PC99
ACIN[33]
6
MBDATA
5
+3VPCU
4
MBCLKTEMP_MBAT
PF1
F1206HA15V024TM
1 2
E@0.1U/50V_6X
12
6
DC_JACK
5
4
D D
PCN2
3
2
1
20121030 by James
PC98
1000P/50V_4X
RevA 1115 Change P/N & FP
AC SET_EC[33]
C C
ID
+3VPCU
B B
BTJ-09BJAB
PR73
*100K_4
10
1
2
3
11
4
5
M-DATA
6
M-CLOCK
7
12
8
9
13
PCN1
A A
100/F_4
PR72
ID_CN
PR68
*0/short_4
MBAT+ BAT-V
TEMP_MBAT_C
PC84
100/F_4
47P/50V_4N
VA1 VIN
PC101
PD6
1SS355_100MA
+3VPCU
ACIN
82.5K/F_6
ID [33]
+3VPCU
PR69
100K_4
1K_4
PR70
PC82
0.01U/25V_4X
PR90
PR84
49.9/F_6
22K/F_6
SBR1045SP5-13
PR122
10K/F_4
PR100
*1U/10V_4X
PD5
1
2
3.2V
PC107
1 2
TEMP_MBAT [33]
3
VA2VA2
PD4
TVS_SMAJ20A
B-TEST change
PC114 0.1U/10V_4X
MBDATA[33]
MBCLK[33]
PC93
0.1U/25V_6X
DCIN
88731ACIN
12
PC111
2200P/50V_4X
0.01_3720
PR85
R1
1 2
PR102
2 1
10/F_6
PR101
10/F_6
( Near by sense R side)
CSIP
( Near by IC side)
11
9
10
13
22
2
3
4
5
6
PR113
2.21K/F_6
12
PC113
0.01U/25V_4X
1
NC
GND33GND32GND31GND
VDDSMB
SDA
SCL
ACOK
DCIN
ACIN
VREF
ICOMP
NC
VCOMP
+3VPCU
MBDATA
MBCLK
0.1U/25V_4X
B-TEST change
PC94
0.1U/10V_4X
28
30
CSSP
NC
7
PR119
*10K/F_4
PC96
220K/F_4
CSIN
27
CSSN
PU3
ISL88732HRTZ-T
ICM
8
PR123
100_4
VA3
PR111
NC
14
26
VCC
PR98
220K/F_4
B-TEST change
PC92 1U/6.3V_4X
1 2
PR78
4.7_6
21
VDDP
25
BOOT
24
UGATE
23
PHASE
20
LGATE
19
PGND
18
CSOP
17
CSON
16
NC
15
VBF
29
GND
GND
12
PC118
10U/10V_8X
1 6
2
3
5
4
PQ9
IMD2AT108
PC102 1U/6.3V_4X
PR77
2.7_6
0.1U/50V_6X
88731A_U_GATE
88731A_PHASE
88731A_L_GATE
PC109
0.1U/10V_4X
( Near by IC side)
B-TEST change
ICMNT [33]
B-TEST change
1 2
PC90
PQ4
AOD403
1
CSOPCSOP
CSON
43
PC81
1U/25V_6X
PC80
2200P/50V_4X
D/C#[33]
VIN
PC89
0.1U/25V_4X
52
4
4
PQ6
AON7410
3
1
52
PQ7
AON7410
3
1
*2200P/50V_4X
1000P/50V_4X
10U/25V_8X
2.2/F_6
PC9
PC88
PC10
PR22
PC17
PC12
10U/25V_8X
3.3UH_7X7_TOK
10U/25V_8X
PL1
( Near by sense R side)
(Please place this R near by battery pack side)
PQ5
AP4439GMT
1
3
PR74
33K_6
2
PC11
*E@10U/25V_8X
1 2
PR11
10/F_6
PR75 100_4
4
3
1
0.01_3720
PR91
52
A TO B
20121220 by James
PR66
10K/F_6
PQ3
2N7002K_300MA
PR10
10/F_6
BAT-V
34
BAT-V
BAT-V
PC8510U/25V_8X
PC870.1U/25V_4X
PC8610U/25V_8X
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
BD9
BD9
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
PROJECT :
CHARGER-ISL88731C A1A
CHARGER-ISL88731C A1A
CHARGER-ISL88731C A1A
BD9
34 41Thursday, December 27, 2012
34 41Thursday, December 27, 2012
1
34 41Thursday, December 27, 2012
5
4
3
2
1
(Peak 35mA)
PC144
16
VIN
EN
UGATE1
BOOT1
RT8223P
PHASE1
LGATE1
VOUT1
FB1
PGOOD
ENTRIP1
1
120K/F_4
69.8K/F_4
+3VPCU
(Peak 0mA)
+5VPCU
1 2
10U/6.3V_6X
12
10U/6.3V_6X
3
17
8
REF
VREG5
VREG3
TOP Side
EMC18GND
ENTRIP26SKIPSEL
14
25
PR49
*0_4/S
PR179
*10K/F_4
PC153
+2VREF+3VPCU
12
PC143
1U/6.3V_4X
4
TONSEL
10
UGATE2
9
BOOT2
11
PHASE2
12
LGATE2
7
OUT2
5
FB2
GND
15
PR167
*0/short_6
RT8223P_PG [33]
PR171
3V_UGATE2
PR180
1 2
2.2_6
3V_LGATE2
3V_FB2
*0_2/S
PQ29
AON7410
PC146
0.1U/25V_6X PL8
4
4
PQ28
AON7752
Rds(on) 13m ohm
PR164
6.8K/F_4
PR165
10K/F_4
+3V_S5
PC58
0.1U/25V_4X
52
PC62
PC52
10U/25V_8X
1024 add
(Peak 5.38A, AVG 3.77A)
3
1
52
3
2.2UH_7X7_TOK
PR183
2.2/F_6
1
PC152
1000P/50V_4X
4
MAIND
+5V_S5
52
3
PR197
*0_2/SPQ30
PQ23
AON7410
1
PR196
*0_2/S
( Near by Output
cap side)
VIN
PC61
0.1U/25V_4X
D D
PC59
*2200P/50V_4X
1024 add
(Peak 9.232A ,AVG 6.424A)
OCP:11.5A
PC162
220U/6.3V_7343P_E15b
C C
+
( Near by Output
cap side)
PR199
*0_2/S
PC66
10U/25V_8X
PL9
2.2UH_7X7_TOK
PR185
2.2/F_6
PR200
*0_2/S
PC151
1000P/50V_4X
20121030 by James
TP42
PQ31
52
AON7410
4
3
1
52
4
3
1
AON7752
PC147
0.1U/25V_6X
20121102 by James
1 2
Rds(on) 13m ohm
20121104 by James
PC78
PD2
BAV99W-7-F_150MA
0.1U/25V_4X
+15V_ALWP
PC79
B-TEST change
B B
PR65
+15V
22_8
PR170
15.4K/F_4
2
3
1
2
3
1
PD1
BAV99W-7-F_150MA
0.1U/25V_6X
10K/F_4
PC68
0.1U/25V_6X
PC67
0.1U/25V_6X
PR169
S5_ON[7,13,33]
3V_LGATE2
VIN
PR54
2.2/F_6
PC154
0.1U/25V_6X
PU8
13
5V_BST1
5V_LGATE1
5V_FB1
12
PR51
10K/F_4
21
22
20
19
24
2
23
PR168
PR166
DDPWRGD_R
5V_UGATE1
PR182
2.2_6
5V_PHASE1 3V_PHASE2
DDPWRGD_R
+3VPCU
*2200P/50V_4X
OCP:7A
20121104 by James
VIN
+
PC155
35
+3V_S5+5V_S5
220U/6.3V_7343P_E15b
+5V
65241
TOP Side
3
PQ34
AO6402A
+3V
2
MAIND[36,37,39]
A A
MAIND
(Peak 3.5342A, AVG 2.474A)
5
4
3
(Peak 4.369A)
1024 CHANGE
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
BD9
BD9
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROJECT :
System 3V/5V(TPS51123A) A1A
System 3V/5V(TPS51123A) A1A
System 3V/5V(TPS51123A) A1A
BD9
1
35 41Tuesday, December 25, 2012
35 41Tuesday, December 25, 2012
35 41Tuesday, December 25, 2012
5
+3V_S5
12
PR127
PR25
*0_2/S
10U/6.3V_6X
*10K/F_4
1
2
3
4
5
PU4
VTTSNS
VLDOIN
VTT
VTTGND
VTTREF
D D
HWPG_1.5V[33]
( Near by Output
cap side)
(Peak 0.5A, AVG 0.35A)
+SMDDR_VTERM
C C
+1.5VSUS_1_LOD
+SMDDR_VREF
PC115
PC116
10U/6.3V_6X
(Peak 0.1A, AVG 0.07A)
PC117 0.22U/10V_4X
B B
PC119
PR126
0.1U/10V_4X
10K/F_4
21
23
PwPad
PwPad-122PwPad-2
TPS51216RUKR
VREF6GND7REFIN8VDDQSNS9PGND
PwPad-324PwPad-425PwPad-5
26
R1
4
Be careful to this two net name.
S3_1.5V
S5_1.5V
PR26
PR129
200K_4
48.7K/F_4
20
19
18S317S516
VBST
TRIP
MODE
PGOOD
DRVH
SW
V5IN
DRVL
10
PR133
15
14
13
12
11
PR131
*0_4
0_4
PR27
100K_4
12
PC30
1U/6.3V_4X
20121113 by James
PR135
2.2/F_6
+5V_S5
Vout = (R1/R2) X 0.75 + 0.75
3
S3_1.5V S5_1.5V
SUSON [33]
PC123
0.1U/25V_6X
1.5SUS_HG
1.5SUS_PHASE1.5SUS_PHASE
1.5SUS_LG
PR28
0_4
20121102 by James
4
4
RDSon=3.3m ohm
+1.5VSUS
5
213
5
213
PQ1
AON6414AL
PQ15
AON6758
2
PC125
0.1U/25V_4X
PL4
1.5UH_10X10
PR29
2.2/F_6
PC41
1000P/50V_4X
+1.5VSUS_1_VDDQSNS
PC32
*2200P/50V_4X
1030 add by James
PR30
PR31
*0_2/S
PC124
*0_8/S
+1.5VSUS_1_LOD
PC38
10U/25V_8X
PC43
*0.1U/10V_4X
( Near by Output
cap side)
1
VIN
10U/25V_8X
OCP:12.5A
(Peak 10.475A, AVG 7.3325A)
ESR : 9mΩ
f : 400k Hz
PC42
+
330U/2V_7343P_E9c
36
+1.5VSUS
65241
3
PR128
A A
5
52.3K/F_4
R2
4
PC120
0.01U/25V_4X
MAIND[35,37,39]
3
MAIND
PQ16
AO6402A
+1.5V
(Peak 0.374A)
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
BD9
BD9
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
PROJECT :
DDR A1A
DDR A1A
DDR A1A
BD9
36 41Tuesday, December 25, 2012
36 41Tuesday, December 25, 2012
36 41Tuesday, December 25, 2012
1
5
4
3
2
1
VIN
37
+5V_S5
PC77
1 2
D D
PC164
R2
51211_EN_3
PC142
R2
1 2
51211_EN_1
12
34.8K/F_4
1 2
12
EC_DUAL_EN[33,39]
C C
EC_DUAL_EN
2012/11/13 by James
B B
PR159 0_4
PR202
0_4
*1U/6.3V_4X
PR198
10K/F_4
0.22U/10V_4X
PR155
10K/F_4
PR203
97.6K/F_4
PR201
3.65K/F_4
PC163
*39P/50V_4N
+5V_S5
PR160
PR158
15.8K/F_4
PC141
*39P/50V_4N
R1
12
1 2
R1
12
1U/6.3V_4X
51211_V5IN_1
51211_VFB_1
PC47
1U/6.3V_4X
51211_V5IN_3
51211_VFB_3
12
12
PR195
470K/F_4
PR154
470K/F_4
TPS51211DSCR
PU9
7
V5IN
2
TRIP
3
EN
4
VFB
5
TST
16
VBST
DRVH
PGOOD
DRVL
GND
SW
GND12GND13GND14GND15GND
PR194
10
1 2
9
2.2_6
8
1
6
11
51211_SW_1
Vout=0.704V*(R1+R2)/R2
TPS51211DSCR
PU7
7
V5IN
2
TRIP
3
EN
4
VFB
5
TST
16
VBST
DRVH
PGOOD
DRVL
GND
SW
GND12GND13GND14GND15GND
PR153
10
1 2
9
2.2_6
8
1
6
11
51211_SW_3
1.8V_S5_PG
PC159
0.1U/25V_6X
PC136
0.1U/25V_6X
51211_DRVH_1
TP43
PR204*10K_4
51211_DRVL_1
RDSon=14m ohm
51211_DRVH_3
1.8V_S5_PG [33]
PR161*10K_4
51211_DRVL_3
RDSon=14m ohm
+3V_S5
+3V_S5
PQ32
AON7410
PQ33
AON7752
PQ24
AON7410
PQ25
AON7752
4
4
4
4
Vout=0.704V*(R1+R2)/R2
52
3
52
3
52
3
52
3
PC74
0.1U/25V_4X
1
1
PC45
0.1U/25V_4X
1
1
2.2UH_7X7_TOK
PR193
*2.2/F_6
PC158
*1000P/50V_4X
3.3UH_7X7_TOK
PR152
*2.2/F_6
PC135
*1000P/50V_4X
PC70
PL6
PC46
PL5
PC65
10U/25V_8X
*2200P/50V_4X
1030 add by James
PR181
*0_2/S
1106 add by James
PC44
10U/25V_8X
*2200P/50V_4X
1030 add by James
1106 add by James
PR32
*0_2/S
+
PC149
+
PC132
OCP:9.5A
(Peak 8.1A, AVG 5.67A)
ESR : 9mΩ
f : 400k Hz
330U/2V_7343P_E9c
PC148
0.1U/10V_4X
( Near by Output
cap side)
VIN
OCP:4A
(Peak 3.388A)
ESR : 9mΩ
f : 400k Hz
330U/2V_7343P_E9c
PC133
0.1U/10V_4X
( Near by Output
cap side)
+0.95V_DUAL
+1.8V_S5
+0.95V_DUAL
PQ26
A A
AON7406
MAIND
52
4
3
1
5
MAIND[35,36,39]
(Peak 6.6A)
+0.95V
MAIND
MAIND
4
+1.8V_S5
65241
3
PQ2
AO6402A
+1.8V
(Peak 1.5A)
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
+0.95V/+1.8V
+0.95V/+1.8V
+0.95V/+1.8V
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
3
2
Tuesday, December 25, 2012
PROJECT :
1
BD9
BD9
BD9
37 41
37 41
37 41
A1A
A1A
A1A
5
+VDDNB_CORE
PR13
VRM_PWRGD[9]
APU_SVC[5]
APU_SVD[5]
+1.8V_S5
APU_SVT[5]
PR3
1 2
9.76K/F_4
PR83
27.4K/F_4
PR118
NTC_470K_4
+1.8V
Place NTC close to the
VDDCORE Hot-Spot.
PR76
*10K/F_6
CPU_PWRGD_SVID_REG_1
PC4
1000P/50V_4X
PR15
0_4
PR14
0_4
5
0_4
1 2
+VDD_CORE
1 2
PR79
27.4K/F_4
PR16
10_4
PR110
10_4
APU_VDDNB_RUN_FB_H[5]
D D
C C
PR115
PR80
100K_4
9.76K/F_4
CORE_PWM_PROCHOT#[5]
PR5
1 2
VRON[33]
B B
NTC_470K_4
Place NTC close to the
VDDNB Hot-Spot.
CPU_PWRGD_SVID_REG[5]
A A
APU_VDD_RUN_FB_H[5]
APU_VDD_RUN_FB_L[5]
PC103
330P/50V_4X
PR89
10_4
PR18
40.2K/F_4
2012/12/25 by James
+3V_S5
PR21
10K/F_4
VRM_PWRGD
PR4 0_4
PR82 0_4
PR81 0_4
CPU_PWRGD_SVID_REG_1
PC5
PR93
133K/F_4
0.1U/25V_4X
A TO B
20121220 by James
PR20
*0_4
PC105
330P/50V_4X
PC112
0.01U/25V_4X
PR112
0_4
NTC_NB
NTC
IMON_NB
IMON
PC16
680P/50V_4X
PC95
100P/50V_4N
PC104
680P/50V_4X
PC14
150P/50V_4N
PC13
47P/50V_4N
PR92
133K/F_4
62771_COMP
PC15
47P/50V_4N
PC108
150P/50V_4N
PC97
100P/50V_4N
2012/10/16 by James
2012/11/04 by James
PR88
1.47K/F_4
PR97
499/F_4
PR104
2K/F_4
PR12
267K/F_4
62771_FB_NB
62771_COMP_NB
35
PGOOD_NB
20
PGOOD
3
SVC
4
VR_HOT_L
5
SVD
6
VDDIO
7
SVT
8
ENABLE
9
PWROK
1
NTC_NB
11
NTC
2
IMON_NB
10
IMON
PC3
0.1U/25V_4X
PR19
2K/F_4
36
19
PR105
267K/F_4
PR99
499/F_4
PR17
1.87K/F_4
4
+5V_S5
PR120
PC23
VSEN_NB
VSEN16RTN
1 2
1 2
25
VDD
PU1
ISL62771HRTZ-T
17
62771_RTN
1/F_6
PR121
0_6
26
PC22
1U/10V_4X
1 2
1 2
0.1U/10V_4X
PC6
1 2
1 2
412/F_4
2012/12/25 by James
PR8
40
39
VDDP
ISUMP_NB
ISUMN_NB
34
EP
PR9
LGATE_NB
33
PHASE_NB
32
UGATE_NB
31
BOOT_NB
30
29
28
27
24
23
22
21
41
+5V_S5
PC2
0.1U/10V_4X
12
12
2012/12/25 by James
LGATE_1
PHASE_1
UGATE_1
BOOT_1
PC1
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
BOOT2
UGATE2
PHASE2
LGATE2
LGATE1
PHASE1
UGATE1
BOOT1
PR96
10K/F_4
ISEN212ISEN113ISUMP14ISUMN
510/F_4
15
ISUMN
1U/10V_4X
62771_VSEN_NB
38
37
FB_NB
COMP_NB
FB18COMP
62771_VSEN
62771_FB
4
3
0.047U/10V_4X
PR6
PC7
Add 9 GND VIAs
for thermal pad
0.047U/10V_4X
1 2
11K/F_4
1 2
1 2
PR1
2.61K/F_4
PR2
11K/F_4
12
PR138
NTC_10K_4
3
12
12
PR7
1 2
PR140
1 2
VSUM+
PC8
0.1U/10V_4X
2.61K/F_4
NTC_10K_4
12
0.1U/10V_4X
PC91
A TO B
20121220 by James
VSUM-
12
BOOT_NB
PHASE_NB
VSUMG+
A TO B
20121220 by James
VSUMG-
PR23
1 2
BOOT_1
2.2_6
PHASE_1
VDDNB_CORE
PC18
PR24
0.22U/25V_6X
2.2_6
UGATE_1
PC20
1 2
0.22U/25V_6X
UGATE_NB
LGATE_NB
VSUMG+
VSUMG-
VDD_CORE
LGATE_1
2
1
38
VIN
1
2
D1D1D1
G1
S1/D2
9
G2
8
1
G1
S1/D2
9
G2
765
8
765
2
S2S2S2
*1000P/50V_4X
D1D1D1
PQ14
HP8S36TB
S2S2S2
*1000P/50V_4X
PQ13
HP8S36TB
( Near by Choke side)
2
PC122
VSUM+
VSUM-
PR132
*2.2/F_6
PC121
PC27
2200P/50V_6X
2012/12/25 by James
PL2 0.36UH_7X7
PR130
*2.2/F_6
PR95
1 2
3.65K/F_6
PR94
1 2
1/F_6
( Near by IC side)
PC29
2200P/50V_6X
2012/12/25 by James
PR86 3.65K/F_6
PR87 1/F_6
( Near by IC side)
PC25
10U/25V_8X
10U/25V_8X
PR134*0_2/S
PR137*0_2/S
0.1U/50V_6X
+
PC31
PC37
22U/6.3V_6X
560U/2V_7343P_E4.5a_3pin
(Peak 17A)
+VDDNB_CORE
PC36
PC34
PC35
22U/6.3V_6X
22U/6.3V_6X
PC19
PC21
( Near by Choke side)
VIN
PC24
10U/25V_8X
PL3 0.36UH_7X7
PR136*0_2/S
PR139*0_2/S
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
PC28
PC26
10U/25V_8X
0.1U/50V_6X
PC126
+
PC33
560U/2V_7343P_E4.5a_3pin
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
CPU_CORE (ISL62771HRTZ-T) A1A
CPU_CORE (ISL62771HRTZ-T) A1A
CPU_CORE (ISL62771HRTZ-T) A1A
1
(Peak 21A)
+VDD_CORE
PC39
PC127
22U/6.3V_6X
22U/6.3V_6X
BD9
BD9
BD9
22U/6.3V_6X
38 41Tuesday, December 25, 2012
38 41Tuesday, December 25, 2012
38 41Tuesday, December 25, 2012
22U/6.3V_6X
PC40
22U/6.3V_6X
5
4
3
2
1
VIN
2012/11/13 by James
D D
PQ8
PDTC143TT_100MA
MAINON[9,33]
C C
B B
A A
5
2
PR106
100K_4
PR107
1M_4
PR108
1M_4
1 3
EC_DUAL_EN[33,37]
2
PR124
22_8
6
PQ11A
2N7002KDW_115MA
1
+3V_S5 +1.5V_S5
1U/6.3V_4X
PR141
10K_4
4
5
12
PC129
PR103
22_8
34
PQ11B
2N7002KDW_115MA
12
PC130
1U/6.3V_4X
2
PU5
G9090-150T11U
1
VIN
2
GND
EN3NC
3
PR125
22_8
6
PQ12A
2N7002KDW_115MA
1
5
VOUT
4
+15V+5V+3V +1.5V
34
5
PR109
1M_4
PQ12B
2N7002KDW_115MA
12
PC128
1U/6.3V_4X
39
MAIND [35,36,37]
PC106
2200P/50V_4X
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Discharge
Discharge
Discharge
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
+1.8V
PR206
22_8
6
PQ35A
2
2N7002KDW_115MA
1
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
5
+0.95V
PR205
22_8
34
PQ35B
2N7002KDW_115MA
BD9
BD9
BD9
39 41Tuesday, December 25, 2012
39 41Tuesday, December 25, 2012
39 41Tuesday, December 25, 2012
1
A1A
A1A
A1A
5
4
3
2
1
Mars VDDC VID TABLE
GFX_CORE_CNTRL5
Int_VGA
D D
[PWM]
62881DPRSLPVR
62881VR_ON
C C
B B
GFX_CORE_CNTRL1[13]
GFX_CORE_CNTRL2[13]
GFX_CORE_CNTRL3[13]
GFX_CORE_CNTRL4[13]
GFX_CORE_CNTRL5[13]
PR57
EV@226K/F_4
PR45
EV@4.7K_4
PE_PWRGD[7,33 ,41]
62881_GND
EV@715/F_4
[PWM]
EV@390P/50V_4X
PR60
GPU_MAINON[22,41]
EV@120K/F_4
PC63
PR43
*EV@10K_4
PR53
R330 EV@0_4
R329 EV@0_4
R332 EV@0_4
R331 EV@0_4
R333 EV@0_4
+3V_S5
PR46 EV@0_ 4
62881_GND
PC71
EV@1000P/50V_4X
PR33 *EV@10K/F_4
PR41 EV@0 _4
PR50 EV@147K/F_4
PR52 EV@8.06K/F_4
PC57
EV@1000P/50V_4X
PC60
EV@56P/50V_4N
PC72
EV@330P/50V_4X
62881_GND
GPU_GPIO0[13,15 ]
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
62881_GND
PR184 *short_4
62881_GND
+3V
PR48
EV@1.91K/F_4
62881PGOOD
PR58
EV@2K/F_4
PC69
EV@330P/50V_4X
PC73
EV@1000P/50V_4X
62881_GND
PR42 *EV@0_4
2012/11/23 by James
62881_GND
1
2
3
62881RBIAS
4
62881VW
5
62881COMP
6
62881FB
7
62881VSEN
62881RTN
PC50
*EV@0.01U/25V_4X
12
PR44 EV@0_4
62881_GND
29
GND
CLK_EN#
PGOOD
RBIAS
VW
COMP
FB
VSEN
RTN
PU2
8
62881DPRSLPVR
62881VR_ON
28
27
VR_ON
DPRSLPVR
EV@ISL62881CHRTZ-T
ISUM-
ISUM+
9
10
62881ISUM-
62881ISUM+
PC75
EV@1U/6.3V_4X
26
VID6
VDD
11
62881VDD
25
VID5
62881_GND
24
VID4
VIN
12
62881VIN
PC76
EV@0.22U/25V_6X
62881_GND
PR62
EV@1/F_6
23
VID3
IMON
13
PR187
EV@2.2/F_4
22
VID2
14
EV@1K/F_4
+5V_S5
VID1
VID0
VCCP
LGATE
VSSP
PHASE
UGATE
BOOT
62881BOOT
PR61
+3V
21
20
19
18
62881LGATE
17
16
62881PHASE
15
62881UGATE
1 2
PR59
EV@2.2/F_6
+5V_S5
VIN
2012/11/23 by James
2012/11/23 by James
PR40 *EV@10K/F_ 4
PR39 *EV@10K/F_ 4
PR38 EV@10K/F_4
PR37 *EV@10K/F_ 4
PR36 EV@10K/F_4
PR35 EV@10K/F_4
PR34 *EV@10K/F_ 4
+5V_S5
PC150
1 2
EV@4.7U/10V_6X
PC64
EV@0.22U/25V_6X
PR172 EV@10K/F_4
PR173 *EV@10K/F_4
PR175 EV@10K/F_4
PR174 *EV@10K/F_4
PR47
EV@2.2/F_6
PC51
EV@1500P/50V_4X
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
PR176 *EV@10K/F_4
PR178 EV@10K/F_4
PR177 EV@10K/F_4
62881_GND
2012/10/16 by James
1
2
G1
S1/D2
9
G2
765
8
D1D1D1
S2S2S2
PQ27
EV@HP8S36TB
VDDC(V)
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
0.775
2012/12/25 by James
(VID5)
0
0 1 1 1 0
0 1 1 1
1
1
1
1
1
1
1
1
1
1 1
1
1
1
PR191
EV@3.65K/F_4
EV@2.61K/F_4
GFX_CORE_CNTRL4 GFX_CORE_CNTRL3 GFX_CORE_CNTRL2 GFX_CORE_CNTRL1
(VID4) (VID3)
1
0
0
0
0
0
0
0 1 1
1 0
1
1
1
PC53
PC55
EV@10U/25V_8X
PL7
EV@0.22UH_7X7X4
PR56
EV@0_4
PR192
PR190
EV@11K/F_4
PC156
EV@0.15U/10V_4X
PC157
*EV@0.1U/10V_4X
PC56
EV@10U/25V_8X
EV@0.1U/25V_4X
+VGPU_CORE-1
PR55
EV@0_4
A TO B
20121220 by James
PR186
EV@NTC_10K_4
10K NTC put close with Inductor
PC161
EV@0.1U/10V_4X
62881_GND
PC160
PR189
EV@649/F_4
*EV@180P/50V_4N
PR188
*EV@100/F_4
1
0
0
0 1
1
1
0
0
0 1
1
1
VIN
PC54
*EV@2200P/50V_4X
PC48
EV@10U/25V_8X
(VID2)
0
0
0
10
0
0
10 1
0
1
0
0
+VGPU_CORE
Countinue current:18A
Peak current:24A
OCP minimum 30A
Loadline=1.5mV/A
+
PC49
EV@330U/2V_7343P_E6b
(VID1)
40
1
1
0
1
0
1
0
1
0
1
0
1
0
111 0
0
1
+VGPU_CORE
+
PC145
EV@330U/2V_7343P_E6b
A A
PR64 EV@0_4
PR63 EV@0_4
5
Parallel
4
PR162 EV@10/F_4
PR163 EV@10/F_4
VGPU_CORE_VSSSENSE [16]
VGPU_CORE_VCCSSENSE [16 ]
20121112 by James
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
PROJECT :
+VGPU_CORE (TPS51728RHAR) A1A
+VGPU_CORE (TPS51728RHAR) A1A
+VGPU_CORE (TPS51728RHAR) A1A
1
BD9
BD9
BD9
40 41Wednesday, January 30, 2013
40 41Wednesday, January 30, 2013
40 41Wednesday, January 30, 2013
1
VIN
2
+0.95V_GPU
+3V_GPU
3
+15V+1.5V_GPU+1.8V_GPU
4
5
PR149
EV@1M/F_4
A A
EV@LTC044EUBFS8TL_30MA
PR147
EV@100K_4
+1.5VSUS
52
3
1
2
PQ22
PQ17
EV@AON7516
1 3
+1.5V_GPU
GPU_MAINON[22,40]
B B
GPU_MAIND
2012/11/16 by James
4
PR148
EV@1M/F_4
GPU_MAIND
+0.95V_DUAL
52
4
3
(Peak 3.1A)
2
PQ18
EV@AON7406
1
PR146
EV@22_8
3
PQ19B
PQ21
EV@2N7002K_300MA
1
(Peak 4.52A)
+0.95V_GPU
EV@2N7002KDW_115MA
34
PR144
EV@22_8
PE_PWRGD[7,33,40]
+3V_S5
5
EV@10U/6.3V_6X
PR143
EV@22_8
6
2
1
PQ19A
EV@2N7002KDW_115MA
PC137 EV@0.1U/10V_4X
PR156 EV@0_4
PC140
EV@0.1U/10V_4X
Vout =0.8(1+R1/R2)
+1.8V_GPU
C C
VIN
PR207
*EV@1M/F_4
3
PR210
*EV@22_8
EV@2N7002KDW_115MA
PC138
PR145
EV@22_8
34
PQ20B
5
+5V_S5
4
2
3
8
9
PC139
*EV@0.1U/10V_4X
PR142
EV@1M/F_4
GPU_MAIND
6
2
1
PQ20A
EV@2N7002KDW_115MA
+3V_S5
PU6
EV@G9661-25ADJF12U
VPP
VEN
VIN
GND
GND
PGOOD
ADJ
7
1
6
VO
5
NC
PC131
*EV@2200P/50V_4X
PR157 *EV@10K_4
PR150
R1
EV@12.7K/F_4
PR151
EV@10K/F_4
R2
+1.8V_GPU
(Peak 1.338A)
PC134
EV@10U/6.3V_6X
41
2
*EV@LTC044EUBFS8TL_30MA
PQ36
PR209
*EV@100K_4
2
1 3
PR208
*EV@1M/F_4
2
PE_PWRGD
D D
1
PQ37
*EV@2N7002K_300MA
1
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
BD9
BD9
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
3
4
Date: Sheet of
PROJECT :
GPU A1A
GPU A1A
GPU A1A
BD9
41 41Tuesday, December 25, 2012
41 41Tuesday, December 25, 2012
41 41Tuesday, December 25, 2012
5
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