QUANTA BD9 Schematics
5
4
3
2
1
PCB STACK UP
LAYER 1 : TOP
LAYER 2 : GND
LAYER 3 : IN1
LAYER 4 : SVCC
LAYER 5 : IN2
D D
LAYER 6 : IN3
LAYER 7 : GND
LAYER 8 : BOT
Transformer
Page 26
RJ45
Page 26
DDRIII-SODIMM1
DDRIII-SODIMM2
Page 10,11
X'TAL
25MHz
Atheros
10/100M
AR8162B
Page 26
WLAN Con.
Page 28
BD9 FT3 Kabini Block Diagram
Single Channel DDR III
800~1866 MHZ
PCIe-0
PCIe-1
PCI-Express
APU
Kabini APU 25W/15W
SoC
Port 0
RTD2136R
For support PRD 1600x900
Port 1
Page 24
LVDS CONN
LVDS Panel
LVDS CONN
eDP Panel
HDMI CONN
Page 30
Page 30
Page 25
01
24.5mm X 24.5mm
C C
Card Reader Con.
B B
SATA - HDD Con.
SATA - ODD Con.
Support zero power ODD
USB/B
Page 23
USB/B
Page 23
Genesys Logic
GL834L
Page 29Page 29
CCD
Page 30
WLAN
Page 28
Page 31
Page 31
USB2_0
USB2_1
USB2_5
USB2_6
USB2_7
SATA 0
SATA 1
USB 2.0 (Port 0 ~ 9)
BATTERY
Azalia
Conexant
Audio Codec
CX20756-11Z
Port-B
Page 27 Page 27 Page 27
A A
Port-A
HP SPK Con.MIC JACK
Page 27
BGA 769 pin
SATA
USB2.0
+1.5V_RTC
IHDA
USB3.0
LPC
HALL Sensor
PCI-E x4
GFX
USB 3.0 (Port 0 ~ 1)
X'TAL
32.768KHz
X'TAL
48 MHz
SPI
Nuvoton
EC NPCE985L
LED
SPI
Page 8
SPI
K/B Con.FAN
dGPU
Mars/Sun
Pro
29mm X 29mm
Page 12~19,22
USB3_0
USB2_8
USB3_1
USB2_9
Touch Pad /B
Con.
VRAM DDR3-256MB*4
VRAM DDR3-512MB*4
X'TAL
27.0MHz
USB3.0 w/ S&C
USB3.0 w/o S&C
Page 23
Page 23
Page 33
Power /B
Con.
Page 32Page 32Page 32Page 29Page 30Page 7
VRAM DDRIII
Page 20, 21
POWER SYSTEM
ISL88732
TPS51123A
TPS51216RUKR
TPS51211DSCR
ISL62771
Discharge
ISL62881CHRTZ-T
G9661-25ADJF12U
CHARGER
+15V
+3VPCU
+3V_S5
+3V
+5VPCU
+5V_S5
+5V
+SMDDR_VTERM
+SMDDR_VREF
+1.5VSUS
+1.5V_S5
+1.5V
+0.95V_DUAL
+0.95V
+1.8V_S5
+1.8V
+VDD_CORE
+VDDNB_CORE
DISCHARGE
+VGPU_CORE
+1.8V_GPU
+1.5V_GPU
+0.95V_GPU
P34
P35
P36
P37
P38
P39
P40
P41
P34
P35
P36
P37
P38
P39
P40
P41
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
5
4
3
2
Tuesday, December 25, 2012
PROJECT :
Block Diagram
Block Diagram
Block Diagram
BD9
BD9
BD9
1 41
1 41
1
1 41
A1A
A1A
A1A
5
4
3
2
1
02
Table of Contents
D D
C C
PAGE DESCRIPTION
Schematic Block Diagram
1
Power Stage
2
Processor
3 - 8
9
Straps
10
SO-DIMM 1 DDR
11
SO-DIMM 2
12 - 19
Mars/Sun Pro(M2) VGA
20 - 21
VRAM - DDR3 VGA
22
PX5 VGA
23
USB U3B/USB
24
eDP to LVDS(RTD2136R) LDS
HDMI/Touch Screen
25
LAN(1AR8162B) LAN
26
Codec (CX20756-11Z)
27
MINI CARD (WLAN)
28
29
CARD READER(GL834L)/LED MMC/LED
30
LDS/CRT/CCD
HDD/ODD
31
32
KB/TouchPad
33
EC 985L
Charger (ISL88731CHRTZ-T)
34
System 5V/3V
35
DDR 1.5V
36
+0.95V_DUAL
37
+VCC_CORE
38
Discharge
39
40
GPU_CORE
41
+0.95V_GPU/+1.8V_GPU/+1.5V_GPU/+3V_GPU
GND PLANE PAGE
B B
GND_SIGNAL
8769GND
BOI-FUNCTION
CPU
CPU
DDR
HDM/TSN
ADO
MNW
LDS/CRT/CCD
HDD/ODD
KBC/TPD
KBC
CHR
PWM
PWM
PWM
PWM
PWM
PWM
PWM
POWER PLANE
VIN
+VCCRTC
+3V
+3V_S5
+3VPCU
+5V
+5V_S5
+5VPCU
+WIMAX_P
+1.5VSUS
+1.5V
VOLTAGE
10V~+19V
+1.5V
+3.3V
+3.3V
+3.3V
+5V
+5V
+5V
+3.3V
+1.5V SUSON
+1.5V
MAIND
S5_ON
MAIND S0
S5_ON S0~S5
AC/DC Insert enable
IOAC_EN
MAIND
CONTROL
SIGNAL
Power States
+1.8V_S5 +1.8V PE_PWRGD ^ PE_GPIO1 S0~S5
+0.95V_DUAL
+0.95V +0.95V_DUAL_EN
+0.95V+0.95V MAIND
+VDD_CORE
~
VRON
+VDDNB_CORE ~ VRON S0
+VGPU_CORE
+1.8V_GPU
+1.8V
+0.95V_GPU +0.95V
+3V_GPU
+1.5V_GPU
+3.3V
+1.5V GPU_MAIND
GPU_MAINON ^ PE_GPIO1
GPU_MAIND
GPU_MAINON ^ PE_GPIO1
GPU_MAIND S0
ACTIVE IN
S0~S5
S0~S5
S0
S0~S5
S0~S5AC/DC Insert enable
S0~S5
S0
S0~S3
S0
S0~S5
S0
S0
S0
S0
S0
S0
GND ALL
ADOGND
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
POWER STAGE & BOI-FUNCTION
POWER STAGE & BOI-FUNCTION
POWER STAGE & BOI-FUNCTION
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
5
4
3
2
Tuesday, December 25, 2012
PROJECT :
1
BD9
BD9
BD9
2 41
2 41
2 41
A1A
A1A
A1A
5
4
3
2
1
Coupling Caps Note:
U22B
D D
PCIe-LAN
PCIe-WLAN
PCIE_RXP_LAN[26]
PCIE_RXN_LAN[26]
PCIE_RXP_WLAN[28]
PCIE_RXN_WLAN[28]
+0.95V +0.95V
R109 1.69K/F_4
PCIE_RXP_LAN
PCIE_RXN_LAN
PCIE_RXP_WLAN
PCIE_RXN_WLAN
P_TX_ZVDD P_RX_ZVDD
R10
N10
R8
R5
R4
N5
N4
N8
W8
P_GPP_RXP0
P_GPP_RXN0
P_GPP_RXP1
P_GPP_RXN1
P_GPP_RXP2
P_GPP_RXN2
P_GPP_RXP3
P_GPP_RXN3
P_TX_ZVDD_095
PCIE
L2
P_GPP_TXP0
P_GPP_TXN0
P_GPP_TXP1
P_GPP_TXN1
P_GPP_TXP2
P_GPP_TXN2
P_GPP_TXP3
P_GPP_TXN3
P_RX_ZVDD_095
PCIE_TXP_LAN_C
L1
PCIE_TXN_LAN_C
K2
PCIE_TXP_WLAN_C
K1
PCIE_TXN_WLAN_C
J2
J1
H2
H1
W7
X5R is required.
C624 LAN@0.1U/10V_4X
C622 0.1U/10V_4X
R104 1K/F_4
C621 LAN@0.1U/10V_4X
C620 0.1U/10V_4X
PCIE_TXP_LAN
PCIE_TXN_LAN
PCIE_TXP_WLAN
PCIE_TXN_WLAN
PCIE_TXP_LAN [26]
PCIE_TXN_LAN [26]
PCIE_TXP_WLAN [28]
PCIE_TXN_WLAN [28]
PCIe-LAN
PCIe-WLAN
03
PEG_RXP0[12]
PEG_RXN0[12]
PEG_RXP1[12]
PEG_RXN1[12]
PEG_RXP2[12]
PEG_RXN2[12]
C C
APU_TRST#[5]
B B
PEG_RXP3[12]
PEG_RXN3[12]
PEG_RXP0
PEG_RXN0
PEG_RXP1
PEG_RXN1
PEG_RXP2
PEG_RXN2
PEG_RXP3
PEG_RXN3
+1.8V
R41
*DEBUG@1K_4
R47 DEBUG@0_4
R53 DEBUG@10K_4
R55 DEBUG@10K_4
R62 DEBUG@10K_4
L5
P_GFX_RXP0
L4
P_GFX_RXN0
J5
P_GFX_RXP1
J4
P_GFX_RXN1
G5
P_GFX_RXP2
G4
P_GFX_RXN2
D7
P_GFX_RXP3
E7
P_GFX_RXN3
FT3 REV 0.53
HDT+ Connector
+1.8V
SPEC X with CHECK LIST
J1
1
CPU_VDDIO1
3
GND1
5
GND2
7
GND3
9
CPU_TRST_L
11
CPU_DBRDY3
13
CPU_DBRDY2
15
CPU_DBRDY1
17
GND4
19
CPU_VDDIO2
*DEBUG@HDT+ HEADER
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TDO
CPU_PWROK_BUF
CPU_RST_L_BUF
CPU_DBRDY0
CPU_DBREQ_L
CPU_PLLTEST0
CPU_PLLTEST1
P_GFX_TXP0
P_GFX_TXN0
P_GFX_TXP1
P_GFX_TXN1
P_GFX_TXP2
P_GFX_TXN2
P_GFX_TXP3
P_GFX_TXN3
FT3
G2
PEG_TXP0_C
G1
PEG_TXN0_C
F2
PEG_TXP1_C
F1
PEG_TXN1_C
E2
PEG_TXP2_C
E1
PEG_TXN2_C
D2
PEG_TXP3_C
D1
2
APU_TCK
4
APU_TMS
6
APU_TDI
8
APU_TDO
10
APU_PWROK_BUFAPU_TRST#
12
APU_RST_L_BUF
14
APU_DBRDY
16
DBREQ#
18
APU_TEST19_PLLTEST0
20
APU_TEST18_PLLTEST1
C619 EV@0.1U/10V_4X
C618 EV@0.1U/10V_4X
C615 EV@0.1U/10V_4X
C614 EV@0.1U/10V_4X
R64 *DEBUG/EVB@0_4
C617 EV@0.1U/10V_4X
C616 EV@0.1U/10V_4X
C613 EV@0.1U/10V_4X
C612 EV@0.1U/10V_4X
APU_TCK [5]
APU_TMS [5]
APU_TDI [5]
APU_TDO [5]
APU_DBRDY [5]
APU_DBREQ#
APU_TEST19_PLLTEST0 [5]
APU_TEST18_PLLTEST1 [5]
PEG_TXP0
PEG_TXN0
PEG_TXP1
PEG_TXN1
PEG_TXP2
PEG_TXN2
PEG_TXP3
PEG_TXN3PEG_TXN3_C
APU_DBREQ# [5]
PEG_TXP0 [12]
PEG_TXN0 [12]
PEG_TXP1 [12]
PEG_TXN1 [12]
PEG_TXP2 [12]
PEG_TXN2 [12]
PEG_TXP3 [12]
PEG_TXN3 [12]
PEG X 4
Debug only
R600 *0_4
Debug only
U3
APU_RST#[5]
APU_PWRGD[5]
A A
APU_PWRGD
C21
*DEBUG@0.1U/10V_4X
1
A1
2
GND
3
A2
*DEBUG@74LVC2G07
R601 *0_4
VCC
6
Y1
5
4
Y2
C26 *E@1000P/50V_4X
APU_RST_L_BUFAPU_RST#
+1.8V
APU_PWROK_BUF
C23
*DEBUG@0.1U/10V_4X
R28 *DEBUG@1K_4
R25 *DEBUG@1K_4
C20
*E@1000P/50V_4X
+1.8V
RevB 1221 Add 0 ohm for debug
5
4
3
2
Close by HDT+ Conector
APU_TDI
APU_TCK
APU_TMS
APU_DBREQ#
C44
*DEBUG@0.1U/10V_4X
R387 *DEBUG@1K_4
R389 *DEBUG@1K_4
R388 *DEBUG@1K_4
R69 *DEBUG@1K_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
Tuesday, December 25, 2012
PROJECT :
APU 1/6(PCIE/GPP)
APU 1/6(PCIE/GPP)
APU 1/6(PCIE/GPP)
+1.8V
1
BD9
BD9
BD9
3 41
3 41
3 41
A1A
A1A
A1A
5
4
3
2
1
04
D D
M_A_A[15:0][10,11]
M_A_BS#[2..0][10,11]
M_A_DM[7..0][10,11]
C C
+1.5VSUS
R113
1K/F_4
B B
M_A_EVENT#[10,11]
+1.5VSUS
R459
1K/F_4
+MEMVREF_CPU
+APU_M_VREFDQ_SUS
R460
1K/F_4
A A
C630
0.47U/6.3V_4X
C631
0.1U/10V_4X
C628
1U/6.3V_4X
C775
39P/50V_4N
RevB 1221 Add cap
M_A_A[15:0]
M_A_BS#[2:0]
M_A_DM[7:0]
M_A_DQSP0[10,11]
M_A_DQSN0[10,11]
M_A_DQSP1[10,11]
M_A_DQSN1[10,11]
M_A_DQSP2[10,11]
M_A_DQSN2[10,11]
M_A_DQSP3[10,11]
M_A_DQSN3[10,11]
M_A_DQSP4[10,11]
M_A_DQSN4[10,11]
M_A_DQSP5[10,11]
M_A_DQSN5[10,11]
M_A_DQSP6[10,11]
M_A_DQSN6[10,11]
M_A_DQSP7[10,11]
M_A_DQSN7[10,11]
+MEMVREF_CPU
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_BS#0
M_A_BS#1
M_A_BS#2
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
TP40
M_A_DQSP0
M_A_DQSN0
M_A_DQSP1
M_A_DQSN1
M_A_DQSP2
M_A_DQSN2
M_A_DQSP3
M_A_DQSN3
M_A_DQSP4
M_A_DQSN4
M_A_DQSP5
M_A_DQSN5
M_A_DQSP6
M_A_DQSN6
M_A_DQSP7
M_A_DQSN7
M_A_CLKP0[10]
M_A_CLKN0[10]
M_A_CLKP1[10]
M_A_CLKN1[10]
M_A_CLKP2[11]
M_A_CLKN2[11]
M_A_CLKP3[11]
M_A_CLKN3[11]
M_A_RST#[10,11]
M_A_CKE0[10]
M_A_CKE1[10]
M_A_CKE2[11]
M_A_CKE3[11]
M_A_ODT0[10]
M_A_ODT1[10]
M_A_ODT2[11]
M_A_ODT3[11]
M_A_CS#0[10]
M_A_CS#1[10]
M_A_CS#2[11]
M_A_CS#3[11]
M_A_RAS#[10,11]
M_A_CAS#[10,11]
M_A_WE#[10,11]
M_A_CLKP0
M_A_CLKN0
M_A_CLKP1
M_A_CLKN1
M_A_CLKP2
M_A_CLKN2
M_A_CLKP3
M_A_CLKN3
M_A_RST#
M_A_EVENT#
M_A_CKE0
M_A_CKE1
M_A_CKE2
M_A_CKE3
M_A_ODT0
M_A_ODT1
M_A_ODT2
M_A_ODT3
M_A_CS#0
M_A_CS#1
M_A_CS#2
M_A_CS#3
M_A_RAS#
M_A_CAS#
M_A_WE#
C625
*1U/10V_4X
AG38
W35
W38
W34
U38
U37
U34
R35
R38
N38
AG34
R34
N37
AN34
L38
L35
AJ38
AG35
N34
B32
B38
G40
N41
AG40
AN41
AY40
AY34
Y40
B33
A33
B40
A40
H41
H40
P41
P40
AH41
AH40
AP41
AP40
BA40
AY41
AY33
BA34
AA40
Y41
AC35
AC34
AA34
AA32
AE38
AE37
AA37
AA38
G38
AE34
L34
J38
J37
J34
AN38
AU38
AN37
AR37
AJ34
AR38
AL38
AN35
AJ37
AL34
AL35
AD40
AC38
C626
*100P/50V_4N
U22A
M_ADD0
M_ADD1
M_ADD2
M_ADD3
M_ADD4
M_ADD5
M_ADD6
M_ADD7
M_ADD8
M_ADD9
M_ADD10
M_ADD11
M_ADD12
M_ADD13
M_ADD14
M_ADD15
M_BANK0
M_BANK1
M_BANK2
M_DM0
M_DM1
M_DM2
M_DM3
M_DM4
M_DM5
M_DM6
M_DM7
M_DM8
M_DQS_H0
M_DQS_L0
M_DQS_H1
M_DQS_L1
M_DQS_H2
M_DQS_L2
M_DQS_H3
M_DQS_L3
M_DQS_H4
M_DQS_L4
M_DQS_H5
M_DQS_L5
M_DQS_H6
M_DQS_L6
M_DQS_H7
M_DQS_L7
M_DQS_H8
M_DQS_L8
M_CLK_H0
M_CLK_L0
M_CLK_H1
M_CLK_L1
M_CLK_H2
M_CLK_L2
M_CLK_H3
M_CLK_L3
M_RESET_L
M_EVENT_L
M0_CKE0
M0_CKE1
M1_CKE0
M1_CKE1
M0_ODT0
M0_ODT1
M1_ODT0
M1_ODT1
M0_CS_L0
M0_CS_L1
M1_CS_L0
M1_CS_L1
M_RAS_L
M_CAS_L
M_WE_L
M_VREF
M_VREFDQ
MEMORY
FT3 REV 0.53
M_DATA0
M_DATA1
M_DATA2
M_DATA3
M_DATA4
M_DATA5
M_DATA6
M_DATA7
M_DATA8
M_DATA9
M_DATA10
M_DATA11
M_DATA12
M_DATA13
M_DATA14
M_DATA15
M_DATA16
M_DATA17
M_DATA18
M_DATA19
M_DATA20
M_DATA21
M_DATA22
M_DATA23
M_DATA24
M_DATA25
M_DATA26
M_DATA27
M_DATA28
M_DATA29
M_DATA30
M_DATA31
M_DATA32
M_DATA33
M_DATA34
M_DATA35
M_DATA36
M_DATA37
M_DATA38
M_DATA39
M_DATA40
M_DATA41
M_DATA42
M_DATA43
M_DATA44
M_DATA45
M_DATA46
M_DATA47
M_DATA48
M_DATA49
M_DATA50
M_DATA51
M_DATA52
M_DATA53
M_DATA54
M_DATA55
M_DATA56
M_DATA57
M_DATA58
M_DATA59
M_DATA60
M_DATA61
M_DATA62
M_DATA63
M_CHECK0
M_CHECK1
M_CHECK2
M_CHECK3
M_CHECK4
M_CHECK5
M_CHECK6
M_CHECK7
M_ZVDDIO_MEM_S
B30
M_A_DQ0
A32
M_A_DQ1
B35
M_A_DQ2
A36
M_A_DQ3
B29
M_A_DQ4
A30
M_A_DQ5
A34
M_A_DQ6
B34
M_A_DQ7
B37
M_A_DQ8
A38
M_A_DQ9
D40
M_A_DQ10
D41
M_A_DQ11
B36
M_A_DQ12
A37
M_A_DQ13
B41
M_A_DQ14
C40
M_A_DQ15
F40
M_A_DQ16
F41
M_A_DQ17
K40
M_A_DQ18
K41
M_A_DQ19
E40
M_A_DQ20
E41
M_A_DQ21
J40
M_A_DQ22
J41
M_A_DQ23
M41
M_A_DQ24
N40
M_A_DQ25
T41
M_A_DQ26
U40
M_A_DQ27
L40
M_A_DQ28
M40
M_A_DQ29
R40
M_A_DQ30
T40
M_A_DQ31
AF40
M_A_DQ32
AF41
M_A_DQ33
AK40
M_A_DQ34
AK41
M_A_DQ35
AE40
M_A_DQ36
AE41
M_A_DQ37
AJ40
M_A_DQ38
AJ41
M_A_DQ39
AM41
M_A_DQ40
AN40
M_A_DQ41
AT41
M_A_DQ42
AU40
M_A_DQ43
AL40
M_A_DQ44
AM40
M_A_DQ45
AR40
M_A_DQ46
AT40
M_A_DQ47
AV41
M_A_DQ48
AW40
M_A_DQ49
BA38
M_A_DQ50
AY37
M_A_DQ51
AU41
M_A_DQ52
AV40
M_A_DQ53
AY39
M_A_DQ54
AY38
M_A_DQ55
BA36
M_A_DQ56
AY35
M_A_DQ57
BA32
M_A_DQ58
AY31
M_A_DQ59
BA37
M_A_DQ60
AY36
M_A_DQ61
BA33
M_A_DQ62
AY32
M_A_DQ63
V41
W40
AB40
AC40
U41
V40
AA41
AB41
AD41
+M_ZVDDIO
Place close to APU within 1"
FT3
M_A_DQ[63:0]
+1.5VSUS
R45839.2/F_4
M_A_DQ[63:0] [10,11]
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
5
4
3
2
Tuesday, December 25, 2012
PROJECT :
APU 2/6(DDR3 MEM)
APU 2/6(DDR3 MEM)
APU 2/6(DDR3 MEM)
BD9
BD9
BD9
A1A
A1A
4 41
4 41
1
4 41
A1A
5
4
3
2
1
U22C
DISPLAY/SVI2/JTAG/TEST
TDP1_TXP0
TDP1_TXN0
TDP1_TXP1
TDP1_TXN1
TDP1_TXP2
TDP1_TXN2
TDP1_TXP3
TDP1_TXN3
LTDP0_TXP0
LTDP0_TXN0
LTDP0_TXP1
LTDP0_TXN1
LTDP0_TXP2
LTDP0_TXN2
LTDP0_TXP3
LTDP0_TXN3
DISP_CLKIN_H
DISP_CLKIN_L
+1.8V
SVT
+1.8V
SVC
+1.8V
SVD
+3V
SIC
+3V
SID
APU_RST_L
LDT_RST_L
APU_PWROK
LDT_PWROK
+3V
PROCHOT_L
+3V
ALERT_L
+1.8V
TDI
+1.8V
TDO
+1.8V
TCK
+1.8V
TMS
+1.8V
TRST_L
+1.8V
DBRDY
+1.8V
DBREQ_L
VDDCR_NB_SENSE
VDDCR_CPU_SENSE
VDDIO_MEM_S_SENSE
VSS_SENSE
VDD_095_FB_H
VDD_095_FB_L
FT3 REV 0.53
Read APU Temperature
+3V
5
Q25B 2N7002KDW_115MA
3 4
R412 *0_4
Q25A
2
6
R406 *0_4
DP_150_ZVSS
DP_2K_ZVSS
+3V
DP_BLON
+3V
DP_DIGON
+3V
DP_VARY_BL
+3V
TDP1_AUXP
+3V
TDP1_AUXN
+3V
TDP1_HPD
+3V
LTDP0_AUXP
+3V
LTDP0_AUXN
+3V
LTDP0_HPD
DAC_RED
DAC_GREEN
DAC_BLUE
+3V
DAC_HSYNC
+3V
DAC_VSYNC
+3V
DAC_SCL
+3V
DAC_SDA
DAC_ZVSS
TEST4
TEST5
TEST6
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST31
RSVD
TEST36
TEST37
TEST42
TEST43
TEST39
TEST40
TEST41
DP_STEREOSYNC
FT3
APU_SIC2ND_MBCLK
2N7002KDW _115MA
1
B16
DP_150_ZVSS
A21
DP_2K_ZVSS
B17
APU_BLON
A17
APU_DIGON
A18
APU_VARY_BL
D17
INT_HDMI_AUXP
E17
INT_HDMI_AUXN
H19
INT_HDMI_HPD
D15
INT_LVDS_AUXP_C
E15
INT_LVDS_AUXN_C
H17
INT_LVDS_HPD_Q
B14
APU_CRT_RED
A14
APU_CRT_GRE
B15
APU_CRT_BLU
G19
APU_CRT_HSYNC
E19
APU_CRT_VSYNC
D19
APU_DDCCLK
D21
APU_DDCDAT
A16
DAC_ZVSS
H27
APU_TEST4
H29
APU_TEST5
D25
APU_TEST6
A27
APU_TEST14
B27
APU_TEST15
A26
APU_TEST16
B26
APU_TEST17
B28
APU_TEST18_PLLTEST1
A28
APU_TEST19_PLLTEST0
B24
APU_TEST25_H
A24
APU_TEST25_L
AV35
APU_TEST28_H
AU35
APU_TEST28_L
E33
APU_TEST31
A29
APU_TEST34
H21
APU_TEST36
H25
APU_TEST37
AJ10
APU_TEST42
AJ8
APU_TEST43
R32
APU_TEST39
N32
APU_TEST40
AP29
APU_TEST41
E21
DP_STEREOSYNC
+3V
R410
1K_4
R409
1K_4
3
R442 150/F_4
1 2
R434 2K/F_4
C42 0.1U/10V_4X
C43 0.1U/10V_4X
R433 499/F_4
R63 1K_4
APU_BL_EN [30]
APU_DIGON [30]
APU_VARY_BL [24,30]
INT_HDMI_AUXP [25]
INT_HDMI_AUXN [25]
INT_HDMI_HPD [25]
INT_LVDS_AUXP
INT_LVDS_AUXN
APU_CRT_RED [30]
APU_CRT_GRE [30]
APU_CRT_BLU [30]
APU_CRT_HSYNC [30]
APU_CRT_VSYNC [30]
APU_DDCCLK [30]
APU_DDCDAT [30]
TP10
TP13
TP8
TP4
TP7
TP5
TP1
APU_TEST18_PLLTEST1 [3]
APU_TEST19_PLLTEST0 [3]
TP3
TP2
TP32
TP29
TP9
TP6
TP12
TP14
TP22
TP21
TP16
TP15
TP31
APU_PWRGD CPU_PWRGD_SVID_REG
SVC SVD BOOT VOLTAGE
000
1
0
111
R42
*1K_4
1.1
1.0
0.9
0.8
LVDS Back Light Control
HDMI AUX
INT_LVDS_AUXP [24]
INT_LVDS_AUXN [24]
layout trace
reference GND
+1.8V
R48
R49
*1K_4
*1K_4
R36 0_4
R44 0_4
Re
R43 0_4
Rf
R424 0_4
Rg
2
EDID PU 4.7K +3.3V @ Conn
eDP to LVDS Translator
R place close to APU
APU_CRT_RED
APU_CRT_GRE
APU_CRT_BLU
INT_LVDS_HPD_Q
Note:
To override VID,Remove Rd,Re, Rf, Rg, install Rc
set VID via SVC & SVD option RES Ra, Rb
Ra RbRdRc
R38
*220_4
R441 150/F_4
R440 150/F_4
R439 150/F_4
+3V
R401
LDS@1K_4
34
LDS@2N7002KDW_115MA
5
Q22B
APU_TEST14
APU_TEST16
APU_TEST17
APU_TEST18_PLLTEST1
APU_TEST19_PLLTEST0
APU_TEST25_H
APU_TEST36
APU_TEST25_L
APU_TEST37
APU_SVTSVT
APU_SVCSVC
APU_SVDSVD
R423
R37
*220_4
*220_4
+5V
R394
LDS@10K_4
6
LDS@2N7002KDW_115MA
2
Q21A
1
R392 eDP@0_4
R60 *1K_4
R59 *1K_4
R50 *1K_4
R79 1K_4
R78 1K_4
R58 510/F_4
R57 *1K_4
R56 *1K_4
R46 510/F_4
R95 *1K_4
R103 *1K_4
C586
*0.1U/10V_4X
INT_LVDS_HPD
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
Tuesday, December 25, 2012
INT_HDMI_AUXP
INT_HDMI_AUXN
INT_LVDS_AUXP_C
INT_LVDS_AUXN_C
INT_LVDS_AUXP_C
INT_LVDS_AUXN_C
R94 *1.8K_4
R96 *1.8K_4
R65 1.8K_4
R70 1.8K_4
R66 *eDP@100K_4
R71 *eDP@100K_4
For eDP Panel
INT_LVDS_HPD [24,30]
R396
100K_4
RevB 1219 Change HDMI strap setting
from PD to PU for HDMI No display issue
+1.8V
APU_CRT_HSYNC
APU_SVT [38]
APU_SVC [38]
APU_SVD [38]
CPU_PWRGD_SVID_REG [38]
APU 3/6(DP/SVI2/JTAG/Test)
APU 3/6(DP/SVI2/JTAG/Test)
APU 3/6(DP/SVI2/JTAG/Test)
+3V
R52
1K_4
R54
*1K_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
AV33
AU33
A9
B9
A10
B10
A11
B11
A12
B12
A4
B4
A5
B5
A6
B6
A7
B7
K15
H15
G31
D27
E29
B22
B21
B20
A20
B19
A19
A22
B18
D29
D31
D35
D33
G27
B25
A25
D23
G23
E25
E23
INT_HDMI_TXDP2[25]
INT_HDMI_TXDN2[25]
INT_HDMI_TXDP1[25]
R427
300_4
C598
150P/50V_4N
INT_HDMI_TXDN1[25]
INT_HDMI_TXDP0[25]
INT_HDMI_TXDN0[25]
INT_HDMI_TXCP[25]
INT_HDMI_TXCN[25]
INT_LVDS_TXP0[24]
INT_LVDS_TXN0[24]
INT_LVDS_TXP1[24]
INT_LVDS_TXN1[24]
INT_LVDS_TXP2[30]
INT_LVDS_TXN2[30]
INT_LVDS_TXP3[30]
INT_LVDS_TXN3[30]
+1.8V +1.8V
R428
300_4
C596
150P/50V_4N
APU_VDDNB_RUN_FB_H[38]
APU_VDD_RUN_FB_H[38]
APU_VDDIO_RUN_FB_H
APU_VDD_RUN_FB_L[38]
D D
LVDS
HDMI
C C
APU_RST#[3]
APU_PWRGD[3]
INT_HDMI_TXDP2
INT_HDMI_TXDN2
INT_HDMI_TXDP1
INT_HDMI_TXDN1
INT_HDMI_TXDP0
INT_HDMI_TXDN0
INT_HDMI_TXCP
INT_HDMI_TXCN
INT_LVDS_TXP0
INT_LVDS_TXN0
INT_LVDS_TXP1
INT_LVDS_TXN1 INT_LVDS_TXN1_C
INT_LVDS_TXP2
INT_LVDS_TXN2
INT_LVDS_TXP3
INT_LVDS_TXN3
C595
*E@0.1U/10V_4X
VDD_095_FB_H
VDD_095_FB_L
C603 HM@0.1U/10V_4X
C602 HM@0.1U/10V_4X
C594 HM@0.1U/10V_4X
C593 HM@0.1U/10V_4X
C601 HM@0.1U/10V_4X
C600 HM@0.1U/10V_4X
C592 HM@0.1U/10V_4X
C591 HM@0.1U/10V_4X
C609 0.1U/10V_4X
C608 0.1U/10V_4X
C607 0.1U/10V_4X
C606 0.1U/10V_4X
C605 eDP@0.1U/10V_4X
C604 eDP@0.1U/10V_4X
C599 eDP@0.1U/10V_4X
C597 eDP@0.1U/10V_4X
R51 1K_4
+3V
R432 1K_4
APU_TDI[3]
APU_TDO[3]
APU_TCK[3]
APU_TMS[3]
APU_TRST#[3]
APU_DBRDY[3]
APU_DBREQ#[3]
APU_VDDNB_RUN_FB_H
APU_VDD_RUN_FB_H
APU_VDDIO_RUN_FB_H
APU_VDD_RUN_FB_L VSS_SENSE
VDD_095_FB_H
VDD_095_FB_L
INT_HDMI_TXDP2_C
INT_HDMI_TXDN2_C
INT_HDMI_TXDP1_C
INT_HDMI_TXDN1_C
INT_HDMI_TXDP0_C
INT_HDMI_TXDN0_C
INT_HDMI_TXCP_C
INT_HDMI_TXCN_C
INT_LVDS_TXP0_C
INT_LVDS_TXN0_C
INT_LVDS_TXP1_C
INT_LVDS_TXP2_C
INT_LVDS_TXN2_C
INT_LVDS_TXP3_C
INT_LVDS_TXN3_C
Reserved for external clock Gen,
leave unconnected.
SVT
SVC
SVD
APU_SIC
APU_SID
APU_RST#
APU_PWRGD
R61 0_4
APU_RST#_R
APU_PWRGD_R
H_PROCHOT
APU_ALERT#
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#
R444 0_4
R435 0_4
1.5V & 0.95V SENSE PIN
TP11
B B
TP33
TP24
APU_VDDIO_RUN_FB_H
VDD_095_FB_H
VDD_095_FB_L
PROC HOT
+3V
H_PROCHOT_EC#[33]
+3V_S5
R34 10K_4
R35 10K_4
2
3
Q7
2N7002K_300MA
1
H_PROCHOT
+3V
2ND_MBCLK[23,33]
2ND_MBDATA[23,33]
2ND_MBDATA APU_SID
2
3
Q6
2N7002K_300MA
5
1
4
+3VPCU
A A
CORE_PWM_PROCHOT#[38]
BD9
BD9
BD9
5 41
5 41
5 41
05
+3V
A1A
A1A
A1A
5
4
3
2
1
06
+1.5VSUS
C103
D D
10U/6.3V_6X
C144
10U/6.3V_6X
C162
180P/50V_4N
+1.5V_S5
R483 0_8
C656
C C
RevB 1219 Change from short pad to mount 0805
+1.8V_S5
1U/6.3V_4X
R82 0_8
C47
*180P/50V_4N
C66
1U/6.3V_4X
C67
1U/6.3V_4X
RevB 1219 Change from short pad to mount 0805
B B
+3VPCU
+VCCRTC_2
R456
10K_4
+BAT
20MIL
12
+0.95V_DUAL
D31
BAT54C-7-F_200MA
CN15
20MIL
20MIL
RTC_VIN
180pF: COG, NP0
Others: X5R
C116
10U/6.3V_6X
C678
1U/10V_4X
C146
180P/50V_4N
C179
C92
0.1U/10V_4X
0.1U/10V_4X
C71
C128
0.1U/10V_4X
0.1U/10V_4X
+APU_VDDIO_AZ_S
C649
1U/6.3V_4X
C655
180P/50V_4N
+APU_VDD18V_S
C56
1U/6.3V_4X
C65
1U/6.3V_4X
C69
1U/6.3V_4X
C68
1U/6.3V_4X
R505 U3@0_8
R108 0_8
+1.5V_RTC_R
NCP698SQ15T1G
1
GND
4
EN
3
VIN2VOUT
U29
R514 1K_4
1.5V level
need a LDO from 3V to 1.5V
W31
W32
W37
AA31
AA35
AC32
AC37
AE31
AE35
AG32
AG37
AJ35
AL32
AL37
AR35
J35
L32
L37
N35
R31
R37
U32
U35
U22F
VDDIO_MEM_S_1
VDDIO_MEM_S_2
VDDIO_MEM_S_3
VDDIO_MEM_S_4
VDDIO_MEM_S_5
VDDIO_MEM_S_6
VDDIO_MEM_S_7
VDDIO_MEM_S_8
VDDIO_MEM_S_9
VDDIO_MEM_S_10
VDDIO_MEM_S_11
VDDIO_MEM_S_12
VDDIO_MEM_S_13
VDDIO_MEM_S_14
VDDIO_MEM_S_15
VDDIO_MEM_S_16
VDDIO_MEM_S_17
VDDIO_MEM_S_18
VDDIO_MEM_S_19
VDDIO_MEM_S_20
VDDIO_MEM_S_21
VDDIO_MEM_S_22
VDDIO_MEM_S_23
C125
180P/50V_4N
C153
0.1U/10V_4X
C139
0.1U/10V_4X
3 A
C165
180P/50V_4N
C109
0.1U/10V_4X
C196
0.1U/10V_4X
0.1 A
C648
C650
1U/6.3V_4X
4.7U/6.3V_6X
0.5 A
C55
4.7U/6.3V_6X
C57
180P/50V_4N
+APU_3V_S
1 A
+VDD_095_USB3_S
0.5 A
+VDD_095_PHY_S
+1.5V_RTC
R140 10K_4
C195
0.22U/10V_4X
RevB 1210 Change P/N to AL000698000
0.2 A
AL10
AL11
AL13
AM13
AR5
AU4
AW5
AE11
AE13
AJ11
AJ13
20MIL
AN4
12
G1
*SHORT_PAD
VDDIO_AZ_ALW_1
VDDIO_AZ_ALW_2
B1
VDD_18_ALW_1
B2
VDD_18_ALW_2
VDD_33_ALW_1
VDD_33_ALW_2
VDD_095_USB3_DUAL_1
VDD_095_USB3_DUAL_2
AV7
VDD_095_USB3_DUAL_3
VDD_095_USB3_DUAL_4
VDD_095_ALW_1
VDD_095_ALW_2
VDD_095_ALW_3
VDD_095_ALW_4
VDDBT_RTC_G
+1.5V_S5
FT3 REV 0.53
POWER
VDDCR_CPU_1
VDDCR_CPU_2
VDDCR_CPU_3
VDDCR_CPU_4
VDDCR_CPU_5
VDDCR_CPU_6
VDDCR_CPU_7
VDDCR_CPU_8
VDDCR_CPU_9
VDDCR_CPU_10
VDDCR_CPU_11
VDDCR_CPU_12
VDDCR_CPU_13
VDDCR_CPU_14
VDDCR_CPU_15
VDDCR_CPU_16
VDDCR_CPU_17
VDDCR_CPU_18
VDDCR_CPU_19
VDDCR_CPU_20
VDDCR_CPU_21
VDDCR_CPU_22
VDDCR_CPU_23
VDDCR_CPU_24
VDDCR_CPU_25
VDDCR_CPU_26
VDDCR_NB_1
VDDCR_NB_2
VDDCR_NB_3
VDDCR_NB_4
VDDCR_NB_5
VDDCR_NB_6
VDDCR_NB_7
VDDCR_NB_8
VDDCR_NB_9
VDDCR_NB_10
VDDCR_NB_11
VDDCR_NB_12
VDDCR_NB_13
VDDCR_NB_14
VDDCR_NB_15
VDDCR_NB_16
VDDCR_NB_17
VDDCR_NB_18
VDDCR_NB_19
VDDCR_NB_20
VDDCR_NB_21
VDD_18_1
VDD_18_2
VDD_18_3
VDD_18_4
VDD_33_1
VDD_33_2
VDD_095_1
VDD_095_2
VDD_095_3
VDD_095_4
VDD_095_5
VDD_095_6
VDD_095_7
VDD_095_8
VDD_095_9
VDD_095_GFX_1
VDD_095_GFX_2
VDD_095_GFX_3
FT3
21 A
L21
L23
L25
L27
L29
N21
N23
N27
R21
R23
R27
U21
U23
U27
W21
W23
W27
AA21
AA23
AA27
AC21
AC23
AC27
AE21
AE23
AE27
17 A
L13
L17
N11
N13
N17
R11
R13
R17
U13
U17
W13
W17
AA13
AA17
AC13
AC17
AE15
AE17
AE19
AG17
AG21
A2
A3
B3
C3
AM15
AM17
AG23
AG27
AJ21
AJ27
AL21
AL23
AL27
AM23
AM25
U10
W10
AA10
1.5 A
0.2 A
+VDDIO_3V
5 A
+VDD_095_GPP
0.6 A
+VDD_095_GFX
C118
EV@1U/6.3V_4X
+VDDIO_18V
RevB 1221 Change EV@
C188
180P/50V_4N
C177
1U/6.3V_4X
C89
C99
10U/6.3V_6X
10U/6.3V_6X
10U/6.3V_6X
C121
C131
1U/6.3V_4X
1U/6.3V_4X
C152
C148
1U/6.3V_4X
1U/6.3V_4X
C95
C104
10U/6.3V_6X
10U/6.3V_6X
C130
1U/6.3V_4X
C168
1U/6.3V_4X
C29
10U/6.3V_6X
C38
1U/6.3V_4X
10U/6.3V_6X
C120
1U/6.3V_4X
C141
1U/6.3V_4X
C36
1U/6.3V_4X
C35
1U/6.3V_4X
RevB 1219 Change from short pad to mount 0805
C94
R117 EV@0_8
C140
+0.95V
C132
1U/6.3V_4X
C115
1U/6.3V_4X
C85
C107
180P/50V_4N
C147
1U/6.3V_4X
C151
1U/6.3V_4X
C79
10U/6.3V_6X
C149
1U/6.3V_4X
C113
1U/6.3V_4X
C39
1U/6.3V_4X
C41
1U/6.3V_4X
C181
1U/6.3V_4X
C155
180P/50V_4N
C169
1U/6.3V_4X
C90
1U/6.3V_4X
+VDDIO_3V
EV@10U/6.3V_6X
+VDD_095_GPP
C174
C658
10U/6.3V_6X
C659
10U/6.3V_6X
1U/6.3V_4X
C178
1U/6.3V_4X
AAA-BAT-054-K01
A A
+3V_S5
+APU_3V_S
+VDD_095_USB3_S
+VDD_095_PHY_S
R488 0_8
C184
1U/6.3V_4X
C176
1U/6.3V_4X
C651
180P/50V_4N
C186
1U/6.3V_4X
C654
1U/6.3V_4X
C197
1U/6.3V_4X
C661
10U/6.3V_6X
C667
10U/6.3V_6X
C105
*10U/6.3V_6X
RevB 1219 Change from short pad to mount 0805
5
4
3
C126
1U/6.3V_4X
C117
1U/6.3V_4X
+VDDNB_CORE
C34
1U/6.3V_4X
C33
180P/50V_4N
C183
1U/6.3V_4X
C163
1U/6.3V_4X
RevB 1219 Change for EODRevB 1219 Change for EOD
+VDD_CORE
C110
1U/6.3V_4X
C170
1U/6.3V_4X
L1
HCB1608KF-181T15_1.5A
C40
1U/6.3V_4X
R473 0_8
C182
180P/50V_4N
C154
1U/6.3V_4X
C156
1U/6.3V_4X
+1.8V
+3V
L29
HCB1608KF-181T15_1.5A
L28
HCB1608KF-181T15_1.5A
C158
1U/6.3V_4X
C172
1U/6.3V_4X
C173
1U/6.3V_4X
2
A8
A13
A23
A31
A35
A39
B8
B13
B23
B31
B39
C1
C2
C5
C7
C9
C11
C13
C15
C17
C19
C21
C23
C25
C27
C29
C31
C33
C35
C37
C39
C41
D9
D11
D13
E3
E4
E9
E11
E13
E27
E31
E35
E38
E39
G3
G7
G11
G13
G15
G17
G21
G25
G29
G35
G37
G39
G41
H11
H13
H23
H31
+0.95V
C157
1U/6.3V_4X
U22G
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
GND
FT3 REV 0.53
U22H
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
J3
J7
J8
J39
K11
K13
K17
K19
K21
K23
K25
K27
K29
K31
L3
L7
L8
L10
L11
L15
L19
L31
L39
L41
M1
M2
N3
N7
N15
N19
N25
N29
N31
N39
P1
P2
R3
R7
R15
R19
R25
R29
R39
R41
U1
U2
U3
U7
U8
U11
U15
U19
U25
U29
U31
U39
W3
W5
W11
W15
W19
W25
W29
W39
W41
AA11
AA15
AA19
AA25
AA29
AA39
AC3
AC7
AC11
AC15
AC19
AC25
AC29
AC31
AC39
AC41
AE25
AE29
AE32
AE39
AG3
AG5
AG10
AG11
AG13
AG15
AG19
AG25
AG29
AG31
AG39
AG41
AH1
AH2
AJ15
AJ17
AJ19
AJ23
AJ25
AJ29
AJ31
AJ32
AJ39
AL15
AL17
AL19
AL25
AL29
Y1
Y2
AA3
AA7
AA8
AE3
AE7
AJ3
AJ7
AL3
AL8
FT3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, December 27, 2012
Date: Sheet of
Thursday, December 27, 2012
Date: Sheet of
Thursday, December 27, 2012
PROJECT :
APU 4/6(POWER/GND/GND)
APU 4/6(POWER/GND/GND)
APU 4/6(POWER/GND/GND)
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
FT3 REV 0.53
1
GND
BD9
BD9
BD9
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSSBG_DAC
VSS_243
VSS_244
FT3
6 41
6 41
6 41
AL39
AL41
AM11
AM27
AM31
AN3
AN7
AN39
AP31
AR3
AR13
AR17
AR21
AR25
AR29
AR39
AR41
AU1
AU2
AU3
AU15
AU19
AU23
AU27
AU39
AV9
AW3
AW7
AW13
AW15
AW17
AW19
AW21
AW23
AW25
AW27
AW31
AW33
AW35
AW37
AW39
AW41
AY13
AY15
AY18
AY30
BA2
BA7
BA13
BA15
BA18
BA21
BA25
BA31
BA35
BA39
A15
AL31
AM29
A1A
A1A
A1A
5
4
3
2
1
+3V_S5
+3V_S5
To PCIE device
LAN, WLAN, Cardreader, GPU
APU_PCIE_RST#[22,26,28]
D D
D7 RB500V-40_100MA
RSMRST_GATE#[33]
C C
+3V_S5
+3V
B B
+3V_S5
RSMRST_GATE#
+1.8V_S5
R218 47K_4
+3V_S5
R508
10K_4
SYS_RST#
12
G3
*SHORT_PAD
R216 *1K_4
R215 *1K_4
R214 *1K_4
NEED TO CHANGE P/N
Debug Only
R189 10K_4
R188 10K_4
R472 10K_4
R203 10K_4
R202 ZRP@10K_4
APU_TEST2
APU_TEST1
APU_TEST0
PCIE_CLKREQ#_LAN
PCIE_CLKREQ#_W LAN
PCIE_CLKREQ#_GPU_R
CLK_REQ3 #
APU_ODD_EN
RevA 1025 Add 10K PU to +3V
R490 10K_4
R180 10K_4
R497 10K_4
R470 10K_4
R468 10K_4
R212 10K_4
R602 10K_4
PWR_BTN#
PCIE_W AKE#
USB_NORMA L_OC#
USB_SC_O C#
ODD_PRSNT#
ODD_MD#
USB_DB_O C#
21
RSMRST#
1U/6.3V_4X
R195 *15K_4
R194 *15K_4
R193 *15K_4
APU_PCIE_RST#
C280
U28
R210 E@0_4
C281
*E@0.1U/10V_4X
R498 *4.7K_4
2
4
1
3 5
*TC7SH08FU(F)
R496 0_4
RSMRST#_R
PCIE_CLKREQ#_GPU[13 ]
USB_NORMA L_OC#[23,33 ]
USB_SC_O C#[23,33]
ODD_PRSNT#[31]
USB_DB_O C#[23,33]
RevA 1025 Add USB_DB_OC#
CLK Source GPP_Clk
GFX_CLKP/N
GFX
GPP_CLK0P/N
Lan
GPP_CLK1P/N
WLan
RevB 1224 Add USB/B OC# Pin PU
D22
D2
2 1
2 1
<THM>
40 MIL
40 MIL
40 MIL40 MIL
C54 2.2U/6.3V_4X
VFAN1[33]
FANSIG1
*VPORT 060 3 220K-V05
+5V_FAN
*VPORT 060 3 220K-V05
+5V
FANPWR = 1.6*VSET
1
4
APE8872 M
5
U5
VIN2VO
/FON
VSET
40 MIL
40 MIL
40 MIL40 MIL
3
+5V_FAN
5
GND
6
GND
7
GND
8
GND
C49
2.2U/10V_6X
FANSIG1[33]
+3V
C53
0.01U/25V_4X
RevB 1222 Change for EOD
FAN Control
A A
C652 15 0P/50V_4N
PLTRST#[28,29,33]
C660 15 0P/50V_4N
DNBSWON#[33]
FCH_PWRGD[9]
PCIE_W AKE#[26,28]
EC_KBRST#[33]
EC_A20GATE[33]
EC_EXT_SCI #[3 3]
PCIE_CLKREQ#_LAN[26]
PCIE_CLKREQ#_W LAN[28]
HDaudio
interface
are
+3V_S5
Clk_Req GPIO
Clk_Req0
Clk_Req1
R422 *10K_4
FANSIG1
C589
*0.01U/25 V_4X
PLTRST#
R479 33_4
PCIE_RST#
R477 33_4
DNBSWON#
FCH_PWRGD
SYS_RST#[9]
SYS_RST#
PCIE_W AKE#
SLP_S3#[2 2,33]
SLP_S5#[33]
SLP_S3#
SLP_S5#
EC_KBRST#
EC_A20GATE
EC_EXT_SCI #
PCIE_CLKREQ#_LAN
PCIE_CLKREQ#_W LAN
R474 EV@0_4
R489 0_4
R469 0_4
R471 0_4
5 6
3
2
1
R462 *10KX8
C632
15P/50V_4C
USE GROUND GUARD FOR 32K_X1 AND 32K_X2
GPIO65Clk_ReqG
GPIO60
GPIO61
CN11
1
2
3
85205-03 00L
4
A_RST#
PCIE_RST#_ R
RSMRST#_R
R478 0_4
APU_TEST0
APU_TEST1
APU_TEST2
GEVENT23#
TP23
BOARD_ID5
PCIE_CLKREQ#_GPU_RPCIE_CLKREQ#_GPU
USB_NORMA L_OC#_RUSB_NORMA L_OC#
USB_SC_O C#_RUSB_SC_O C#
ODD_PRSNT#
USB_DB_O C#_RUSB_DB_O C#
74
8
9
10
R461 20M_4
41
2 3
Y4
32.768KHZ_10
Azalia
Local Temp
AY4
AY9
AY5
BA8
PWR_BTN#
AM19
AY7
AW11
AY3
BA5
AU13
AY10
AY6
AR23
AR31
AN5
AL7
AP15
AV13
BA9
BA10
AV15
AU29
AW29
AR27
AV27
CLK_REQ3 #
AY29
AY8
AW1
AV1
AY1
ACZ_BCLK_R
ACZ_SDOUT_R
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
ACZ_SDIN3
ACZ_SYNC_R
ACZ_RST#_R
AN2
AN1
AK2
AK1
AM1
AL2
AM2
AL1
AJ2
32K_X1
AJ1
32K_X2
AMD recomanded 15pF
C633
15P/50V_4C
<ADO>
ACZ_SDOUT_R
ACZ_SYNC_R
ACZ_BCLK_R
ACZ_RST#_R
ACZ_SDIN0
+5V_FAN
U22D
LPC_RST_L
PCIE_RST_L
RSMRST_L
PWR_BTN_L
PWR_GOOD
SYS_RESET_L/GEVENT19_L
WAKE_L/GEVENT8_L
SLP_S3_L
SLP_S5_L
+3V_S5
TEST0
+3V_S5
TEST1/TMS
+3V_S5
TEST2
+3V
KBRST_L
GA20IN/GEVENT0_L
LPC_PME_L/GEVENT3_L
LPC_SMI_L/GEVENT23_L
AC_PRES/IR_RX0/GEVENT16_L
IR_TX0/GEVENT21_L
IR_TX1/GEVENT6_L
IR_RX1/GEVENT20_L
IR_LED_L/LLB_L/GPIO184
CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60
CLK_REQ1_L/GPIO61
CLK_REQ2_L/GPIO62
CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63
CLK_REQG_L/GPIO65/OSCIN
USB_OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L
USB_OC1_L/TDI/GEVENT13_L
USB_OC2_L/TCK/GEVENT14_L
USB_OC3_L/TDO/GEVENT15_L
AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST_L
X32K_X1
X32K_X2
+3V_S5
+1.8V_S5
+1.8V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V
+3V_S5
+3V_S5
+3V_S5
+3V
+3V
+3V_S5
+3V
+3V_S5
+3V_S5
+3V_S5
ACPI/SD/AZ/GPIO/RTC/MISC
+3V
+3V
+3V_S5
FT3 REV 0.53
+3V_S5
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V_S5
+3V_S5
+3V
+3V
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V
+3V
+3V
+3V
SD_DATA0/GPIO77
SD_DATA1/GPIO78
SD_DATA2/GPIO79
SD_DATA3/GPIO80
+3V
+3V
+3V
DEVSLP[0]/GPIO55
+3V
+3V
DEVSLP[1]/GPIO59
+3V
+3V
+3V
+3V
+3V
+3V
BLINK/GEVENT18_L
GENINT1_L/GPIO32
GENINT2_L/GPIO33
FANOUT0/GPIO52
SD_PWR_CTRL
SD_CLK/GPIO73
SD_CMD/GPIO74
SD_CD/GPIO75
SD_WP/GPIO76
SD_LED/GPIO45
SCL0/GPIO43
SDA0/GPIO47
SCL1/GPIO227
SDA1/GPIO228
SPKR/GPIO66
GPIO174
GEVENT2_L
GEVENT4_L
GEVENT7_L
GEVENT10_L
GEVENT11_L
GEVENT17_L
GEVENT22_L
FANIN0/GPIO56
BA23
AY22
AY23
AY20
Without SD,
BA20
Left Unconnected.
BA22
AY21
AY24
BA24
AY25
AU25
SMB_RUN_CL K
AV25
SMB_RUN_DA T
AY11
SMB_LAN_ CLK
BA11
SMB_LAN_ DAT
AP27
GPIO49
AY28
BOARD_ID8
GPIO50
BA28
BOARD_ID3
GPIO51
AV23
AP21
APU_ODD_EN
GPIO57
BA26
BOARD_ID4
GPIO58
AV19
BOARD_ID9
AY27
GPIO64
BA27
PCBEEP
AU21
GPIO68
AY26
BOARD_ID6
GPIO69
AV21
BOARD_ID7
GPIO70
AM21
BOARD_ID1 0
GPIO71
BA3
BOARD_ID1 1
AV17
GEVENT2#
BA4
AR15
GEVENT7#
AP17
AP11
GEVENT11#
AN8
ODD_MD#
AU17
GEVENT18#
BA6
RevA 1023 ODD_MD# CRB assign GEVENT17
BA29
PASSW DCLR
AP23
AV31
BOARD_ID1
AU31
BOARD_ID2
AV11
RTCCLK
FT3
To Azalia
R159 33_4
R156 33_4
R158 33 _4
C235
R157 33_4
*22P/50V _4N
ACZ_SDOUT [27]
ACZ_SYNC [27]
ACZ_BITCLK [27]
ACZ_RST# [27]
ACZ_SDIN0 [27]
<THM>
+5V VIN +5VP CU
U32
2
Q28
1 3
*MMBT2222A _600MA
R531 *100K_4
R532
*100K_4
R533
*162K/F_4
1
1 OUT
2
1 IN-
3
VFAN1
3
1 IN+
GND42 IN+
*LM358
2 OUT
2 IN-
8
VCC
7
6
5
SMB_RUN_CL K [10 ,11]
SMB_RUN_DA T [10,1 1]
SMB_LAN_ CLK [24,28,32]
SMB_LAN_ DAT [24,28,32 ]
TP34
APU_ODD_EN [31]
PE_GPIO0 [22]
PCBEEP [27]
PE_GPIO1 [22]
GEVENT2# [9]
TP28
TP30
TP27
R200 0_4
Local Temp
R484 15 0_4
+3VPCU
R549
*IV@NTC_470 K_4
R546
*48.7K/F_ 4
ODD_MD# [31]
PE_PW RGD [33,40,41]
RTC_CLK [9,33]
<THM>
HYST=VCC for 10
degree Hys.
HYST=GND for 30
degree Hys.
R552
*EV@NTC_470 K_4
+3VPCU_HW _SD
C664
0.1U/16V_4Y
2
+3V
R548
*499K/F_4
R545
*499K/F_4
SMB_RUN_CL K
SMB_RUN_DA T
SMB_LAN_ CLK
SMB_LAN_ DAT
R481
10K_4
12
G2
*SHORT_PAD
BOARD_ID[1:11]
U26
5
VCC
4
HYST
G708T1U
34
Q30B
5
*2N7002K DW_115MA
6
Q30A
2
*2N7002K DW_115MA
1
+3V
R4932.2K_4
R4942.2K_4
+3V_S5
R4752.2K_4
R4762.2K_4
BOARD_ID[1:11] [8,27,32]
GPIONet I/O Power Well DOS
Function
I +3.3V
O
O +3.3V
GPIO64
GPIO68
DGPU_PWRGD
DGPU_RST#
PE_PWRGD
PE_GPIO0 "0->1"
PE_GPIO1
Rset(Kohm)=0.0012T*T-0.9308T+96.147
R513 EV@2 4.9K/F_4
1
R507 IV@24.9K/F_4
SET
2
GND
3
S5_ON
R556
*IV@1M_4
OT#
R553
*EV@1M_4
R511 *470K_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Docu ment Number Rev
Size Docu ment Number Rev
Size Docu ment Number Rev
Date: S heet of
Tuesday, December 25, 2012
Date: S heet of
Tuesday, December 25, 2012
Date: S heet of
Tuesday, December 25, 2012
PROJECT :
APU 5/6(ACPI/SD/AZ/GPIO/RTC/MISC)
APU 5/6(ACPI/SD/AZ/GPIO/RTC/MISC)
APU 5/6(ACPI/SD/AZ/GPIO/RTC/MISC)
1
+3.3V
+3VPCU
"0->1"GPIO33
"0->1"DGPU_PWREN
S5_ON [13,3 3,35]
BD9
BD9
BD9
7 41
7 41
7 41
07
A1A
A1A
A1A
5
SATA_TXP0[31]
SATA HDD
SATA ODD
D D
CLK_PCIE_VGAP[12]
Reference GND
Do not change layer
and cross plane
CLK_PCIE_VGAN[12]
CLK_PCIE_LANP[26]
CLK_PCIE_LANN[26]
CLK_PCIE_WLANP[28]
CLK_PCIE_WLANN[28]
SATA_TXN0[31]
SATA_RXN0[31]
SATA_RXP0[31]
SATA_TXP1[31]
SATA_TXN1[31]
SATA_RXN1[31]
SATA_RXP1[31]
+0.95V
RP1 0X2
RP2 0X2
RP3 0X2
C627 15P/50V_4C
RevB 1222 Change cap value for vendor suggestion
PCLK_DEBUG[28]
PCLK_591[ 33]
C C
For EMI
PCLK_DEBUG
PCLK_591
C251 * 15P/50V_4C
C248 * 15P/50V_4C
LPC_CLK0[9]
LPC_CLK1[9]
LFRAME#[9,28,33]
SERIRQ[33] FCH_SPI_SO[33]
CLKRUN#[33]
LPCPD#[33]
C623 15P/50V_4C
LPC_CLK0
LPC_CLK1
LAD0[28,33]
LAD1[28,33]
LAD2[28,33]
LAD3[28,33]
LAD0
LAD1
LAD2
LAD3
LFRAME#
SERIRQ
CLKRUN#
LPCPD#
R170 1K/F_4
R169 1K/F_4
TP41
241
241
241
Y3
48MHZ_15
R178 0_4
R164 22_4
R172 22_4
R167 22_4
R495 10K_4
+3V_S5
4
Integrated Clock Mode:
Leave unconnected.
INT_CLK_PCIE_VGAPCLK_PCIE_VGAP
3
INT_CLK_PCIE_VGANCLK_PCIE_VGAN
INT_CLK_PCIE_LANPCLK_PCIE_LANP
3
INT_CLK_PCIE_LANNCLK_PCIE_LANN
INT_CLK_PCIE_WLANPCLK_PCIE_WLANP
3
INT_CLK_PCIE_WLANNCLK_PCIE_WLANN
Integrated Clock Mode:
Leave unconnected.
Cardreader pass through PCIE
Leave unconnected.
2
R457
1M_4
1 3
4
TP25
SATA_CALRN
SATA_CALRP
SATA_LED#
48M_X1
48M_X2
LPC_CLK0_R
LPC_CLK1_R
U22E
BA14
SATA_TX0P
AY14
SATA_TX0N
BA16
SATA_RX0N
AY16
SATA_RX0P
AY19
SATA_TX1P
BA19
SATA_TX1N
AY17
SATA_RX1N
BA17
SATA_RX1P
AR19
SATA_ZVSS
AP19
SATA_ZVDD_095
BA30
SATA_ACT_L/GPIO67
AY12
SATA_X1
BA12
SATA_X2
U4
GFX_CLKP
U5
GFX_CLKN
AC8
GPP_CLK0P
AC10
GPP_CLK0N
AE4
GPP_CLK1P
AE5
GPP_CLK1N
AC4
GPP_CLK2P
AC5
GPP_CLK2N
AA5
GPP_CLK3P
AA4
GPP_CLK3N
AP13
X14M_25M_48M_OSC
N2
X48M_X1
N1
X48M_X2
AY2
LPCCLK0
AW2
LPCCLK1
AT2
+3V_S5
LAD0
AT1
+3V_S5
LAD1
AR2
+3V_S5
LAD2
AR1
+3V_S5
LAD3
AP2
LFRAME_L
AP1
LDRQ0_L
AV29
SERIRQ/GPIO48
AP25
LPC_CLKRUN_L
AV2
LPC_PD_L/GEVENT5_L/SPI_TPM_CS_L
+3V
+3V
+3V_S5
+3V_S5
+3V
+3V
+3V
CLK/SATA/USB/SPI/LPC
+3V_S5
FT3 REV 0.53
USBCLK/14M_25M_48M_OSC
USB_SS_ZVDD_095_USB3_DUAL
+3V
+3V
+3V
+3V_S5
+3V_S5
+3V_S5
+3V_S5
USB_ZVSS
USB_HSD0P
USB_HSD0N
USB_HSD1P
USB_HSD1N
USB_HSD2P
USB_HSD2N
USB_HSD3P
USB_HSD3N
USB_HSD4P
USB_HSD4N
USB_HSD5P
USB_HSD5N
USB_HSD6P
USB_HSD6N
USB_HSD7P
USB_HSD7N
USB_HSD8P
USB_HSD8N
USB_HSD9P
USB_HSD9N
USB_SS_ZVSS
USB_SS_0TXP
USB_SS_0TXN
USB_SS_0RXP
USB_SS_0RXN
USB_SS_1TXP
USB_SS_1TXN
USB_SS_1RXP
USB_SS_1RXN
SPI_CLK/GPIO162
SPI_CS1_L/GPIO165
SPI_CS2_L/GPIO166
SPI_DO/GPIO163
SPI_DI/GPIO164
SPI_HOLD_L/GEVENT9_L
SPI_WP_L/GPIO161
3
W4
AG4
USB_ZVSS
AL4
USBP0+
AL5
USBP0-
AJ4
USBP1+
AJ5
USBP1-
AG7
RevA 1023 Add USBP1 for BD9
AG8
AG1
AG2
AF1
USBP4+
AF2
USBP4-
AE1
USBP5+
AE2
USBP5-
AD1
USBP6+_CCD
AD2
USBP6-_CCD
AC1
USBP7+
AC2
USBP7-
AB1
USBP8+
AB2
USBP8-
AA1
USBP9+
AA2
USBP9-
AE10
USBSS_CALRN
AE8
USBSS_CALRP
T2
USB3_TXP0
T1
USB3_TXN0
V2
USB3_RXP0
V1
USB3_RXN0
R1
USB3_TXP1
R2
USB3_TXN1
W1
USB3_RXP1
W2
USB3_RXN1
AU7
FCH_SPI_CLK_R
FCH_SPI_CS0#_R
FCH_SPI_SO_R
double check
R190 33_4
R197 0_4
R199 0_4
AW9
AR4
AR11
AR7
AU11
AU9
FT3
TP17
R131 11. 8K/F_6
USBP0+ [23]
USBP0- [23]
USBP1+ [23]
USBP1- [23]
USBP4+ [25]
USBP4- [25]
USBP5+ [29]
USBP5- [29]
USBP6+_CCD [30]
USBP6-_CCD [30]
USBP7+ [28]
USBP7- [28]
USBP8+ [23]
USBP8- [23]
USBP9+ [23]
USBP9- [23]
R124 1K/F_4
R125 1K/F_4
USB3_TXP0 [23]
USB3_TXN0 [23]
USB3_RXP0 [23]
USB3_RXN0 [23]
USB3_TXP1 [23]
USB3_TXN1 [23]
USB3_RXP1 [23]
USB3_RXN1 [23]
FCH_SPI_CLK
FCH_SPI_CS0#
FCH_SPI_SO
FCH_SPI_SI
SPI_HOLD#
FCH_SPI_WP
To USB 2.0 Daughter/B
To USB 2.0 Daughter/B
Touch Screen
Card Reader
CCD on LVDS
WLAN
USB3.0/2.0 S&C
USB2.0/3.0 w/o S&C
+0.95V_DUAL
USB3.0 S&C
USB3.0 Port 2
TP26
2
1
08
HUB1
HUB2
HUB3
W25Q32BVSSIG:AKE391P0N00
W25Q64FVSSIQ:AKE3EFP0N07
R517 10K_4
U30
FCH_SPI_CS0#[33]
FCH_SPI_CLK[33]
FCH_SPI_SI[33]
FCH_SPI_CS0#
FCH_SPI_CLK
FCH_SPI_SO
FCH_SPI_SI SPI_HOLD#FCH_SPI_SI_R
R519 0_4
+3V_S5
R524 10K_4
FCH_SPI_WP
1
6
5
2
3
C687
*22P/50V_4N
RevB 1225 Change from 8M to 4M
CE#
VDD
SCK
SI
SO
HOLD#
WP#
VSS
W25Q32BVSSIG
8
7
4
+3V_S5
C684
0.1U/10V_4X
R520
10K_4
BOARD_ID[1:11][7,27,32]
BOARD ID SETTING
ID7
ID9ID8ID1 ID2Board ID ID3
ID10
ID11
ID12 ID13
H
H
L
H
L
H
L
H
L
4
ID5
ID6
B B
RevB 1221 Modify Board ID
Always PU
Always PU
RevC 0130 Change Board ID setting
Reserve PD
A A
5
UMA SKU
PX SKU
VRAM 1GHz
VRAM 900M
USB3.0
USB2.0
14" MTN
17" BD9
W/O S&C
W S&C
N-METAL (W/O KBLED)
METAL (W/ KBLED)
N-Brand
Brand (ONKYO) L
W/O HDMI
W HDMI
N-Brand
Brand(Harman/Kardon)
Metal/IMR
TEXTURE
RSVD
RSVD
H
L
ID4
H
L
H
L
H
L
H
L
H
L
+3V
+3V_S5
BOARD_ID[1:11]
R165 UMA@10K_4
R163 *10K_4
R510 U3@10K_4
R491 *MTN@10K_4
R492 KBLED@10K_4
R187 N-Brand@10K_4
R509 NHM@10K_4
R198 10K_4
R186 Metal@10K_4
R487 *10K_4
R192 NS&C@10K_4
3
BOARD_ID1
R171 EV@10K_4
BOARD_ID2
R160 10K_4
BOARD_ID3
R501 U2@10K_4
BOARD_ID4
R485 BD9@10K_4
BOARD_ID6
R486 *NKBLED@10K_4
BOARD_ID7
R168 *ONKYO@10K_4
BOARD_ID8
R500 HM@10K_4
BOARD_ID9
R184 *10K_4
BOARD_ID10
R201 Texture@10K_4
BOARD_ID11
R480 10K_4
BOARD_ID5
R179 S&C@10K_4
RevC 0130 Change Board ID 9 for Harman-Kardon
Stuff R198, Remove R184
2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, January 30, 2013
Date: Sheet of
Wednesday, January 30, 2013
Date: Sheet of
Wednesday, January 30, 2013
PROJECT :
APU 6/7(CLK/SATA/USB/SPI)
APU 6/7(CLK/SATA/USB/SPI)
APU 6/7(CLK/SATA/USB/SPI)
1
BD9
BD9
BD9
8 41
8 41
8 41
A1A
A1A
A1A
5
4
3
2
1
STRAPS PINS
D D
+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5
R162
R217
R166
R182
*10K_4
LPC_CLK0[8]
LPC_CLK1[8]
LFRAME#[8,28,33]
RTC_CLK[7,33]
C C
B B
GEVENT2#[7]
LPC_CLK0
LPC_CLK1
LFRAME#
RTC_CLK
GEVENT2#
REQUIRED
STRAPS
PULL
HIGH
PULL
LOW
R183
2K/F_4
LPC_CLK0 LFRAME#
LPC_CLK1
Internal
BOOT
Fail Timer
ENABLE
BOOT
Fail Timer
DISABLE
DEFAULT
SPI
CLKGEN
ROM
ENABLED
DEFAULT DEFAULT DEFAULT
Internal
LPC
CLKGEN
ROM
DISABLED
10K_4
R173
*2K/F_4
RTC_CLK
Normal
Power Timing
ENABLE
Normal
Power Timing
DISABLE
10K_4
R161
*2K/F_4
10K_4
*2.2K_4
GEVENT2#
SPI
Voltage
1.8V
SPI
Voltage
3.3V
DEFAULT
R213
*10K_4
R191
2.2K_4
+1.8V_S5 +1.8V_S5
R512
1U/10V_6X
10K_4
C677
U27
2 4
3 5
R506 0_4
C674
*0.1U/10V_4X
R502 *0_4
*SN74LVC1G17DCKR
FCH_PWRGDVRM_PWRGD
FCH_PWRGD [7]
MPWROK
D29 *1SS355_100MA
D32 1SS355_100MAR196
D28 1SS355_100MA
D30 *1SS355_100MA
SYS_RST#[7]
VRM_PWRGD[38]
MPWROK[33]
MAINON[33,39]
PWRGD CIRCUIT
09
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
5
4
3
2
Tuesday, December 25, 2012
PROJECT :
APU 7/7(STRAP & PWRGD)
APU 7/7(STRAP & PWRGD)
APU 7/7(STRAP & PWRGD)
1
BD9
BD9
BD9
9 41
9 41
9 41
A1A
A1A
A1A
5
4
3
2
1
DDR_STD(DDR)
JDIM2A
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12/BC#
119
A13
80
A14
78
A15
109
BA0
108
BA1
79
BA2
114
S0#
121
S1#
101
CK0
103
CK0#
102
CK1
104
CK1#
73
CKE0
74
CKE1
115
CAS#
110
RAS#
113
WE#
197
SA0
201
SA1
202
SCL
200
SDA
116
ODT0
120
ODT1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
10
DQS#0
27
DQS#1
45
DQS#2
62
DQS#3
135
DQS#4
152
DQS#5
169
DQS#6
186
DQS#7
DDRSK-20401-TP8D
C72
1U/10V_4X
C261
*10U/6.3V_6X
PC2100 DDR3 SDRAM SO-DIMM
C91
1U/10V_4X
+1.5VSUS
4
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
C93
1U/10V_4X
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
(204P)
C137
1U/10V_4X
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
RevB 1219 Change for EOD
EMI Suggestion
C76
ESD@39P/50V_4N
C75
ESD@39P/50V_4N
C127
10U/6.3V_6X
+0.75V_VREF_CA
C123
10U/6.3V_6X
C51
ESD@39P/50V_4N
M_A_DQ[0..63]
M_A_DQ[0..63] [4,11]
+0.75V_VREF_DQ
+0.75V_VREF_CA
C5329 placed between JDIM1 and JDIM2
+1.5VSUS
R111
1K/F_4
R122 0_6
+0.75V_VREF_DQ
C13
0.1U/10V_4X
C52
ESD@39P/50V_4N
MEM_VREFCA_SUS
R112
1K/F_4
+APU_M_VREFDQ_SUS
C14
1000P/50V_4X
C74
ESD@39P/50V_4N
3
C70
ESD@39P/50V_4N
M_A_EVENT#[4,11]
M_A_RST#[4,11]
R123 *0_6
C150
0.47U/6.3V_4X
R21
1K/F_4
R20 *0_6
R23
1K/F_4
2.48A
+3V
C27 *E@0.1U/10V_4X
+SMDDR_VREF
+1.5VSUS
C83
ESD@39P/50V_4N
+1.5VSUS
DQ_OP-
DQ_OP+
C19
0.47U/6.3V_4X
+0.75V_VREF_CA
U2
4
-
3
+
C159
0.1U/10V_4X
2
JDIM2B
75
VDD1
76
VDD2
81
VDD3
82
VDD4
87
VDD5
88
VDD6
93
VDD7
94
VDD8
99
VDD9
100
VDD10
105
VDD11
106
VDD12
111
VDD13
112
VDD14
117
VDD15
118
VDD16
123
VDD17
124
VDD18
199
VDDSPD
77
NC1
122
NC2
125
NCTEST
198
EVENT#
30
RESET#
1
VREF_DQ
126
VREF_CA
2
VSS1
3
VSS2
8
VSS3
9
VSS4
13
VSS5
14
VSS6
19
VSS7
20
VSS8
25
VSS9
26
VSS10
31
VSS11
32
VSS12
37
VSS13
38
VSS14
43
VSS15
DDRSK-20401-TP8D
R27 *0_4
R30 *0_4
+3V_S5
2
*0.1U/10V_4X
V+
V-
*MCP6001RT-E/OT
5
C160
1000P/50V_4X
(204P)
PC2100 DDR3 SDRAM SO-DIMM
C18
1
OP_OUT
R19 0_6
44
VSS16
48
VSS17
49
VSS18
54
VSS19
55
VSS20
60
VSS21
61
VSS22
65
VSS23
66
VSS24
71
VSS25
72
VSS26
127
VSS27
128
VSS28
133
VSS29
134
VSS30
138
VSS31
139
VSS32
144
VSS33
145
VSS34
150
VSS35
151
VSS36
155
VSS37
156
VSS38
161
VSS39
162
VSS40
167
VSS41
168
VSS42
172
VSS43
173
VSS44
178
VSS45
179
VSS46
184
VSS47
185
VSS48
189
VSS49
190
VSS50
195
VSS51
196
VSS52
203
VTT1
204
VTT2
205
GND
206
GND
R18 *0_6
C22*0.1U/10V_4X
+SMDDR_VTERM
+APU_M_VREFDQ_SUS
R17
*0_4
+0.75V_VREF_DQ
R24 *0_6
C16
0.1U/10V_4X
R26
*10K_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
DDR3 DIMM-0
DDR3 DIMM-0
DDR3 DIMM-0
Tuesday, December 25, 2012
Tuesday, December 25, 2012
Tuesday, December 25, 2012
C17
0.1U/10V_4X
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
BD9
BD9
BD9
1
10
+SMDDR_VREF
10 41
10 41
10 41
A1A
A1A
A1A
C269
1U/6.3V_4X
M_A_A[15:0]
M_A_BS#[2:0]
M_A_CS#0[4]
M_A_CS#1[4]
M_A_CLKP0[4]
M_A_CLKN0[4]
M_A_CLKP1[4]
M_A_CLKN1[4]
M_A_CKE0[4]
M_A_CKE1[4]
M_A_CAS#[4,11]
M_A_RAS#[4,11]
M_A_WE#[4,11]
SMB_RUN_CLK[7,11]
SMB_RUN_DAT[7,11]
M_A_ODT0[4]
M_A_ODT1[4]
C88
10U/6.3V_6X
C263
1U/6.3V_4X
M_A_DM[7:0]
M_A_DQSP[7:0]
M_A_DQSN[7:0]
C102
10U/6.3V_6X
C264
1U/6.3V_4X
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_BS#0
M_A_BS#1
M_A_BS#2
M_A_CS#0
M_A_CS#1
M_A_CLKP0
M_A_CLKN0
M_A_CLKP1
M_A_CLKN1
M_A_CKE0
M_A_CKE1
M_A_CAS#
M_A_RAS#
M_A_WE#
DIMM0_SA0
DIMM0_SA1
SMB_RUN_CLK
SMB_RUN_DAT
M_A_ODT0
M_A_ODT1
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7
M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7
C87
10U/6.3V_6X
C270
1U/6.3V_4X
C61
*10U/6.3V_6X
C274
10U/6.3V_6X
M_A_A[15:0][4,11]
D D
M_A_BS#[2..0][4,11]
R499 10K_4
R504 10K_4
C C
B B
A A
Reserve ICT test point
+1.5VSUS
C78
C62
10U/6.3V_6X
10U/6.3V_6X
+3V
C238
2.2U/10V_6X
C242
0.1U/10V_4X
M_A_DM[7..0][4,11]
M_A_DQSP[7:0][4,11]
M_A_DQSN[7:0][4,11]
Place these Caps near So-Dimm0.
C119
10U/6.3V_6X
+SMDDR_VTERM
RevB 1222 Change for EOD
5
5
4
3
2
1
DDR_STD(DDR)
JDIM1A
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12/BC#
119
A13
80
A14
78
A15
109
BA0
108
BA1
79
BA2
114
S0#
121
S1#
101
CK0
103
CK0#
102
CK1
104
CK1#
73
CKE0
74
CKE1
115
CAS#
110
RAS#
113
WE#
197
SA0
201
SA1
202
SCL
200
SDA
116
ODT0
120
ODT1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
10
DQS#0
27
DQS#1
45
DQS#2
62
DQS#3
135
DQS#4
152
DQS#5
169
DQS#6
186
DQS#7
DDRSK-20401-TP4B
5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
(204P)
PC2100 DDR3 SDRAM SO-DIMM
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
M_A_DQ0
7
M_A_DQ1
15
M_A_DQ2
17
M_A_DQ3
4
M_A_DQ4
6
M_A_DQ5
16
M_A_DQ6
18
M_A_DQ7
21
M_A_DQ8
23
M_A_DQ9
33
M_A_DQ10
35
M_A_DQ11
22
M_A_DQ12
24
M_A_DQ13
34
M_A_DQ14
36
M_A_DQ15
39
M_A_DQ16
41
M_A_DQ17
51
M_A_DQ18
53
M_A_DQ19
40
M_A_DQ20
42
M_A_DQ21
50
M_A_DQ22
52
M_A_DQ23
57
M_A_DQ24
59
M_A_DQ25
67
M_A_DQ26
69
M_A_DQ27
56
M_A_DQ28
58
M_A_DQ29
68
M_A_DQ30
70
M_A_DQ31
129
M_A_DQ32
131
M_A_DQ33
141
M_A_DQ34
143
M_A_DQ35
130
M_A_DQ36
132
M_A_DQ37
140
M_A_DQ38
142
M_A_DQ39
147
M_A_DQ40
149
M_A_DQ41
157
M_A_DQ42
159
M_A_DQ43
146
M_A_DQ44
148
M_A_DQ45
158
M_A_DQ46
160
M_A_DQ47
163
M_A_DQ48
165
M_A_DQ49
175
M_A_DQ50
177
M_A_DQ51
164
M_A_DQ52
166
M_A_DQ53
174
M_A_DQ54
176
M_A_DQ55
181
M_A_DQ56
183
M_A_DQ57
191
M_A_DQ58
193
M_A_DQ59
180
M_A_DQ60
182
M_A_DQ61
192
M_A_DQ62
194
M_A_DQ63
M_A_DQ[0..63]
M_A_DQ[0..63] [4,10]
M_A_EVENT#[4,10]
M_A_RST#[4,10]
+0.75V_VREF_DQ
+0.75V_VREF_CA
2.48A
+3V
+1.5VSUS
JDIM1B
75
VDD1
76
VDD2
81
VDD3
82
VDD4
87
VDD5
88
VDD6
93
VDD7
94
VDD8
99
VDD9
100
VDD10
105
VDD11
106
VDD12
111
VDD13
112
VDD14
117
VDD15
118
VDD16
123
VDD17
124
VDD18
199
VDDSPD
77
NC1
122
NC2
125
NCTEST
198
EVENT#
30
RESET#
1
VREF_DQ
126
VREF_CA
2
VSS1
3
VSS2
8
VSS3
9
VSS4
13
VSS5
14
VSS6
19
VSS7
20
VSS8
25
VSS9
26
VSS10
31
VSS11
32
VSS12
37
VSS13
38
VSS14
43
VSS15
DDRSK-20401-TP4B
44
VSS16
48
VSS17
49
VSS18
54
VSS19
55
VSS20
60
VSS21
61
VSS22
65
VSS23
66
VSS24
71
VSS25
72
VSS26
127
VSS27
128
VSS28
133
VSS29
134
VSS30
138
VSS31
139
VSS32
144
VSS33
145
VSS34
150
VSS35
151
VSS36
155
VSS37
156
VSS38
161
VSS39
162
VSS40
167
VSS41
168
VSS42
172
VSS43
173
VSS44
178
VSS45
179
VSS46
184
VSS47
185
VSS48
189
VSS49
190
VSS50
195
VSS51
196
VSS52
(204P)
PC2100 DDR3 SDRAM SO-DIMM
VTT1
VTT2
GND
GND
203
204
205
206
+SMDDR_VTERM
11
M_A_CS#2[4]
M_A_CS#3[4]
M_A_CLKP2[4]
M_A_CLKN2[4]
M_A_CLKP3[4]
M_A_CLKN3[4]
M_A_CKE2[4]
M_A_CKE3[4]
M_A_CAS#[4,10]
M_A_RAS#[4,10]
M_A_WE#[4,10]
SMB_RUN_CLK[7,10]
SMB_RUN_DAT[7,10]
M_A_ODT2[4]
M_A_ODT3[4]
M_A_A[15:0]
M_A_BS#[2:0]
M_A_DM[7:0]
M_A_DQSP[7:0]
M_A_DQSN[7:0]
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_BS#0
M_A_BS#1
M_A_BS#2
M_A_CS#2
M_A_CS#3
M_A_CLKP2
M_A_CLKN2
M_A_CLKP3
M_A_CLKN3
M_A_CKE2
M_A_CKE3
M_A_CAS#
M_A_RAS#
M_A_WE#
DIMM1_SA0
DIMM1_SA1
SMB_RUN_CLK
SMB_RUN_DAT
M_A_ODT2
M_A_ODT3
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7
M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7
M_A_A[15:0][4,10]
D D
M_A_BS#[2..0][4,10]
R176 10K_4
+3V
R177 10K_4
C C
B B
Reserve ICT test point
M_A_DM[7..0][4,10]
M_A_DQSP[7:0][4,10]
M_A_DQSN[7:0][4,10]
+1.5VSUS
C106
10U/6.3V_6X
Place these Caps near So-Dimm0.
C98
10U/6.3V_6X
C60
10U/6.3V_6X
C64
10U/6.3V_6X
C77
10U/6.3V_6X
C96
10U/6.3V_6X
C80
*10U/6.3V_6X
C100
1U/10V_4X
C58
1U/10V_4X
C112
1U/10V_4X
C97
1U/10V_4X
C142
10U/6.3V_6X
C50
10U/6.3V_6X
+0.75V_VREF_DQ
C12
0.1U/10V_4X
C15
1000P/50V_4X
RevB 1219 Change for EOD
RevB 1219 Change for EOD
C108
ESD@39P/50V_4N
4
EMI Suggestion
C143
ESD@39P/50V_4N
C63
ESD@39P/50V_4N
C84
ESD@39P/50V_4N
C59
ESD@39P/50V_4N
3
C129
ESD@39P/50V_4N
C73
ESD@39P/50V_4N
+0.75V_VREF_CA
C167
0.1U/10V_4X
C161
1000P/50V_4X
2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
Tuesday, December 25, 2012
Date: Sheet of
Tuesday, December 25, 2012
PROJECT :
DDR3 DIMM-1
DDR3 DIMM-1
DDR3 DIMM-1
BD9
BD9
BD9
11 41
11 41
1
11 41
A1A
A1A
A1A
+3V
A A
C246
2.2U/10V_6X
C252
0.1U/10V_4X
+SMDDR_VTERM
C275
1U/6.3V_4X
C266
1U/6.3V_4X
C276
1U/6.3V_4X
C265
1U/6.3V_4X
C279
10U/6.3V_6X
+1.5VSUS
C262
*10U/6.3V_6X
RevB 1222 Change for EOD
5
<VGA>
PART 1 0F 9
U33A
12
PEG_TXP0[3]
PEG_TXN0[3]
PEG_TXP1[3]
PEG_TXN1[3]
PEG_TXP2[3]
PEG_TXN2[3]
PEG_TXP3[3]
PEG_TXN3[3]
CLK_PCIE_VGAP[8]
CLK_PCIE_VGAN[8]
R301 EV@10K_4
PERST#_BUF[22]
PERST#_BUF
R249 EV@0_4
C403
*E@0.1U/10V_4X
PEG_TXP0
PEG_TXN0
PEG_TXP1
PEG_TXN1
PEG_TXP2
PEG_TXN2
PEG_TXP3
PEG_TXN3
PERST#_BUF_R
AA38
W36
W38
M37
M35
G36
G38
AB35
AA36
AH16
AA30
Y37
Y35
V37
V35
U36
U38
T37
T35
R36
R38
P37
P35
N36
N38
L36
L38
K37
K35
H37
H35
F37
F35
E37
J36
J38
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
NC_PCIE_RX8P
NC_PCIE_RX8N
NC_PCIE_RX9P
NC_PCIE_RX9N
NC_PCIE_RX10P
NC_PCIE_RX10N
NC_PCIE_RX11P
NC_PCIE_RX11N
NC_PCIE_RX12P
NC_PCIE_RX12N
NC_PCIE_RX13P
NC_PCIE_RX13N
NC_PCIE_RX14P
NC_PCIE_RX14N
NC_PCIE_RX15P
NC_PCIE_RX15N
CLOCK
PCIE_REFCLKP
PCIE_REFCLKN
TEST_PG
PERSTB
PCI EXPRESS INTERFACE
EV@Mars_M2
PCIE_TX0P C329 EV@0.1U/10V_4X
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
NC_PCIE_TX8P
NC_PCIE_TX8N
NC_PCIE_TX9P
NC_PCIE_TX9N
NC_PCIE_TX10P
NC_PCIE_TX10N
NC_PCIE_TX11P
NC_PCIE_TX11N
NC_PCIE_TX12P
NC_PCIE_TX12N
NC_PCIE_TX13P
NC_PCIE_TX13N
NC_PCIE_TX14P
NC_PCIE_TX14N
NC_PCIE_TX15P
NC_PCIE_TX15N
CALIBRATION
PCIE_CALR_TX
PCIE_CALR_RX
Y33
Y32
W33
W32
U33
U32
U30
U29
T33
T32
T30
T29
P33
P32
P30
P29
N33
N32
N30
N29
L33
L32
L30
L29
K33
K32
J33
J32
K30
K29
H33
H32
Y30
Y29
CPEG_RXP0
CPEG_RXN0
CPEG_RXP1
CPEG_RXN1
CPEG_RXP2
CPEG_RXN2
CPEG_RXP3
CPEG_RXN3
C337 EV@0.1U/10V_4X
C327 EV@0.1U/10V_4X
C331 EV@0.1U/10V_4X
C321 EV@0.1U/10V_4X
C320 EV@0.1U/10V_4X
C322 EV@0.1U/10V_4X
C323 EV@0.1U/10V_4X
R251 *EV@1.27K/F_4
R250 EV@1.69K/F_4
R265 EV@1K/F_4
+5VRUN/+3VRUN/VDDR3
RUNPWROK
MVDDQ/VDDC/VDDCI
1.8V_IO/PCIE_VDDC
PWRGOOD
PCIE_RST#(PERSTB)
PCIE Clock
+0.95V_GPU
PEG_RXP0 [3]
PEG_RXN0 [3]
PEG_RXP1 [3]
PEG_RXN1 [3]
PEG_RXP2 [3]
PEG_RXN2 [3]
PEG_RXP3 [3]
PEG_RXN3 [3]
Mars Power-on sequence
1 => +3V_GPU
2 => +VDDC,+VDDCI,+1.5V_GPU,+0.95V_GPU
3 => +1.8V_GPU
PEG
Intel platform: Lane0 ~ Lane15
Brazos platform: Lane12 ~ Lane15
Comal and Sabine platform: Lane8 ~Lane15
Richland and Kabini platform: Lane0 ~ Lane7
Power Up Reset Sequence
20ms max
100ms min 100ms min
100us min
Asic in Reset Hardware Reset Sequence DFG Space Ready
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
100ms max
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Mars_M2/ PEG*8
Mars_M2/ PEG*8
Mars_M2/ PEG*8
BD9
BD9
BD9
A1A
A1A
A1A
12 41Tuesday, December 25, 2012
12 41Tuesday, December 25, 2012
12 41Tuesday, December 25, 2012
<VGA>
Q17A EV@2N7002KDW_115MA
3ND_MBCLK[24,33]
3ND_MBDATA[24,33]
S5_ON[7,33,35]
On Mars only HPD1 and GPIO_14_HPD2
are available for display hot-plug detection
+1.8V_GPU
6
2
5
3 4
Q17B EV@2N7002KDW_115MA
3
Q34
2
*ME2N7002E_200MA
1
+1.8V_GPU
R310
EV@499/F_4
R311
EV@249/F_4
1.8V@8mA
EV@BLM15BD121SN1D_300MAL8
on-die thermal sensor power
1
R312
EV@10K/F_4
+3V_GPU
R315
EV@10K/F_4
+3V_GPU
R573 EV@10K_4
GPIO_19_CTF
R577
*EV@100K_4
Place close to Chip
C448
EV@0.1U/10V_4X
PU:Disable MLPS
PD:Enable MLPS
C429
EV@10U/6.3V_6X
GENIL_CLK[15]
GENIL_VSYNC[15]
GPU_SMBCLK
1.8V GPIO
GPU_SMBDAT
Tempeature function: Connect to EC
R307 EV@4.7K_4
R292 EV@4.7K_4
GPU_GPIO0[15,40]
GPU_GPIO1[15]
GPU_GPIO2[15]
GPU_GPIO8[15]
GPU_GPIO9[15]
GPU_GPIO10[15]
GPU_GPIO11[15]
GPU_GPIO12[15]
GPU_GPIO13[15]
GFX_CORE_CNTRL1[40]
GFX_CORE_CNTRL5[40]
GFX_CORE_CNTRL2[40]
GPU_GPIO21[15]
GPU_GPIO22[15]
PCIE_CLKREQ#_GPU[7]
GFX_CORE_CNTRL3[40]
GFX_CORE_CNTRL4[40]
GPU_GENERICC[15]
GPU_VREFG
+3V_GPU
+3V_GPU
C428
EV@1U/6.3V_4X
GPU_SMBCLK
GPU_SMBDAT
GPU_SCL
GPU_SDA
T7
T6
T5
T26
T3
T8
T11
T23
R260 *EV@4.7K_4
R256 EV@1K_4
R255 *EV@5.11K/F_4
R290 *EV@10K/F_4
R291 EV@10K/F_4
TSVDD
C427
EV@0.1U/10V_4X
T29
T25
T28
T24
T27
T16
T18
AD29
AC29
AJ21
AK21
AW8
AW3
AW5
AW6
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12
AJ23
AH23
AK26
AJ26
AH20
AH18
AN16
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13
AG32
AG33
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24
AC30
AK24
AH13
AL21
AD28
AM23
AN23
AK23
AL24
AM24
AF29
AG29
AK32
AL31
AJ32
AJ33
AR8
AU8
AP8
AR3
AR1
AU1
AU3
AP6
AU5
AR6
AU6
AT7
AV7
AN7
AV9
AT9
PART 2 0F 9
MUTI GFX
GENLK_CLK
GENLK_VSYNC
SWAPLOCKA
SWAPLOCKB
NC_DVPCNTL_MVP_0
NC_DVPCNTL_MVP_1
DBG_CNTL0
NC_DVPCNTL_1
NC_DVPCNTL_2
NC_DVPCLK
DBG_DATA0
DBG_DATA1
DBG_DATA2
DBG_DATA3
DBG_DATA4
DBG_DATA5
DBG_DATA6
DBG_DATA7
DBG_DATA8
DBG_DATA9
DBG_DATA10
DBG_DATA11
DBG_DATA12
DBG_DATA13
DBG_DATA14
DBG_DATA15
DBG_DATA16
DBG_DATA17
DBG_DATA18
DBG_DATA19
DBG_DATA20
DBG_DATA21
DBG_DATA22
DBG_DATA23
SMBCLK
SMBus
SMBDATA
SCL
I2C
SDA
GENERAL PURPOSE I/O
GPIO_0
GPIO_1
GPIO_2
GPIO_5_AC_BATT
GPIO_6_TACH
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21
GPIO_22_ROMCSB
CLKREQB
GPIO_29
GPIO_30
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE
GENERICF
GENERICG
CEC_1
HPD1
DBG_VREFG
BACO
PX_EN
DEBUG
TESTEN
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
THERMAL
DPLUS
DMINUS
GPIO_28_FDO
TS_A
TSVDD
TSVSS
U33B
NC_TXCAP_DPA3P
NC_TXCAM_DPA3N
NC_TX0P_DPA2P
NC_TX0M_DPA2N
DPA
NC_TX1P_DPA1P
NC_TX1M_DPA1N
NC_TX2P_DPA0P
NC_TX2M_DPA0N
NC_TXCBP_DPB3P
NC_TXCBM_DPB3N
NC_TX3P_DPB2P
NC_TX3M_DPB2N
DPB
NC_TX4P_DPB1P
NC_TX4M_DPB1N
NC_TX5P_DPB0P
NC_TX5M_DPB0N
NC_TXCCP_DPC3P
NC_TXCCM_DPC3N
NC_TX0P_DPC2P
NC_TX0M_DPC2N
DPC
NC_TX1P_DPC1P
NC_TX1M_DPC1N
NC_TX2P_DPC0P
NC_TX2M_DPC0N
NC_TXCDP_DPD3P
NC_TXCDM_DPD3N
NC_TX3P_DPD2P
NC_TX3M_DPD2N
DPD
NC_TX4P_DPD1P
NC_TX4M_DPD1N
NC_TX5P_DPD0P
NC_TX5M_DPD0N
DAC1
MLPS
DDC/AUX
NC_DDCCLK_AUX3P
NC_DDCDATA_AUX3N
NC_DDCCLK_AUX4P
NC_DDCDATA_AUX4N
NC_DDCCLK_AUX5P
NC_DDCDATA_AUX5N
NC_DDCCLK_AUX6P
NC_DDCDATA_AUX6N
EV@Mars_M2
AVSSN#1
AVSSN#2
AVSSN#3
HSYNC
VSYNC
RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
NC_SVI2
NC_SVI2
NC_SVI2
NC_TSVSSQ
DDC1CLK
DDC1DATA
DDC2CLK
DDC2DATA
DDCVGACLK
DDCVGADATA
AU24
AV23
AT25
AR24
AU26
AV25
AT27
AR26
AR30
AT29
AV31
AU30
AR32
AT31
AT33
AU32
AU14
AV13
AT15
AR14
AU16
AV15
AT17
AR16
AU20
AT19
AT21
AR20
AU22
AV21
AT23
AR22
AD39
R
AD37
AE36
G
AD35
AF37
B
AE38
AC36
AC38
AB34
AD34
AE34
AC33
AC34
V13
NC#1
U13
NC#2
AC31
AD30
AC32
NC#5
AD32
AF32
NC#7
AA29
NC#8
AG21
NC#9
NC_TSVSSQ should be tied
to GND on Thames/Whistler/Seymour
AF33
PS_0 should be tied to GND on
Thames/Whistler/Seymour
AM34
PS_0
AD31
PS_1
AG31
PS_2
AD33
PS_3
PS_1,PS_2, PS_3 are NC on
Thames/Whistler/Seymour
AM26
AN26
AM27
AUX1P
AL27
AUX1N
AM19
AL19
AN20
AUX2P
AM20
AUX2N
AL30
AM30
AL29
AM29
AN21
AM21
AK30
AK29
AJ30
AJ31
T20
T22
T21
GPU_HSYNC [15]
GPU_VSYNC [15]
R252 EV@499/F_4
AVDD
VDD1DI
T2
T1
T13
T14
T15
T19
T17
T12
T4
PS_0
PS_1
PS_2
PS_3
PS_3 [15]
DAC1 Analog Power
AVDD
C715
Mars@0.1U/10V_4X
VDD1DI
C714
Mars@0.1U/10V_4X
Close to ASIC
11001 11000 00000 for Mars
PS_0 PS_1 PS_2
C420
*EV@0.1U/10V_4X
VDDC_CT VDDC_CT VDDC_CT
R285
EV@8.45K/F_4
R_pu
R286
R_pdCa
EV@2K/F_4
C412
*EV@0.1U/10V_4X
R_pu
R_pdCa
C716
Mars@1U/6.3V_4X
C713
Mars@1U/6.3V_4X
R266
*EV@8.45K/F_4
R267
EV@4.75K/F_4
1.8V@18mA
C717
Mars@4.7U/6.3V_6X
DAC1 Digital Power
1.8V@117mA
C712
Mars@4.7U/6.3V_6X
Mars@BLM15BD121SN1D_300MAL35
Mars@BLM15BD121SN1D_300MAL34
01000 for Sun
PS_2
C774
Mars@0.68U/6.3V_4X
RevB 1221 Add for Mars
System Memory Aperture size
PS0[3:1]
ROMIDCFG[2:0]
128M
256M
64M
000
001
010
011Reserved
MLPS
R_pu R_pd
4.75K
NC
2K
8.45K
2K
4.53K
4.99K
6.98K
4.99K
4.53K
5.62K
3.24K
3.4K
10K
NC
Ca Bits [5:4]
680nF
82nF
10nF
NC
00
01
10
11
Bits [3:1]
000
001
010
011
100
101
110
1114.75K
P/N
CH4681K9B00 X5R
CH4681JEB00 X6S
CH3823K1B00
CH31003KB11
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Mars_M2/ GPIO_DP_CRT_I2C
Mars_M2/ GPIO_DP_CRT_I2C
Mars_M2/ GPIO_DP_CRT_I2C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Ra P/N
2K
3.24K
3.4K
4.53K
4.75K
4.99K
5.62K
6.98K
8.45K
10K
MLPS Bit Bits [5:1]
PS_0
PS_1
PS_2
PS_3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
+1.8V_GPU
R_pu
R_pdCa
C419
EV@0.082U/16V_4X
CS22002FB19
CS23242FB09
CS23402FB08
CS24532FB08
CS24752FB12
CS24992FB26
CS25622FB18
CS26982FB01
CS28452FB12
CS31002FB26
11001
11000
01000
11XXX
BD9
BD9
BD9
13 41Wednesday, January 30, 2013
13 41Wednesday, January 30, 2013
13 41Wednesday, January 30, 2013
13
R283
*EV@10K/F_4
R284
EV@4.75K/F_4
A1A
A1A
A1A
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