How it Works
Quanta
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BD3G DABD3GMB6E0
Schematic
43 pgs1.63 Mb0

Quanta BD3G DABD3GMB6E0, Satellite A300D Schematic

5
BD3G BLOCK DIAGRAM
DDRII-SODIMM1
D D
DDRII-SODIMM2
CRT TV HDMI
C C
LVDS
MXM Module
PG 21
SATA - ODD
B B
Device IDSEL# REQ#/GNT# Interrupt
OZ129 AD17 REQ0# / GNT0# INTE#
E - SATA
NAND FLASH CARD
PCI ROUTING TABLE
PG 8,9
PG 8,9
S-VIDEO
SATA - HDD1
SATA - HDD2
HDMI
PG 19
LVDS
PG 20
PG 18
CRT
PG 18
PG 27
PG 27
PG 27
PG ??
PG ??
DDR II 667 MHZ
LVDS(2ch)
PCI-E X16
SATA0
SATA1
SATA4
SATA2
IDE /133
PCI Bus 33MHz
HT_LINK
HDMI
RX780/RS780M/RS780MC
A_LINK (X4)
4
AMD S1g2
Griffin Processor
(638 S1g2 socket)
21mm X 21mm, 528pin BGA
PG 4,5,6,7
PG 10,11,12,13
SB700
21mm X 21mm, 528pin BGA
4.5W(Ext)
4.3W(Int)
PG 14,15,16,17,18
LPC
CPU_CLK
NBGFX_CLK
NBGPP_CLK
SBLINK_CLK
PCI-E, 1X (port2)
PCI-E, 1X (port0)
USB2.0 (P3)
PCI-E, 1X (port1)
PCI-E, 1X (port3)
USB2.0 (P6)
SBSRC_CLK
USB2.0 (P2)
USB2.0 (P4)
USB2.0 (P5)
USB2.0 (P8)
Azalia
3
CLOCK GENERATOR
ICS9LPRS476AKLFT
SLG8SP628VTR
RTM880N-795
8040T(10/100)/8055(Giga)
RJ45
Mini Card (WLAN)
MINI CARD (HD Video Decoder)
NEW CARD
CCD
Fingerprint
Felica
Bluetooth
PG 28
PG 19
PG 28
PG 28
Azalia Audio Codec
PORT-A
PG 3
PG 24PG 24
PG 25
PG 25
PG 25
CX20561
HOST 200MHz
PCIE 100MHz
USB 48MHz
REF 14MHz
USB2.0 (P0)
USB2.0 (P1)
USB2.0 (P7)
PORT-B
2
CPU VDDNB_CORE
+1.35V_VDDHTTX
+SMDDR_VTERM
USB2.0 I/O Ports X1
(MB)
USB2.0 I/O Ports X1
(DB)
USB2.0 I/O Ports X1
(DB)
PG 22
Speaker Amplifier G1441R51U
PG 22
CPU_CORE1 CPU_CORE2
+NB_CORE
+2.5V
+1.5V
+1.2V
+1.1V_NB
+1.2V_S5
+1.8VSUS +1.8V
+3VPCU +3V_S5 +3VSUS +3V +5VPCU +5V
PG 28
PG 28
PG 28
MDC CONN
PG 23
CPU CORE
NB CORE
(1.0~1.2V)
+2.5V
+1.5V
+1.2V
+1.8VSUS SMDDR VTERM
3V/5V
FM Radio
PCB STACK UP
PG 34
LAYER 1 : TOP LAYER 2 : GND
PG 35
LAYER 3 : IN1 LAYER 4 : IN2 LAYER 5 : VCC LAYER 6 : BOT
Daughter Board
PG 37
MMB Board
USB Board
PG 36
Touch Pad board
Touch Pad board (with Fingerprinter)
PG 33
PG 23
1
O2Micro OZ129T
A A
PG 26
EC
WPCE775
PG 29
H.P/ SPDIF
PG 23
MIC JACK
PG 23
INT. MIC
PG 23
INT. S.P.
PG 22
MDC Board
RJ11
SPI
PROJECT : BD3G
PROJECT : BD3G
Quanta Computer Inc.
Quanta Computer Inc.
of
of
1
of
2A
2A
2A
IEEE1394 CN.
5
Card Reader
PG 26 PG 26
VR
PG 23
FAN
PG 6
4
Keyboard
PG 30
Flash ROM
Touch Pad
PG 29 PG 28
CIR
PG 28
Kill SW
PG 30
3
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
Date: Sheet
Date: Sheet
2
Date: Sheet
5
4
3
2
1
BD3G Power On Sequence
From AC,Battery VIN
D D
From PWM
From Power Button
From EC
+5VPCU +3VPCU
SYS_HWPG(PCU)
NBSWON#
S5_ON
+5V_S5
+3V_S5
From EC
From EC
From SB
From SB to EC
From EC
+1.2V_S5
RSMRST#
DNBSWON#
PCIE_WAKE#
SUSB#,SUSC#
SUSON
>10ms
>100ms
SUSON
+3VSUS +1.8VSUS SMDDR_VREF SMDDR_VTERM
From PWM
C C
From EC
HWPG_1.8V (SUS)
MAINON
MAINON
+5V +3V +2.5V +1.8V +1.5V +NB_CORE +1.1V_NB +1.35V_VDDHTTX
From PWM
From EC
HWPG_1.5V,HWPG_2.5V,GFXPG(MAIN) HWPG_1.2_NB
VRON
CPU_CORE0, CPU_CORE1, CPU VDDNB_CORE, +1.2V
From PWM
VRM_PWRGD (CPU)
HWPG
From EC
From SB
From SB
From SB
B B
From SB
ECPWROK
SB_PWRGD
NB_PWRGD
CPU_PWRGD
PLTRST# PCIRST#
CPU_LDT_RST#
CPU_LDT_STOP#
0ns~30ns
99ms~108ms
Items Function BTO Name Description
CIR
1
HDMI port
2
HDMI transmitter
3
HDMI-CEC
4
Discrete VGA
5
UMA
6
New Card
7
RJ11
8
RJ45-10/100
9
RJ45-1000
10
Option for RJ45-10/100 and RJ45-1000
11
TV
12
Cardbus
13
FM transmitter
14
Mainstream ID LED
15
Low cost ID LED
16
CCD
17
INT MIC
18
AMD Hyper Flash
19
North bridge(690MC/RS780MC)
20
North bridge(RX780)
21
PowerXpress
22
PowerXpress with UMA SKU
23
PowerXpress with Discrete VGA SKU
24
Power player/Power Shift
25
BOM naming rule
v
v
v
v
v
v
v
v
v
CIR@
HDM@
SI@
Silicon image SiI 1392/1932
CEC@
Renesas R8C/1B
EV@
External VGA stuff
IV@
Internal VGA stuff
NEW@
MD@
Modem
40@
Marvell 8040T(10/100)
55@
Marvell 8055(Giga)
40@55@
Option for 8040/8055
TV@
CB@
FM@
MID@
LID@
CCD@
I_MIC@
HF@
Only for AMD platform
MC@
Only for AMD platform
RX@
Only for AMD platform
PX@
Only for AMD platform
PX@IV@
Only for AMD platform
Only for AMD platform
PX@EV@
PP@
Only for AMD platform
*Note: EC will sampling SUSB# & SUSC# every 5ms.
AMD SB700 SMBUS Table
SB700 SDATA0/SCLK0(+3V)
A A
SB700 SDATA1/SCLK1(+3V_S5)
SB700 SDATA2/SCLK2(+3V_S5)
Power
Reserve MOS ckt
5
CLK GEN RAM Mini Card (HD-Decoder) Mini-card(WL) New Card HDMI
V
VVVV
V
+3V +3V +3V (Atheros) +3V +3V_S5
+3V
VVVVV V
4
EC775 SDATA1/SCLK1(+3VPCU)
EC775 SDATA2/SCLK2(+3VPCU)
EC775 SDATA3/SCLK3(+3VPCU)
EC775 SDATA4/SCLK4(+3VPCU)
Power
Reserve MOS ckt
3
Battery CPU thermal Sensor EC EEPROM VGA thermal Sensor Touch Sensor HDMI CEC
V
+3VPCU +3V +3VPCU +3V +3VPCU +5VPCU
XX XVVV
EC SMBUS Table
VV
2
VVV
PROJECT : BD3G
PROJECT : BD3G
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Quanta Computer Inc.
SYSTEM INFORMATION
SYSTEM INFORMATION
SYSTEM INFORMATION
1
2A
2A
2A
2 42Thursday, May 29, 2008
2 42Thursday, May 29, 2008
2 42Thursday, May 29, 2008
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5
4
3
2
1
CLK_GEN_SLG8SP628
+3V +3V_CLK_VDD +1.2V +1.2V_CLK_VDDIO
L22
L22
BK1608HS600
BK1608HS600
D D
L21
L21
BK1608HS600
BK1608HS600
10/25 modify it
C C
R498
R498
*10K_4
*10K_4
CLKREQ4#
R300
R300
*10K_4
*10K_4
CLKREQ2#
B:(10/25) Add WLAN & LAN CLKREQ circuit (BOI request)
B B
+3V
Q39Q39
*RHU002N06 *RHU002N06
2
+3V
*RHU002N06 *RHU002N06
2
3
Q30Q30
3
CLKREQ_LAN# 24
CLKREQ_WLAN# 25
1
1
12/8 change from 20p to 33p
+3V_CLK_VDD
R148 8.2K_4 R148 8.2K_4 R146 8.2K_4 R146 8.2K_4
NEW_CLKREQ# CLK_PD#
New Card CLKREQ#
RX780 RS780CLOCKS name
NBGFX_CLKP NBGFX_CLKN
MXM_REFCLKP MXM_REFCLKN
A A
NBGPP_CLKP NBGPP_CLKN
SBLINK_CLKP SBLINK_CLKN
RP1001 STUFF
RP66 STUFF to M82-S external reference clock -RX780 only
RP1001 STUFF
RP66 NC
RP1005 STUFF RP1005 NC
RP1003 STUFF RP1003 STUFF
5
to NB for VGA reference clock
to NB for RX780 for PCIEX2 interface reference clock only RS780 is internal share with AC-LINK clock,RS780 not need
to NB for AC-LINK reference clock
C242
C242
10u/10V_8
10u/10V_8
+3V_CLK_48
C220
C220
0.1u/10V_4
0.1u/10V_4
NEW_CLKREQ# 25
Clock pin function
C236
C236
C233
C233
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
+3V_CLK_VDD+3V
+1.2V_CLK_VDDIO
7,8,14,25 PCLK_SMB
PDAT_SMB 7,8,14,25
NEW_CLKREQ#
C225 33p/50V_4 C225 33p/50V_4
1 2
C223 33p/50V_4 C223 33p/50V_4
1 2
T25 T25
T33 T33
C219
C219
0.1u/10V_4
0.1u/10V_4
CG_XIN CG_XOUT
CLK_PD#
CLKREQ2#
CLKREQ4#
21
Y1Y1
14.318MHZ 14.318MHZ
C232
C232
C535
C535
C218
0.1u/10V_4
0.1u/10V_4
C218
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
ICS9LPRS480 P/N : ALPRS480000
CG_XIN
CG_XOUT
4
SLG8SP628
RTM880N-796
U2
U2
4
VDDDOT
16
VDDSRC
26
VDDATIG
35
VDDSB_SRC
40
VDDSATA
48
VDDCPU
55
VDDHTT
56
VDDREF
63
VDD48
11
VDDSRC_IO0
17
VDDSRC_IO1
25
VDDATIG_IO
34
VDDSB_SRC_IO
47
VDDCPU_IO
1
GND48
7
GNDDOT
10
GNDSRC0
18
GNDSRC1
24
GNDATIG
33
GNDSB_SRC
43
GNDSATA
46
GNDCPU
52
GNDHTT
60
GNDREF
61
X1
62
X2
2
SMBCLK
3
SMBDAT
51
PD#
23
CLKREQ0#
45
CLKREQ1#
44
CLKREQ2#
39
CLKREQ3#
38
CLKREQ4#
SLG8SP628
SLG8SP628
P/N : AL8SP628000
P/N : AL000880000
QFN64
QFN64
TGND065TGND166TGND267TGND368TGND469TGND570TGND671TGND772TGND873TGND9
+3V_CLK_VDD
C231
C231
C235
C235
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
CPUCLKP_R
50
CPUK8_0T CPUK8_0C
ATIG0T ATIG0C ATIG1T ATIG1C
SB_SRC0T SB_SRC0C SB_SRC1T SB_SRC1C
SRC0T SRC0C SRC1T SRC1C SRC2T SRC2C SRC3T SRC3C SRC4T SRC4C
SRC6T/SATAT
SRC6C/SATAC SRC7T/27M_SS SRC7C/27M_NS
HTT0T/66M
HTT0C/66M
48MHz_0
REF0/SEL_HTT66
REF1/SEL_SATA
REF2/SEL_27
74
10/17 Add 10p for EMI issue (Suggestion by Seligo)
R442R442
8.2K_4 8.2K_4
R136R136
R445R445
*8.2K_4 *8.2K_4
8.2K_4 8.2K_4
CPUCLKN_R
49
NBGFX_CLKP_R NBGFX_CLKP
30
NBGFX_CLKN_R
29
MXM_REFCLKP _R
28
MXM_REFCLKN_R
27
SBLINK_CLKP_R
37
SBLINK_CLKN_R
36
SBSRC_CLKP_R
32
SBSRC_CLKN_R
31
NBGPP_CLKP_R
22
NBGPP_CLKN_R
21
CLK_PCIE_NEW_R
20
CLK_PCIE_NEW#_R
19
CLK_PCIE_MINI_R
15
CLK_PCIE_MINI#_R
14
CLK_PCIE_MINI2_R
13
CLK_PCIE_MINI2#_R
12
CLK_PCIE_LAN_R
9
CLK_PCIE_LAN#_R
8
42 41 6 5
54 53
64
59 58 57
SEL_SATA SEL_HTT66 SEL_27
R443R443
8.2K_4 8.2K_4
T27 T27 T32 T32 T21 T21 T22 T22
NBHT_REFCLKP_R NBHT_REFCLKP NBHT_REFCLKN_R
CLK_48M_USB_R
SEL_HTT66 SEL_SATA
C201C201 *10p/50V_4 *10p/50V_4
3
Clock chip has internal serial terminations for differencial pairs, external resistors are reserved for debug purpose.
Place within 0.5" of CLKGEN
RP16 0X2RP16 0X2
1 3
RP15 0X2RP15 0X2
1 3
RP14 EV@0X2 RP14 EV@0X2
1 3
RP18 0X2RP18 0X2
1 3
RP17 0X2RP17 0X2
1 3
RP12 *0X2RP12 *0X2
1 3
RP11 NEW@0X2 RP11 NEW@0X2
1 3
RP2 0X2RP2 0X2
1 3
RP1 0X2RP1 0X2
1 3
RP3 0X2RP3 0X2
1 3
RP13 0X2RP13 0X2
1 3
R446 33_4R446 33_4
Ra
R141 158/F_4 R141 158/F_4 R138 90.9/F_4 R138 90.9/F_4
Rb
C541C541 *10p/50V_4 *10p/50V_4
RES CHIP 130 1/16W +-1%(0402)L-F -->CS11302FB15 RES CHIP 158 1/16W +-1%(0402) -->CS11582FB00 RES CHIP 90.9 1/16W +-1%(0402) -->CS09092FB15 RES CHIP 82.5 1/16W +-1%(0402) -->CS08252FB11
SEL_HTT66
SEL_SATA
SEL_27
L23
L23
BK1608HS600
BK1608HS600
R147
R147
*261/F_4
2 4
2 4 2 4
2 4 2 4
2 4 2 4 2 4 2 4 2 4
2 4
*261/F_4
NBGFX_CLKN MXM_REFCLKP MXM_REFCLKN
SBLINK_CLKP SBLINK_CLKN SBSRC_CLKP SBSRC_CLKN
CLK_PCIE_NEW CLK_PCIE_NEW# CLK_PCIE_WLAN CLK_PCIE_WLAN# CLK_PCIE_MINICARD CLK_PCIE_MINICARD# CLK_PCIE_LAN CLK_PCIE_LAN#
NBHT_REFCLKN
CLK_48M_USB
EXT_NB_OSCSEL_27
RS780RX780
1.1V
1.8V
82.5RRa
158R
90.9R
130RRb
66 MHz 3.3V single ended HTT clock
1
100 MHz differential HTT clock
* 0
100 MHz non-spreading differential SRC clock
1 *
100 MHz spreading differential SRC clock
0
27MHz and 27M SS outputs
1
0*
100 MHz SRC clock
* default
C221
C221
10u/10V_8
10u/10V_8
NBGPP_CLKP NBGPP_CLKN
C230
C230
C234
C234
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
CPUCLKP CPUCLKN
MXM_REFCLKP 21 MXM_REFCLKN 21
SBLINK_CLKP 11 SBLINK_CLKN 11 SBSRC_CLKP 13 SBSRC_CLKN 13
CLK_PCIE_NEW 25 CLK_PCIE_NEW# 25 CLK_PCIE_WLAN 25 CLK_PCIE_WLAN# 25 CLK_PCIE_MINICARD 25 CLK_PCIE_MINICARD# 25 CLK_PCIE_LAN 24 CLK_PCIE_LAN# 24
NBHT_REFCLKP 11 NBHT_REFCLKN 11
CLK_48M_USB 14
EXT_NB_OSC 11
2
C216
C216
C222
C222
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
CPUCLKP 4 CPUCLKN 4
NBGFX_CLKP 11 NBGFX_CLKN 11
To NB
To SB
NBGPP_CLKP 11 NBGPP_CLKN 11
To New Card
To Mini PCIE Slot
To Mini PCIE Slot
To LAN Controller
To NB
To SB
To NB
C217
C217
0.1u/10V_4
0.1u/10V_4
To CPU
RS780/RX780 for VGA
To NB
11/4 check RX781 , RX781 not use
RX780 only
To NB
NB CLOCK INPUT TABLE
NB CLOCKS
HT_REFCLKP
HT_REFCLKN
REFCLK_P
REFCLK_N
GFX_REFCLK
GPP_REFCLK
GPPSB_REFCLK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
RX780 RS780
100M DIFF
100M DIFF
14M SE (1.8V)
NC vref
100M DIFF
100M DIFF
100M DIFF
CLOCK GENERATOR_SLG8SP628
CLOCK GENERATOR_SLG8SP628
CLOCK GENERATOR_SLG8SP628
100M DIFF(IN/OUT)*
NC or 100M DIFF OUTPUT
PROJECT : BD3G
PROJECT : BD3G
Quanta Computer Inc.
Quanta Computer Inc.
1
100M DIFF
100M DIFF
14M SE (1.1V)
100M DIFF
03
3 42Thursday, May 29, 2008
3 42Thursday, May 29, 2008
3 42Thursday, May 29, 2008
of
of
of
1A
1A
1A
5
+1.2V +1.2V_VLDT
R469 0_8 R469 0_8
R467 0_8 R467 0_8
D D
HT_NB_CPU_CAD_H[15..0] 9
9 HT_NB_CPU_CAD_L[15..0]
9 HT_NB_CPU_CLK_H[1..0]
9 HT_NB_CPU_CLK_L[1..0]
9 HT_NB_CPU_CTL_H[1..0]
HT_NB_CPU_CTL_L[1..0] 9
9 HT_CPU_NB_CAD_H[15..0]
9 HT_CPU_NB_CAD_L[15..0]
9 HT_CPU_NB_CLK_H[1..0]
9 HT_CPU_NB_CLK_L[1..0]
9 HT_CPU_NB_CTL_H[1..0]
HT_CPU_NB_CTL_L[1..0] 9
C C
+3V
CPU_LDT_REQ#_CPU
C795C795
*100p/50V_4 *100p/50V_4
B B
+1.8VSUS
+1.8VSUS
+1.8VSUS
+1.8VSUS
CPU_PROCHOT_L#
+1.2V_VLDT
C583 4.7U/6.3V_6 C583 4.7U/6.3V_6 C582 4.7U/6.3V_6 C582 4.7U/6.3V_6 C581 0.22u/6.3V_4 C581 0.22u/6.3V_4 C580 180p/50V_4 C580 180p/50V_4
HT_NB_CPU_CAD_H[15..0]
HT_NB_CPU_CAD_L[15..0]
HT_NB_CPU_CLK_H[1..0]
HT_NB_CPU_CLK_L[1..0]
HT_NB_CPU_CTL_H[1..0]
HT_NB_CPU_CTL_L[1..0]
HT_CPU_NB_CAD_H[15..0]
HT_CPU_NB_CAD_L[15..0]
HT_CPU_NB_CLK_H[1..0]
HT_CPU_NB_CLK_L[1..0]
HT_CPU_NB_CTL_H[1..0]
HT_CPU_NB_CTL_L[1..0]
CNTR_VREF
R126 20K/F_4 R126 20K/F_4
C172 0.1u/10V_4 C172 0.1u/10V_4
R132 34.8K/F_4 R132 34.8K/F_4
2
Q19 *BSS138_NL/SOT23 Q19 *BSS138_NL/SOT23
3
1
R122 0_6 R122 0_6
*100p/50V_4 *100p/50V_4
CNTR_VREF
C796C796
2/4 reserve C795,C796 change R122 to 0 0603
R447 10K/F_4 R447 10K/F_4
CPU_MEMHOT_L#
R456 10K/F_4 R456 10K/F_4
R458 300_4 R458 300_4
1/31 leakage issue ,add R687, no stuff R686
2
Q35
Q35 MMBT3904
MMBT3904
13
2
Q36
Q36
1 3
MMBT3904
MMBT3904
R687 0_4 R687 0_4
HT_NB_CPU_CAD_H0 HT_NB_CPU_CAD_L0 HT_NB_CPU_CAD_H1 HT_NB_CPU_CAD_L1 HT_NB_CPU_CAD_H2 HT_NB_CPU_CAD_L2 HT_NB_CPU_CAD_H3 HT_NB_CPU_CAD_L3 HT_NB_CPU_CAD_H4 HT_NB_CPU_CAD_L4 HT_NB_CPU_CAD_H5 HT_NB_CPU_CAD_L5 HT_NB_CPU_CAD_H6 HT_NB_CPU_CAD_L6 HT_NB_CPU_CAD_H7 HT_NB_CPU_CAD_L7 HT_NB_CPU_CAD_H8 HT_NB_CPU_CAD_L8 HT_NB_CPU_CAD_H9 HT_NB_CPU_CAD_L9 HT_NB_CPU_CAD_H10 HT_NB_CPU_CAD_L10 HT_NB_CPU_CAD_H11 HT_NB_CPU_CAD_L11 HT_NB_CPU_CAD_H12 HT_NB_CPU_CAD_L12 HT_NB_CPU_CAD_H13 HT_NB_CPU_CAD_L13 HT_NB_CPU_CAD_H14 HT_NB_CPU_CAD_L14 HT_NB_CPU_CAD_H15 HT_NB_CPU_CAD_L15
HT_NB_CPU_CLK_H0 HT_NB_CPU_CLK_L0 HT_NB_CPU_CLK_H1 HT_NB_CPU_CLK_L1
HT_NB_CPU_CTL_H0 HT_NB_CPU_CTL_L0 HT_NB_CPU_CTL_H1 HT_NB_CPU_CTL_L1
CPU_LDT_REQ# 11
CPU_MEMHOT#
+3V
*10K_4
*10K_4
CPU_PROCHOT_SB# 13
+2.5V
CNTR_VREF
R686
R686
CPU_PROCHOT# 29
+1.2V_VLDT +1.2V_VLDT +1.2V_VLDT +1.2V_VLDT
CPU_MEMHOT# 8,14
BLM21PG221SN1D(220,100M,2A)_8
BLM21PG221SN1D(220,100M,2A)_8
L19
L19
LS0805-100M-N
C166
C166
10u/6.3V_8
10u/6.3V_8
U12A
U12A
D1
VLDT_A0
D2
VLDT_A1
D3
VLDT_A2
D4
VLDT_A3
E3
L0_CADIN_H0
E2
L0_CADIN_L0
E1
L0_CADIN_H1
F1
L0_CADIN_L1
G3
L0_CADIN_H2
G2
L0_CADIN_L2
G1
L0_CADIN_H3
H1
L0_CADIN_L3
J1
L0_CADIN_H4
K1
L0_CADIN_L4
L3
L0_CADIN_H5
L2
L0_CADIN_L5
L1
L0_CADIN_H6
M1
L0_CADIN_L6
N3
L0_CADIN_H7
N2
L0_CADIN_L7
E5
L0_CADIN_H8
F5
L0_CADIN_L8
F3
L0_CADIN_H9
F4
L0_CADIN_L9
G5
L0_CADIN_H10
H5
L0_CADIN_L10
H3
L0_CADIN_H11
H4
L0_CADIN_L11
K3
L0_CADIN_H12
K4
L0_CADIN_L12
L5
L0_CADIN_H13
M5
L0_CADIN_L13
M3
L0_CADIN_H14
M4
L0_CADIN_L14
N5
L0_CADIN_H15
P5
L0_CADIN_L15
J3
L0_CLKIN_H0
J2
L0_CLKIN_L0
J5
L0_CLKIN_H1
K5
L0_CLKIN_L1
N1
L0_CTLIN_H0
P1
L0_CTLIN_L0
P3
L0_CTLIN_H1
P4
L0_CTLIN_L1
SOCKET_638_PIN
SOCKET_638_PIN
R131
R131 0_4
0_4
CPU_LDT_RST#
12
G3G3 *SHORT_ PAD1 *SHORT_ PAD1
for debug only
+1.8VSUS
CPU FAN
SYSFANON# 21
A A
THER_SHD#
+3V +5V
1
Q46
Q46
R500
R500
ME2N7002D
ME2N7002D
*0_4
*0_4
5
+5V
C750
R504R504 *10K_4 *10K_4
2
3
C750
2.2u/6.3V_6
2.2u/6.3V_6
CPUFAN#_ON_R
VFAN 29
FANPWR = 1.6*VSET
G995/Pin1- internal pull high (+5V)
2
1
4
U17
U17
VIN VO
/FON
VSET
G995
G995
3 5
GND
6
GND
7
GND
8
GND
2/4 reserve D92,D93 for FAN
4
W/S= 15 mil/20mil
+CPUVDDA
C170C170
C167C167
C168
0.22u/6.3V_4 0.22u/6.3V_4
AE2 AE3 AE4 AE5
AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3
Y1 W1 Y4 Y3
R2 R3 T5 R5
+3V
R123
R123 1K/F_4
1K/F_4
CPU_LDT_RST_HTPA#
C168 3300p/50V_4
3300p/50V_4
+1.2V_VLDT +1.2V_VLDT +1.2V_VLDT +1.2V_VLDT
HT_CPU_NB_CAD_H0 HT_CPU_NB_CAD_L0 HT_CPU_NB_CAD_H1 HT_CPU_NB_CAD_L1 HT_CPU_NB_CAD_H2 HT_CPU_NB_CAD_L2 HT_CPU_NB_CAD_H3 HT_CPU_NB_CAD_L3 HT_CPU_NB_CAD_H4 HT_CPU_NB_CAD_L4 HT_CPU_NB_CAD_H5 HT_CPU_NB_CAD_L5 HT_CPU_NB_CAD_H6 HT_CPU_NB_CAD_L6 HT_CPU_NB_CAD_H7 HT_CPU_NB_CAD_L7 HT_CPU_NB_CAD_H8 HT_CPU_NB_CAD_L8 HT_CPU_NB_CAD_H9 HT_CPU_NB_CAD_L9 HT_CPU_NB_CAD_H10 HT_CPU_NB_CAD_L10 HT_CPU_NB_CAD_H11 HT_CPU_NB_CAD_L11 HT_CPU_NB_CAD_H12 HT_CPU_NB_CAD_L12 HT_CPU_NB_CAD_H13 HT_CPU_NB_CAD_L13 HT_CPU_NB_CAD_H14 HT_CPU_NB_CAD_L14 HT_CPU_NB_CAD_H15 HT_CPU_NB_CAD_L15
HT_CPU_NB_CLK_H0 HT_CPU_NB_CLK_L0 HT_CPU_NB_CLK_H1 HT_CPU_NB_CLK_L1
HT_CPU_NB_CTL_H0 HT_CPU_NB_CTL_L0 HT_CPU_NB_CTL_H1 HT_CPU_NB_CTL_L1
HT LINK
HT LINK
1
4.7U/6.3V_6 4.7U/6.3V_6
VLD T_B0 VLD T_B1 VLD T_B2 VLDT_B3
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H15 L0_CADOUT_L15
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
2
3
Q20
Q20 BSS138_NL/SOT23
BSS138_NL/SOT23
4/16 change CPU_LDT_RST# shot pad location to G3
+1.8VSUS
3
Q21
Q21
R135
CPU_COREPG 29,34
R454 300_4 R454 300_4
CPU_THERMTRIP_L#
TH_FAN_POWER
C753
C753
10u/10V_8
10u/10V_8
FANSIG 29
R508 0_6 R508 0_6
C752
C752
0.01u/16V_4
0.01u/16V_4
4
2
1
2
1 3
Q26
Q26
MMBT3904
MMBT3904
D9 2 *VPORT D92 *VPORT
D9 3 *VPORT D93 *VPORT
FDV301N
FDV301N
R140
R140 1K_4
1K_4
10/26 modify it
R144 *0_6 R144 *0_6
TH_FAN_POWER_R
2 1
2 1
R135
*10K_4
*10K_4
D3
*BAS316D3*BAS316
R139 100K_6 R139 100K_6
CPU_THERMTRIP# 14
SYS_SHDN# 33
+3V
R524
R524
10K_4
10K_4
CN35
CN35
1
4 2 3
5
PTI_CWY030-B0G1Z
PTI_CWY030-B0G1Z
FANSIG
TH_FAN_POWER_R
3
CPU CLK
CPUCLKP3 CPUCLKN3
Keep trace from resisor to CPU within 0.6" keep trace from caps to CPU within 1.2"
CPUCLKIN
C5724.7U/6.3V_6 C5724.7U/6.3V_6 C5730.22u/6.3V_4 C5730.22u/6.3V_4
CPUCLKP
C571 180p/50V_4 C571 180p/50V_4
CPUCLKN
CPUCLKP CPUCLKN
R133 169/F_4R133 169/F_4
C174 3900p/25V_4 C174 3900p/25V_4 C175 3900p/25V_4 C175 3900p/25V_4
SideBand Temp sense I2C
+1.2V_VLDT
34 CPU_VDD0_FB_L
34 CPU_VDD1_FB_H
+1.8VSUS
R453 300_4 R453 300_4
5/13 follow AMD design guide 1.03 stuff R675
10/9 AMD suggest remove MOS and connect directly
SB_SCLK3 14
SB_SDATA3 14
SB_SCLK3
SB_SDATA3
THERM_ALERT#_R
R462 1K/F_4 R462 1K/F_4 R459 1K/F_4 R459 1K/F_4
+1.8VSUS
CPU_SVC_R
R457 0_4 R457 0_4
CPU_SVD_R CPU_SVD
R461 0_4 R461 0_4R452 300_4 R452 300_4
CPU_PWRGD
R125 0_4 R125 0_4
R455 *220_4 R455 *220_4 R464 *220_4 R464 *220_4 R124 *220_4 R124 *220_4
CPU Thermal monitor
2ND_MBCLK 29
2ND_MBDATA 29
THERM_ALERT# 15
3
CPUCLKIN#
CPU_LDT_RST# 11,13
13 CPU_PWRGD
CPU_LDT_STOP# 11,13
R471 R470 44.2/F_4 R470 44.2/F_4
CPU_VDD0_FB_H 34
CPU_VDD1_FB_L 34
+1.8VSUS
R134 510/F_4 R134 510/F_4
R286 *0_4 R286 *0_4
R282 *0_4 R282 *0_4
3
3
+3V
10/30 change to G781
4/24 remove C762 to meet PWRGD timing spec
+CPUVDDA
CPU_LDT_RST# CPU_PWRGD CPU_LDT_STOP# CPU_LDT_REQ#_CPU
44.2/F_4 R471 44.2/F_4
place them to CPU within 1.5"
CPU_DBRDY CPU_TMS CPU_TCK CPU_TRST# CPU_TDI
T16 T16
R671*300_4 R671*300_4 R672*300_4 R672*300_4
R128 510/F_4 R128 510/F_4
R676 300_4 R676 300_4 R675 300_4 R675 300_4 R678 300_4 R678 300_4 R677*300_4 R677*300_4 R679*300_4 R679*300_4
R463 0_4 R463 0_4
3
*BSS138_NL/SOT23
*BSS138_NL/SOT23
W/S= 15 mil/20mil
+CPUVDDA +CPUVDDA
CPUCLKIN CPUCLKIN#
CPU_SIC CPU_SID CPU_ALERT
CPU_HTREF0 CPU_HTREF1
CPUTEST23
CPUTEST18 CPUTEST19
CPUTEST25H CPUTEST25L
CPUTEST21 CPUTEST20 CPUTEST24 CPUTEST22 CPUTEST12 CPUTEST27
CNTR_VREF
2
CPU_SIC
Q38
Q38
1
F8 F9
A9 A8
B7 A7
F10
C6
AF4 AF5 AE6
R6
P6
F6 E6
Y6
AB6
G10 AA9 AC9 AD9 AF9
AD7
H10
G9
E9 E8
AB8 AF7 AE7 AE8 AC8 AF8
C2
AA6
A3 A5 B3 B5 C1
R472
R472 390_4
390_4
CPU_SID
CPU_ALERT
+1.8VSUS
U12D
U12D
VDDA1 VDDA2
CLKIN_H CLKIN_L
RESET_L PWROK LDTSTOP_L LDTREQ_L
SIC SID ALERT_L
HT_REF0 HT_REF1
VDD0_FB_H VDD0_FB_L
VDD1_FB_H VDD1_FB_L
DBRDY TMS TCK TRST_L TDI
TEST23
TEST18 TEST19
TEST25_H TEST25_L
TEST21 TEST20 TEST24 TEST22 TEST12 TEST27
TEST9 TEST6
RSVD1 RSVD2 RSVD3 RSVD4 RSVD5
SOCKET_638_PIN
SOCKET_638_PIN
Serial VID
CPU_SVC
CPU_PWRGD_SVID_REG
+3V
Q11
Q11
2
RHU002N06
RHU002N06
1
+3V
Q6
2
RHU002N06Q6RHU002N06
1
R114
R114
*8.2K_4
*8.2K_4
3
+3V
R116 10K_4 R116 10K_4
CPU_SVC 34 CPU_SVD 34 CPU_PWRGD_SVID_REG 34
+3V
R112
R112
2
*10K_4
*10K_4
THERM_ALERT#_R
1
Q13*2N7002E-LF Q13*2N7002E-LF
THER_SHD#
<check list> Layout Note:Routing 10:10 mils and away from noise source with ground gard
2
THERMTRIP_L
PROCHOT_L
MEMHOT_L
VDDIO_FB_H VDDIO_FB_L
VDDNB_FB_H VDDNB_FB_L
2/4 pull up R691 CPU_BDREQ# to avoid noise cause system shut down
R468
R468 390_4
390_4
KEY1 KEY2
THERMDC THERMDA
DBREQ_L
TEST28_H TEST28_L
TEST17 TEST16 TEST15 TEST14
TEST7
TEST10
TEST8
TEST29_H TEST29_L
RSVD10
RSVD9 RSVD8 RSVD7 RSVD6
R473
R473 1K/F_4
1K/F_4
SVC SVD
TDO
CPU_LDT_RST# CPU_LDT_STOP#
CPU_LDT_REQ#_CPU
CPU_PWRGD
M11 W18
CPU_SVC_R
A6
CPU_SVD_R
A4
CPU_THERMTRIP_L#
AF6
CPU_PROCHOT_L#
AC7
CPU_MEMHOT_L#
AA8
CPU_THERMDC
W7
CPU_THERMDA
W8
VDDIO_FB_H
W9
VDDIO_FB_L
Y9
H6 G6
CPU_DBREQ#
E10
CPU_TDO
AE9
CPUTEST28H
J7
CPUTEST28L
H8
CPUTEST17
D7
CPUTEST16
E7
CPUTEST15
F7
CPUTEST14
C7
C3 K8
C4
CPUTEST29H
C9
CPUTEST29L
C8
H18 H19 AA7 D5 C5
+1.8VSUS
C762
C762
*0.1u/10V_4
*0.1u/10V_4
1/30 leakage issue , change +1.8Vsus to +1.8V
R113 0_4 R113 0_4 R111 0_4 R111 0_4
V DDIO_FB_H 36
VDDIO_FB_L 36
CPU_VDDNB_FB_H 34 CPU_VDDNB_FB_L 34
T8 T8 T5 T5
T4 T4 T3 T3
12/7 Add 300ohm to GND for AMD request
T10 T10 T7 T7
CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO
C741 *0.1u/10V_4 C741 *0.1u/10V_4
+1.8VSUS
R691
R691 300_4
300_4
CPU_DBREQ#
1
R130 300_4 R130 300_4 R129 300_4 R129 300_4
R460 300_4 R460 300_4
R127 300_4 R127 300_4
12/4 Add 0.1u for AMD CPU
10/9 AMD suggest
1. pull up CPU_PWRGD to +1.8SUS
2. pop R5563 pull up to +1.8SUS
H_THERMDC H_THERMDA
R673*300_4 R673*300_4 R674*300_4 R674*300_4
HDT Connector
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
KEY
KEY
CN26
CN26
VFIX MODE
SVC SVD Voltage Output
00 001 1
+3V
R110
R110
R107
R107
10K_4
10K_4
10K_4
10K_4
U1
8
SCLK
7
SDA
6
ALERT#
4
OVERT#
G786P81UU1G786P81U
ADDRESS: 98H
MAX6657,G781P8,W83L771G
2
2/19 change G781 to G786P81U
R106
R106
200_6
200_6
LM86VCC
1
VCC
2
DXP
3
DXN
5
GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
11
THER_SHD#
C147
C147
0.1u/10V_4
0.1u/10V_4
C154
C154
2200p/50V_4
2200p/50V_4
H_THERMDC
1 3
H_THERMDA
R718 *0_4 R718 *0_4
PROJECT : BD3G
PROJECT : BD3G
Quanta Computer Inc.
Quanta Computer Inc.
S1G2 HT,CTL I/F 1/3
S1G2 HT,CTL I/F 1/3
S1G2 HT,CTL I/F 1/3
+3V
2
2/18 G781 reverse R718 0 ohm for Griffin CPU
1
+1.8V
03
+1.8V
CPU_LDT_RST_HTPA#
25
*HDT CONN
*HDT CONN
VID Override Circuit
1.4V
1.2V
1.0V
0.8V
R115
R115 330_4
330_4
Q18
Q18 MMBT3904
MMBT3904
4 42Thursday, May 29, 2008
4 42Thursday, May 29, 2008
4 42Thursday, May 29, 2008
SYS_SHDN# 33
of
of
of
1A
1A
1A
A
B
C
D
E
+SMDDR_VTERM +SMDDR_VTERM
PLACE THEM CLOSE TO CPU WITHIN 1"
R448 39.2/F_4 R448 39.2/F_4
+1.8VSUS
4 4
3 3
2 2
1 1
MEM_MA_ADD[0..15] 7,8
7,8 MEM_MA0_ODT0 7,8 MEM_MA0_ODT1
7,8 MEM_MA0_CS#0 7,8 MEM_MA0_CS#1
7,8 MEM_MA_CKE0 7,8 MEM_MA_CKE1
7 MEM_MA_CLK1_P 7 MEM_MA_CLK1_N 7 MEM_MA_CLK7_P
7,8 MEM_MA_BANK0 7,8 MEM_MA_BANK1 7,8 MEM_MA_BANK2
7,8 MEM_MA_RAS# 7,8 MEM_MA_CAS#
R451 39.2/F_4 R451 39.2/F_4
T23 T23
T41 T41 T38 T38
T37 T37 T30 T30
T29 T29 T43 T43
MEM_MA_CLK7_N 7
T42T42 T39 T39
MEM_MA_WE# 7,8
A
M_ZP M_ZN
MEM_MA_RESET#
MEM_MA1_ODT0 MEM_MA1_ODT1
CPU_MA1_CS_L0 CPU_MA1_CS_L1
CPU_MA_CLK_H5 CPU_MA_CLK_L5
CPU_MA_CLK_H4 CPU_MA_CLK_L4
MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15
MEM_MB_CLK7_P
MEM_MB_CLK7_N
MEM_MB_CLK1_P
MEM_MB_CLK1_N
U12B
U12B
D10
VTT1
C10
VTT2
B10
VTT3
AD10
VTT4
AF10
MEMZP
AE10
MEMZN
H16
RSVD_M1
T19
MA0_ODT0
V22
MA0_ODT1
U21
MA1_ODT0
V19
MA1_ODT1
T20
MA0_CS_L0
U19
MA0_CS_L1
U20
MA1_CS_L0
V20
MA1_CS_L1
J22
MA_CKE0
J20
MA_CKE1
N19
MA_CLK_H5
N20
MA_CLK_L5
E16
MA_CLK_H1
F16
MA_CLK_L1
Y16
MA_CLK_H7
AA16
MA_CLK_L7
P19
MA_CLK_H4
P20
MA_CLK_L4
N21
MA_ADD0
M20
MA_ADD1
N22
MA_ADD2
M19
MA_ADD3
M22
MA_ADD4
L20
MA_ADD5
M24
MA_ADD6
L21
MA_ADD7
L19
MA_ADD8
K22
MA_ADD9
R21
MA_ADD10
L22
MA_ADD11
K20
MA_ADD12
V24
MA_ADD13
K24
MA_ADD14
K19
MA_ADD15
R20
MA_BANK0
R23
MA_BANK1
J21
MA_BANK2
R19
MA_RAS_L
T22
MA_CAS_L
T24
MA_WE_L
SOCKET_638_PIN
SOCKET_638_PIN
+SMDDR_VTERM
C534C534
4.7U/6.3V_6 4.7U/6.3V_6
+SMDDR_VTERM
C542
C542
1000p/50V_4
1000p/50V_4
C238C238
1.5p/50V_4 1.5p/50V_4
C532C532
1.5p/50V_4 1.5p/50V_4
W10
MEM:CMD/CTRL/CLK
MEM:CMD/CTRL/CLK
VTT5 VTT6 VTT7 VTT8 VTT9
VTT_SENSE
MEMVREF
RSVD_M2
MB0_ODT0 MB0_ODT1 MB1_ODT0
MB0_CS_L0 MB0_CS_L1 MB1_CS_L0
MB_CKE0 MB_CKE1
MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4
MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8
MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15
MB_BANK0 MB_BANK1 MB_BANK2
MB_RAS_L MB_CAS_L
MB_WE_L
AC10 AB10 AA10 A10
CPU_VTT_SENSE
Y10
MEMVREF_CPU
W17
MEM_MB_RESET#
B18
W26 W23
MEM_MB1_ODT0
Y26
V26 W25 U22
J25 H26
CPU_MB_CLK_H5
P22
CPU_MB_CLK_HL5
R22 A17 A18 AF18 AF17
CPU_MB_CLK_H4
R26
CPU_MB_CLK_L4
R25
P24 N24 P26 N23 N26 L23 N25 L24 M26 K26 T26 L26 L25 W24 J23 J24
R24 U26 J26
U25 U24 U23
Place close to socket
C546C546
4.7U/6.3V_6 4.7U/6.3V_6
C190
C190
1000p/50V_4
1000p/50V_4
Close to CPU within 1500 mils
C545C545
4.7U/6.3V_6 4.7U/6.3V_6
C538
C538
1000p/50V_4
1000p/50V_4
B
MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15
C536C536
4.7U/6.3V_6 4.7U/6.3V_6
C184
C184
1000p/50V_4
1000p/50V_4
MEM_MA_CLK7_P
MEM_MA_CLK7_N
MEM_MA_CLK1_P
MEM_MA_CLK1_N
750 mA
CPU_VTT_SENSE 36
T136 T136
MEM_MB0_ODT0 7,8 MEM_MB0_ODT1 7,8
T31 T31
MEM_MB0_CS#0 7,8 MEM_MB0_CS#1 7,8
T36T36
MEM_MB_CKE0 7,8 MEM_MB_CKE1 7,8
T34 T34 T28 T28
MEM_MB_CLK1_P 7 MEM_MB_CLK1_N 7 MEM_MB_CLK7_P 7
MEM_MB_CLK7_N 7
T35 T35 T40 T40
MEM_MB_BANK0 7,8
MEM_MB_BANK1 7,8
MEM_MB_BANK2 7,8
MEM_MB_RAS# 7,8
MEM_MB_CAS# 7,8
MEM_MB_WE# 7,8
C186C186
0.22u/6.3V_4 0.22u/6.3V_4
C183
C183
180p/50V_4
180p/50V_4
R143
R143
2K/F_4
2K/F_4
R142
R142
2K/F_4
2K/F_4
11/05 change to RC0402-C
MEM_MB_ADD[0..15] 7,8
C539C539
0.22u/6.3V_4 0.22u/6.3V_4
C181
C181
180p/50V_4
180p/50V_4
C540C540
1.5p/50V_4 1.5p/50V_4
C533C533
1.5p/50V_4 1.5p/50V_4
+1.8VSUS
C544C544
0.22u/6.3V_4 0.22u/6.3V_4
C543
C543
180p/50V_4
180p/50V_4
+SMDDR_VREF
R137
R137 *0_4
*0_4
C200C200
0.1u/10V_4 0.1u/10V_4
0.22u/6.3V_4 0.22u/6.3V_4
180p/50V_4
180p/50V_4
C193C193
C537
C537
MEM_MB_DATA[0..63] 7
Reserved
1000p/50V_4
1000p/50V_4
MEM_MB_DM[0..7] 7
C
C208
C208
7 MEM_MB_DQS0_P 7 MEM_MB_DQS0_N 7 MEM_MB_DQS1_P 7 MEM_MB_DQS1_N 7 MEM_MB_DQS2_P 7 MEM_MB_DQS2_N 7 MEM_MB_DQS3_P 7 MEM_MB_DQS3_N 7 MEM_MB_DQS4_P 7 MEM_MB_DQS4_N 7 MEM_MB_DQS5_P 7 MEM_MB_DQS5_N 7 MEM_MB_DQS6_P 7 MEM_MB_DQS6_N 7 MEM_MB_DQS7_P
MEM_MB_DQS7_N 7
Processor Memory Interface
U12C
U12C
MEM:DATA
MEM_MB_DATA0 MEM_MB_DATA1 MEM_MB_DATA2 MEM_MB_DATA3 MEM_MB_DATA4 MEM_MB_DATA5 MEM_MB_DATA6 MEM_MB_DATA7 MEM_MB_DATA8 MEM_MB_DATA9 MEM_MB_DATA10 MEM_MB_DATA11 MEM_MB_DATA12 MEM_MB_DATA13 MEM_MB_DATA14 MEM_MB_DATA15 MEM_MB_DATA16 MEM_MB_DATA17 MEM_MB_DATA18 MEM_MB_DATA19 MEM_MB_DATA20 MEM_MB_DATA21 MEM_MB_DATA22 MEM_MB_DATA23 MEM_MB_DATA24 MEM_MB_DATA25 MEM_MB_DATA26 MEM_MB_DATA27 MEM_MB_DATA28 MEM_MB_DATA29 MEM_MB_DATA30 MEM_MB_DATA31 MEM_MB_DATA32 MEM_MB_DATA33 MEM_MB_DATA34 MEM_MB_DATA35 MEM_MB_DATA36 MEM_MB_DATA37 MEM_MB_DATA38 MEM_MB_DATA39 MEM_MB_DATA40 MEM_MB_DATA41 MEM_MB_DATA42 MEM_MB_DATA43 MEM_MB_DATA44 MEM_MB_DATA45 MEM_MB_DATA46 MEM_MB_DATA47 MEM_MB_DATA48 MEM_MB_DATA49 MEM_MB_DATA50 MEM_MB_DATA51 MEM_MB_DATA52 MEM_MB_DATA53 MEM_MB_DATA54 MEM_MB_DATA55 MEM_MB_DATA56 MEM_MB_DATA57 MEM_MB_DATA58 MEM_MB_DATA59 MEM_MB_DATA60 MEM_MB_DATA61 MEM_MB_DATA62 MEM_MB_DATA63
MEM_MB_DM0 MEM_MB_DM1 MEM_MB_DM2 MEM_MB_DM3 MEM_MB_DM4 MEM_MB_DM5 MEM_MB_DM6 MEM_MB_DM7
C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23
G24 AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11
Y11 AE14 AF14 AF11 AD11
A12
B16
A22
E25 AB26 AE22 AC16 AD12
C12
B12
D16
C16
A24
A23
F26
E26 AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12
SOCKET_638_PIN
SOCKET_638_PIN
MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63
MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7
MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7
D
MEM:DATA
MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8
MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63
MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
04
MEM_MA_DATA0
G12
MEM_MA_DATA1
F12
MEM_MA_DATA2
H14
MEM_MA_DATA3
G14
MEM_MA_DATA4
H11
MEM_MA_DATA5
H12
MEM_MA_DATA6
C13
MEM_MA_DATA7
E13
MEM_MA_DATA8
H15
MEM_MA_DATA9
E15
MEM_MA_DATA10
E17
MEM_MA_DATA11
H17
MEM_MA_DATA12
E14
MEM_MA_DATA13
F14
MEM_MA_DATA14
C17
MEM_MA_DATA15
G17
MEM_MA_DATA16
G18
MEM_MA_DATA17
C19
MEM_MA_DATA18
D22
MEM_MA_DATA19
E20
MEM_MA_DATA20
E18
MEM_MA_DATA21
F18
MEM_MA_DATA22
B22
MEM_MA_DATA23
C23
MEM_MA_DATA24
F20
MEM_MA_DATA25
F22
MEM_MA_DATA26
H24
MEM_MA_DATA27
J19
MEM_MA_DATA28
E21
MEM_MA_DATA29
E22
MEM_MA_DATA30
H20
MEM_MA_DATA31
H22
MEM_MA_DATA32
Y24
MEM_MA_DATA33
AB24
MEM_MA_DATA34
AB22
MEM_MA_DATA35
AA21
MEM_MA_DATA36
W22
MEM_MA_DATA37
W21
MEM_MA_DATA38
Y22
MEM_MA_DATA39
AA22
MEM_MA_DATA40
Y20
MEM_MA_DATA41
AA20
MEM_MA_DATA42
AA18
MEM_MA_DATA43
AB18
MEM_MA_DATA44
AB21
MEM_MA_DATA45
AD21
MEM_MA_DATA46
AD19
MEM_MA_DATA47
Y18
MEM_MA_DATA48
AD17
MEM_MA_DATA49
W16
MEM_MA_DATA50
W14
MEM_MA_DATA51
Y14
MEM_MA_DATA52
Y17
MEM_MA_DATA53
AB17
MEM_MA_DATA54
AB15
MEM_MA_DATA55
AD15
MEM_MA_DATA56
AB13
MEM_MA_DATA57
AD13
MEM_MA_DATA58
Y12
MEM_MA_DATA59
W11
MEM_MA_DATA60
AB14
MEM_MA_DATA61
AA14
MEM_MA_DATA62
AB12
MEM_MA_DATA63
AA12
MEM_MA_DM0
E12
MEM_MA_DM1
C15
MEM_MA_DM2
E19
MEM_MA_DM3
F24
MEM_MA_DM4
AC24
MEM_MA_DM5
Y19
MEM_MA_DM6
AB16
MEM_MA_DM7
Y13
G13 H13 G16 G15 C22 C21 G22 G21 AD23 AC23 AB19 AB20 Y15 W15 W12 W13
Size D ocument Number R ev
Size D ocument Number R ev
Size D ocument Number R ev
Date: Sheet
Date: Sheet
Date: Sheet
S1G2 DDRII MEMORY I/F 2/3
S1G2 DDRII MEMORY I/F 2/3
S1G2 DDRII MEMORY I/F 2/3
MEM_MA_DATA[0..63] 7
MEM_MA_DM[0..7] 7
MEM_MA_DQS0_P 7 MEM_MA_DQS0_N 7 MEM_MA_DQS1_P 7 MEM_MA_DQS1_N 7 MEM_MA_DQS2_P 7 MEM_MA_DQS2_N 7 MEM_MA_DQS3_P 7 MEM_MA_DQS3_N 7 MEM_MA_DQS4_P 7 MEM_MA_DQS4_N 7 MEM_MA_DQS5_P 7 MEM_MA_DQS5_N 7 MEM_MA_DQS6_P 7 MEM_MA_DQS6_N 7 MEM_MA_DQS7_P 7 MEM_MA_DQS7_N 7
PROJECT : BD3G
PROJECT : BD3G
Quanta Computer Inc.
Quanta Computer Inc.
of
of
of
5 42Thursday, May 29, 2008
5 42Thursday, May 29, 2008
5 42Thursday, May 29, 2008
E
1A
1A
1A
5
U12E
U12E
G4
VDD0_1
H2
VDD0_2
J9
VDD0_3
J11
VDD0_4
J13
VDD0_5
D D
CPU VDDNB_CORE
3A
+1.8VSUS
2A
C C
B B
J15
VDD0_6
K6
VDD0_7
K10
VDD0_8
K12
VDD0_9
K14
VDD0_10
L4
VDD0_11
L7
VDD0_12
L9
VDD0_13
L11
VDD0_14
L13
VDD0_15
L15
VDD0_16
M2
VDD0_17
M6
VDD0_18
M8
VDD0_19
M10
VDD0_20
N7
VDD0_21
N9
VDD0_22
N11
VDD0_23
K16
VDDNB_1
M16
VDDNB_2
P16
VDDNB_3
T16
VDDNB_4
V16
VDDNB_5
H25
VDDIO1
J17
VDDIO2
K18
VDDIO3
K21
VDDIO4
K23
VDDIO5
K25
VDDIO6
L17
VDDIO7
M18
VDDIO8
M21
VDDIO9
M23
VDDIO10
M25
VDDIO11
N17
VDDIO12
SOCKET_638_PIN
SOCKET_638_PIN
VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 VDD1_8
VDD1_9 VDD1_10 VDD1_11 VDD1_12 VDD1_13 VDD1_14 VDD1_15 VDD1_16 VDD1_17 VDD1_18 VDD1_19 VDD1_20 VDD1_21 VDD1_22 VDD1_23 VDD1_24 VDD1_25 VDD1_26
VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13
CPU_CORE1CPU_CORE0 CPU_CORE0
P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4 AD2
Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18
+1.8VSUS
4
U12F
U12F
AA4
VSS1
AA11
VSS2
AA13
VSS3
AA15
VSS4
AA17
VSS5
AA19
VSS6
AB2
VSS7
AB7
VSS8
AB9
VSS9
AB23
VSS10
AB25
VSS11
AC11
VSS12
AC13
VSS13
AC15
VSS14
AC17
VSS15
AC19
VSS16
AC21
VSS17
AD6
VSS18
AD8
VSS19
AD25
VSS20
AE11
VSS21
AE13
VSS22
AE15
VSS23
AE17
VSS24
AE19
VSS25
AE21
VSS26
AE23
VSS27
B4
VSS28
B6
VSS29
B8
VSS30
B9
VSS31
B11
VSS32
B13
VSS33
B15
VSS34
B17
VSS35
B19
VSS36
B21
VSS37
B23
VSS38
B25
VSS39
D6
VSS40
D8
VSS41
D9
VSS42
D11
VSS43
D13
VSS44
D15
VSS45
D17
VSS46
D19
VSS47
D21
VSS48
D23
VSS49
D25
VSS50
E4
VSS51
F2
VSS52
F11
VSS53
F13
VSS54
F15
VSS55
F17
VSS56
F19
VSS57
F21
VSS58
F23
VSS59
F25
VSS60
H7
VSS61
H9
VSS62
H21
VSS63
H23
VSS64
J4
VSS65
SOCKET_638_PIN
SOCKET_638_PIN
VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98
VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129
3
J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6
22u/6.3V_8
22u/6.3V_8
CPU_CORE1
CPU VDDNB_CORE
DECOUPLING BETWEEN PROCESSOR AND DIMMs PLACE CLOSE TO PROCESSOR AS POSSIBLE
+1.8VSUS
+1.8VSUS
BOTTOM SIDE DECOUPLING
C188
C188
C197
C197
22u/6.3V_8
22u/6.3V_8
C196
C196
22u/6.3V_8
22u/6.3V_8
22u/6.3V_8
22u/6.3V_8
C207
C207
22u/6.3V_8
22u/6.3V_8
22u/6.3V_8
22u/6.3V_8
C525C525
4.7U/6.3V_6 4.7U/6.3V_6
0.22u/6.3V_4 0.22u/6.3V_4
C251C251
4.7U/6.3V_6 4.7U/6.3V_6
0.22u/6.3V_4 0.22u/6.3V_4
C241C241
C187
C187
C194
C194
C516C516
2
C192
C192
22u/6.3V_8
22u/6.3V_8
22u/6.3V_8
22u/6.3V_8
C206
C206
22u/6.3V_8
22u/6.3V_8
C248C248
0.01u/16V_4 0.01u/16V_4
22u/6.3V_8
22u/6.3V_8
C199
C199
+1.8VSUS
C515C515
4.7U/6.3V_6 4.7U/6.3V_6
C198
C198
C195
C195
22u/6.3V_8
22u/6.3V_8
C209
C209 22u/6.3V_8
22u/6.3V_8
4.7U/6.3V_6 4.7U/6.3V_6
0.01u/16V_4 0.01u/16V_4
C179C179
0.22u/6.3V_4 0.22u/6.3V_4
0.22u/6.3V_4 0.22u/6.3V_4
C212
C212
22u/6.3V_8
22u/6.3V_8
C526C526
C237
C237C245 C245
180p/50V_4
180p/50V_4
C177C177
0.22u/6.3V_4 0.22u/6.3V_4
C180C180
0.01u/16V_4 0.01u/16V_4
0.01u/16V_4 0.01u/16V_4
C211C211
0.22u/6.3V_4 0.22u/6.3V_4
C239C239
180p/50V_4
180p/50V_4
180p/50V_4
180p/50V_4
C527C527
0.22u/6.3V_4 0.22u/6.3V_4
C247C247
0.22u/6.3V_4 0.22u/6.3V_4
C178
C178
C191
C191C182 C182
1
C185C185
0.01u/16V_4 0.01u/16V_4
C210
C210
180p/50V_4
180p/50V_4
C250
C250
180p/50V_4
180p/50V_4
05
PROCESSOR POWER AND GROUND
A A
PROJECT : BD3G
PROJECT : BD3G
Quanta Computer Inc.
Size D ocument Number R ev
Size D ocument Number R ev
Size D ocument Number R ev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
Quanta Computer Inc.
S1G2 PWR & GND 3/3
S1G2 PWR & GND 3/3
S1G2 PWR & GND 3/3
1
of
of
of
6 42Thursday, May 29, 2008
6 42Thursday, May 29, 2008
6 42Thursday, May 29, 2008
1A
1A
1A
5
MEM_MA_ADD[0..15] 5,8
D D
MEM_MA_BANK[0..2] 5,8
5 MEM_MA_DQS0_P 5 MEM_MA_DQS1_P 5 MEM_MA_DQS2_P 5 MEM_MA_DQS3_P 5 MEM_MA_DQS4_P 5 MEM_MA_DQS5_P 5 MEM_MA_DQS6_P
C C
B B
A A
5 MEM_MA_DQS7_P
5 MEM_MA_DQS0_N 5 MEM_MA_DQS1_N 5 MEM_MA_DQS2_N 5 MEM_MA_DQS3_N 5 MEM_MA_DQS4_N 5 MEM_MA_DQS5_N 5 MEM_MA_DQS6_N 5 MEM_MA_DQS7_N
5 MEM_MA_CLK1_P 5 MEM_MA_CLK1_N 5 MEM_MA_CLK7_P 5 MEM_MA_CLK7_N
5,8 MEM_MA_CKE0 5,8 MEM_MA_CKE1
5,8 MEM_MA_RAS# 5,8 MEM_MA_CAS# 5,8 MEM_MA_WE# 5,8 MEM_MA0_CS#0
MEM_MA0_CS#1 5,8
5,8 MEM_MA0_ODT0
MEM_MA0_ODT1 5,8
3,8,14,25 PDAT_SMB
PCLK_SMB 3,8,14,25
C387C387
2.2u/6.3V_6 2.2u/6.3V_6
+3V
C383C383
0.1u/10V_4 0.1u/10V_4
MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8
MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15
MEM_MA_BANK0 MEM_MA_BANK1 MEM_MA_BANK2
MEM_MA_DM0 MEM_MA_DM1 MEM_MA_DM2 MEM_MA_DM3 MEM_MA_DM4 MEM_MA_DM5 MEM_MA_DM6 MEM_MA_DM7
PDAT_SMB PCLK_SMB
C496
C496
1000p/50V_4
1000p/50V_4
+1.8VSUS +1.8VSUS
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10
90
A11
89
A12
116
A13
86
A14
84
A15
107
BA0
106
BA1
85
BA2
10
DM0
26
DM1
52
DM2
67
DM3
130
DM4
147
DM5
170
DM6
185
DM7
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
11
DQS0
29
DQS1
49
DQS2
68
DQS3
129
DQS4
146
DQS5
167
DQS6
186
DQS7
30
CK0
32
CK0
164
CK1
166
CK1
79
CKE0
80
CKE1
108
RAS
113
CAS
109
WE
110
S0
115
S1
114
ODT0
119
DIM1_SA0 DIM1_SA1
C466C466
0.1u/10V_4 0.1u/10V_4
ODT1
198
SA0
200
SA1
195
SDA
197
SCL
199
VDDspd
1
VREF
2
VSS0
3
VSS1
8
VSS2
9
VSS3
12
VSS4
15
VSS5
18
VSS6
21
VSS7
24
VSS8
27
VSS9
28
VSS10
33
VSS11
34
VSS12
39
VSS13
40
VSS14
41
VSS15
42
VSS16
47
VSS17
48
VSS18
53
VSS19
54
VSS20
103
VDD081VDD182VDD287VDD388VDD495VDD596VDD6
SO-DIMM
SO-DIMM
VSS2577VSS26 66VSS2371VSS24 60VSS2165VSS22
72
59
111
104
112
117
VDD8
VDD7
VDD9
(Reverse)
(Reverse)
VSS29
VSS30
VSS28 78VSS27
122
127
121
H=5.2
R271 10K/F_4 R271 10K/F_4 R272 10K/F_4 R272 10K/F_4
SMbus address A0
5
4
118
CN23
CN23
5
DQ0
7
DQ1
17
DQ2
VDD10
VDD11
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
50
NC1
69
NC2
83
NC3
120
NC4
163
NC/TEST
196
VSS56
193
VSS55
190
VSS54
187
VSS53
184
VSS52
183
VSS51
178
VSS50
177
VSS49
172
VSS48
171
VSS47
168
VSS46
165
VSS45
162
VSS44
161
VSS43
156
VSS42
155
VSS41
150
VSS40
149
VSS39
145
VSS38
144
VSS37
139
VSS36
138
VSS35
133
VSS34
VSS33
VSS31
VSS32
128
132
DDR SO-DIMM SOCKET 1.8V
DDR SO-DIMM SOCKET 1.8V
DIM1_SA0 DIM1_SA1
4
MEM_MA_DATA0 MEM_MA_DATA1 MEM_MA_DATA2 MEM_MA_DATA3 MEM_MA_DATA4 MEM_MA_DATA5 MEM_MA_DATA6 MEM_MA_DATA7 MEM_MA_DATA8 MEM_MA_DATA9 MEM_MA_DATA10 MEM_MA_DATA11 MEM_MA_DATA12 MEM_MA_DATA13 MEM_MA_DATA14 MEM_MA_DATA15 MEM_MA_DATA16 MEM_MA_DATA17 MEM_MA_DATA18 MEM_MA_DATA19 MEM_MA_DATA20 MEM_MA_DATA21 MEM_MA_DATA22 MEM_MA_DATA23 MEM_MA_DATA24 MEM_MA_DATA25 MEM_MA_DATA26 MEM_MA_DATA27 MEM_MA_DATA28 MEM_MA_DATA29 MEM_MA_DATA30 MEM_MA_DATA31 MEM_MA_DATA36 MEM_MA_DATA37 MEM_MA_DATA35 MEM_MA_DATA39 MEM_MA_DATA38 MEM_MA_DATA32 MEM_MA_DATA33 MEM_MA_DATA34 MEM_MA_DATA40 MEM_MA_DATA41 MEM_MA_DATA46 MEM_MA_DATA47 MEM_MA_DATA44 MEM_MA_DATA45 MEM_MA_DATA42 MEM_MA_DATA43 MEM_MA_DATA52 MEM_MA_DATA49 MEM_MA_DATA54 MEM_MA_DATA55 MEM_MA_DATA53 MEM_MA_DATA48 MEM_MA_DATA51 MEM_MA_DATA50 MEM_MA_DATA61 MEM_MA_DATA60 MEM_MA_DATA63 MEM_MA_DATA62 MEM_MA_DATA56 MEM_MA_DATA57 MEM_MA_DATA58 MEM_MA_DATA59
MEMHOT_SODIMM#_1 MEM_MA_RESET#1
MEM_MA_NC5
MEM_MA_DATA[0..63] 5
R279 0_4 R279 0_4
T122 T122
T123 T123
+0.9VSMVREF_DIMM+0.9VSMVREF_DIMM
Only for reserved
1/18 Change CN23 footprint from DDR-C-1734071-200P to DDR-C-1734071-200P-BD3A (SMT open issue)
R281 *0_4 R281 *0_4
MEMHOT_SODIMM# 8
C497
C497
2.2u/6.3V_6
2.2u/6.3V_6
+0.9VSMVREF_DIMM +SMDDR_VREF
+0.9VSMVREF_DIMM
3
MEM_MB_ADD[0..15] 5,8 MEM_MB_DATA[0..63] 5
MEM_MB_BANK[0..2] 5,8
MEM_MB_DM[0..7] 5MEM_MA_DM[0..7] 5
MEM_MB_DQS0_P 5 MEM_MB_DQS1_P 5
5 MEM_MB_DQS2_P
MEM_MB_DQS3_P 5 5 MEM_MB_DQS4_P 5 MEM_MB_DQS5_P 5 MEM_MB_DQS6_P
MEM_MB_DQS7_P 5
MEM_MB_DQS0_N 5
MEM_MB_DQS1_N 5 5 MEM_MB_DQS2_N
MEM_MB_DQS3_N 5 5 MEM_MB_DQS4_N
MEM_MB_DQS5_N 5 5 MEM_MB_DQS6_N
MEM_MB_DQS7_N 5
MEM_MB_CLK1_P 5 MEM_MB_CLK1_N 5
5 MEM_MB_CLK7_P
MEM_MB_CLK7_N 5
5,8 MEM_MB_CKE0
MEM_MB_CKE1 5,8
5,8 MEM_MB_RAS# 5,8 MEM_MB_CAS# 5,8 MEM_MB_WE#
5,8 MEM_MB0_CS#0
MEM_MB0_CS#1 5,8
5,8 MEM_MB0_ODT0
MEM_MB0_ODT1 5,8
+3V
C382
C382
0.1u/10V_4
0.1u/10V_4
+1.8VSUS
R277
R277 2K/F_4
2K/F_4
R288
R288 2K/F_4
2K/F_4
MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD8
MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15
MEM_MB_BANK0 MEM_MB_BANK1 MEM_MB_BANK2
MEM_MB_DM0 MEM_MB_DM1 MEM_MB_DM2 MEM_MB_DM3 MEM_MB_DM4 MEM_MB_DM5 MEM_MB_DM6 MEM_MB_DM7
DIM2_SA0 DIM2_SA1
PDAT_SMB PCLK_SMB
C468C468
0.1u/10V_4 0.1u/10V_4
C384
C384 1000p/50V_4
1000p/50V_4
102
A0
101
A1
99 98 97 94 92 93 91
90 89
86 84
85
10 26 52 67
13 31 51 70
11 29 49 68
30 32
79 80
o
12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54
1
2 3 8 9
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
BA0 BA1 BA2
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7
CK0 CK0 CK1 CK1
CKE0 CKE1
RAS CAS WE S0 S1
ODT0 ODT1
SA0 SA1
SDA SCL
VDDspd
VREF
VSS0 VSS1 VSS2
o
VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20
DIM2_SA0 DIM2_SA1
VDD081VDD182VDD287VDD388VDD495VDD596VDD6
59
100
105
116
107 106
130 147 170 185
131 148 169 188
129 146 167 186
164 166
108 113 109 110 115
114 119
198 200
195 197
199
SMbus address A2
3
2
103
111
104
112
117
118
VDD8
VDD7
VDD9
VDD10
VDD11
NC/TEST
VSS56
SO-DIMM
(REVERSE)
SO-DIMM
(REVERSE)
VSS55 VSS54 VSS53 VSS52 VSS51 VSS50 VSS49 VSS48 VSS47 VSS46 VSS45 VSS44 VSS43 VSS42 VSS41 VSS40 VSS39 VSS38 VSS37 VSS36 VSS35
VSS2577VSS26 66VSS2371VSS24 60VSS2165VSS22
72
R295 10K/F_4 R295 10K/F_4 R296 10K/F_4 R296 10K/F_4
VSS34
VSS33
VSS31
VSS32
VSS29
VSS30
VSS28 78VSS27
128
132
122
127
121
2
CN19
CN19
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
NC1 NC2 NC3 NC4
H=9.2
MEM_MB_DATA4
5
MEM_MB_DATA5
7
MEM_MB_DATA2
17
MEM_MB_DATA3
19
MEM_MB_DATA0
4
MEM_MB_DATA1
6
MEM_MB_DATA6
14
MEM_MB_DATA7
16
MEM_MB_DATA13
23
MEM_MB_DATA12
25
MEM_MB_DATA11
35
MEM_MB_DATA10
37
MEM_MB_DATA8
20
MEM_MB_DATA9
22
MEM_MB_DATA14
36
MEM_MB_DATA15
38
MEM_MB_DATA16
43
MEM_MB_DATA17
45
MEM_MB_DATA18
55
MEM_MB_DATA19
57
MEM_MB_DATA20
44
MEM_MB_DATA21
46
MEM_MB_DATA22
56
MEM_MB_DATA23
58
MEM_MB_DATA24
61
MEM_MB_DATA25
63
MEM_MB_DATA26
73
MEM_MB_DATA27
75
MEM_MB_DATA28
62
MEM_MB_DATA29
64
MEM_MB_DATA30
74
MEM_MB_DATA31
76
MEM_MB_DATA37
123
MEM_MB_DATA36
125
MEM_MB_DATA34
135
MEM_MB_DATA35
137
MEM_MB_DATA33
124
MEM_MB_DATA32
126
MEM_MB_DATA38
134
MEM_MB_DATA39
136
MEM_MB_DATA40
141
MEM_MB_DATA45
143
MEM_MB_DATA47
151
MEM_MB_DATA46
153
MEM_MB_DATA44
140
MEM_MB_DATA41
142
MEM_MB_DATA43
152
MEM_MB_DATA42
154
MEM_MB_DATA52
157
MEM_MB_DATA53
159
MEM_MB_DATA50
173
MEM_MB_DATA51
175
MEM_MB_DATA48
158
MEM_MB_DATA49
160
MEM_MB_DATA54
174
MEM_MB_DATA55
176
MEM_MB_DATA56
179
MEM_MB_DATA60
181
MEM_MB_DATA58
189
MEM_MB_DATA59
191
MEM_MB_DATA61
180
MEM_MB_DATA57
182
MEM_MB_DATA62
192
MEM_MB_DATA63
194
MEMHOT_SODIMM#_2
50
MEM_MB_RESET#2
69 83 120
MEM_MB_NC5
163
196 193 190 187 184 183 178 177 172 171 168 165 162 161 156 155 150 149 145 144 139 138 133
+3V
R294 0_4 R294 0_4
T106 T106
T104 T104
1/18 Change CN19 footprint from DDR-C-292564-200P to DDR-C-292564-200P-BD3A (SMT open issue)
DDR SO-DIMM SOCKET 1.8V
DDR SO-DIMM SOCKET 1.8V
Size Doc ument Number Rev
Size Doc ument Number Rev
Size Doc ument Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
MEMHOT_SODIMM#
PROJECT : BD3G
PROJECT : BD3G
Quanta Computer Inc.
Quanta Computer Inc.
DDR2 SODIMMS: A/ B CHANNEL
DDR2 SODIMMS: A/ B CHANNEL
DDR2 SODIMMS: A/ B CHANNEL
1
07
1A
1A
1A
of
7 42Thursday, May 29, 2008
7 42Thursday, May 29, 2008
7 42Thursday, May 29, 2008
1
5
4
3
2
1
5,7 MEM_MA_ADD[0..15]
MEM_MA_BANK[0..2] 5,7
MEM_MA_BANK2
D D
C C
MEM_MA_CKE0 5,7
MEM_MA_WE# 5,7 MEM_MA_CAS# 5,7
5,7 MEM_MA0_ODT1
MEM_MA0_CS#1 5,7
MEM_MA_CKE1 5,7
5,7 MEM_MA_RAS#
MEM_MA0_ODT0 5,7
MEM_MA_CKE0 MEM_MA_ADD12 MEM_MA_ADD9 MEM_MA_ADD8 MEM_MA_ADD5 MEM_MA_ADD3 MEM_MA_ADD1 MEM_MA_ADD10 MEM_MA_BANK0 MEM_MA_WE# MEM_MA_CAS# MEM_MA0_ODT1 MEM_MA0_CS#1 MEM_MA_ADD15 MEM_MA_CKE1
MEM_MA_ADD7 MEM_MA_ADD14 MEM_MA_ADD6 MEM_MA_ADD11
MEM_MA_ADD2 MEM_MA_ADD4
MEM_MA_BANK1 MEM_MA_ADD0
MEM_MA0_CS#0 MEM_MA_RAS#
MEM_MA_ADD13 MEM_MA0_ODT0
+1.8VSUS
RP25 47_4P2R_4 RP25 47_4P2R_4
RP24 47_4P2R_4 RP24 47_4P2R_4
RP20 47_4P2R_4 RP20 47_4P2R_4
RP19 47_4P2R_4 RP19 47_4P2R_4
RP23 47_4P2R_4 RP23 47_4P2R_4
RP22 47_4P2R_4 RP22 47_4P2R_4
RP21 47_4P2R_4 RP21 47_4P2R_4
RP32 47_4P2R_4 RP32 47_4P2R_4
RP31 47_4P2R_4 RP31 47_4P2R_4
RP30 47_4P2R_4 RP30 47_4P2R_4
RP27 47_4P2R_4 RP27 47_4P2R_4
RP26 47_4P2R_4 RP26 47_4P2R_4
RP29 47_4P2R_4 RP29 47_4P2R_4
RP28 47_4P2R_4 RP28 47_4P2R_4
C513
C513
0.1u/10V_4
0.1u/10V_4
C505
C505
0.1u/10V_4
0.1u/10V_4
MEM_MA_ADD[0..15]
MEM_MA_BANK[0..2]
+SMDDR_VTERM
4
3
2
1
4
3
2
1
2
1
4
3
2
1
4
3
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
2
1
4
3
4
3
2
1
4
3
2
1
PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH
C498
C503
C503
0.1u/10V_4
0.1u/10V_4
C498
0.1u/10V_4
0.1u/10V_4
C446 0.1u/10V_4 C446 0.1u/10V_4
C386 0.1u/10V_4 C386 0.1u/10V_4
C361 0.1u/10V_4 C361 0.1u/10V_4
C341 0.1u/10V_4 C341 0.1u/10V_4
C355 0.1u/10V_4 C355 0.1u/10V_4
C390 0.1u/10V_4 C390 0.1u/10V_4
C491 0.1u/10V_4 C491 0.1u/10V_4
C328 0.1u/10V_4 C328 0.1u/10V_4
C360 0.1u/10V_4 C360 0.1u/10V_4
C329 0.1u/10V_4 C329 0.1u/10V_4
C495 0.1u/10V_4 C495 0.1u/10V_4
C369 0.1u/10V_4 C369 0.1u/10V_4
C445 0.1u/10V_4 C445 0.1u/10V_4
C318 0.1u/10V_4 C318 0.1u/10V_4
C444 0.1u/10V_4 C444 0.1u/10V_4
C448 0.1u/10V_4 C448 0.1u/10V_4
C517
C517
0.1u/10V_4
0.1u/10V_4
C522
C522
0.1u/10V_4
0.1u/10V_4
+1.8VSUS
+1.8VSUS
+1.8VSUS
+1.8VSUS
+1.8VSUS
+1.8VSUS
+1.8VSUS
+1.8VSUS
MEM_MB_CKE0 5,7
5,7 MEM_MB_W E# 5,7 MEM_MB_CAS#
MEM_MB0_ODT1 5,7 MEM_MB0_CS#1 5,7 MEM_MB_CKE1 5,7
MEM_MB0_CS#0 5,75,7 MEM_MA0_CS#0 MEM_MB_RAS# 5,7
MEM_MB0_ODT0 5,7
5,7 MEM_MB_ADD[0..15]
MEM_MB_BANK[0..2] 5,7
MEM_MB_CKE0 MEM_MB_BANK2 MEM_MB_ADD12 MEM_MB_ADD9 MEM_MB_ADD8 MEM_MB_ADD5 MEM_MB_ADD3 MEM_MB_ADD1 MEM_MB_ADD10 MEM_MB_BANK0 MEM_MB_WE# MEM_MB_CAS# MEM_MB0_ODT1 MEM_MB0_CS#1 MEM_MB_CKE1 MEM_MB_ADD15
MEM_MB_ADD7 MEM_MB_ADD14
MEM_MB_ADD6 MEM_MB_ADD11
MEM_MB_ADD2 MEM_MB_ADD4
MEM_MB_BANK1 MEM_MB_ADD0
MEM_MB0_CS#0 MEM_MB_RAS#
MEM_MB0_ODT0 MEM_MB_ADD13
+1.8VSUS
C499
C499
0.1u/10V_4
0.1u/10V_4
MEM_MB_ADD[0..15]
MEM_MB_BANK[0..2]
+SMDDR_VTERM
RP40 47_4P2R_4 RP40 47_4P2R_4
4
3
2
RP39 47_4P2R_4 RP39 47_4P2R_4
RP38 47_4P2R_4 RP38 47_4P2R_4
RP37 47_4P2R_4 RP37 47_4P2R_4
RP36 47_4P2R_4 RP36 47_4P2R_4
RP35 47_4P2R_4 RP35 47_4P2R_4
RP41 47_4P2R_4 RP41 47_4P2R_4
RP44 47_4P2R_4 RP44 47_4P2R_4
RP43 47_4P2R_4 RP43 47_4P2R_4
RP42 47_4P2R_4 RP42 47_4P2R_4
RP48 47_4P2R_4 RP48 47_4P2R_4
RP47 47_4P2R_4 RP47 47_4P2R_4
RP46 47_4P2R_4 RP46 47_4P2R_4
RP45 47_4P2R_4 RP45 47_4P2R_4
PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH
C511
C511
0.1u/10V_4
0.1u/10V_4
1
2
1
4
3
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
2
1
4
3
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
2
1
4
3
C519
C519
0.1u/10V_4
0.1u/10V_4
C524
C524
0.1u/10V_4
0.1u/10V_4
C365 0.1u/10V_4 C365 0.1u/10V_4
C440 0.1u/10V_4 C440 0.1u/10V_4
C357 0.1u/10V_4 C357 0.1u/10V_4
C325 0.1u/10V_4 C325 0.1u/10V_4
C356 0.1u/10V_4 C356 0.1u/10V_4
C449 0.1u/10V_4 C449 0.1u/10V_4
C494 0.1u/10V_4 C494 0.1u/10V_4
C441 0.1u/10V_4 C441 0.1u/10V_4
C492 0.1u/10V_4 C492 0.1u/10V_4
C349 0.1u/10V_4 C349 0.1u/10V_4
C493 0.1u/10V_4 C493 0.1u/10V_4
C376 0.1u/10V_4 C376 0.1u/10V_4
C359 0.1u/10V_4 C359 0.1u/10V_4
C340 0.1u/10V_4 C340 0.1u/10V_4
C362 0.1u/10V_4 C362 0.1u/10V_4
C343 0.1u/10V_4 C343 0.1u/10V_4
C520
C520
0.1u/10V_4
0.1u/10V_4
+1.8VSUS
+1.8VSUS
+1.8VSUS
+1.8VSUS
+1.8VSUS
+1.8VSUS
+1.8VSUS
C470
C470
0.1u/10V_4
0.1u/10V_4
08
+1.8VSUS
PLACE CLOSE TO SOCKET( PER EMI/EMC)
B B
+3V
R298
R298 *10K/F_4
*10K/F_4
Close DDR2 socket
U5
U5
A0 7 +VS
+3V
3,7,14,25 PDAT_SMB
PCLK_SMB 3,7,14,25
A A
PDAT_SMB PCLK_SMB
+3V
5
6
A1
5
A2
1
SDA
2
SCL
*DS75U+T&R
*DS75U+T&R
R291 10K/F_4 R291 10K/F_4
+3V
8
MEMHOT_SODIMM#
3
O.S
4
GND
Address:92h
MEMHOT_SODIMM#
C463 0.1u/10V_4 C463 0.1u/10V_4
MEMHOT_SODIMM# 7
4
2
Q29Q29
*2N7002E-G *2N7002E-G
R299 *33_4 R299 *33_4
3
1
2
Q28Q28
*2N7002E-G *2N7002E-G
+3V
R297
R297 *10K/F_4
*10K/F_4
3
1
3
CPU_MEMHOT# 4,14
PLACE CLOSE TO SOCKET( PER EMI/EMC)
Size D ocument Number R ev
Size D ocument Number R ev
Size D ocument Number R ev
Date: Sheet
Date: Sheet
2
Date: Sheet
PROJECT : BD3G
PROJECT : BD3G
Quanta Computer Inc.
Quanta Computer Inc.
DDR2 SODIMMS TERMINATIONS
DDR2 SODIMMS TERMINATIONS
DDR2 SODIMMS TERMINATIONS
1
of
of
of
8 42Thursday, May 29, 2008
8 42Thursday, May 29, 2008
8 42Thursday, May 29, 2008
1A
1A
1A
5
HT_CPU_NB_CAD_H0 HT_CPU_NB_CAD_L0 HT_CPU_NB_CAD_H1 HT_CPU_NB_CAD_L1 HT_CPU_NB_CAD_H2 HT_CPU_NB_CAD_L2 HT_CPU_NB_CAD_H3 HT_CPU_NB_CAD_L3 HT_CPU_NB_CAD_H4 HT_CPU_NB_CAD_L4 HT_CPU_NB_CAD_H5 HT_CPU_NB_CAD_L5
D D
C C
HT_CPU_NB_CAD_H6 HT_CPU_NB_CAD_L6 HT_CPU_NB_CAD_H7 HT_CPU_NB_CAD_L7
HT_CPU_NB_CAD_H8 HT_CPU_NB_CAD_L8 HT_CPU_NB_CAD_H9 HT_CPU_NB_CAD_L9 HT_CPU_NB_CAD_H10 HT_CPU_NB_CAD_L10 HT_CPU_NB_CAD_H11 HT_CPU_NB_CAD_L11 HT_CPU_NB_CAD_H12 HT_CPU_NB_CAD_L12 HT_CPU_NB_CAD_H13 HT_CPU_NB_CAD_L13 HT_CPU_NB_CAD_H14 HT_CPU_NB_CAD_L14 HT_CPU_NB_CAD_H15 HT_CPU_NB_CAD_L15
HT_CPU_NB_CLK_H0 HT_CPU_NB_CLK_L0 HT_CPU_NB_CLK_H1 HT_CPU_NB_CLK_L1
HT_CPU_NB_CTL_H0 HT_CPU_NB_CTL_L0 HT_CPU_NB_CTL_H1 HT_CPU_NB_CTL_L1
R476 300/F_4 R476 300/F_4
HT_RXCALP HT_RXCALN
4
Y25 Y24 V22 V23 V25 V24 U24 U25 T25 T24 P22 P23 P25 P24 N24 N25
AC24 AC25 AB25 AB24 AA24 AA25
Y22
Y23 W 21 W 20
V21
V20
U20
U21
U19
U18
T22
T23
AB23 AA22
M22 M23 R21 R20
C23
A24
U14A
U14A
HT_RXCAD0P HT_RXCAD0N HT_RXCAD1P HT_RXCAD1N HT_RXCAD2P HT_RXCAD2N HT_RXCAD3P HT_RXCAD3N HT_RXCAD4P HT_RXCAD4N HT_RXCAD5P HT_RXCAD5N HT_RXCAD6P HT_RXCAD6N HT_RXCAD7P HT_RXCAD7N
HT_RXCAD8P HT_RXCAD8N HT_RXCAD9P HT_RXCAD9N HT_RXCAD10P HT_RXCAD10N HT_RXCAD11P HT_RXCAD11N HT_RXCAD12P HT_RXCAD12N HT_RXCAD13P HT_RXCAD13N HT_RXCAD14P HT_RXCAD14N HT_RXCAD15P HT_RXCAD15N
HT_RXCLK0P HT_RXCLK0N HT_RXCLK1P HT_RXCLK1N
HT_RXCTL0P HT_RXCTL0N HT_RXCTL1P HT_RXCTL1N
HT_RXCALP HT_RXCALN
RS780(RX780)
RS780(RX780)
PART 1 OF 6
PART 1 OF 6
HYPER TRANSPORT CPU I/F
HYPER TRANSPORT CPU I/F
HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N
HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P
HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N
HT_TXCLK0P HT_TXCLK0N HT_TXCLK1P HT_TXCLK1N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
HT_TXCALP HT_TXCALN
HT_NB_CPU_CAD_H0
D24
HT_NB_CPU_CAD_L0
D25
HT_NB_CPU_CAD_H1
E24
HT_NB_CPU_CAD_L1
E25
HT_NB_CPU_CAD_H2
F24
HT_NB_CPU_CAD_L2
F25
HT_NB_CPU_CAD_H3
F23
HT_NB_CPU_CAD_L3
F22
HT_NB_CPU_CAD_H4
H23
HT_NB_CPU_CAD_L4
H22
HT_NB_CPU_CAD_H5
J25
HT_NB_CPU_CAD_L5
J24
HT_NB_CPU_CAD_H6
K24
HT_NB_CPU_CAD_L6
K25
HT_NB_CPU_CAD_H7
K23
HT_NB_CPU_CAD_L7
K22
HT_NB_CPU_CAD_H8
F21
HT_NB_CPU_CAD_L8
G21
HT_NB_CPU_CAD_H9
G20
HT_NB_CPU_CAD_L9
H21
HT_NB_CPU_CAD_H10
J20
HT_NB_CPU_CAD_L10
J21
HT_NB_CPU_CAD_H11
J18
HT_NB_CPU_CAD_L11
K17
HT_NB_CPU_CAD_H12
L19
HT_NB_CPU_CAD_L12
J19
HT_NB_CPU_CAD_H13
M19
HT_NB_CPU_CAD_L13
L18
HT_NB_CPU_CAD_H14
M21
HT_NB_CPU_CAD_L14
P21
HT_NB_CPU_CAD_H15
P18
HT_NB_CPU_CAD_L15
M18
HT_NB_CPU_CLK_H0
H24
HT_NB_CPU_CLK_L0
H25
HT_NB_CPU_CLK_H1
L21
HT_NB_CPU_CLK_L1
L20
HT_NB_CPU_CTL_H0
M24
HT_NB_CPU_CTL_L0
M25
HT_NB_CPU_CTL_H1
P19
HT_NB_CPU_CTL_L1
R18
HT_TXCALP
B24
HT_TXCALN
B25
3
R641R655
R475 300/F_4 R475 300/F_4
2
HT_CPU_NB_CAD_H[15..0]
HT_CPU_NB_CAD_L[15..0]
HT_CPU_NB_CLK_H[1..0]
HT_CPU_NB_CLK_L[1..0]
HT_CPU_NB_CTL_H[1..0]
HT_CPU_NB_CTL_L[1..0]
HT_NB_CPU_CAD_H[15..0]
HT_NB_CPU_CAD_L[15..0]
HT_NB_CPU_CLK_H[1..0]
HT_NB_CPU_CLK_L[1..0]
HT_NB_CPU_CTL_H[1..0]
HT_NB_CPU_CTL_L[1..0]
HT_CPU_NB_CAD_H[15..0] 4
HT_CPU_NB_CAD_L[15..0] 4
HT_CPU_NB_CLK_H[1..0] 4
HT_CPU_NB_CLK_L[1..0] 4
HT_CPU_NB_CTL_H[1..0] 4
HT_CPU_NB_CTL_L[1..0] 4
HT_NB_CPU_CAD_H[15..0] 4
HT_NB_CPU_CAD_L[15..0] 4
HT_NB_CPU_CLK_H[1..0] 4
HT_NB_CPU_CLK_L[1..0] 4
HT_NB_CPU_CTL_H[1..0] 4
HT_NB_CPU_CTL_L[1..0] 4
signals RS780 RX780
HT_TXCALP
HT_TXCALN
HT_RXCALP
HT_RXCALN
R641 300 ohm 1%
R655 300 ohm 1%
R641
1.21k ohm 1%
R655
1.21k ohm 1%
1
11/4 modify
RES CHIP 1.21K 1/16W +-1%(0402) P/N : CS21212FB18
RES CHIP 300 1/16W +-1%(0402) P/N : CS13002FB00
08
A12 version RS780M AJ067400T05 100-CK2612(216-0674008-00) RS780MC AJ067400T06 100-CK2613(216-0674010-00) RX781 AJ067400T10 100-CK2642(215-0674024) SB700 AJA12FG0T18 100-CK2614(218S7EALA12FG)
U14D
4
AB12 AE16
V11 AE15 AA12 AB16 AB14
AD14 AD13 AD15 AC16
AE13
AC14
Y14
AD16
AE17
AD17
W
Y12
AD18
AB13 AB18
V14
V15
W 14
AE12
AD12
12
U14D
MEM_A0(NC) MEM_A1(NC) MEM_A2(NC) MEM_A3(NC) MEM_A4(NC) MEM_A5(NC) MEM_A6(NC) MEM_A7(NC) MEM_A8(NC) MEM_A9(NC) MEM_A10(NC) MEM_A11(NC) MEM_A12(NC) MEM_A13(NC)
MEM_BA0(NC) MEM_BA1(NC) MEM_BA2(NC)
MEM_RASb(NC) MEM_CASb(NC) MEM_WEb(NC) MEM_CSb(NC) MEM_CKE(NC) MEM_ODT(NC)
MEM_CKP(NC) MEM_CKN(NC)
MEM_COMPP(NC) MEM_COMPN(NC)
RS780(RX780)
RS780(RX780)
A13 version RS780M AJ067400T18 100-CK2699(216-0674022) RS780MC AJ067400T20 100-CK2704(216-0674024) RX781 AJ067400T21 100-CK2706(215-0674034) A12 version SB700 AJA12FG0T18
B B
A A
5
This block is for UMA RS780 only , RX780 can remove all component
PAR 4 OF 6
PAR 4 OF 6
MEM_DQ0/DVO_VSYNC(NC) MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC) MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC) MEM_DQ5/DVO_D1(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7/DVO_D4(NC) MEM_DQ8/DVO_D3(NC) MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC) MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC) MEM_DQ14/DVO_D10(NC) MEM_DQ15/DVO_D11(NC)
MEM_DQS0P/DVO_IDCKP(NC) MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC) MEM_DQS1N(NC)
MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)
SBD_MEM/DVO_I/F
SBD_MEM/DVO_I/F
IOPLLVDD18(NC)
IOPLLVDD(NC)
IOPLLVSS(NC)
MEM_VREF(NC)
AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21
Y17 W18 AD20 AE21
W17 AE19
+1.8_IOPLLVDD18_NB
AE23
+1.1V_IOPLLVDD
AE24
AD23
AE18
3
R480 R479 0_6 R479 0_6
IOPLLVDD- memory PLL not applicable to RX780
2/1 R480,R479 no stuff when RS780M without side port / RX781
0_6 R480 0_6
+1.8V
+1.1V_NB
4/24 stuff R480,R479
PROJECT : BD3G
PROJECT : BD3G
Quanta Computer Inc.
Size D ocument Number R ev
Size D ocument Number R ev
Size D ocument Number R ev
Date: Sheet
Date: Sheet
2
Date: Sheet
Quanta Computer Inc.
RS740/RS780-HT LINK I/F 1/5
RS740/RS780-HT LINK I/F 1/5
RS740/RS780-HT LINK I/F 1/5
1
of
of
of
9 42Thursday, May 29, 2008
9 42Thursday, May 29, 2008
9 42Thursday, May 29, 2008
1A
1A
1A
5
U14B
PEG_RXP15 PEG_RXN15 PEG_RXP14 PEG_RXN14 PEG_RXP13 PEG_RXN13 PEG_RXP12 PEG_RXN12 PEG_RXP11 PEG_RXN11 PEG_RXP10
D D
25 PCIE_RXP0
24 PCIE_RXP2
PCIE_RXN2 24 25 PCIE_RXP3
C C
13 PCIE_SB_NB_RX0P 13 PCIE_SB_NB_RX0N 13 PCIE_SB_NB_RX1P 13 PCIE_SB_NB_RX1N 13 PCIE_SB_NB_RX2P 13 PCIE_SB_NB_RX2N 13 PCIE_SB_NB_RX3P
PCIE_SB_NB_RX3N 13
PEG_RXN10 PEG_RXP9 PEG_RXN9 PEG_RXP8 PEG_RXN8 PEG_RXP7 PEG_RXN7 PEG_RXP6 PEG_RXN6 PEG_RXP5 PEG_RXN5 PEG_RXP4 PEG_RXN4 PEG_RXP3 PEG_RXN3 PEG_RXP2 PEG_RXN2 PEG_RXP1 PEG_RXN1 PEG_RXP0 PEG_RXN0
PCIE_RXP0
PCIE_RXN0 25 PCIE_RXP1 25 PCIE_RXN1 25
PCIE_RXN3 25
PCIE_RXN0 PCIE_RXP1 PCIE_RXN1 PCIE_RXP2 PCIE_RXN2 PCIE_RXP3 PCIE_RXN3
U14B
D4
GFX_RX0P
C4
GFX_RX0N
A3
GFX_RX1P
B3
GFX_RX1N
C2
GFX_RX2P
C1
GFX_RX2N
E5
GFX_RX3P
F5
GFX_RX3N
G5
GFX_RX4P
G6
GFX_RX4N
H5
GFX_RX5P
H6
GFX_RX5N
J6
GFX_RX6P
J5
GFX_RX6N
J7
GFX_RX7P
J8
GFX_RX7N
L5
GFX_RX8P
L6
GFX_RX8N
M8
GFX_RX9P
L8
GFX_RX9N
P7
GFX_RX10P
M7
GFX_RX10N
P5
GFX_RX11P
M5
GFX_RX11N
R8
GFX_RX12P
P8
GFX_RX12N
R6
GFX_RX13P
R5
GFX_RX13N
P4
GFX_RX14P
P3
GFX_RX14N
T4
GFX_RX15P
T3
GFX_RX15N
AE3
GPP_RX0P
AD4
GPP_RX0N
AE2
GPP_RX1P
AD3
GPP_RX1N
AD1
GPP_RX2P
AD2
GPP_RX2N
V5
GPP_RX3P
W6
GPP_RX3N
U5
GPP_RX4P
U6
GPP_RX4N
U8
GPP_RX5P
U7
GPP_RX5N
AA8
SB_RX0P
Y8
SB_RX0N
AA7
SB_RX1P
Y7
SB_RX1N
AA5
SB_RX2P
AA6
SB_RX2N
W5
SB_RX3P
Y5
SB_RX3N
RS780(RX780)
RS780(RX780)
PART 2 OF 6
PART 2 OF 6
PCIE I/F GFX
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F GPP
PCIE I/F SB
PCIE I/F SB
PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)
4
GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P
GFX_TX9N GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N
SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N
A5 B5 A4 B4 C3 B2 D1 D2 E2 E1 F4 F3 F1 F2 H4 H3 H1 H2 J2 J1 K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2
AC1 AC2 AB4 AB3 AA2 AA1 Y1 Y2 Y4 Y3 V1 V2
AD7 AE7 AE6 AD6 AB6 AC6 AD5 AE5
AC8 AB8
C_PEG_TXP15 C_PEG_TXN15 C_PEG_TXP14 C_PEG_TXN14 C_PEG_TXP13 C_PEG_TXN13 C_PEG_TXP12 C_PEG_TXN12 C_PEG_TXP11 C_PEG_TXN11 C_PEG_TXP10 C_PEG_TXN10 C_PEG_TXP9 C_PEG_TXN9 C_PEG_TXP8 C_PEG_TXN8 C_PEG_TXP7 C_PEG_TXN7 C_PEG_TXP6 C_PEG_TXN6 C_PEG_TXP5 C_PEG_TXN5 C_PEG_TXP4 C_PEG_TXN4 C_PEG_TXP3 C_PEG_TXN3 C_PEG_TXP2 C_PEG_TXN2 C_PEG_TXP1 C_PEG_TXN1 C_PEG_TXP0 C_PEG_TXN0
PCIE_TXP0_C PCIE_TXN0_C PCIE_TXP1_C PCIE_TXN1_C PCIE_TXP2_C PCIE_TXN2_C PCIE_TXP3_C PCIE_TXN3_C
A_TX0P_CA_TX0P_C A_TX0N_CA_TX0N_C A_TX1P_CA_TX1P_C A_TX1N_CA_TX1N_C A_TX2P_C A_TX2N_C A_TX3P_C A_TX3N_C
NB_PCIECALRP NB_PCIECALRN
3
C587 EV@0.1u/10V_4 C587 EV@0.1u/10V_4 C586 EV@0.1u/10V_4 C586 EV@0.1u/10V_4 C589 EV@0.1u/10V_4 C589 EV@0.1u/10V_4 C588 EV@0.1u/10V_4 C588 EV@0.1u/10V_4 C591 EV@0.1u/10V_4C591 EV@0.1u/10V_4 C590 EV@0.1u/10V_4 C590 EV@0.1u/10V_4 C593 EV@0.1u/10V_4 C593 EV@0.1u/10V_4 C592 EV@0.1u/10V_4 C592 EV@0.1u/10V_4 C595 EV@0.1u/10V_4 C595 EV@0.1u/10V_4 C594 EV@0.1u/10V_4 C594 EV@0.1u/10V_4 C600 EV@0.1u/10V_4 C600 EV@0.1u/10V_4 C596 EV@0.1u/10V_4 C596 EV@0.1u/10V_4 C605 EV@0.1u/10V_4 C605 EV@0.1u/10V_4 C603 EV@0.1u/10V_4 C603 EV@0.1u/10V_4 C607 EV@0.1u/10V_4 C607 EV@0.1u/10V_4 C606 EV@0.1u/10V_4 C606 EV@0.1u/10V_4 C609 EV@0.1u/10V_4 C609 EV@0.1u/10V_4 C608 EV@0.1u/10V_4 C608 EV@0.1u/10V_4 C611 EV@0.1u/10V_4 C611 EV@0.1u/10V_4 C610 EV@0.1u/10V_4 C610 EV@0.1u/10V_4 C613 EV@0.1u/10V_4 C613 EV@0.1u/10V_4 C145 HDM@0.1u/10V_4 C145 HDM@0.1u/10V_4 C612 EV@0.1u/10V_4 C612 EV@0.1u/10V_4 C615 EV@0.1u/10V_4 C615 EV@0.1u/10V_4 C614 EV@0.1u/10V_4 C614 EV@0.1u/10V_4 C624 EV@0.1u/10V_4 C624 EV@0.1u/10V_4 C617 EV@0.1u/10V_4 C617 EV@0.1u/10V_4 C654 EV@0.1u/10V_4 C654 EV@0.1u/10V_4 C653 EV@0.1u/10V_4 C653 EV@0.1u/10V_4 C662 EV@0.1u/10V_4 C662 EV@0.1u/10V_4 C660 EV@0.1u/10V_4 C660 EV@0.1u/10V_4 C647 EV@0.1u/10V_4 C647 EV@0.1u/10V_4 C627 EV@0.1u/10V_4 C627 EV@0.1u/10V_4
C453 0.1u/10V_4 C453 0.1u/10V_4 C452 0.1u/10V_4 C452 0.1u/10V_4 C530 0.1u/10V_4 C530 0.1u/10V_4 C531 0.1u/10V_4 C531 0.1u/10V_4 C744 0.1u/10V_4 C744 0.1u/10V_4 C743 0.1u/10V_4 C743 0.1u/10V_4 C680 0.1u/10V_4 C680 0.1u/10V_4 C740 0.1u/10V_4 C740 0.1u/10V_4
C626 0.1u/10V_4 C626 0.1u/10V_4 C625 0.1u/10V_4 C625 0.1u/10V_4 C649 0.1u/10V_4 C649 0.1u/10V_4 C630 0.1u/10V_4 C630 0.1u/10V_4 C655 0.1u/10V_4 C655 0.1u/10V_4 C656 0.1u/10V_4 C656 0.1u/10V_4 C665 0.1u/10V_4 C665 0.1u/10V_4 C663 0.1u/10V_4 C663 0.1u/10V_4
R58 1.27K/F_4 R58 1.27K/F_4 R56 2K/F_4 R56 2K/F_4
PEG_TXP15 PEG_TXN15 PEG_TXP14 PEG_TXN14 PEG_TXP13 PEG_TXN13 PEG_TXP12 PEG_TXN12 PEG_TXP11 PEG_TXN11 PEG_TXP10 PEG_TXN10 PEG_TXP9 PEG_TXN9 PEG_TXP8 PEG_TXN8 PEG_TXP7 PEG_TXN7 PEG_TXP6 PEG_TXN6 PEG_TXP5 PEG_TXN5 PEG_TXP4 PEG_TXN4 PEG_TXP3 PEG_TXN3 PEG_TXP2 PEG_TXN2 PEG_TXP1 PEG_TXN1 PEG_TXP0 PEG_TXN0
PCIE_TXP0 25
PCIE_TXN0 25
PCIE_TXP1 25
PCIE_TXN1 25 PCIE_TXP2 24 PCIE_TXN2 24
PCIE_TXP3 25
PCIE_TXN3 25
PCIE_NB_SB_TX0P 13 PCIE_NB_SB_TX0N 13 PCIE_NB_SB_TX1P 13 PCIE_NB_SB_TX1N 13 PCIE_NB_SB_TX2P 13 PCIE_NB_SB_TX2N 13 PCIE_NB_SB_TX3P 13 PCIE_NB_SB_TX3N 13
+1.1V_NB
21 PEG_RXN[15:0]
PEG_RXP[15:0] 21
TO WLAN
TO MINI CARD
TO PCIE-LAN
TO EPRESS CARD
PEG_RXN[15:0]
PEG_RXP[15:0]
Close to North Bridge
C_PEG_TXP15 C_PEG_TXN15
C_PEG_TXP14 C_PEG_TXN14
C_PEG_TXP13 C_PEG_TXN13
C_PEG_TXP12 C_PEG_TXN12
2
PEG_TXN[15:0]
PEG_TXP[15:0]
PEG_TXN[15:0] 21
PEG_TXP[15:0] 21
BTO
Close to North Bridge
C159 HDM@0.1u/10V_4 C159 HDM@0.1u/10V_4 C160 HDM@0.1u/10V_4 C160 HDM@0.1u/10V_4
C152 HDM@0.1u/10V_4 C152 HDM@0.1u/10V_4 C158 HDM@0.1u/10V_4 C158 HDM@0.1u/10V_4
C150 HDM@0.1u/10V_4 C150 HDM@0.1u/10V_4
C140 HDM@0.1u/10V_4 C140 HDM@0.1u/10V_4 C144 HDM@0.1u/10V_4 C144 HDM@0.1u/10V_4
NOTE:
RS780MC no support Graphic / HDMI
1
IV_HDMITX2P 19
IV_HDMITX2N 19
IV_HDMITX1P 19
IV_HDMITX1N 19
IV_HDMITX0P 19
IV_HDMITX0N 19
IV_HDMICLK+ 19
IV_HDMICLK- 19
To HDMI CONN
9
11/4 modify
B B
A A
RX780/RS740/RS780 difference table (PCIE LINK)
NB_PCIECALRP
GPP4
GPP5
5
RS740 RX780/RS780
562R (GND)
NC
NC
1.27K (GND)
GPP4
GPP5
RS780 Display Port Support (muxed on GFX)
DP0
DP1
4
GFX_TX0,TX1,TX2 and TX3
AUX0 and HPD0
GFX_TX4,TX5,TX6 and TX7
AUX1 and HPD1
PROJECT : BD3G
PROJECT : BD3G
Quanta Computer Inc.
Size Doc ument Number Rev
Size Doc ument Number Rev
Size Doc ument Number Rev
Date: Sheet
Date: Sheet of
3
2
Date: Sheet of
Quanta Computer Inc.
RS740/RS780-PCIE I/F 2/5
RS740/RS780-PCIE I/F 2/5
RS740/RS780-PCIE I/F 2/5
1
of
10 42Thursday, May 29, 2008
10 42Thursday, May 29, 2008
10 42Thursday, May 29, 2008
1A
1A
1A
5
RX780: Powered from the 1.8-V rail and driven by SB600 LDT_RST#, or SB700 LDT_RST# or A_RST#. RS780: Powered from the 3.3-V rail and driven by SB600 LDT_RST#, or SB700 LDT_RST# or A_RST#.
RX780
CPU_LDT_RST# 4,13
RS780
D D
NB_PLTRST# 13
R30 *0_4 R30 *0_4
R31 0_4 R31 0_4
North Bridge RESET
10/26 change to 4 pin S-video conn , no need TV_comp
2/1 follow A13 request change R103 from 150 to 140 CS11402FB19
NB_RST#_IN
11/4 stuff R5160 for RS780M/MC/RX781
RX780
+1.1V_NB
10/9 add 2K pull up to DDCDAT /DDCCLK for RX780
R47 *2K/F_4 R47 *2K/F_4
R46 *2K/F_4 R46 *2K/F_4
INT_CRT_DDCDAT
INT_CRT_DDCCLK
11/4 no stuff for RS780M/MC/RX781
12/22 stuff R48 2.2K for power play
C C
+NB_CORE_ON
selects Loading of straps from EPROM 1 : use default vaule , default 0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected RX780 --RS780_AUX_CAL RS780 -- SUS_ATAT
Enables Debug Bus acess through memory T/O pads and GPIO.
B B
1 : Enable RX780 , Default 0 : Disable RX780
R44 *10K/F_4 R44 *10K/F_4
R48 2.2K_4 R48 2.2K_4
+3V
RS780_AUX_CAL
INT_TV_C/R
RX780
R491 *3K_4 R491 *3K_4
RX780
R96 *3K_4 R96 *3K_4
Reserved only
12/22 stuff R65
Enables Debug Bus acess through memory T/O pads and GPIO. 1 : Enable RS780 , Default 0 : Disable RS780 (RS780 use VSYNC#)
Indicates if memory Side port is available or not 0: available RS780 , Default 1: Not available RS780 ( RS780 use HSYNC#)
A A
10/19 RS780M Databook rev 1.01 define High disable
5
INT_VSYNC
INT_HSYNC
RS780
R65 3K_4 R65 3K_4
R66 *3K_4 R66 *3K_4
RS780
R489 3K_4 R489 3K_4
R490 *3K_4 R490 *3K_4
4
18 INT_TV_C/R
INT_TV_Y/G 18
INT_CRT_RED 18
INT_CRT_GRN 18
INT_CRT_BLU 18
18 INT_HSYNC 18 INT_VSYNC
18 INT_CRT_DDCDAT
INT_CRT_DDCCLK 18
NB_PWRGD_IN 17
NBHT_REFCLKP 3
NBHT_REFCLKN 3
EXT_NB_OSC 3
+1.1V_NB
3 NBGFX_CLKP
NBGFX_CLKN 3
3 NBGPP_CLKP
NBGPP_CLKN 3
3 SBLINK_CLKP
SBLINK_CLKN 3
20 INT_LVDS_EDIDDATA
INT_LVDS_EDIDCLK 20
IV_HDMI_DDCDATA 19 IV_HDMI_DDCCLK 19
+3V
+3V
4
R95 IV@150/F_4 R95 IV@150/F_4 R89 IV@150/F_4 R89 IV@150/F_4 R84 *150/F_4 R84 *150/F_4
R103 IV@140/F_4 R103 IV@140/F_4
R99 IV@ 150/F_4 R99 IV@150/F_4
R102 IV@150/F_4 R102 IV@150/F_4
R79 IV@715/F_6 R79 IV@715/F_6
R50R50
RS780
4.7K_4 4.7K_4
+3V
BLM18PG221SN1D(220,1.4A)_6
BLM18PG221SN1D(220,1.4A)_6
AVDD-DAC Analog not applicable to RX780
+1.8V
BLM18PG221SN1D(220,1.4A)_6
BLM18PG221SN1D(220,1.4A)_6
C124
C124 10u/6.3V_8
10u/6.3V_8
PLLVDD18 - Graphics PLL not applicable to RX780
+1.8V
VDDA18PCIEPLL -PCIE PLL
BLM18PG221SN1D(220,1.4A)_6
BLM18PG221SN1D(220,1.4A)_6
R54R54
RS780
4.7K_4 4.7K_4
+NB_CORE_ON 35
L2
L2
L12
L12
2.2u/6.3V_6
2.2u/6.3V_6
L1
L1
VDDA18HTPLL -HT LINK PLL
L13
L13
BLM18PG221SN1D(220,1.4A)_6
BLM18PG221SN1D(220,1.4A)_6
R485 0_4 R485 0_4 R53 0_4 R53 0_4
INT_LVDS_EDIDDATA INT_LVDS_EDIDCLK IV_HDMI_DDCDATA IV_HDMI_DDCCLK
T145 T145 T144 T144
R49 0_4 R49 0_4
T143 T143
+3V_AVDD_NB
C104
C104
2.2u/6.3V_6
2.2u/6.3V_6
+1.8V_PLLVDD18
C110
C110
20mils width
+1.8V_VDDA18PCIEPLL
C79
C79
2.2u/6.3V_6
2.2u/6.3V_6
20mils width
+1.8V_VDDA18HTPLL
C131
C131
2.2u/6.3V_6
2.2u/6.3V_6
+3V_AVDD_NB
+1.8V_AVDDDI_NB
+1.8V_AVDDQ_NB
INT_TV_C/R INT_TV_Y/G INT_TV_COMP
INT_CRT_RED
INT_CRT_GRN
INT_CRT_BLU
INT_HSYNC INT_VSYNC INT_CRT_DDCDAT INT_CRT_DDCCLK
DAC_RSET_NBDAC_RSET_NB
+1.1V_PLLVDD +1.8V_PLLVDD18
+1.8V_VDDA18HTPLL
+1.8V_VDDA18PCIEPLL
NB_RST#_IN NB_PWRGD_IN NB_LDT_STOP# NB_ALLOW_LDTSTOP
NBHT_REFCLKP NBHT_REFCLKN
NB_REFCLK_P NB_REFCLK_N
NBGFX_CLKP NBGFX_CLKN
NBGPP_CLKP NBGPP_CLKN
SBLINK_CLKP SBLINK_CLKN
RS740_DFT_GPIO1
RS780_AUX_CAL
+1.1V_NB
+1.8V
3
U14C
U14C
F12
AVDD1(NC)
E12
AVDD2(NC)
F14
AVDDDI(NC)
G15
AVSSDI(NC)
H15
AVDDQ(NC)
H14
AVSSQ(NC)
E17
C_Pr(DFT_GPIO5)
F17
Y(DFT_GPIO2)
F15
COMP_Pb(DFT_GPIO4)
G18
RED(DFT_GPIO0)
G17
REDb(NC)
E18
GREEN(DFT_GPIO1)
F18
GREENb(NC)
E19
BLUE(DFT_GPIO3)
F19
BLUEb(NC)
A11
DAC_HSYNC(PWM_GPIO4)
B11
DAC_VSYNC(PWM_GPIO6)
E8
DAC_SDA(PCE_TCALRN)
F8
DAC_SCL(PCE_RCALRN)
G14
DAC_RSET(PWM_GPIO1)
A12
PLLVDD(NC)
D14
PLLVDD18(NC)
B12
PLLVSS(NC)
H17
VDDA18HTPLL
D7
VDDA18PCIEPLL1
E7
VDDA18PCIEPLL2
D8
SYSRESETb
A10
POWERGOOD
C10
LDTSTOPb
C12
ALLOW_LDTSTOP
C25
HT_REFCLKP
C24
E11 F11
T2 T1
U1 U2
V4 V3
A9 B9 B8 A8 B7 A7
STRP_DATA
B10
G11
C8
BLM18PG221SN1D(220,1.4A)_6
BLM18PG221SN1D(220,1.4A)_6
L52
L52
R76 0_6 R76 0_6
BLM18PG221SN1D(220,1.4A)_6
BLM18PG221SN1D(220,1.4A)_6
L17
L17
1/31 voltage leakage issue remove Q5,Q3,R83,R80,R97 stuff R88,R77
CPU_LDT_STOP# 4,13
CPU_LDT_REQ# 4
ALLOW_LDTSTOP 13
3
I
HT_REFCLKN
REFCLK_P/OSCIN(OSCIN) REFCLK_N(PWM_GPIO3)
GFX_REFCLKP
I/O
GFX_REFCLKN
GPP_REFCLKP
I/O
GPP_REFCLKN
GPPSB_REFCLKP(SB_REFCLKP) GPPSB_REFCLKN(SB_REFCLKN)
I2C_DATA I2C_CLK DDC_DATA/AUX0N(NC) DDC_CLK/AUX0P(NC) AUX1P(NC) AUX1N(NC)
STRP_DATA
RSVD
AUX_CAL(NC)
RS780(RX780)
RS780(RX780)
+1.1V_PLLVDD
C646
C646
2.2u/6.3V_6
2.2u/6.3V_6
+1.8V_AVDDDI_NB
C98
C98
2.2u/6.3V_6
2.2u/6.3V_6
+1.8V_AVDDQ_NB
C136
C136
2.2u/6.3V_6
2.2u/6.3V_6
Q5Q5 *BSS138_NL/SOT23 *BSS138_NL/SOT23
Q3Q3
*BSS138_NL/SOT23 *BSS138_NL/SOT23
R74 0_4 R74 0_4
PART 3 OF 6
PART 3 OF 6
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3N(DBG_GPIO2)
TXOUT_U1P(PCIE_RESET_GPIO3) TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U3P(PCIE_RESET_GPIO5)
CRT/TVOUT
CRT/TVOUT
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3) TXCLK_UP(PCIE_RESET_GPIO4) TXCLK_UN(PCIE_RESET_GPIO1)
LVTM
LVTM
PM
PM
I
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
CLOCKs PLL PWR
CLOCKs PLL PWR
MIS.
MIS.
TVCLKIN(PWM_GPIO5)
THERMALDIODE_P
THERMALDIODE_N
PLLVDD - Graphics PLL not applicable to RX780
AVDDI-DAC Digital not applicable to RX780
AVDDQ-DAC Bandgap Reference not applicable to RX780
+1.8V +VDDG_NB
2
+1.8V
2
R77 0_4 R77 0_4
3
+VDDG_NB
3
1
R88 0_4 R88 0_4
RS780
1
RS780
TXOUT_L0P(NC) TXOUT_L0N(NC) TXOUT_L1P(NC) TXOUT_L1N(NC) TXOUT_L2P(NC)
TXOUT_L3P(NC)
TXOUT_U0P(NC) TXOUT_U0N(NC)
TXOUT_U2P(NC) TXOUT_U2N(NC)
TXOUT_U3N(NC)
VDDLTP18(NC)
VSSLTP18(NC)
VDDLT18_1(NC) VDDLT18_2(NC) VDDLT33_1(NC) VDDLT33_2(NC)
VSSLT1(VSS) VSSLT2(VSS) VSSLT3(VSS) VSSLT4(VSS) VSSLT5(VSS) VSSLT6(VSS) VSSLT7(VSS)
TMDS_HPD(NC)
HPD(NC)
TESTMODE
R83R83 *4.7K_4 *4.7K_4
NB_LDT_STOP#
R80R80 *4.7K_4 *4.7K_4
NB_ALLOW_LDTSTOP
2
A22 B22 A21 B21 B20 A20 A19 B19
B18 A18 A17 B17 D20 D21 D18 D19
B16 A16 D16 D17
+1.8V_VDDLTP18_NB
A13 B13
+1.8V_VDDLT_18_NB
A15 B15 A14 B14
C14 D15 C16 C18 C20 E20 C22
E9 F7 G12
TMDS_HPD0
D9
TMDS_HPD1
D10
SUS_STAT#_NB
D12
R_NB_THRMDA
AE8
R_NB_THRMDC
AD8
TEST_EN
D13
1/17 RX781 connect to GND C104,C110,C646,C98,C136,C103,C118 change to CS00003J951
+1.8V
L51
L51
L10
L10
2
INT_TXLOUT0+ 20 INT_TXLOUT0- 20 INT_TXLOUT1+ 20 INT_TXLOUT1- 20 INT_TXLOUT2+ 20 INT_TXLOUT2- 20
T139 T139 T137 T137
INT_TXUOUT0+ 20 INT_TXUOUT0- 20 INT_TXUOUT1+ 20 INT_TXUOUT1- 20 INT_TXUOUT2+ 20 INT_TXUOUT2- 20
T140 T140 T138 T138
INT_TXLCLKOUT+ 20 INT_TXLCLKOUT- 20 INT_TXUCLKOUT+ 20 INT_TXUCLKOUT- 20
+3V_VDLT33_NB
11/01 exchange LVDS_PWM /LVDS_BLON
R25 *1.27K/F_4 R25 *1.27K/F_4
R11 *1.27K/F_4 R11 *1.27K/F_4
R26
R26 IV@0_4
IV@0_4
T2 T2
R71 0_4 R71 0_4
T142 T142 T141 T141
R75R75
1.82K/F_4 1.82K/F_4
BLM18PG221SN1D(220,1.4A)_6
BLM18PG221SN1D(220,1.4A)_6
C103C103
2.2u/6.3V_6 2.2u/6.3V_6
BLM21PG221SN1D(220,100M,2A)_8
BLM21PG221SN1D(220,100M,2A)_8
C118
C118
0.1u/10V_4
0.1u/10V_4
4.7u/6.3V_6
4.7u/6.3V_6
RX780
RS780
+3V
*BLM21PG221SN1D(220,100M,2A)_8
*BLM21PG221SN1D(220,100M,2A)_8
VDDLT33 - LVDS or DVI/HDMI ANALOG RS740 only
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
INT_LVDS_DIGON 20 INT_LVDS_PWM 20 INT_LVDS_BLON 20
For RX780 only
IV_HDMI_HPD 19
SUS_STAT# 14
+1.8V_VDDLTP18_NB
VDDLTP18 - LVDS or DVI/HDMI PLL not applicable to RX780
+1.8V_VDDLT_18_NB
1/17 RX781 no stuff them
C115
C115
L2,L12,C124,L52,R76,L17,L51,L10,C115
R100 *0_6 R100 *0_6
+1.8V +VDDG_NB
R97 *0_6 R97 *0_6
+3V
L9
L9
1
VDDLT18 - LVDS or DVI/HDMI digital not applicable to RX780
+3V_VDLT33_NB
C108
C108
*2.2u/6.3V_6
*2.2u/6.3V_6
PROJECT : BD3G
PROJECT : BD3G
Quanta Computer Inc.
Quanta Computer Inc.
RS740/RS780-SYSTEM I/F 3/5
RS740/RS780-SYSTEM I/F 3/5
RS740/RS780-SYSTEM I/F 3/5
1
10
of
of
of
11 42Thursday, May 29, 2008
11 42Thursday, May 29, 2008
11 42Thursday, May 29, 2008
1A
1A
1A
5
4
3
2
1
1
11
C807C807 *0.1u/10V_4 *0.1u/10V_4
12 42Thursday, May 29, 2008
12 42Thursday, May 29, 2008
12 42Thursday, May 29, 2008
+NB_CORE
of
of
of
1A
1A
1A
D11
E14
E15
J12
K14
L7
U14F
U14F
D D
C C
VSSAPCIE1A2VSSAPCIE2B1VSSAPCIE3D3VSSAPCIE4D5VSSAPCIE5E4VSSAPCIE6G1VSSAPCIE7G2VSSAPCIE8G4VSSAPCIE9
PART 6/6
PART 6/6
VSSAHT1
VSSAHT2
A25
D23
VDDHTRX - HT LINK RX I/O for RX780/RS780
+1.2V 2A for RS780M+SB700
+1.2V
BLM21PG221SN1D(220,100M,2A)_8
BLM21PG221SN1D(220,100M,2A)_8
+1.35V for A1-1 chip bug , A1-2 can remove
B B
VDDA18PCIE ­PCIE TX stage I/O for RX780/RS780
A A
+1.8V 1A for RS780M+SB700
+1.8V
BLM21PG221SN1D(220,100M,2A)_8
BLM21PG221SN1D(220,100M,2A)_8
H7
VSSAPCIE10J4VSSAPCIE11R7VSSAPCIE12L1VSSAPCIE13L2VSSAPCIE14L4VSSAPCIE15
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
J22
L17
L22
E22
G22
VDDHT - HT LINK digital I/O for RX780/RS780
VDDHTTX - HT LINK TX I/O for RX780/RS780
L24
H19
G24
G25
L36
L36
L3
L3
VDD18 - RS780 I/O transform
5
VSSAPCIE16M6VSSAPCIE17N4VSSAPCIE18P6VSSAPCIE19R1VSSAPCIE20R2VSSAPCIE21R4VSSAPCIE22V7VSSAPCIE23U4VSSAPCIE24V8VSSAPCIE25V6VSSAPCIE26W1VSSAPCIE27W2VSSAPCIE28W4VSSAPCIE29W7VSSAPCIE30W8VSSAPCIE31Y6VSSAPCIE32
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT20
L25
N22
M20
+1.1V_NB
0.6A
0.45A
P20
V19
R19
R22
R24
R25
U22
H20
W22
W24
W25
+1.1V 2A for RS780M
L11
L11 BLM21PG221SN1D(220,100M,2A)_8
BLM21PG221SN1D(220,100M,2A)_8
L18
L18 BLM21PG221SN1D(220,100M,2A)_8
BLM21PG221SN1D(220,100M,2A)_8
0.5A
C601C601
4.7U/6.3V_6 4.7U/6.3V_6
12/14 del L15 stuff L36 for A12
600mA
C95C95
C94C94
4.7U/6.3V_6 4.7U/6.3V_6
4.7U/6.3V_6 4.7U/6.3V_6
+1.8V
VDD18_MEM For UMA RS780 only Not applicable to RX780 memory I/O transform
+1.8V
GROUND
GROUND
VSSAHT26
VSSAHT27
VSS11
VSS12
VSS13
L12
Y21
N13
M14
AD25
C121C121
4.7U/6.3V_6 4.7U/6.3V_6
C143C143
4.7U/6.3V_6 4.7U/6.3V_6
C117C117
0.1u/10V_4 0.1u/10V_4
C93C93
0.1u/10V_4 0.1u/10V_4
R70 0_6 R70 0_6
R484 0_6 R484 0_6
AA4
VSS14
P12
AB5
AB1
VSSAPCIE33
VSSAPCIE34
VSS15
VSS16
P15
R11
C126C126
0.1u/10V_4 0.1u/10V_4
AB7
VSSAPCIE35
VSS17
R14
AC3
T12
0.005A
C89
C89 1u/10V_4
1u/10V_4
0.005A
AE14
AC4
AE1
AE4
AB2
VSS2
VSS1
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
V12
U14
C114C114
0.1u/10V_4 0.1u/10V_4
C125C125
0.1u/10V_4 0.1u/10V_4
C90C90
0.1u/10V_4 0.1u/10V_4
AA14
U11
U15
W11
W15
AC12
+1.1V_VDDHT
C116C116
0.1u/10V_4 0.1u/10V_4
+1.1V_VDDHTRX
C142C142
0.1u/10V_4 0.1u/10V_4
+1.2V_VDDHTTX
C120C120
0.1u/10V_4 0.1u/10V_4
+1.8V_VDDA18PCIE
C88C88
0.1u/10V_4 0.1u/10V_4
C616C616 *1u/10V_4 *1u/10V_4
1/17 RX781 no stuff them R484
1/17 RX781 connect to GND C616 change to CS00002JB38
4
M11
J15
VSS3G8VSS4
VSS5
VSS7
VSS8
VSS6
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
Y18
AB11
AB15
AB17
AB19
AE20
AB21
C123C123
0.1u/10V_4 0.1u/10V_4
C141C141
0.1u/10V_4 0.1u/10V_4
C129C129
0.1u/10V_4 0.1u/10V_4
C91C91
0.1u/10V_4 0.1u/10V_4
+1.8V_VDDG18_NB
+1.8V_VDD18_MEM
L15
VSS9
VSS10
VSS34
VSS33
K11
U14E
U14E
J17
VDDHT_1
K16
VDDHT_2
L16
VDDHT_3
M16
VDDHT_4
P16
VDDHT_5
R16
VDDHT_6
T16
VDDHT_7
H18
VDDHTRX_1
G19
VDDHTRX_2
F20
VDDHTRX_3
E21
VDDHTRX_4
D22
VDDHTRX_5
B23
VDDHTRX_6
A23
VDDHTRX_7
AE25
VDDHTTX_1
AD24
VDDHTTX_2
AC23
VDDHTTX_3
AB22
VDDHTTX_4
AA21
VDDHTTX_5
Y20
VDDHTTX_6
W
19
VDDHTTX_7
V18
VDDHTTX_8
U17
VDDHTTX_9
T17
VDDHTTX_10
R17
VDDHTTX_11
P17
VDDHTTX_12
M17
VDDHTTX_13
J10
VDDA18PCIE_1
P10
VDDA18PCIE_2
K10
VDDA18PCIE_3
M10
VDDA18PCIE_4
L10
VDDA18PCIE_5
W9
VDDA18PCIE_6
H9
VDDA18PCIE_7
T10
VDDA18PCIE_8
R10
VDDA18PCIE_9
Y9
VDDA18PCIE_10
AA9
VDDA18PCIE_11
AB9
VDDA18PCIE_12
AD9
VDDA18PCIE_13
AE9
VDDA18PCIE_14
U10
VDDA18PCIE_15
F9
VDDG18_1(VDD18_1)
G9
VDDG18_2(VDD18_2)
AE11
VDD18_MEM1(NC)
AD11
VDD18_MEM2(NC)
RS780(RX780)
RS780(RX780)
PART 5/6
PART 5/6
VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8
VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17
VDDC_10 VDDC_11
POWER
POWER
VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22
VDD_MEM1(NC) VDD_MEM2(NC) VDD_MEM3(NC) VDD_MEM4(NC) VDD_MEM5(NC) VDD_MEM6(NC)
VDDG33_1(NC) VDDG33_2(NC)
3
PIN NAME
VDDHT
VDDHTRX
VDDHTTX
VDDA18PCIE
VDD18_MEM
VDDPCIE
VDDC
VDD_MEM
VDDG33
IOPLLVDD18
VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8 VDDC_9
RX780/RS780 POWER DIFFERENCE TABLE
RX780
+1.1V
+1.1V
+1.2V
+1.8V
+1.8VVDDG18
NC
+1.1V +1.1V +1.8V
+1.1V
+1.8V/1.5V
NC
NC
+1.1V_VDD_PCIE
A6 B6 C6 D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9
K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16
AE10 AA11 Y11 AD10 AB10 AC10
H11 H12
C77C77
0.1u/10V_4 0.1u/10V_4
C96C96
0.1u/10V_4 0.1u/10V_4
C102C102
0.1u/10V_4 0.1u/10V_4
+1.8V_VDD_MEM
+3V_VDDG33
C92C92
0.1u/10V_4 0.1u/10V_4
PIN NAME
RS780
IOPLLVDD
+1.1V
+1.1V
+1.2V
AVDDDI
AVDDQ
+1.8V
PLLVDD
+1.8V
+1.8V
PLLVDD18
VDDA18PCIEPLL
+1.1V
VDDA18HTPLL
VDDLTP18
VDDLT18
+3.3V
VDDLT33
+1.8VNC
C86
C86
C85C85
1u/10V_4
1u/10V_4
0.1u/10V_4 0.1u/10V_4
C111C111
C100C100
0.1u/10V_4 0.1u/10V_4
0.1u/10V_4 0.1u/10V_4
C109C109
0.1u/10V_4 0.1u/10V_4
10/18 follow AMD design guide 1.0
1.8V(0.15A)
R27 0_6 R27 0_6
C99C99
0.1u/10V_4 0.1u/10V_4
RX780 RS780
NC
+1.1V
NC
+3.3VAVDD
NC +1.8V
NC +1.8V
NC
+1.1V
NC
+1.8V
+1.8V
+1.8V
+1.8V
+1.8V
NC
+1.8V
NC
NC
NC
0.7A
C76
C76 1u/10V_4
1u/10V_4
C105C105
0.1u/10V_4 0.1u/10V_4
C113C113
0.1u/10V_4 0.1u/10V_4
R67 *0_6 R67 *0_6
R57 0_6 R57 0_6
RS780
3.3V(0.03A)
VDD33 - 3.3V I/O Not applicable to RX780
2
VDDPCIE - PCIE-E Main power
R55 0_8 R55 0_8
C78C78
4.7U/6.3V_6 4.7U/6.3V_6
2/13 EMI stuff C804~C807 for +NB_CORE
VDDC - Core Logic power
7A
C598
C598
10u/6.3V_8
10u/6.3V_8
C597
C597
10u/6.3V_8
10u/6.3V_8
+1.8V
Size D ocument Number R ev
Size D ocument Number R ev
Size D ocument Number R ev
Date: Sheet
Date: Sheet
Date: Sheet
+1.1V_NB
C804C804
C805C805 *0.1u/10V_4 *0.1u/10V_4
C806C806
0.1u/10V_4 0.1u/10V_4
0.1u/10V_4 0.1u/10V_4
5/28 del C805,C807
VDD_MEM For UMA RS780 only Not applicable to RX780 memory I/O transform
+3V
PROJECT : BD3G
PROJECT : BD3G
Quanta Computer Inc.
Quanta Computer Inc.
RS740/RS780-POWER5/5
RS740/RS780-POWER5/5
RS740/RS780-POWER5/5
5
4
3
2
1
2/4 reserve C800 PLTRST#
Q33
Q33 MMBT3904
MMBT3904
13
2
12
+3V
C317
C317
1u/10V_4
1u/10V_4
of
of
of
13 42Thursday, May 29, 2008
13 42Thursday, May 29, 2008
13 42Thursday, May 29, 2008
C316
C316
0.1u/10V_4
0.1u/10V_4
1A
1A
1A
NB_PLTRST# 11
C800
C800
PLTRST#
*.1U_4
*.1U_4
D D
PLACE THESE PCIE AC COUPLING CAPS CLOSE TO U600
+1.2V
PLTRST# 19,21,24,25,27,29
10 PCIE_SB_NB_RX0P
PCIE_SB_NB_RX0N 10 10 PCIE_SB_NB_RX1P 10 PCIE_SB_NB_RX1N
PCIE_SB_NB_RX2P 10
PCIE_SB_NB_RX2N 10 10 PCIE_SB_NB_RX3P
PCIE_SB_NB_RX3N 10
PCIE_NB_SB_TX0P 10
To RS780
PCIE_NB_SB_TX0N 10
10 PCIE_NB_SB_TX1P
PCIE_NB_SB_TX1N 10 10 PCIE_NB_SB_TX2P 10 PCIE_NB_SB_TX2N
PCIE_NB_SB_TX3P 10
PCIE_NB_SB_TX3N 10
+1.2V_PCIE_VDDR
L27 BLM18PG221SN1D(220,1.4A)_6 L27 BLM18PG221SN1D(220,1.4A)_6
PCIE_PVDD-- PCIE PLL POWER
C C
SBSRC_CLKP 3 SBSRC_CLKN 3
B B
Y3
Y3
R341
R341
*20M_6
*20M_6
A A
4
32.768KHZ
32.768KHZ
R339 20M_6 R339 20M_6
C474
C474 18p/50V_4
18p/50V_4
RTC_X1
10/18 AMD suggest to not connect to GND
23
RTC_X2
1
C473
C473 18p/50V_4
18p/50V_4
+1.8V
+1.8VSUS
11 ALLOW_LDTSTOP
4 CPU_PROCHOT_SB#
CPU_PWRGD 4
CPU_LDT_STOP# 4,11
CPU_LDT_RST# 4,11
1/31 voltage leakage remove R349
5
R160 33_4 R160 33_4 R165 33_4 R165 33_4
C509 0.1u/10V_4 C509 0.1u/10V_4 C512 0.1u/10V_4 C512 0.1u/10V_4 C510 0.1u/10V_4 C510 0.1u/10V_4 C508 0.1u/10V_4 C508 0.1u/10V_4 C502 0.1u/10V_4 C502 0.1u/10V_4 C507 0.1u/10V_4 C507 0.1u/10V_4 C500 0.1u/10V_4 C500 0.1u/10V_4 C504 0.1u/10V_4 C504 0.1u/10V_4
R363 562/F_4 R363 562/F_4 R360 2.05K/F_4 R360 2.05K/F_4
T80 T80 T71 T71
T119 T119 T118 T118
T69 T69 T64 T64
T120 T120 T87 T87
T110 T110 T108T108
T111 T111 T75 T75
T72 T72 T66 T66
T65 T65 T60 T60
T103 T103
R254 *10K/F_4 R254 *10K/F_4
R349 *10K/F_4 R349 *10K/F_4
PCIE_NB_SB_TX0P PCIE_NB_SB_TX0N PCIE_NB_SB_TX1P PCIE_NB_SB_TX1N PCIE_NB_SB_TX2P PCIE_NB_SB_TX2N PCIE_NB_SB_TX3P PCIE_NB_SB_TX3N
C321
C321 10u/6.3V_8
10u/6.3V_8
ALLOW_LDTSTOP CPU_PROCHOT_SB# CPU_PWRGD CPU_LDT_STOP# CPU_LDT_RST#
A_RST#_SB
A_RX0P_C A_RX0N_C A_RX1P_C A_RX1N_C A_RX2P_C A_RX2N_C A_RX3P_C A_RX3N_C
PCIE_CALRP_SB PCIE_CALRN_SB
+1.2V_PCIE_PVDD
40mA
C322
C322 1u/10V_4
1u/10V_4
SBSRC_CLKPSBSRC_CLKPSBSRC_CLKPSBSRC_CLKP SBSRC_CLKNSBSRC_CLKNSBSRC_CLKNSBSRC_CLKNSBSRC_CLKNSBSRC_CLKNSBSRC_CLKNSBSRC_CLKN
NB_DISP_CLKP NB_DISP_CLKN
NB_HT_CLKP NB_HT_CLKN
CPU_HT_CLKP CPU_HT_CLKN
SLT_GFX_CLKP SLT_GFX_CLKN
GPP_CLK0P GPP_CLK0N
GPP_CLK1P GPP_CLK1N
GPP_CLK2P GPP_CLK2N
GPP_CLK3P GPP_CLK3N
T78 T78
T85 T85
RTC_X1
RTC_X2
4
U6A
U6A
N2
A_RST#
V23
PCIE_TX0P
V22
PCIE_TX0N
V24
PCIE_TX1P
V25
PCIE_TX1N
U25
PCIE_TX2P
U24
PCIE_TX2N
T23
PCIE_TX3P
T22
PCIE_TX3N
U22
PCIE_RX0P
U21
PCIE_RX0N
U19
PCIE_RX1P
V19
PCIE_RX1N
R20
PCIE_RX2P
R21
PCIE_RX2N
R18
PCIE_RX3P
R17
PCIE_RX3N
T25
PCIE_CALRP
T24
PCIE_CALRN
P24
PCIE_PVDD
P25
PCIE_PVSS
N25
PCIE_RCLKP/NB_LNK_CLKP
N24
PCIE_RCLKN/NB_LNK_CLKN
K23
NB_DISP_CLKP
K22
NB_DISP_CLKN
M24
NB_HT_CLKP
M25
NB_HT_CLKN
P17
CPU_HT_CLKP
M18
CPU_HT_CLKN
M23
SLT_GFX_CLKP
M22
SLT_GFX_CLKN
J19
GPP_CLK0P
J18
GPP_CLK0N
L20
GPP_CLK1P
L19
GPP_CLK1N
M19
GPP_CLK2P
M20
GPP_CLK2N
N22
GPP_CLK3P
P22
GPP_CLK3N
L18
25M_48M_66M_OSC
J21
25M_X1
J20
25M_X2
A3
X1
B3
X2
F23
ALLOW_LDTSTP
F24
PROCHOT#
F22
LDT_PG
G25
LDT_STP#
G24
LDT_RST#
SB700
SB700
IC CTRL(528P) SB700 A11(218S7EALA11FG) P/N : AJALA110T00
100MHZ
RTC XTAL
RTC XTAL
SB700
SB700
Part 1 of 5
Part 1 of 5
PCI EXPRESS INTERFACE
PCI EXPRESS INTERFACE
CPU
CPU
PCI CLKS
PCI CLKS
PCI INTERFACE
PCI INTERFACE
CLOCK GENERATOR
CLOCK GENERATOR
LPC
LPC
LDRQ1#/GNT5#/GPIO68
BMREQ#/REQ5#/GPIO65
INTRUDER_ALERT#
RTC
RTC
PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4
PCICLK5/GPIO41
PCIRST#
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8
AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
CBE0# CBE1# CBE2# CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR STOP# PERR# SERR# REQ0# REQ1# REQ2#
REQ3#/GPIO70 REQ4#/GPIO71
GNT0# GNT1# GNT2#
GNT3#/GPIO72 GNT4#/GPIO73
CLKRUN#
LOCK#
INTE#/GPIO33
INTF#/GPIO34 INTG#/GPIO35 INTH#/GPIO36
LPCCLK0 LPCCLK1
LAD0 LAD1 LAD2 LAD3
LFRAME#
LDRQ0#
SERIRQ
RTCCLK
VBAT
3
P4 P3 P1 P2 T4 T3
N1
U2 P7 V4 T1 V3 U1 V1 V2 T2 W1 T9 R6 R7 R5 U8 U5 Y7 W8 V9 Y8 AA8 Y4 Y3 Y2 AA2 AB4 AA1 AB3 AB2 AC1 AC2 AD1 W2 U7 AA7 Y1 AA6 W5 AA5 Y5 U6 W6 W4 V7 AC3 AD4 AB7 AE6 AB6 AD2 AE4 AD5 AC6 AE5 AD6 V5
AD3 AC4 AE2 AE3
G22 E22 H24 H23 J25 J24 H25 H22 AB8 AD7 V15
C3 C2 B2
PORT_C#
PE_GPIO1
PCI_CLK0_R
PCI_CLK2_R PCI_CLK3_R PCI_CLK4_R PCI_CLK5_R
PCIRST#_L
R367 33_4 R367 33_4
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
T53 T53 T52 T52
T131 T131 T44 T44
T45 T45
T133 T133 T135 T135 T46 T46 T134 T134
CLKRUN#_R
T54 T54
INTE# INTF#
T132 T132
INTG# INTH#
T130 T130
LPC_CLK0 LPC_CLK1 LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ0#_SB LDRQ1#_SB SB_GPIO65 SERIRQ
RTC_CLK INTRUDER_ALERT# VCCRTC
R396 22_4 R396 22_4
R369 22_4 R369 22_4 R394 22_4 R394 22_4 R424 22_4 R424 22_4 R408 22_4 R408 22_4
CBE0# 26 CBE1# 26 CBE2# 26 CBE3# 26 FRAME# 26 DEVSEL# 26 IRDY# 26 TRDY# 26 PAR 26 STOP# 26
REQ0# 26
PORT_C# 22
GNT0# 26
R437 0_4 R437 0_4
R435 0_4 R435 0_4
R251 22_4 R251 22_4 R348 22_4 R348 22_4
T81 T81 T51 T51 T47 T47
T107 T107
T58 T58
PCIRST#
AD[0..31] 17,26
All the PCI bus has build-in Pull-UP/Down resistors
RTC
25,29 25,29
2
D7 CH500H-40 D7 CH500H-40
CLKRUN# 26,29
+3VPCU
LAD0 25,29 LAD1 25,29 LAD2 LAD3 LFRAME# 25,29
SERIRQ 29
RTC_CLK 17
PCLK_OZ129 26
PCI_CLK2 17 PCI_CLK3 17 PCI_CLK4 17 PCI_CLK5 17
PCIRST# 25,26
INTE# 26
FM_INTX 28
PCLK_591 17,29 PCLK_DBC 17,25
VCCRTC
C486
C486
0.1u/10V_4
0.1u/10V_4
A11 default PCICLK5 A12 default GPIO41
PE_GPIO1
R209 8.2K_4 R209 8.2K_4
R212 *8.2K_4 R212 *8.2K_4
SB_GPIO65
R202 100K/F_4 R202 100K/F_4
Maybe can remove
4/16 change RTC pad location to G1
VCCRTC
D10
D10 CH500H-40
CH500H-40
R238
R238 1K_6
1K_6
CN24
CN24
1
1
2
2
ACS_85204-0200L
ACS_85204-0200L
+5VPCU
R571+R667 = (5V - 0.2V-2V)/0.2mA = 14k
R302R302
2K/F_4 2K/F_4
R332R332
6.8K_4 6.8K_4
R333
R333
15K_6
15K_6
1/17 R301,R302 change from 8.66k to 2k. R332 change from 4.7K to 6.8K
Size D ocument Number R ev
Size D ocument Number R ev
Size D ocument Number R ev
Date: Sheet
Date: Sheet
Date: Sheet
12
G1
G1
*SHORT_PAD
*SHORT_PAD
R350
R350
0_4
0_4
VCCRTC_3
R301R301
2K/F_4 2K/F_4
PROJECT : BD3G
PROJECT : BD3G
Quanta Computer Inc.
Quanta Computer Inc.
SB700-PCIE/PCI/CPU/LPC 1/4
SB700-PCIE/PCI/CPU/LPC 1/4
SB700-PCIE/PCI/CPU/LPC 1/4
1
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