5
www.schematic-x.blogspot.com
4
3
2
1
BD3A BLOCK DIAGRAM
DDRII-SODIMM1
D D
DDRII-SODIMM2
PG 8,9
PG 8,9
DDR II 667 MHZ
AMD S1g1
Turion Rev.G Dual-Core
Sempron
Dual-Core 35W
(638 S1g1 socket)
PG 4,5,6,7
HDMI
PG 19
LVDS
PG 20
S-VIDEO
CRT
PG 18
PG 18
CRT TV HDMI
C C
LVDS
MXM Module
PG 21
LVDS(2ch)
PCI-E X16
HT_LINK
HDMI
RS690M
465 FCBGA
PG 10,11,12,13
A_LINK (X4)
SATA - HDD1
PG 27
SATA - HDD2
PG 27
Internal ODD
CD-ROM
B B
PCI ROUTING TABLE
Device IDSEL# REQ#/GNT# Interrupt
OZ129 AD17 REQ0# / GNT0# INTE#
PG 27
SATA0
SATA1
PATA 133
PCI Bus 33MHz
SB600
549 BGA
PG 14,15,16,17,18
LPC
HOST 200MHz
PCIE 100MHz
USB 48MHz
REF 14MHz
PCI-E, 1X (port2)
PCI-E, 1X (port0)
USB2.0 (P3)
PCI-E, 1X (port1)
PCI-E, 1X (port3)
USB2.0 (P6)
USB2.0 (P2)
USB2.0 (P4)
USB2.0 (P5)
USB2.0 (P8)
Azalia
CLOCK GENERATOR
PG 3
8040T(10/100)/8055(Giga)
RJ45
Mini Card (WLAN)
MINI CARD (HD Video Decoder)
NEW CARD
CCD
Fingerprint
Felica
Bluetooth
PG 28
PG 19
PG 28
PG 28
Azalia Audio Codec
PG 24PG 24
PG 25
PG 25
PG 25
USB2.0 (P0)
USB2.0 (P1)
USB2.0 (P7)
USB2.0 (P9)
CX20561
VCC_CORE
+NB_CORE
+2.5V
+1.5V
+1.2V
+1.2V_S5
+1.8VSUS
+1.8V
+SMDDR_VTERM
PG 22
CPU CORE
NB CORE
(1.0~1.2V)
+2.5V
+1.5V
+1.2V
+1.8VSUS
SMDDR
VTERM
+3VPCU
3V/5V
+3V_S5
+3VSUS
+3V
+5VPCU
+5V
USB2.0 I/O Ports X1
(MB)
USB2.0 I/O Ports X1
(DB)
USB2.0 I/O Ports X1
(DB)
USB2.0 I/O Ports X1
(MB)
PG 28
PG 28
PG 28
PG 28
PCB STACK UP
PG 34
LAYER 1 : TOP
LAYER 2 : GND
PG 35
LAYER 3 : IN1
LAYER 4 : IN2
PG 37
LAYER 5 : VCC
LAYER 6 : BOT
PG 37
Daughter Board
PG 37
USB Board
(With RJ11)
USB Board
(With FM)
PG 36
Touch Pad board Touch Pad board
PG 33
MDC board
Power board
(with Fingerprinter)
O2Micro OZ129T
PG 26
EC
WPCE775
PG 29
PORT-A
PORT-B
Speaker Amplifier
G1441R51U
PG 22
MDC CONN
PG 23
FM Radio
PG 23
SPI
IEEE1394 CN.
A A
5
Card Reader
PG 26 PG 26
VR
PG 23
FAN
PG 6
Keyboard
PG 30
4
Flash
ROM
PG 29 PG 28
Touch
Pad
CIR
PG 28
Kill SW
PG 30
3
H.P/
SPDIF
PG 23
MIC
JACK
PG 23
INT.
MIC
PG 23
INT.
S.P.
PG 22
2
MDC
Board
RJ11
PROJECT : BD3A
PROJECT : BD3A
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
Quanta Computer Inc.
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
of
138Wednesday, February 13, 2008
138Wednesday, February 13, 2008
1
138Wednesday, February 13, 2008
3C
3C
3C
5
4
3
2
1
BOM naming rule
D D
C C
B B
CIR
1
HDMI port
2
HDMI transmitter
3
HDMI-CEC
4
Discrete VGA
5
UMA
6
New Card
7
RJ11
8
RJ45-10/100
9
RJ45-1000
10
Option for RJ45-10/100 and RJ45-1000
11
TV
12
Cardbus
13
FM transmitter
14
Mainstream ID LED
15
Low cost ID LED
16
CCD
17
INT MIC
18
AMD Hyper Flash
19
North bridge(690MC/RS780MC)
20
North bridge(RX780)
21
PowerXpress
22
PowerXpress with UMA SKU
23
PowerXpress with Discrete VGA SKU
24
Power player/Power Shift
25
CIR@
v
HDM@
v
SI@
v
CEC@
v
EV@
IV@
Silicon image SiI 1392/1932
Renesas R8C/1B
External VGA stuff
Internal VGA stuff
NEW@
MD@
v
40@
55@
40@55@
TV@
v
Modem
Marvell 8040T(10/100)
Marvell 8055(Giga)
Option for 8040/8055
CB@
FM@
v
MID@
LID@
CCD@
v
I_MIC@
v
HF@
MC@
RX@
PX@
PX@IV@
PX@EV@
PP@
Only for AMD platform
Only for AMD platform
Only for AMD platform
Only for AMD platform
Only for AMD platform
Only for AMD platform
Only for AMD platform
Items Function BTO Name Description
A A
PROJECT : BD3A
PROJECT : BD3A
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Quanta Computer Inc.
SYSTEM INFORMATION
SYSTEM INFORMATION
SYSTEM INFORMATION
1
3C
3C
238Wednesday, February 13, 2008
238Wednesday, February 13, 2008
238Wednesday, February 13, 2008
3C
5
4
3
2
1
+3V
L30 BK1608HS600_6L30 BK1608HS600_6
D D
+3V
L61 BK1608HS600_6L61 BK1608HS600_6
+3V
L33 BK1608HS600_6L33 BK1608HS600_6
CLK_VDD
R273
R273
10K_4
10K_4
C C
Clock Gen I2C
Q39
Q39
*RHU002N06
*RHU002N06
SCLK08,15,25
B B
SDATA08,15,25
Q71
Q71
*RHU002N06
*RHU002N06
CLK_VDD
C288
C288
10u/10V_8
10u/10V_8
C611
C611
C612
C612
1u/6.3V_4
1u/6.3V_4
*0.1u/10V_4
*0.1u/10V_4
C302
C302
C303
C303
*0.1u/10V_4
*0.1u/10V_4
2.2u/6.3V_6
2.2u/6.3V_6
C322 33p/50V_4C322 33p/50V_4
14.318MHZY514.318MHZ
C323 33p/50V_4C323 33p/50V_4
Parallel Resonance Crystal
+3V
R272
R272
2
*10K_4
3
R267 0_4R267 0_4
+3V
3
R563 0_4R563 0_4
*10K_4
1
R564
R564
2
*10K_4
*10K_4
1
Put Decoupling Caps close to Clock Fen. power pin
C615
C615
C599
C599
C587
C587
*0.1u/10V_4
*0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
CLK_VDD
CLK_VDD_USB
CLK_VDD_REF
CLK_XIN
CLK_XOUT
T66T66
R550
R550
475/F_4
475/F_4
CLKREQA# CONTROL SRC5,6,7
CLKREQB# CONTROL SRC2,3,4 ATIG3
CLKREQC# CONTROL SRC0,1 ATIG0,1,2
0.1u/10V_4
0.1u/10V_4
U17
U17
54
14
23
28
44
5
39
2
60
53
15
22
29
45
8
38
1
58
3
4
11
61
9
10
48
ICS951462
ICS951462
VDDCPU
VDD_SRC1
VDD_SRC2
VDD_SRC3
VDD_SRC4
VDD_48
VDD_ATIG
VDD_REF
VDDHTT
GND_CPU
GND_SRC1
GND_SRC2
GND_SRC3
GND_SRC4
GND_48
GND_ATIG
GND_REF
GNDHTT
XIN
XOUT
RESET_IN#
NC
SMBCLK
SMBDAT
IREF
C598
C598
0.1u/10V_4
0.1u/10V_4
CLK_VDD_USB
CLK_VDD_REF
Y5
CGCLK_SMB
CGDAT_SMB
C614
C614
0.1u/10V_4
0.1u/10V_4
21
R277
R277
*1M_4
*1M_4
CGCLK_SMB
CGDAT_SMB
Ioh = 5 * Iref
(2.32mA)
Voh = 0.71V @ 60 ohm
C597
C597
0.1u/10V_4
0.1u/10V_4
C588
C588
0.1u/10V_4
0.1u/10V_4
CPUCLK8T0
CPUCLK8C0
CPUCLK8T1
CPUCLK8C1
SRCCLKT6
SRCCLKC6
ATIGCLKT0
ATIGCLKC0
ATIGCLKT1
ATIGCLKC1
ATIGCLKT2
ATIGCLKC2
ATIGCLKT3
ATIGCLKC3
SRCCLKT5
SRCCLKC5
SRCCLKT4
SRCCLKC4
SRCCLKT3
SRCCLKC3
SRCCLKT2
SRCCLKC2
SRCCLKT0
SRCCLKC0
SRCCLKT1
SRCCLKC1
SRCCLKT7
SRCCLKC7
CLKREQA#
CLKREQB#
CLKREQC#
48MHz_1
48MHz_0
FS1/REF1
FS0/REF0
FS2/REF2
HTTCLK0
VDDA
GNDA
C613
C613
0.1u/10V_4
0.1u/10V_4
50
49
56
55
52
51
16
17
41
40
37
36
35
34
30
31
18
19
20
21
24
25
26
27
47
46
43
42
12
13
57
32
33
7
6
63
64
62
59
CLK_VDDA
CPUCLK_EXT_R
CPUCLK#_EXT_R
T60T60
T65T65
SBLINK_CLKP_R
SBLINK_CLKN_R
NBSRC_CLKP_R
NBSRC_CLKN_R
MXM_REFCLKP_R
MXM_REFCLKN_R
T61T61
T64T64
T150T150
T149T149
SBSRC_CLKP_R
SBSRC_CLKN_R
T83T83
T81T81
GPP_CLK1P_R
GPP_CLK1N_R
GPP_CLK2P_R
GPP_CLK2N_R
T62T62
T63T63
GPP_CLK3P_R
GPP_CLK3N_R
GPP_CLK0P_R
GPP_CLK0N_R
CLKREQA#
CLKREQB#
NEW_CLKREQ#
CLK_48M_2_R
R271 33_4R271 33_4
CLK_VDDA
C586
C586
0.1u/10V_4
0.1u/10V_4
R248 47.5/F_4R248 47.5/F_4
R249 47.5/F_4R249 47.5/F_4
3
RP28 33X2RP28 33X2
1
1
RP26 33X2RP26 33X2
3
1
RP27 EV@33X2RP27 EV@33X2
3
3
RP29
RP29
1
3
RP31
RP31
1
3
RP32
RP32
1
NEW@33X2
RP25
RP25
SB_OSCIN_R
NB_OSCIN_R
HTREFCLK_R
NEW@33X2
1
3
3
1
RP30 33X2RP30 33X2
USBCLK 15
R238 33_4R238 33_4
R233 33_4R233 33_4
R243 33_4R243 33_4
C271
C271
*10p_4
*10p_4
L28 BK1608HS600_6L28 BK1608HS600_6
C270
C270
10u/10V_8
10u/10V_8
4
2
2
4
2
4
4
33X2
33X2
2
4
33X2
33X2
2
4
33X2
33X2
2
2
4
4
2
R229 EV@49.9/F_4R229 EV@49.9/F_4
R230 EV@49.9/F_4R230 EV@49.9/F_4
R234
R234
49.9/F_4
49.9/F_4
R280 49.9/F_4R280 49.9/F_4
R254
R254
10K_4
10K_4
R279 49.9/F_4R279 49.9/F_4
CLK_VDD
C186
C186
10p/50V_4
10p/50V_4
R289 49.9/F_4R289 49.9/F_4
R555
R555
10K_4
10K_4
+3V
R235 261/F_4R235 261/F_4
R287 49.9/F_4R287 49.9/F_4
R288 49.9/F_4R288 49.9/F_4
R286 49.9/F_4R286 49.9/F_4
R285 49.9/F_4R285 49.9/F_4
R237
R237
10K_4
10K_4
R241 *0_4R241 *0_4
R556 *0_4R556 *0_4
R236 *0_4R236 *0_4
C572
C572
18p/50V_4
18p/50V_4
R231 NEW@49.9/F_4R231 NEW@49.9/F_4
R284 49.9/F_4R284 49.9/F_4
SB_OSCIN 15
NB_OSC 12
HTREFCLK 12
R226 NEW@49.9/F_4R226 NEW@49.9/F_4
R228 49.9/F_4R228 49.9/F_4
R227 49.9/F_4R227 49.9/F_4
R283 49.9/F_4R283 49.9/F_4
14.318MHz
14.318MHz
66MHz
CPUCLKP 6
CPUCLKN 6
R282 49.9/F_4R282 49.9/F_4
SBLINK_CLKP 12
SBLINK_CLKN 12
NBSRC_CLKP 12
NBSRC_CLKN 12
MXM_REFCLKP 21
MXM_REFCLKN 21
CLK_PCIE_MINICARD 25
CLK_PCIE_MINICARD# 25
SBSRCCLKP 14
SBSRCCLKN 14
CLK_PCIE_WLAN 25
CLK_PCIE_WLAN# 25
CLK_PCIE_NEW 25
CLK_PCIE_NEW# 25
CLK_PCIE_LAN 24
CLK_PCIE_LAN# 24
CLKREQA#
CLKREQB#
NEW_CLKREQ#
10K_4
10K_4
10K_4
10K_4
R678
R678
R632
R632
+3V
Q60
Q60
RHU002N06
RHU002N06
2
+3V
RHU002N06
RHU002N06
2
+3V
3
Q58
Q58
3
R665
R665
NEW@10K_4
NEW@10K_4
CLKREQ_LAN# 24
CLKREQ_WLAN# 25
NEW_CLKREQ# 25
1
1
EXT CLK FREQUENCY SELECT TABLE(MHZ)
USB
Hi-Z
X/3 X/6
60.00
36.56
66.66
66.66
66.66
PCI
Hi-Z
48.00
48.00
48.00
30.00
48.00
73.12
48.00
33.33
33.33
48.00
33.33 48.00
COMMENT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Normal Turion/Sempron operation
4
PROJECT : BD3A
PROJECT : BD3A
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Quanta Computer Inc.
CLOCK GENERATOR
CLOCK GENERATOR
CLOCK GENERATOR
3C
3C
338Wednesday, February 13, 2008
338Wednesday, February 13, 2008
1
338Wednesday, February 13, 2008
3C
CPU
FS1
FS0 HTT
FS2
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 1
A A
5
Hi-Z
X
180.00
220.00
100.00
133.33
200.00
SRCCLK
[2:1]
100.00
100.00
100.00
100.00
100.00
100.00
100.00
5
D D
C C
VLDT_RUN
B B
4
HT_CADIN15_P10
HT_CADIN15_N10
HT_CADIN14_P10
HT_CADIN14_N10
HT_CADIN13_P10
HT_CADIN13_N10
HT_CADIN12_P10
HT_CADIN12_N10
HT_CADIN11_P10
HT_CADIN11_N10
HT_CADIN10_P10
HT_CADIN10_N10
HT_CADIN9_P10
HT_CADIN9_N10
HT_CADIN8_P10
HT_CADIN8_N10
HT_CADIN7_P10
HT_CADIN7_N10
HT_CADIN6_P10
HT_CADIN6_N10
HT_CADIN5_P10
HT_CADIN5_N10
HT_CADIN4_P10
HT_CADIN4_N10
HT_CADIN3_P10
HT_CADIN3_N10
HT_CADIN2_P10
HT_CADIN2_N10
HT_CADIN1_P10
HT_CADIN1_N10
HT_CADIN0_P10
HT_CADIN0_N10
HT_CLKIN1_P10
HT_CLKIN1_N10
HT_CLKIN0_P10
HT_CLKIN0_N10
R99 51/F_4R99 51/F_4
R100 51/F_4R100 51/F_4
HT_CTLIN0_P10
HT_CTLIN0_N10
VLDT_RUN
U25AU25A
D4
VLDT_A3
D3
VLDT_A2
D2
VLDT_A1
D1
VLDT_A0
N5
L0_CADIN_H15
P5
L0_CADIN_L15
M3
L0_CADIN_H14
M4
L0_CADIN_L14
L5
L0_CADIN_H13
M5
L0_CADIN_L13
K3
L0_CADIN_H12
K4
L0_CADIN_L12
H3
L0_CADIN_H11
H4
L0_CADIN_L11
G5
L0_CADIN_H10
H5
L0_CADIN_L10
F3
L0_CADIN_H9
F4
L0_CADIN_L9
E5
L0_CADIN_H8
F5
L0_CADIN_L8
N3
L0_CADIN_H7
N2
L0_CADIN_L7
L1
L0_CADIN_H6
M1
L0_CADIN_L6
L3
L0_CADIN_H5
L2
L0_CADIN_L5
J1
L0_CADIN_H4
K1
L0_CADIN_L4
G1
L0_CADIN_H3
H1
L0_CADIN_L3
G3
L0_CADIN_H2
G2
L0_CADIN_L2
E1
L0_CADIN_H1
F1
L0_CADIN_L1
E3
L0_CADIN_H0
E2
L0_CADIN_L0
J5
L0_CLKIN_H1
K5
L0_CLKIN_L1
J3
L0_CLKIN_H0
J2
L0_CLKIN_L0
P3
L0_CTLIN_H1
P4
L0_CTLIN_L1
N1
L0_CTLIN_H0
P1
L0_CTLIN_L0
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
Athlon 64 S1
Processor Socket
3
VLDT_B3
VLDT_B2
VLDT_B1
VLDT_B0
AE5
AE4
AE3
AE2
T4
T3
V5
U5
V4
V3
Y5
W5
AB5
AA5
AB4
AB3
AD5
AC5
AD4
AD3
T1
R1
U2
U3
V1
U1
W2
W3
AA2
AA3
AB1
AA1
AC2
AC3
AD1
AC1
Y4
Y3
Y1
W1
T5
R5
R2
R3
2
C447
C447
4.7u/6.3V_6
4.7u/6.3V_6
HT_CADOUT15_P 10
HT_CADOUT15_N 10
HT_CADOUT14_P 10
HT_CADOUT14_N 10
HT_CADOUT13_P 10
HT_CADOUT13_N 10
HT_CADOUT12_P 10
HT_CADOUT12_N 10
HT_CADOUT11_P 10
HT_CADOUT11_N 10
HT_CADOUT10_P 10
HT_CADOUT10_N 10
HT_CADOUT9_P 10
HT_CADOUT9_N 10
HT_CADOUT8_P 10
HT_CADOUT8_N 10
HT_CADOUT7_P 10
HT_CADOUT7_N 10
HT_CADOUT6_P 10
HT_CADOUT6_N 10
HT_CADOUT5_P 10
HT_CADOUT5_N 10
HT_CADOUT4_P 10
HT_CADOUT4_N 10
HT_CADOUT3_P 10
HT_CADOUT3_N 10
HT_CADOUT2_P 10
HT_CADOUT2_N 10
HT_CADOUT1_P 10
HT_CADOUT1_N 10
HT_CADOUT0_P 10
HT_CADOUT0_N 10
HT_CLKOUT1_P 10
HT_CLKOUT1_N 10
HT_CLKOUT0_P 10
HT_CLKOUT0_N 10
HT_CPU_CTLOUT1_PHT_CTLIN1_P
HT_CPU_CTLOUT1_NHT_CTLIN1_N
T30T30
T32T32
HT_CTLOUT0_P 10
HT_CTLOUT0_N 10
1
+1.2V
L22
L22
FBJ3216HS800_1206
FBJ3216HS800_1206
A A
5
4
VLDT_RUN
C206
C206
4.7u/6.3V_6
4.7u/6.3V_6
C204
C204
4.7u/6.3V_6
4.7u/6.3V_6
C221
C221
0.22u/10V_4
0.22u/10V_4
C219
C219
0.22u/10V_4
0.22u/10V_4
3
12
C218
C218
180p/50V_4
180p/50V_4
12
C220
C220
180p/50V_4
180p/50V_4
PROJECT : BD3A
PROJECT : BD3A
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
TURION 64 HT I/F
TURION 64 HT I/F
TURION 64 HT I/F
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
438Wednesday, February 13, 2008
438Wednesday, February 13, 2008
438Wednesday, February 13, 2008
1
3C
3C
3C
5
Processor DDR2 Memory Interface
C112
C112
1000p/50V_4
1000p/50V_4
U25B
U25B
MEMVREF
VTT_SENSE
MEMZN
MEMZP
MA0_CS_L3
MA0_CS_L2
MA0_CS_L1
MA0_CS_L0
MB0_CS_L3
MB0_CS_L2
MB0_CS_L1
MB0_CS_L0
MB_CKE1
MB_CKE0
MA_CKE1
MA_CKE0
MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0
MA_BANK2
MA_BANK1
MA_BANK0
MA_RAS_L
MA_CAS_L
MA_WE_L
+1.8VSUS
R96
R96
2K/F_4
2K/F_4
R94
R94
2K/F_4
2K/F_4
DDR II: CMD/CTRL/CLK
DDR II: CMD/CTRL/CLK
Athlon 64 S1
Processor Socket
D D
CPU_M_VREF
C116
VTT_SENSE
M_A_A15
M_A_A14
M_A_A13
M_A_A12
M_A_A11
M_A_A10
M_A_A9
M_A_A8
M_A_A7
M_A_A6
M_A_A5
M_A_A4
M_A_A3
M_A_A2
M_A_A1
M_A_A0
C116
0.1u/10V_4
0.1u/10V_4
W17
Y10
AE10
AF10
V19
J22
V22
T19
Y26
J24
W24
U23
H26
J23
J20
J21
K19
K20
V24
K24
L20
R19
L19
L22
L21
M19
M20
M24
M22
N22
N21
R21
K22
R20
T22
T20
U20
U21
PLACE THEM CLOSE TO
CPU WITHIN 1"
+1.8VSUS
R444
R444
39.2/F_4
39.2/F_4
1 2
C C
R443
R443
39.2/F_4
39.2/F_4
1 2
B B
A A
T25T25
M_ZN
M_ZP
M_A_CS#38,9
M_A_CS#28,9
M_A_CS#18,9
M_A_CS#08,9
M_B_CS#38,9
M_B_CS#28,9
M_B_CS#18,9
M_B_CS#08,9
M_CKE38,9
M_CKE28,9
M_CKE18,9
M_CKE08,9
M_A_A[0..15]8,9
M_A_BS#28,9
M_A_BS#18,9
M_A_BS#08,9
M_A_RAS#8,9
M_A_CAS#8,9
M_A_WE#8,9
4
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
MA0_CLK_H2
MA0_CLK_L2
MA0_CLK_H1
MA0_CLK_L1
MB0_CLK_H2
MB0_CLK_L2
MB0_CLK_H1
MB0_CLK_L1
MB0_ODT1
MB0_ODT0
MA0_ODT1
MA0_ODT0
MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10
MB_ADD9
MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0
MB_BANK2
MB_BANK1
MB_BANK0
MB_RAS_L
MB_CAS_L
MB_WE_L
+SMDDR_VTERM
D10
C10
B10
AD10
W10
AC10
AB10
AA10
A10
Y16
AA16
E16
F16
AF18
AF17
A17
A18
W23
W26
V20
U19
J25
J26
W25
L23
L25
U25
L24
M26
L26
N23
N24
N25
N26
P24
P26
T24
K26
T26
U26
U24
V26
U22
+SMDDR_VTERM
M_B_A15
M_B_A14
M_B_A13
M_B_A12
M_B_A11
M_B_A10
M_B_A9
M_B_A8
M_B_A7
M_B_A6
M_B_A5
M_B_A4
M_B_A3
M_B_A2
M_B_A1
M_B_A0
M_CLKOUT1 8
M_CLKOUT1# 8
M_CLKOUT0 8
M_CLKOUT0# 8
M_CLKOUT4 8
M_CLKOUT4# 8
M_CLKOUT3 8
M_CLKOUT3# 8
M_ODT3 8,9
M_ODT2 8,9
M_ODT1 8,9
M_ODT0 8,9
M_B_A[0..15] 8,9
M_B_BS#2 8,9
M_B_BS#1 8,9
M_B_BS#0 8,9
M_B_RAS# 8,9
M_B_CAS# 8,9
M_B_WE# 8,9
3
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQ63
M_B_DQ62
M_B_DQ61
M_B_DQ60
M_B_DQ59
M_B_DQ58
M_B_DQ57
M_B_DQ56
M_B_DQ55
M_B_DQ54
M_B_DQ53
M_B_DQ52
M_B_DQ51
M_B_DQ50
M_B_DQ49
M_B_DQ48
M_B_DQ47
M_B_DQ46
M_B_DQ45
M_B_DQ44
M_B_DQ43
M_B_DQ42
M_B_DQ41
M_B_DQ40
M_B_DQ39
M_B_DQ38
M_B_DQ37
M_B_DQ36
M_B_DQ35
M_B_DQ34
M_B_DQ33
M_B_DQ32
M_B_DQ31
M_B_DQ30
M_B_DQ29
M_B_DQ28
M_B_DQ27
M_B_DQ26
M_B_DQ25
M_B_DQ24
M_B_DQ23
M_B_DQ22
M_B_DQ21
M_B_DQ20
M_B_DQ19
M_B_DQ18
M_B_DQ17
M_B_DQ16
M_B_DQ15
M_B_DQ14
M_B_DQ13
M_B_DQ12
M_B_DQ11
M_B_DQ10
M_B_DQ9
M_B_DQ8
M_B_DQ7
M_B_DQ6
M_B_DQ5
M_B_DQ4
M_B_DQ3
M_B_DQ2
M_B_DQ1
M_B_DQ0
M_B_DM7
M_B_DM6
M_B_DM5
M_B_DM4
M_B_DM3
M_B_DM2
M_B_DM1
M_B_DM0
M_B_DQ[0..63]8
M_B_DM[0..7]8
M_B_DQS[0..7]8
M_B_DQS#[0..7]8
M_B_DQS7
M_B_DQS#7
M_B_DQS6
M_B_DQS#6
M_B_DQS5
M_B_DQS#5
M_B_DQS4
M_B_DQS#4
M_B_DQS3
M_B_DQS#3
M_B_DQS2
M_B_DQS#2
M_B_DQS1
M_B_DQS#1
M_B_DQS0
M_B_DQS#0
AD11
AF11
AF14
AE14
Y11
AB11
AC12
AF13
AF15
AF16
AC18
AF19
AD14
AC14
AE18
AD18
AD20
AC20
AF23
AF24
AF20
AE20
AD22
AC22
AE25
AD26
AA25
AA26
AE24
AD24
AA23
AA24
G24
G23
D26
C26
G26
G25
E24
E23
C24
B24
C20
B20
C25
D24
A21
D20
D18
C18
D14
C14
A20
A19
A16
A15
A13
D12
E11
G11
B14
A14
A11
C11
AD12
AC16
AE22
AB26
E25
A22
B16
A12
AF12
AE12
AE16
AD16
AF21
AF22
AC25
AC26
F26
E26
A24
A23
D16
C16
C12
B12
U25C
U25C
MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0
MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0
MB_DQS_H7
MB_DQS_L7
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_H4
MB_DQS_L4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0
2
DDR: DATA
DDR: DATA
Athlon 64 S1
Processor Socket
MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0
MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0
MA_DQS_H7
MA_DQS_L7
MA_DQS_H6
MA_DQS_L6
MA_DQS_H5
MA_DQS_L5
MA_DQS_H4
MA_DQS_L4
MA_DQS_H3
MA_DQS_L3
MA_DQS_H2
MA_DQS_L2
MA_DQS_H1
MA_DQS_L1
MA_DQS_H0
MA_DQS_L0
AA12
AB12
AA14
AB14
W11
Y12
AD13
AB13
AD15
AB15
AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21
J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12
Y13
AB16
Y19
AC24
F24
E19
C15
E12
W12
W13
Y15
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21
G16
G15
G13
H13
M_A_DQ63
M_A_DQ62
M_A_DQ61
M_A_DQ60
M_A_DQ59
M_A_DQ58
M_A_DQ57
M_A_DQ56
M_A_DQ55
M_A_DQ54
M_A_DQ53
M_A_DQ52
M_A_DQ51
M_A_DQ50
M_A_DQ49
M_A_DQ48
M_A_DQ47
M_A_DQ46
M_A_DQ45
M_A_DQ44
M_A_DQ43
M_A_DQ42
M_A_DQ41
M_A_DQ40
M_A_DQ39
M_A_DQ38
M_A_DQ37
M_A_DQ36
M_A_DQ35
M_A_DQ34
M_A_DQ33
M_A_DQ32
M_A_DQ31
M_A_DQ30
M_A_DQ29
M_A_DQ28
M_A_DQ27
M_A_DQ26
M_A_DQ25
M_A_DQ24
M_A_DQ23
M_A_DQ22
M_A_DQ21
M_A_DQ20
M_A_DQ19
M_A_DQ18
M_A_DQ17
M_A_DQ16
M_A_DQ15
M_A_DQ14
M_A_DQ13
M_A_DQ12
M_A_DQ11
M_A_DQ10
M_A_DQ9
M_A_DQ8
M_A_DQ7
M_A_DQ6
M_A_DQ5
M_A_DQ4
M_A_DQ3
M_A_DQ2
M_A_DQ1
M_A_DQ0
M_A_DM7
M_A_DM6
M_A_DM5
M_A_DM4
M_A_DM3
M_A_DM2
M_A_DM1
M_A_DM0
M_A_DQS7
M_A_DQS#7
M_A_DQS6
M_A_DQS#6
M_A_DQS5
M_A_DQS#5
M_A_DQS4
M_A_DQS#4
M_A_DQS3
M_A_DQS#3
M_A_DQS2
M_A_DQS#2
M_A_DQS1
M_A_DQS#1
M_A_DQS0
M_A_DQS#0
To SODIMM socket A (near)To SODIMM socket B (Far)
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
1
M_A_DQ[0..63] 8
M_A_DM[0..7] 8
M_A_DQS[0..7] 8
M_A_DQS#[0..7] 8
C445
C445
4.7u/6.3V_6
4.7u/6.3V_6
C500
C500
4.7u/6.3V_6
4.7u/6.3V_6
5
C444
C444
4.7u/6.3V_6
4.7u/6.3V_6
C446
C446
4.7u/6.3V_6
4.7u/6.3V_6
C516
C516
0.22u/10V_4
0.22u/10V_4
C497
C497
0.22u/10V_4
0.22u/10V_4
C440
C440
0.22u/10V_4
0.22u/10V_4
C525
C525
0.22u/10V_4
0.22u/10V_4
4
C443
C443
1000p/50V_4
1000p/50V_4
C505
C505
1000p/50V_4
1000p/50V_4
C508
C508
1000p/50V_4
1000p/50V_4
C496
C496
1000p/50V_4
1000p/50V_4
C442
C442
180p/50V_4
180p/50V_4
3
C498
C498
180p/50V_4
180p/50V_4
C441
C441
180p/50V_4
180p/50V_4
C439
C439
180p/50V_4
180p/50V_4
PROJECT : BD3A
PROJECT : BD3A
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
TURION 64 DDRII I/F
TURION 64 DDRII I/F
TURION 64 DDRII I/F
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
538Wednesday, February 13, 2008
538Wednesday, February 13, 2008
538Wednesday, February 13, 2008
1
3C
3C
3C
5
4
3
2
1
ATHLON Control and Debug
+1.8VSUS
3
Q52
If AMD SI is not used, the SID pin can be left unconnected and SIC
should have a 300-Ω (±5%) pulldown to VSS.
C573
C573
*100p/50V_4
*100p/50V_4
R442 *300_4R442 *300_4
R441 *300_4R441 *300_4
R437 *0_4R437 *0_4
R446 *0_4R446 *0_4
C502 3900P/50V_4C502 3900P/50V_4
C503 3900P/50V_4C503 3900P/50V_4
R490
R490
R480
R480
680_4
680_4
680_4
680_4
+3V
Q13
Q13
2
RHU002N06
3
3
RHU002N06
+3V
Q18
Q18
2
RHU002N06
RHU002N06
+3V
R65
R65
*8.2K_4
*8.2K_4
+3V
CPU_SIC_R
CPU_SID_R
R464
R464
169/F_6
169/F_6
R466 0_4R466 0_4
R489 0_4R489 0_4
L75 0_6L75 0_6
R469
R469
680_4
680_4
1
1
2
3
Q19*2N7002E-LF Q19*2N7002E-LF
R58 10K_4R58 10K_4
R438300_4 R438300_4
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
+3V
R57
R57
*10K_4
*10K_4
THERM_ALERT#_R
1
THER_SHD#
CPU_ALL_PWROK
CPU_LDTSTOP#
CPU_HT_RESET#
*100p/50V_4
*100p/50V_4
R51
R51
10K_4
10K_4
C574
C574
R56
R56
10K_4
10K_4
+3V
U6
8
SCLK
7
SDA
6
ALERT#
4
OVERT#
GMT G781U6GMT G781
ADDRESS: 98H
D D
C C
+1.8VSUS
CPU_SIC14
CPU_SID14
CPUCLKP3
CPUCLKN3
CPU_PWRGD14
LDT_STOP#12,14
LDT_RST#14
CPU Thermal monitor
B B
2ND_MBCLK29
2ND_MBDATA29
(0903) add res8.2K and PH 3V
THERM_ALERT#15
CPU_COREPG29,34,35,37
H_THERMTRIP#
R46
R46
200_6
200_6
LM86VCC
1
VCC
2
DXP
3
DXN
5
GND
<check list>
Layout Note:Routing 10:10 mils and away
from noise source with ground gard
C50
C50
.1U_4
.1U_4
C51
C51
2200P/50V_4
2200P/50V_4
CPU FAN
C33
C33
10U_8
10U_8
FANSIG29
R25 0_6R25 0_6
A A
SYSFANON#21
THER_SHD#
+3V +5V
2
1
Q11
Q11
ME2N7002D
ME2N7002D
R26
R26
*0_4
*0_4
+5V
C34
C34
2.2u/6.3V_6
R27
R27
*10K_4
*10K_4
3
VFAN29
5
2.2u/6.3V_6
U5
VIN2VO
CPUFAN#_ON_R
FANPWR = 1.6*VSET
G995/Pin1- internal pull high (+5V)
GND
1
/FON
GND
GND
4
VSET
GND
G995U5G995
TH_FAN_POWER
3
5
6
7
8
C32
C32
.01U_4
.01U_4
4
21
D29
D29
*VPORT
*VPORT
TH_FAN_POWER_R
21
D35
D35
*VPORT
*VPORT
Q52
2
FDV301N
FDV301N
1
R430
R430
10K_4
10K_4
2
R422 *0_6R422 *0_6
1 3
MMBT3904
MMBT3904
Q54
Q54
CPU_TEST27_SINGLECHAIN
CPU_TEST26_BURNIN#
CPU_PRESENT#
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST18_PLLTEST1
+3V
THER_SHD#
1 3
H_THERMDA
H_THERMDC
+3V
R408
R408
10K_4
10K_4
C434
C434
*.01U_4
*.01U_4
CN19
CN19
1
2
345
PTI_CWY030-B0G1Z
PTI_CWY030-B0G1Z
R436
R436
*10K_4
*10K_4
R431 *300_4R431 *300_4
R439 300_4R439 300_4
R47 1K/F_4R47 1K/F_4
R479 510/F_4R479 510/F_4
R49 300_4R49 300_4
R434 *300_4R434 *300_4
R433 *300_4R433 *300_4
R432 *300_4R432 *300_4
R50 *300_4R50 *300_4
R481 *300_4R481 *300_4
R470 *300_4R470 *300_4
R491 510/F_4R491 510/F_4
R482 300_4R482 300_4
R471 300_4R471 300_4
R435
R435
330_4
330_4
Q53
Q53
2
MMBT3904
MMBT3904
+2.5V
L55 30ohm_4AL55 30ohm_4A
D31
D31
*BAS316
*BAS316
R687 100K_6R687 100K_6
SB_THERMTRIP# 15
SYS_SHDN# 33
COREFB+V34
COREFB-34 PWR_PSI# 34
*100u/6.3V_3528
*100u/6.3V_3528
+1.8VSUS
SYS_SHDN# 33
C494
C494
VLDT_RUN
T45T45
T46T46
R467
R467
*HDT@F2.2K_4
*HDT@F2.2K_4
H_PROCHOT#
3
R48
R48
300_4
300_4
VDDA_RUN
C492
C492
4.7u/6.3V_6
4.7u/6.3V_6
CPU_HT_RESET#
T140T140
CPU_ALL_PWROK
T138T138
CPU_LDTSTOP#
T139T139
CPU_SIC_R
CPU_SID_R
R98 44.2F_4R98 44.2F_4
R95 44.2F_4R95 44.2F_4
place them to CPU within 1"
CPU_VDDIO_SUS_FB_H
T7T7
CPU_VDDIO_SUS_FB_L
T13T13
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
CPU_TEST17_BP3CPU_TEST19_PLLTEST0
T47T47
CPU_TEST16_BP2
T50T50
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST12_SCANSHIFTENB
CPU_TEST07_ANALOG_T
T132T132
CPU_TEST6_DIECRACKMON
T9T9
H_THERMDC
H_THERMDA
CPU_TEST3_GATE0
T10T10
CPU_TEST2_DRAIN0
T14T14
CPU_RSVD_MA0_CLK3_P
T34T34
CPU_RSVD_MA0_CLK3_N
T36T36
CPU_RSVD_MA0_CLK0_P
T40T40
CPU_RSVD_MA0_CLK0_N
T38T38
CPU_RSVD_MB0_CLK3_P
T28T28
CPU_RSVD_MB0_CLK3_N
T26T26
CPU_RSVD_MB0_CLK0_P
T33T33
CPU_RSVD_MB0_CLK0_N
T31T31
+1.8VSUS
2
Q68
Q68
1
*HDT@FDV301N
*HDT@FDV301N
+1.8VSUS+1.8VSUS
R429
R429
10K_4
10K_4
2
13
Q55 MMBT3904Q55 MMBT3904
C190
C190
0.22u/10V_4
0.22u/10V_4
+3V
FD4
FD4
*HDT@BAS316
*HDT@BAS316
R500
R500
*HDT@2K_4
*HDT@2K_4
3
+3V
R424
R424
4.7K_4
4.7K_4
12
CPU_HTREF1
CPU_HTREF0
CPU to HDT RESET#CPU_HT_RESET#
R426 *0_4R426 *0_4
C191
C191
3300p/50V_4
3300p/50V_4
F8
F9
B7
A7
F10
AF4
AF5
P6
R6
F6
E6
W9
Y9
A9
A8
G10
AA9
AC9
AD9
AF9
E9
E8
G9
H10
AA7
C2
D7
E7
F7
C7
AC8
C3
AA6
W7
W8
Y6
AB6
P20
P19
N20
N19
R26
R25
P22
R22
U25D
U25D
VDDA2
VDDA1
RESET_L
PWROK
LDTSTOP_L
SIC
SID
HT_REF1
HT_REF0
VDD_FB_H
VDD_FB_L
VDDIO_FB_H
VDDIO_FB_L
CLKIN_H
CLKIN_L
DBRDY
TMS
TCK
TRST_L
TDI
TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9
TEST17
TEST16
TEST15
TEST14
TEST12
TEST7
TEST6
TEST5
TEST4
TEST3
TEST2
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
THERMTRIP_L
PROCHOT_L
CPU_PRESENT_L
MISC
MISC
AMD NPT S1 SOCKET
Processor Socket
TALERT# 16
AMD_PROCHOT 14,29
2
R445
R445
300_4
300_4
H_THERMTRIP#
AF6
H_PROCHOT#
AC7
A5
VID5
C6
VID4
A6
VID3
A4
VID2
C5
VID1
B5
VID0
CPU_PRESENT#
AC6
A3
PSI_L
PSI_L is a Power Status Indicator signal. This signal is asserted
when the processor is in a low powerstate. PSI_L should be
connected to the power supply controller, if the controller
supports “skipmode, or diode emulation mode”. PSI_L is asserted by
the processor during the C3 and S1 states.
CPU_DBREQ#
E10
DBREQ_L
CPU_TDO
AE9
TDO
CPU_TEST29_H_FBCLKOUT_P
C9
TEST29_H
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
TEST8
RSVD8
RSVD9
C8
AE7
AD7
AE8
AB8
AF7
J7
H8
AF8
AE6
K8
C4
H16
B18
B3
C1
H6
G6
D5
R24
W18
R23
AA8
H18
H19
+1.8VSUS
R53 *HDT@220_4R53 *HDT@220_4
CPU_TEST29_L_FBCLKOUT_N
CPU_TEST24_SCANCLK1
CPU_TEST23_TSTUPD
CPU_TEST22_SCANSHIFTEN
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST28_H_PLLCHRZ_P
CPU_TEST28_L_PLLCHRZ_N
CPU_TEST27_SINGLECHAIN
CPU_TEST26_BURNIN#
CPU_TEST10_ANALOGOUT
CPU_TEST08_DIG_T
CPU_MA_RESET#
CPU_MB_RESET#
CPU_RSVD_VIDSTRB1
CPU_RSVD_VIDSTRB0
CPU_RSVD_VDDNB_FB_P
CPU_RSVD_VDDNB_FB_N
CPU_RSVD_CORE_TYPE
IF no use which Net
R440 *HDT@220_4R440 *HDT@220_4
need pull-up or down
R54 *HDT@220_4R54 *HDT@220_4
R485 *HDT@220_4R485 *HDT@220_4
R55 *HDT@220_4R55 *HDT@220_4
PLACE IT CLOSE TO CPU WITHIN 1"
ROUTE AS 80 Ohm DIFFERENTIAL PAIR
HDT CONNECTOR
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
TURION 64 CTRL & DEBUG
TURION 64 CTRL & DEBUG
TURION 64 CTRL & DEBUG
Date: Sheet of
Date: Sheet of
Date: Sheet of
+1.8VSUS+1.8VSUS
R484
R484
300_4
300_4
H_VID5 34
H_VID4 34
H_VID3 34
H_VID2 34
H_VID1 34
H_VID0 34
R462 80.6F_4R462 80.6F_4
T8T8
T49T49
T56T56
T53T53
T135T135
T54T54
T133T133
T136T136
T131T131
T52T52
T51T51
T134T134
T48T48
T55T55
T6T6
T5T5
T128T128
T4T4
T129T129
T141T141
PROJECT : BD3A
PROJECT : BD3A
Quanta Computer Inc.
Quanta Computer Inc.
1
CPU to HDT RESET#
638Wednesday, February 13, 2008
638Wednesday, February 13, 2008
638Wednesday, February 13, 2008
3C
3C
3C
5
4
3
2
1
PROCESSOR POWER AND GROUND
D D
U25F
U25F
AA4
VSS1
AA11
VSS2
AA13
VSS3
AA15
VSS4
AA17
VSS5
AA19
VSS6
AB2
VSS7
AB7
VSS8
AB9
VSS9
AB23
VSS10
AB25
VCC_CORE VCC_CORE
C C
B B
A1
AC4
AD2
M10
N11
R11
U11
U13
J11
J13
K10
K12
K14
L11
L13
P10
T10
T12
T14
V10
U25E
U25E
VDD1
VDD2
G4
VDD3
H2
VDD4
J9
VDD5
VDD6
VDD7
K6
VDD8
VDD9
VDD10
VDD11
L4
VDD12
L7
VDD13
L9
VDD14
VDD15
VDD16
M2
VDD17
M6
VDD18
M8
VDD19
VDD20
N7
VDD21
N9
VDD22
VDD23
P8
VDD24
VDD25
R4
VDD26
R7
VDD27
R9
VDD28
VDD29
T2
VDD30
T6
VDD31
T8
VDD32
VDD33
VDD34
VDD35
U7
VDD36
U9
VDD37
VDD38
VDD39
V6
VDD40
V8
VDD41
VDD42
POWER
POWER
Athlon 64 S1
Processor Socket
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
V12
V14
W4
Y2
J15
K16
L15
M16
P16
T16
U15
V16
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23
T25
U17
V18
V21
V23
V25
Y25
+1.8VSUS
A26
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B11
B13
B15
B17
B19
B21
B23
B25
D11
D13
D15
D17
D19
D21
D23
D25
H21
H23
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
B4
VSS28
B6
VSS29
B8
VSS30
B9
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
D6
VSS40
D8
VSS41
D9
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
E4
VSS51
F2
VSS52
F11
VSS53
F13
VSS54
F15
VSS55
F17
VSS56
F19
VSS57
F21
VSS58
F23
VSS59
F25
VSS60
H7
VSS61
H9
VSS62
VSS63
VSS64
J4
VSS65
GROUND
GROUND
Athlon 64 S1
Processor Socket
Athlon 64 S1g1
uPGA638
Top View
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
M11
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
VCC_CORE
C133
VCC_CORE
+1.8VSUS
C147
C147
10u/6.3V_6
10u/6.3V_6
C122
C122
0.22u/10V_4
0.22u/10V_4
C130
C130
10u/10V_8
10u/10V_8
C114
C114
10u/6.3V_6
10u/6.3V_6
C121
C121
0.22u/10V_4
0.22u/10V_4
C166
C166
10u/10V_8
10u/10V_8
C129
C129
10u/6.3V_6
10u/6.3V_6
C120
C120
0.01u/25V_4
0.01u/25V_4
C491
C491
0.22u/10V_4
0.22u/10V_4
C133
10u/6.3V_6
10u/6.3V_6
C146
C146
0.22u/10V_4
0.22u/10V_4
C168
C168
10u/6.3V_6
10u/6.3V_6
C119
C119
180p/50V_4
180p/50V_4
C124
C124
10u/6.3V_6
10u/6.3V_6
C140
C140
10u/6.3V_6
10u/6.3V_6
DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE
+1.8VSUS
C108
BOTTOMSIDE DECOUPLING
C108
4.7u/6.3V_6
4.7u/6.3V_6
C136
C136
0.22u/10V_4
0.22u/10V_4
C473
C473
0.22u/10V_4
0.22u/10V_4
C176
C176
0.22u/10V_4
0.22u/10V_4
C160
C160
0.22u/10V_4
0.22u/10V_4
C182
C182
0.01u/25V_4
0.01u/25V_4
+1.8VSUS
C106
C106
4.7u/6.3V_6
4.7u/6.3V_6
C109
C109
0.01u/25V_4
0.01u/25V_4
C110
C110
4.7u/6.3V_6
4.7u/6.3V_6
C193
C193
180p/50V_4
180p/50V_4
C105
C105
4.7u/6.3V_6
4.7u/6.3V_6
C104
C104
180p/50V_4
180p/50V_4
C154
C154
10u/6.3V_6
10u/6.3V_6
C107
C107
0.22u/10V_4
0.22u/10V_4
C143
C143
180p/50V_4
180p/50V_4
C163
C163
10u/6.3V_6
10u/6.3V_6
C150
C150
0.22u/10V_4
0.22u/10V_4
A A
AF1
PROJECT : BD3A
PROJECT : BD3A
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
TURION 64 PWR & GND
TURION 64 PWR & GND
TURION 64 PWR & GND
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
738Wednesday, February 13, 2008
738Wednesday, February 13, 2008
738Wednesday, February 13, 2008
1
3C
3C
3C
5
+1.8VSUS
103
111
104
201
M_A_A[0..15]5,9
R80 *4.7K_4R80 *4.7K_4
+3V
R74 *4.7K_4R74 *4.7K_4
D D
M_A_DM[0..7]5
C C
B B
A A
M_A_DQS[0..7]5
M_A_DQS#[0..7]5
+3V
+1.8VSUS
SA0_A
SA1_A
12
12
R72 0_4R72 0_4
M_A_BS#05,9
M_A_BS#15,9
M_A_BS#25,9
M_CLKOUT05
M_CLKOUT0#5
M_CLKOUT15
M_CLKOUT1#5
M_CKE05,9
M_CKE15,9
M_A_RAS#5,9
M_A_CAS#5,9
M_A_WE#5,9
M_A_CS#05,9
M_A_CS#15,9
M_ODT05,9
M_ODT15,9
C250 0.1u/10V_4C250 0.1u/10V_4
C246
C246
2.2u/10V_8
2.2u/10V_8
M_CLKOUT0
C231
C231
1.5p/50V_4
1.5p/50V_4
M_CLKOUT0#
M_CLKOUT1
C449
C449
1.5p/50V_4
1.5p/50V_4
M_CLKOUT1#
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
0_4
0_4
M_A_A7
M_A_A8
M_A_A9
R85
R85
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_CLKOUT0
M_CLKOUT0#
M_CLKOUT1
M_CLKOUT1#
SA0_A
SA1_A
DDRDAT_SMB DDRCLK_SMB
DDRCLK_SMB
C83 0.1u/10V_4C83 0.1u/10V_4
MVREF_DIM
C247
C247
0.1u/10V_4
0.1u/10V_4
1 2
5
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10
90
A11
89
A12
116
A13
86
A14
84
A15
107
BA0
106
BA1
85
BA2
10
DM0
26
DM1
52
DM2
67
DM3
130
DM4
147
DM5
170
DM6
185
DM7
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
11
DQS0
29
DQS1
49
DQS2
68
DQS3
129
DQS4
146
DQS5
167
DQS6
186
DQS7
30
CK0
32
CK0
164
CK1
166
CK1
79
CKE0
80
CKE1
108
RAS
113
CAS
109
WE
110
S0
115
S1
114
ODT0
119
ODT1
198
SA0
200
SA1
195
SDA
197
SCL
199
VDDspd
1
VREF
2
VSS0
3
VSS1
8
VSS2
9
VSS3
12
VSS4
15
VSS5
18
VSS6
21
VSS7
24
VSS8
27
VSS9
28
VSS10
33
VSS11
34
VSS12
39
VSS13
40
VSS14
41
VSS15
42
VSS16
47
VSS17
48
VSS18
53
VSS19
54
VSS20
202
VDD081VDD182VDD287VDD388VDD495VDD596VDD6
GND PAD0
GND PAD1
SPD Address:0xA0
(H=5.6)
59
112
VDD8
VDD7
VDD9
REVERSE
SO-DIMM
SO-DIMM
VSS30
VSS29
VSS2878VSS2777VSS2672VSS2571VSS2466VSS2365VSS2260VSS21
122
121
117
VDD10
VSS31
127
118
VDD11
NC/TEST
VSS33
VSS32
132
128
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
4
CN24
CN24
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
50
NC1
69
NC2
83
NC3
120
NC4
163
196
193
190
187
184
183
178
177
172
171
168
165
162
161
156
155
150
149
145
144
139
138
133
DDRII_SODIMM_R
DDRII_SODIMM_R
4
M_A_DQ1
M_A_DQ5
M_A_DQ2
M_A_DQ3
M_A_DQ0
M_A_DQ4
M_A_DQ7
M_A_DQ6
M_A_DQ12
M_A_DQ8
M_A_DQ10
M_A_DQ14
M_A_DQ13
M_A_DQ9
M_A_DQ15
M_A_DQ11
M_A_DQ21
M_A_DQ17
M_A_DQ23
M_A_DQ18
M_A_DQ20
M_A_DQ19
M_A_DQ22
M_A_DQ16
M_A_DQ29
M_A_DQ28
M_A_DQ31
M_A_DQ26
M_A_DQ25
M_A_DQ24
M_A_DQ27
M_A_DQ30
M_A_DQ32
M_A_DQ36
M_A_DQ37
M_A_DQ35
M_A_DQ33
M_A_DQ38
M_A_DQ34
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ46
M_A_DQ44
M_A_DQ45
M_A_DQ43
M_A_DQ47
M_A_DQ55
M_A_DQ54
M_A_DQ50
M_A_DQ51
M_A_DQ53
M_A_DQ48
M_A_DQ49
M_A_DQ52
M_A_DQ56
M_A_DQ60
M_A_DQ59
M_A_DQ58
M_A_DQ57
M_A_DQ61
M_A_DQ63
M_A_DQ62
T58T58
T137T137
T130T130
+SMDDR_VREF
Stuff No Stuff
M_A_DQ[0..63] 5
+3V
M_A_CS#2 5,9
M_A_CS#3 5,9
+3V
+1.8VSUS
+1.8VSUS
R215
R215
0_6
0_6
MVREF_DIM
C257
C257
1u/6.3V_4
1u/6.3V_4
1.This part should not contain any substances which are specified in SS-00259-1
2.Purchase ink, paint, wire rods and molding resins only from the business partners that Sony approves as Green Partners.
M_B_A[0..15]5,9
R79 4.7K_4R79 4.7K_4
R73 *4.7K_4R73 *4.7K_4
R71 0_4R71 0_4
M_B_DM[0..7]5
M_B_DQS[0..7]5
M_B_DQS#[0..7]5
M_CLKOUT35
M_CLKOUT3#5
M_CLKOUT45
M_CLKOUT4#5
M_CKE25,9
M_CKE35,9
M_B_RAS#5,9
M_B_CAS#5,9
M_B_WE#5,9
M_B_CS#05,9
M_B_CS#15,9
M_ODT25,9
M_ODT35,9
C260 0.1u/10V_4C260 0.1u/10V_4
2.2u/10V_8
2.2u/10V_8
R207
R207
*1K/F_4
*1K/F_4
R206
R206
No Stuff
*1K/F_4
*1K/F_4
12
C251
C251
12
R83 *0_4R83 *0_4
M_B_BS#05,9
M_B_BS#15,9
M_B_BS#25,9
SA0_B
SA1_B
SA0_B
SA1_B
DDRDAT_SMB
C72 0.1u/10V_4C72 0.1u/10V_4
1 2
M_CLKOUT3
C230
C230
1.5p/50V_4
1.5p/50V_4
M_CLKOUT3#
M_CLKOUT4
C448
C448
1.5p/50V_4
1.5p/50V_4
M_CLKOUT4#
3
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_CLKOUT3
M_CLKOUT3#
M_CLKOUT4
M_CLKOUT4#
MVREF_DIM
C259
C259
0.1u/10V_4
0.1u/10V_4
3
201
202
102
A0
101
A1
100
A2
99
A3
98
GND PAD0
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10
90
A11
89
A12
116
A13
86
A14
84
A15
107
BA0
106
BA1
85
BA2
10
DM0
26
DM1
52
DM2
67
DM3
130
DM4
147
DM5
170
DM6
185
DM7
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
11
DQS0
29
DQS1
49
DQS2
68
DQS3
129
DQS4
146
DQS5
167
DQS6
186
DQS7
30
CK0
32
CK0
164
CK1
166
CK1
79
CKE0
80
CKE1
108
RAS
113
CAS
109
WE
110
S0
115
S1
114
ODT0
119
ODT1
198
SA0
200
SA1
195
SDA
197
SCL
199
VDDspd
1
VREF
2
VSS0
3
VSS1
8
VSS2
9
VSS3
12
VSS4
15
VSS5
18
VSS6
21
VSS7
24
VSS8
27
VSS9
28
VSS10
33
VSS11
34
VSS12
39
VSS13
40
VSS14
41
VSS15
42
VSS16
47
VSS17
48
VSS18
53
VSS19
54
VSS20
+1.8VSUS
103
111
104
112
117
VDD081VDD182VDD287VDD388VDD495VDD596VDD6
GND PAD1
VDD7
VDD8
VDD9
REVERSE
SPD Address:0xA2
SO-DIMM
SO-DIMM
(H=10.1)
VSS30
VSS29
VSS2878VSS2777VSS2672VSS2571VSS2466VSS2365VSS2260VSS21
59
127
122
121
118
CN23
CN23
DQ0
DQ1
VDD10
VDD11
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
NC1
NC2
NC3
NC4
NC/TEST
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
DDRII_SODIMM_R
DDRII_SODIMM_R
132
128
2
SDATA03,15,25
SCLK03,15,25
M_B_DQ[0..63] 5
+1.8VSUS
*10u/10V_8C216 *10u/10V_8C216
*10u_8C167 *10u_8C167
10u/10V_8C102 10u/10V_8C102
10u/10V_8C222 10u/10V_8C222
0.1u/10V_4C465 0.1u/10V_4C465
0.1u/10V_4C161 0.1u/10V_4C161
0.1u/10V_4C199 0.1u/10V_4C199
0.1u/10V_4C223 0.1u/10V_4C223
0.1u/10V_4C486 0.1u/10V_4C486
0.1u/10V_4C460 0.1u/10V_4C460
0.1u/10V_4C464 0.1u/10V_4C464
0.1u/10V_4C472 0.1u/10V_4C472
0.1u/10V_4C468 0.1u/10V_4C468
0.1u/10V_4C162 0.1u/10V_4C162
0.1u/10V_4C463 0.1u/10V_4C463
0.1u/10V_4C213 0.1u/10V_4C213
0.1u/10V_4C485 0.1u/10V_4C485
0.1u/10V_4C224 0.1u/10V_4C224
0.1u/10V_4C466 0.1u/10V_4C466
0.1u/10V_4C198 0.1u/10V_4C198
0.1u/10V_4C180 0.1u/10V_4C180
0.1u/10V_4C181 0.1u/10V_4C181
0.1u/10V_4C212 0.1u/10V_4C212
0.1u/10V_4C461 0.1u/10V_4C461
+1.8VSUS
*0.1u/10V_4C489 *0.1u/10V_4C489
*0.1u/10V_4C248 *0.1u/10V_4C248
*0.1u/10V_4C462 *0.1u/10V_4C462
M_B_CS#2 5,9
M_B_CS#3 5,9
+3V
3
R44 *0_4R44 *0_4
+3V
3
R70 *0_4R70 *0_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
DDRII SODIMM X 2
DDRII SODIMM X 2
DDRII SODIMM X 2
Date: Sheet of
Date: Sheet of
Date: Sheet
*0.1u/10V_4C261 *0.1u/10V_4C261
Q21
Q21
2
RHU002N06
RHU002N06
1
Q20
Q20
2
RHU002N06
RHU002N06
1
PROJECT : BD3A
PROJECT : BD3A
Quanta Computer Inc.
Quanta Computer Inc.
M_B_DQ4
5
M_B_DQ1
7
M_B_DQ2
17
M_B_DQ3
19
M_B_DQ5
4
M_B_DQ0
6
M_B_DQ6
14
M_B_DQ7
16
M_B_DQ8
23
M_B_DQ9
25
M_B_DQ10
35
M_B_DQ15
37
M_B_DQ12
20
M_B_DQ13
22
M_B_DQ14
36
M_B_DQ11
38
M_B_DQ16
43
M_B_DQ21
45
M_B_DQ19
55
M_B_DQ23
57
M_B_DQ20
44
M_B_DQ17
46
M_B_DQ18
56
M_B_DQ22
58
M_B_DQ29
61
M_B_DQ28
63
M_B_DQ26
73
M_B_DQ27
75
M_B_DQ24
62
M_B_DQ25
64
M_B_DQ30
74
M_B_DQ31
76
M_B_DQ32
123
M_B_DQ36
125
M_B_DQ39
135
M_B_DQ35
137
M_B_DQ33
124
M_B_DQ37
126
M_B_DQ34
134
M_B_DQ38
136
M_B_DQ40
141
M_B_DQ41
143
M_B_DQ46
151
M_B_DQ43
153
M_B_DQ44
140
M_B_DQ45
142
M_B_DQ47
152
M_B_DQ42
154
M_B_DQ53
157
M_B_DQ49
159
M_B_DQ55
173
M_B_DQ54
175
M_B_DQ48
158
M_B_DQ52
160
M_B_DQ50
174
M_B_DQ51
176
M_B_DQ60
179
M_B_DQ57
181
M_B_DQ62
189
M_B_DQ59
191
M_B_DQ61
180
M_B_DQ56
182
M_B_DQ63
192
M_B_DQ58
194
50
T59T59
69
T57T57
83
120
163
T29T29
196
193
190
187
184
183
178
177
172
171
168
165
162
161
156
155
150
149
145
144
139
138
133
2
R67
R67
10K_4
10K_4
1
R66
R66
10K_4
10K_4
DDRDAT_SMB
DDRCLK_SMB
1
3C
3C
3C
of
838Wednesday, February 13, 2008
838Wednesday, February 13, 2008
838Wednesday, February 13, 2008
5
D D
+SMDDR_VTERM
C C
4
+1.8VSUS
*10u/10V_8C63 *10u/10V_8C63
*10u/10V_8C59 *10u/10V_8C59
0.1u/10V_4C126 0.1u/10V_4C126
0.1u/10V_4C499 0.1u/10V_4C499
0.1u/10V_4C225 0.1u/10V_4C225
0.1u/10V_4C527 0.1u/10V_4C527
0.1u/10V_4C97 0.1u/10V_4C97
0.1u/10V_4C237 0.1u/10V_4C237
0.1u/10V_4C132 0.1u/10V_4C132
0.1u/10V_4C100 0.1u/10V_4C100
0.1u/10V_4C92 0.1u/10V_4C92
*0.1u/10V_4C117 *0.1u/10V_4C117
*0.1u/10V_4C229 *0.1u/10V_4C229
0.1u/10V_4C115 0.1u/10V_4C115
0.1u/10V_4C118 0.1u/10V_4C118
0.1u/10V_4C99 0.1u/10V_4C99
0.1u/10V_4C495 0.1u/10V_4C495
0.1u/10V_4C137 0.1u/10V_4C137
*0.1u/10V_4C507 *0.1u/10V_4C507
0.1u/10V_4C138 0.1u/10V_4C138
0.1u/10V_4C139 0.1u/10V_4C139
0.1u/10V_4C493 0.1u/10V_4C493
*0.1u/10V_4C236 *0.1u/10V_4C236
0.1u/10V_4C243 0.1u/10V_4C243
0.1u/10V_4C515 0.1u/10V_4C515
0.1u/10V_4C96 0.1u/10V_4C96
*0.1u/10V_4C103 *0.1u/10V_4C103
0.1u/10V_4C490 0.1u/10V_4C490
+SMDDR_VTERM
0.1u/10V_4C195 0.1u/10V_4C195
0.1u/10V_4C175 0.1u/10V_4C175
0.1u/10V_4C201 0.1u/10V_4C201
0.1u/10V_4C169 0.1u/10V_4C169
0.1u/10V_4C197 0.1u/10V_4C197
0.1u/10V_4C170 0.1u/10V_4C170
0.1u/10V_4C200 0.1u/10V_4C200
0.1u/10V_4C165 0.1u/10V_4C165
0.1u/10V_4C183 0.1u/10V_4C183
0.1u/10V_4C184 0.1u/10V_4C184
0.1u/10V_4C174 0.1u/10V_4C174
0.1u/10V_4C158 0.1u/10V_4C158
0.1u/10V_4C159 0.1u/10V_4C159
0.1u/10V_4C164 0.1u/10V_4C164
0.1u/10V_4C194 0.1u/10V_4C194
0.1u/10V_4C196 0.1u/10V_4C196
3
M_CKE05,8
M_CKE15,8
M_CKE25,8
M_CKE35,8
M_ODT05,8
M_ODT15,8
M_ODT25,8
M_ODT35,8
M_A_BS#05,8
M_A_BS#15,8
M_A_BS#25,8
M_A_WE#5,8
M_A_CAS#5,8
M_A_RAS#5,8
M_B_BS#05,8
M_B_BS#15,8
M_B_BS#25,8
M_B_WE#5,8
M_B_CAS#5,8
M_B_RAS#5,8
M_A_CS#05,8
M_A_CS#15,8
M_A_CS#25,8
M_A_CS#35,8
M_B_CS#05,8
M_B_CS#15,8
M_B_CS#25,8
M_B_CS#35,8
M_A_A[0..15]5,8
M_A_A13
M_A_A10
M_A_A0
M_A_A2
M_A_A4
M_A_A6
M_A_A7
M_A_A11
M_A_A12
M_A_A9
M_A_A3
M_A_A1
M_A_A8
M_A_A5
M_A_A14
M_A_A15
2
R167 47_4R167 47_4
R164 47_4R164 47_4
R170 47_4R170 47_4
R155 47_4R155 47_4
R120 47_4R120 47_4
R115 47_4R115 47_4
R112 47_4R112 47_4
R119 47_4R119 47_4
R130 47_4R130 47_4
R137 47_4R137 47_4
R159 47_4R159 47_4
R133 47_4R133 47_4
R121 47_4R121 47_4
R132 47_4R132 47_4
R140 47_4R140 47_4
R127 47_4R127 47_4
R161 47_4R161 47_4
R124 47_4R124 47_4
R129 47_4R129 47_4
R123 47_4R123 47_4
R128 47_4R128 47_4
R126 47_4R126 47_4
R163 47_4R163 47_4
R114 47_4R114 47_4
R118 47_4R118 47_4
R113 47_4R113 47_4
R166 47_4R166 47_4
R101 47_4R101 47_4
R125 47_4R125 47_4
R139 47_4R139 47_4
RP13 0404-47X2RP13 0404-47X2
1 2
3 4
RP17 0404-47X2RP17 0404-47X2
1 2
3 4
RP21 0404-47X2RP21 0404-47X2
1 2
3 4
RP22 0404-47X2RP22 0404-47X2
1 2
3 4
RP14 0404-47X2RP14 0404-47X2
1 2
3 4
RP18 0404-47X2RP18 0404-47X2
1 2
3 4
RP24 0404-47X2RP24 0404-47X2
1 2
3 4
1
+SMDDR_VTERM
B B
A A
5
4
M_B_A[0..15]5,8
3
M_B_A0
M_B_A2
M_B_A4
M_B_A6
M_B_A7
M_B_A11
M_B_A3
M_B_A1
M_B_A8
M_B_A5
M_B_A12
M_B_A9
M_B_A10
M_B_A13
M_B_A14
M_B_A15
RP11 0404-47X2RP11 0404-47X2
1 2
3 4
RP12 0404-47X2RP12 0404-47X2
1 2
3 4
RP16 0404-47X2RP16 0404-47X2
1 2
3 4
RP15 0404-47X2RP15 0404-47X2
1 2
3 4
RP19 0404-47X2RP19 0404-47X2
1 2
3 4
RP23 0404-47X2RP23 0404-47X2
1 2
3 4
R134 47_4R134 47_4
R106 47_4R106 47_4
RP20 0404-47X2RP20 0404-47X2
1 2
3 4
2
PROJECT : BD3A
PROJECT : BD3A
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
DDRII TERMINATION
DDRII TERMINATION
DDRII TERMINATION
Date: Sheet of
Date: Sheet of
Date: Sheet of
938Wednesday, February 13, 2008
938Wednesday, February 13, 2008
938Wednesday, February 13, 2008
1
3C
3C
3C
5
D D
HT_CADOUT15_P4
HT_CADOUT15_N4
HT_CADOUT14_P4
HT_CADOUT14_N4
HT_CADOUT13_P4
HT_CADOUT13_N4
HT_CADOUT12_P4
HT_CADOUT12_N4
HT_CADOUT11_P4
HT_CADOUT11_N4
HT_CADOUT10_P4
HT_CADOUT10_N4
HT_CADOUT9_P4
HT_CADOUT9_N4
HT_CADOUT8_P4
HT_CADOUT8_N4
C C
VDDHT_PKG
B B
HT_CADOUT7_P4
HT_CADOUT7_N4
HT_CADOUT6_P4
HT_CADOUT6_N4
HT_CADOUT5_P4
HT_CADOUT5_N4
HT_CADOUT4_P4
HT_CADOUT4_N4
HT_CADOUT3_P4
HT_CADOUT3_N4
HT_CADOUT2_P4
HT_CADOUT2_N4
HT_CADOUT1_P4
HT_CADOUT1_N4
HT_CADOUT0_P4
HT_CADOUT0_N4
HT_CLKOUT1_P4
HT_CLKOUT1_N4
HT_CLKOUT0_P4
HT_CLKOUT0_N4
HT_CTLOUT0_P4
HT_CTLOUT0_N4
4
R452 49.9_4R452 49.9_4
3
U24A
U24A
R19
HT_RXCAD15P
R18
HT_RXCAD15N
R21
HT_RXCAD14P
R22
HT_RXCAD14N
U22
HT_RXCAD13P
U21
HT_RXCAD13N
U18
HT_RXCAD12P
U19
HT_RXCAD12N
W19
HT_RXCAD11P
W20
HT_RXCAD11N
AC21
HT_RXCAD10P
AB22
HT_RXCAD10N
AB20
HT_RXCAD9P
AA20
HT_RXCAD9N
AA19
HT_RXCAD8P
Y19
HT_RXCAD8N
T24
HT_RXCAD7P
R25
HT_RXCAD7N
U25
HT_RXCAD6P
U24
HT_RXCAD6N
V23
HT_RXCAD5P
U23
HT_RXCAD5N
V24
HT_RXCAD4P
V25
HT_RXCAD4N
AA25
HT_RXCAD3P
AA24
HT_RXCAD3N
AB23
HT_RXCAD2P
AA23
HT_RXCAD2N
AB24
HT_RXCAD1P
AB25
HT_RXCAD1N
AC24
HT_RXCAD0P
AC25
HT_RXCAD0N
W21
HT_RXCLK1P
W22
HT_RXCLK1N
Y24
HT_RXCLK0P
W25
HT_RXCLK0N
P24
HT_RXCTLP
P25
HT_RXCTLN
A24
HT_RXCALN HT_TXCALN
C24
HT_RXCALP
HT_RXCALN
RS690M
RS690M
PART 1 OF 5
PART 1 OF 5
HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N
HT_TXCLK1P
HT_TXCLK1N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCTLP
HYPER TRANSPORT CPU I/F
HYPER TRANSPORT CPU I/F
HT_TXCTLN
HT_TXCALP
HT_TXCALN
P21
P22
P18
P19
M22
M21
M18
M19
L18
L19
G22
G21
J20
J21
F21
F22
N24
N25
L25
M24
K25
K24
J23
K23
G25
H24
F25
F24
E23
F23
E24
E25
L21
L22
J24
J25
N23
P23
C25
D24
HT_TXCALPHT_RXCALP
HT_CADIN15_P 4
HT_CADIN15_N 4
HT_CADIN14_P 4
HT_CADIN14_N 4
HT_CADIN13_P 4
HT_CADIN13_N 4
HT_CADIN12_P 4
HT_CADIN12_N 4
HT_CADIN11_P 4
HT_CADIN11_N 4
HT_CADIN10_P 4
HT_CADIN10_N 4
HT_CADIN9_P 4
HT_CADIN9_N 4
HT_CADIN8_P 4
HT_CADIN8_N 4
HT_CADIN7_P 4
HT_CADIN7_N 4
HT_CADIN6_P 4
HT_CADIN6_N 4
HT_CADIN5_P 4
HT_CADIN5_N 4
HT_CADIN4_P 4
HT_CADIN4_N 4
HT_CADIN3_P 4
HT_CADIN3_N 4
HT_CADIN2_P 4
HT_CADIN2_N 4
HT_CADIN1_P 4
HT_CADIN1_N 4
HT_CADIN0_P 4
HT_CADIN0_N 4
HT_CLKIN1_P 4
HT_CLKIN1_N 4
HT_CLKIN0_P 4
HT_CLKIN0_N 4
HT_CTLIN0_P 4
HT_CTLIN0_N 4
R451 100_4R451 100_4R454 49.9_4R454 49.9_4
2
1
A A
PROJECT : BD3A
PROJECT : BD3A
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
RS690M HT LINK I/F
RS690M HT LINK I/F
RS690M HT LINK I/F
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
10 38Wednesday, February 13, 2008
10 38Wednesday, February 13, 2008
10 38Wednesday, February 13, 2008
1
3C
3C
3C
5
4
3
2
1
BTO
D D
Place these caps close to connector
U24B
U24B
PEG_RXP15
PEG_RXN15
PEG_RXP14
PEG_RXN14
PEG_RXP13
PEG_RXN13
PEG_RXP12
PEG_RXN12
PEG_RXP11
PEG_RXN[15:0]21
PEG_RXP[15:0]21
C C
B B
PEG_RXN[15:0] PEG_TXN[15:0]
GPP_RX1P_WLAN25
GPP_RX1N_WLAN25
GPP_RX2P_MINICARD25
GPP_RX2N_MINICARD25
GPP_RX0P_LAN24
GPP_RX0N_LAN24
GPP_RX3P_NEWCARD25
GPP_RX3N_NEWCARD25
A_RX0P14
A_RX0N14
A_RX1P14
A_RX1N14
A_RX2P14
A_RX2N14
A_RX3P14
A_RX3N14
PEG_RXN11
PEG_RXP10
PEG_RXN10
PEG_RXP9
PEG_RXN9
PEG_RXP8
PEG_RXN8
PEG_RXP7
PEG_RXN7
PEG_RXP6
PEG_RXN6
PEG_RXP5
PEG_RXN5
PEG_RXP4
PEG_RXN4
PEG_RXP3
PEG_RXN3
PEG_RXP2
PEG_RXN2
PEG_RXP1
PEG_RXN1
PEG_RXP0
PEG_RXN0
R88 *10K/F_4R88 *10K/F_4
R89 *8.25K/F_4R89 *8.25K/F_4
G5
GFX_RX0P
G4
GFX_RX0N
J8
GFX_RX1P
J7
GFX_RX1N
J4
GFX_RX2P
J5
GFX_RX2N
L8
GFX_RX3P
L7
GFX_RX3N
L4
GFX_RX4P
L5
GFX_RX4N
M8
GFX_RX5P
M7
GFX_RX5N
M4
GFX_RX6P
M5
GFX_RX6N
P8
GFX_RX7P
P7
GFX_RX7N
P4
GFX_RX8P
P5
GFX_RX8N
R4
GFX_RX9P
R5
GFX_RX9N
R7
GFX_RX10P
R8
GFX_RX10N
U4
GFX_RX11P
U5
GFX_RX11N
W4
GFX_RX12P
W5
GFX_RX12N
Y4
GFX_RX13P
Y5
GFX_RX13N
V9
GFX_RX14P
W9
GFX_RX14N
AB7
GFX_RX15P
AB6
GFX_RX15N
AD16
GPP_RX0P
AE16
GPP_RX0N
AD20
GPP_RX1P
AE20
GPP_RX1N
Y7
GPP_RX2P
AA7
GPP_RX2N
AB9
GPP_RX3P
AA9
GPP_RX3N
W14
SB_RX0P
W15
SB_RX0N
AB12
SB_RX1P
AA12
SB_RX1N
W11
SB_RX2P
W12
SB_RX2N
AA11
SB_RX3P
AB11
SB_RX3N
AA14
PCE_ISET(PCE_CALI)
AB14
PCE_TXISET(NC)
RS690M
RS690M
PART 2 OF 5
PART 2 OF 5
PCIE I/F GFX
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F GPP
PCIE I/F SB
PCIE I/F SB
PCE_PCAL(PCE_CALRP)
PCE_NCAL(PCE_CALRN)
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
J1
H2
K2
K1
K3
L3
L1
L2
N2
N1
P2
P1
P3
R3
R1
R2
T2
U1
V2
V1
V3
W3
W1
W2
Y2
AA1
AA2
AB2
AB1
AC1
AE3
AE4
AD14
AD15
AD19
AE19
AD4
AE5
AD5
AD6
AE9
AD10
AC8
AD9
AD8
AE8
AD7
AE7
AD11
AE11
C_PEG_TXP15
C_PEG_TXN15
C_PEG_TXP14
C_PEG_TXN14
C_PEG_TXP13
C_PEG_TXN13
C_PEG_TXP12
C_PEG_TXN12
C_PEG_TXP11
C_PEG_TXN11
C_PEG_TXP10
C_PEG_TXN10
C_PEG_TXP9
C_PEG_TXN9
C_PEG_TXP8
C_PEG_TXN8
C_PEG_TXP7
C_PEG_TXN7
C_PEG_TXP6
C_PEG_TXN6
C_PEG_TXP5
C_PEG_TXN5
C_PEG_TXP4
C_PEG_TXN4
C_PEG_TXP3
C_PEG_TXN3
C_PEG_TXP2
C_PEG_TXN2
C_PEG_TXP1
C_PEG_TXN1
C_PEG_TXP0
C_PEG_TXN0
A_CALRP
A_CALRN
C545 EV@0.1u/10V_4C545 EV@0.1u/10V_4
C544 EV@0.1u/10V_4C544 EV@0.1u/10V_4
C513 EV@0.1u/10V_4C513 EV@0.1u/10V_4
C512 EV@0.1u/10V_4C512 EV@0.1u/10V_4
C543 EV@0.1u/10V_4C543 EV@0.1u/10V_4
C542 EV@0.1u/10V_4C542 EV@0.1u/10V_4
C510 EV@0.1u/10V_4C510 EV@0.1u/10V_4
C509 EV@0.1u/10V_4C509 EV@0.1u/10V_4
C537 EV@0.1u/10V_4C537 EV@0.1u/10V_4
C536 EV@0.1u/10V_4C536 EV@0.1u/10V_4
C518 EV@0.1u/10V_4C518 EV@0.1u/10V_4
C517 EV@0.1u/10V_4C517 EV@0.1u/10V_4
C539 EV@0.1u/10V_4C539 EV@0.1u/10V_4
C538 EV@0.1u/10V_4C538 EV@0.1u/10V_4
C520 EV@0.1u/10V_4C520 EV@0.1u/10V_4
C519 EV@0.1u/10V_4C519 EV@0.1u/10V_4
C541 EV@0.1u/10V_4C541 EV@0.1u/10V_4
C540 EV@0.1u/10V_4C540 EV@0.1u/10V_4
C522 EV@0.1u/10V_4C522 EV@0.1u/10V_4
C521 EV@0.1u/10V_4C521 EV@0.1u/10V_4
C535 EV@0.1u/10V_4C535 EV@0.1u/10V_4
C534 EV@0.1u/10V_4C534 EV@0.1u/10V_4
C529 EV@0.1u/10V_4C529 EV@0.1u/10V_4
C528 EV@0.1u/10V_4C528 EV@0.1u/10V_4
C531 EV@0.1u/10V_4C531 EV@0.1u/10V_4
C526 EV@0.1u/10V_4C526 EV@0.1u/10V_4
C532 EV@0.1u/10V_4C532 EV@0.1u/10V_4
C530 EV@0.1u/10V_4C530 EV@0.1u/10V_4
C547 EV@0.1u/10V_4C547 EV@0.1u/10V_4
C533 EV@0.1u/10V_4C533 EV@0.1u/10V_4
C549 EV@0.1u/10V_4C549 EV@0.1u/10V_4
C546 EV@0.1u/10V_4C546 EV@0.1u/10V_4
GPP_TX0P_C
GPP_TX0N_C
GPP_TX1P_C
GPP_TX1N_C
GPP_TX2P_C
GPP_TX2N_C
GPP_TX3P_C
GPP_TX3N_C
A_TX0P_C
A_TX0N_C
A_TX1P_C
A_TX1N_C
A_TX2P_C
A_TX2N_C
A_TX3P_C
A_TX3N_C
C48 0.1u/10V_4C48 0.1u/10V_4
C45 0.1u/10V_4C45 0.1u/10V_4
C459 IV@0.1u/10V_4C459 IV@0.1u/10V_4
C454 IV@0.1u/10V_4C454 IV@0.1u/10V_4
C665 0.1u/10V_4C665 0.1u/10V_4
C662 0.1u/10V_4C662 0.1u/10V_4
C663 NEW@0.1u/10V_4C663 NEW@0.1u/10V_4
C453 0.1u/10V_4C453 0.1u/10V_4
C452 0.1u/10V_4C452 0.1u/10V_4
C458 0.1u/10V_4C458 0.1u/10V_4
C457 0.1u/10V_4C457 0.1u/10V_4
C451 0.1u/10V_4C451 0.1u/10V_4
C450 0.1u/10V_4C450 0.1u/10V_4
C456 0.1u/10V_4C456 0.1u/10V_4
C455 0.1u/10V_4C455 0.1u/10V_4
R447 562_4R447 562_4
R448 2K_4R448 2K_4
PEG_TXP15
PEG_TXN15
PEG_TXP14
PEG_TXN14
PEG_TXP13
PEG_TXN13
PEG_TXP12
PEG_TXN12
PEG_TXP11
PEG_TXN11
PEG_TXP10
PEG_TXN10
PEG_TXP9
PEG_TXN9
PEG_TXP8
PEG_TXN8
PEG_TXP7
PEG_TXN7
PEG_TXP6
PEG_TXN6
PEG_TXP5
PEG_TXN5
PEG_TXP4
PEG_TXN4
PEG_TXP3
PEG_TXN3
PEG_TXP2
PEG_TXN2
PEG_TXP1
PEG_TXN1
PEG_TXP0
PEG_TXN0
C660 NEW@0.1u/10V_4C660 NEW@0.1u/10V_4
VDDA12_PKG2
C_PEG_TXP15
C_PEG_TXN15
C_PEG_TXP14
C_PEG_TXN14
C_PEG_TXP13
C_PEG_TXN13
C_PEG_TXP12
C_PEG_TXN12
PEG_TXP[15:0]PEG_RXP[15:0]
GPP_TX1P_WLAN 25
GPP_TX1N_WLAN 25
GPP_TX2P_MINICARD 25
GPP_TX2N_MINICARD 25
GPP_TX0P_LAN 24
GPP_TX0N_LAN 24
GPP_TX3P_NEWCARD 25
GPP_TX3N_NEWCARD 25
A_TX0P 14
A_TX0N 14
A_TX1P 14
A_TX1N 14
A_TX2P 14
A_TX2N 14
A_TX3P 14
A_TX3N 14
C241 IV@0.1u/10V_4C241 IV@0.1u/10V_4
C242 IV@0.1u/10V_4C242 IV@0.1u/10V_4
C234 IV@0.1u/10V_4C234 IV@0.1u/10V_4
C235 IV@0.1u/10V_4C235 IV@0.1u/10V_4
C239 IV@0.1u/10V_4C239 IV@0.1u/10V_4
C240 IV@0.1u/10V_4C240 IV@0.1u/10V_4
C232 IV@0.1u/10V_4C232 IV@0.1u/10V_4
C233 IV@0.1u/10V_4C233 IV@0.1u/10V_4
PEG_TXN[15:0] 21
PEG_TXP[15:0] 21
IV_HDMITX2P 19
IV_HDMITX2N 19
IV_HDMITX1P 19
IV_HDMITX1N 19
IV_HDMITX0P 19
IV_HDMITX0N 19
IV_HDMICLK+ 19
IV_HDMICLK- 19
To HDMI CONN
Close to North Bridge
A A
PROJECT : BD3A
PROJECT : BD3A
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
RS690M PCIE LINK I/F
RS690M PCIE LINK I/F
RS690M PCIE LINK I/F
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
11 38Wednesday, February 13, 2008
11 38Wednesday, February 13, 2008
11 38Wednesday, February 13, 2008
1
3C
3C
3C
5
+1.8V
L17
L17
BK1608HS600_6
BK1608HS600_6
+1.8V
D D
L54
L54
BK1608HS600_6
BK1608HS600_6
+1.8V AVDDQ
L53
L53
BK1608HS600_6
BK1608HS600_6
+3V AVDD_NB
L19
L19
BK1608HS600_6
BK1608HS600_6
C C
LDT_STOP#6,14
+3V
B B
HTPVDD
*10u/10V_8
*10u/10V_8
C173
C173
PLLVDD
*10u/10V_8
*10u/10V_8
C483
C483
*10u/10V_8
*10u/10V_8
C481
C481
C207
C207
2.2u/6.3V_6
2.2u/6.3V_6
+1.8V
R102
R102
2.2K_4
2.2K_4
2
1 3
Q27
Q27
MMBT3904
MMBT3904
R141 10K_4R141 10K_4
R117 *3K_4R117 *3K_4
R136 *10K_4R136 *10K_4
+3V
R111
R111
10K_4
10K_4
LDT_STOP#_NB
TV_SWITCH
LOAD_ROM#
STRP_DATA
C187
C187
2.2u/6.3V_6
2.2u/6.3V_6
C470
C470
2.2u/6.3V_6
2.2u/6.3V_6
C480
C480
2.2u/10V_8
2.2u/10V_8
1 2
C205
C205
*0.1u/10V_4
*0.1u/10V_4
+1.8V AVDDI
R456 0_6R456 0_6
2.2u/10V_8
2.2u/10V_8
1 2
INT_TV_C/R18
INT_TV_Y/G18
BTO
INT_CRT_RED18
INT_CRT_GRN18
INT_CRT_BLU18
BTO
PLLVDD12
C477
C477
2.2u/6.3V_6
2.2u/6.3V_6
LOAD_ROM# : LOAD ROM STRAP ENABLE
High, LOAD ROM STRAP DISABLE
Low, LOAD ROM STRAP ENABLE
DFT_GPIO0
High, MEMORY SIDE PORT DISABLE
Low, MEMORY SIDE PORT ENABLE
+NB_CORE_ON35
NB_OSC
R122 68_4R122 68_4
A A
R135 0_4R135 0_4
5
STRP_DATA
C171 22P_4C171 22P_4
C482
C482
R153IV@150_4 R153IV@150_4
R149IV@150_4 R149IV@150_4
R152IV@150_4 R152IV@150_4
R151IV@150_4 R151IV@150_4
INT_LVDS_EDIDCLK20
INT_LVDS_EDIDDATA20
IV_HDMI_DDCDATA19
4
R150IV@150_4 R150IV@150_4
ALLOW_LDTSTOP14
IV_HDMI_HPD19
4
3
BTO
INT_TV_C/R
INT_TV_Y/G
U24C
AVDD_NB
AVDDI
AVDDQ
C475
C475
*0.1u/10V_4
*0.1u/10V_4
INT_VSYNC18
INT_HSYNC18
BTO
INT_CRT_DDCCLK18
INT_CRT_DDCDAT18
PLLVDD
HTPVDD
NB_RST#14
NB_PWRGD29
HTREFCLK3
NB_OSC3
VDDA12
NBSRC_CLKP3
NBSRC_CLKN3
SBLINK_CLKP3
SBLINK_CLKN3
T41T41
T27T27
T21T21
R145 IV@0_4R145 IV@0_4
R146 IV@0_4R146 IV@0_4
R138 10K_4R138 10K_4
L52
L52
R107 *2.7K_4R107 *2.7K_4
R110 *2.7K_4R110 *2.7K_4
R116 *2.7K_4R116 *2.7K_4
R147 *2.7K_4R147 *2.7K_4
R455 *2.7K_4R455 *2.7K_4
NB_THERMDA
NB_THERMDC
INT_TV_C/R
INT_TV_Y/G
INT_TV_COMP
T39T39
INT_VSYNC_R
INT_HSYNC_R
LDT_STOP#_NB
TV_SWITCH
PLLVDD12
DFT_GPIO0
LOAD_ROM#
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4
DFT_GPIO5
STRP_DATA
R103
R103
DAC_RSET
R154 715_6R154 715_6
BK1608HS600_6
BK1608HS600_6
R156
R156
4.7K_4
4.7K_4
IV@39K_4
IV@39K_4
NB_PWRGD NB_PWRGD_+5V
U24C
B22
AVDD1
C22
AVDD2
G17
AVSSN1
H17
AVSSN2
A20
AVDDDI
B20
AVSSDI
A21
AVDDQ
A22
AVSSQ
C21
C
C20
Y
D19
COMP
E19
RED
F19
GREEN
G19
BLUE
C6
DACVSYNC
A5
DACHSYNC
B21
RSET
B6
DACSCL
A6
DACSDA
A10
PLLVDD18
B10
PLLVSS
B24
HTPVDD
B25
HTPVSS
C10
SYSRESET#
C11
POWERGOOD
C5
LDTSTOP#
B5
ALLOW_LDTSTOP
C23
HTTSTCLK
B23
HTREFCLK
C2
TVCLKIN
B11
OSCIN
A11
OSCOUT(PLLVDD12)
F2
GFX_CLKP
E1
GFX_CLKN
G1
SB_CLKP
G2
SB_CLKN
D6
DFT_GPIO0
D7
DFT_GPIO1
C8
DFT_GPIO2
C7
DFT_GPIO3
B8
DFT_GPIO4
A8
DFT_GPIO5
B2
BMREQ#
A2
I2C_CLK
B4
I2C_DATA
AA15
THERMALDIODE_P
AB15
THERMALDIODE_N
C14
TMDS_HPD
B3
DDC_DATA
C3
TESTMODE
A3
STRP_DATA
RS690M
RS690M
+3V
2
1
Q26 IV@FDV301NQ26 IV@FDV301N
3
3
CRT/TVOUT
CRT/TVOUT
+5V
R97
R97
IV@15K_4
IV@15K_4
PART 3 OF 5
PART 3 OF 5
PM
PM
PLL PWR
PLL PWR
CLOCKs
CLOCKs
DEBUG
DEBUG
MIS.
MIS.
C127
C127
*IV@.1U_4
*IV@.1U_4
LVDS
LVDS
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
TXCLK_LP
TXCLK_LN
TXCLK_UP
TXCLK_UN
LPVDD
LPVSS
LVDDR18D_1
LVDDR18D_2
LVDDR33_1
LVDDR33_2
LVSSR1
LVSSR3
LVSSR5
LVSSR6
LVSSR7
LVSSR8
LVSSR12
LVSSR13
LVDS_DIGON
LVDS_BLON
LVDS_BLEN
DEBUG_6
DEBUG_9
DEBUG_10
DEBUG_15
DEBUG_0
DEBUG_2
DEBUG_1
DEBUG_14
DEBUG_13
PX_HDMI_DDC_EN16
INT_LVDS_EDIDCLK20
B14
B15
B13
A13
H14
G14
D17
E17
A15
B16
C17
C18
B17
A17
A18
B18
E15
D15
H15
G15
D14
E14
A12
B12
C12
C13
A16
A14
D12
C19
C15
C16
F14
F15
E12
G12
F12
AE15
AC17
AD18
AE21
AD13
AC13
AE13
AE17
AD17
3
2
1
3
2
1
3
2
1
LVDDR18D
LVDDR33
INT_LVDS_DIGON_L
INT_LVDS_PWM_L
INT_LVDS_BLON_L
Q28
Q28
IV@FDV301N
IV@FDV301N
0.65v<Vt<1.5v
INT_LVDS_DIGON_L
Q29
Q29
IV@FDV301N
IV@FDV301N
0.65v<Vt<1.5v
INT_LVDS_PWM_L
Q30
Q30
IV@FDV301N
IV@FDV301N
0.65v<Vt<1.5v
INT_LVDS_BLON_L
2
R77 IV@0_4R77 IV@0_4
R84 *IV@0_4R84 *IV@0_4
INT_TXLOUT0+ 20
INT_TXLOUT0- 20
INT_TXLOUT1+ 20
INT_TXLOUT1- 20
INT_TXLOUT2+ 20
INT_TXLOUT2- 20
T37T37
T35T35
INT_TXUOUT0+ 20
INT_TXUOUT0- 20
INT_TXUOUT1+ 20
INT_TXUOUT1- 20
INT_TXUOUT2+ 20
INT_TXUOUT2- 20
T42T42
T44T44
INT_TXLCLKOUT+ 20
INT_TXLCLKOUT- 20
INT_TXUCLKOUT+ 20
INT_TXUCLKOUT- 20
C203
C203
0.1u/10V_4
0.1u/10V_4
C474
C474
0.1u/10V_4
0.1u/10V_4
T23T23
T17T17
T20T20
T18T18
T22T22
T24T24
T19T19
T16T16
T12T12
R144
R144
IV@2.2K_4
IV@2.2K_4
R142
R142
IV@2.2K_4
IV@2.2K_4
R143
R143
IV@2.2K_4
IV@2.2K_4
2
R76 IV@100K_4R76 IV@100K_4
+3V
1
5
U12
U12
2 4
IV@NC7SZ126M5
IV@NC7SZ126M5
3
LPVDD
L23 BK1608HS600_6L23 BK1608HS600_6
C210
C210
4.7u/6.3V_6
4.7u/6.3V_6
GND_LPVSS
C478
C478
4.7u/6.3V_6
4.7u/6.3V_6
R104 0_6R104 0_6
R160 0_6R160 0_6
INT_LVDS_DIGON 20
INT_LVDS_PWM 20
INT_LVDS_BLON 20
1
IV_HDMI_DDCCLK 19
+1.8V
+3V
+1.8V
L51 BK1608HS600_6L51 BK1608HS600_6
C202
C202
0.1u/10V_4
0.1u/10V_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
L21
L21
BK1608HS600_6
BK1608HS600_6
C211
C211
4.7u/6.3V_6
4.7u/6.3V_6
GND_LVSSR
GND_LPVSS
PROJECT : BD3A
PROJECT : BD3A
Quanta Computer Inc.
Quanta Computer Inc.
RS690M PLL & VEDIO I/F
RS690M PLL & VEDIO I/F
RS690M PLL & VEDIO I/F
1
3C
3C
3C
of
12 38Wednesday, February 13, 2008
12 38Wednesday, February 13, 2008
12 38Wednesday, February 13, 2008
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