QUANTA AW3 Schematics
5
4
3
2
1
AW3 Block Diagram
1
Dothan+Alviso(915PM)+ICH6-M
D D
VRAM
64MB/128MB/
256MB
PG 19,20
478 PIN micro FC-BGA
Intel
Dothan/Yonah
27W/31W
FSB
PG 4,5
400/533MHz
LCD Panel
CRT Port
C C
S-Video
HDTV
ODD
HDD-2
PG 12
PG 29
PG 20
PG 21
PG 21
PG 21
LVDS
R,G,B
TV
PATA
VGA Chip
ATI M24
708 BGA
PG 14~19
Spread Spectrum
HDD-1
PG 12
Marvell
88SA8040
PG 29
PG 14
PCIE x 16
2.5Gb/s
PATA 66/100
SATA
Memory Control Hub
MCH
Alviso 915PM
1257 Pin BGA
DMIx4
ICH6-M
I/O Control Hub
POWER Block Diagram
Azalia
PG 27
Int SPK
82801FBM
609 BGA
AmpMIC
3
TouchPAD
PG 28
PG 11,12,13
PG 30
12V
5VPCU
SUSON
5VSUS
VIN
MAX1907
VCC_CORE
G2996
VMEM_VTT
VIN
LP2951
REF3V
MAX1632
3VPCU
RVCCON
RVCC3
MAX1993
PG32 PG33
VGACORE
RVCC_ONMAINON
MAX1715
RVCC1.5VCC2.5
MAINON
PG34
VCC1.5
VRON
GMCH_VTT
PG38
SUSON
3VSUS
VIN
5
PG34
MAINON
VCC1.5
MAINON
SUSON
MAX1844
1.8VSUS
SC338
PG36
PG33
VCC1.2
PG35
MAINON
VCC1.8
SMDDR_VTERM
MAINON
USB PORT 0,1,2,3
USB Conn.
PG 30
USB PORT 4
IR Receiver
PG 30
USB PORT 5
TV MODULE
PG 30
USB PORT 6
Finger Printer
G2996
PG 30
MAINON
PG35
USB 2.0
MDC
Audio Codec
ALC260
PG 26
RJ11
PG 25
4
Amp
PG 27
HP
PG 27
PG 27 PG 28
B B
MAINON
VCC5
VRON
A A
SUSON
CPU Thermal
Sensor
MAX6642ATT98-T
Channel A
DDR2 INTERFACE, 400/533MHz
Channel B
PG 6~9
CARDBUS
TI7411
Express
Card
3.3V LPC
33MHz
EC/KBC
PC87591
176 Pins LQFP
Keyboard Flash BOM
PG 30
PG 31
PG 4
33MHZ, 3.3V PCI BUS
PG 22,23
PG 22
FAN
PG 27
PG 31
2
Clock Gen.
ICS954201
PG 3
DDR-SODIMM1
DDR-SODIMM2
MINI-PCI
PG 10
PG 10
LAN
BCM4401
BCM5788
PG 26
PG 24
RJ45
PG 25
QUANTA
Title
Size Document Number Re v
Custom
Date: Sheet
COMPUTER
System Block Diagram
AW3
1
1
1A
41Tuesday, March 15, 2005
of
1
Voltage Rails
Voltage Rails ON S0~S2
VCC_CORE
GMCH_VTT
SMDDR_VREF 0. 9V for DDR2 Termination voltage
VMEM_VTT
A A
VGA_CORE VGA CORE (powerplay 1.0V to 1.2V)
RVCC1.5
RVCC3
VCC1.2
VCC1.5
VCC1.8
VCC2.5
VCC3
VCC5
Core voltage for Processor
Core voltage for CPU / NB
1.25V for VRAM Termination voltage
2
ON S3 ON S4/S5 G3
X
X
X
X
X
X
X
X
X
X
X
X
X
3
Ctl Signal
VR_ON
VR_ON
MAINON
MAINON
MAINON
X
X
XX
RVCC_ON
RVCCD
VGA_P_REF
MAINON
MAINON
MAINON
MAIND
4
5
Board Stack up Description
PCB Layers
Layer 1
Layer 2
Layer 3
Layer 4
Layer 5
Layer 6
TOP(FSB,DDR2,CLK,PCIE Component)
Ground Plane
IN1(FSB,CLOCK,DDR2,PEG,CLK)
IN2(PCI,IDE,LPC)
Power Plane
BOTTOM, (Component,Other)
6
7
Power On Sequencing Timing Diagram
VID
VR_ON
Vcc-core
CPU_UP
Vccp_UP
Tsft_star_vcc
Tboot
Tcpu_up
Tvccp_up
Vccgmch
GMCHPWRGD
Tgmch_pwrgd
CLK_ENABLE#
IMVP4_PWRGD
8
2
Vboot
Tboot-vid-tr
Tcpu_pwrgd
MAIND
1.8VSUS
3VSUS
B B
5VSUS
3VPCU
5VPCU
9VPCU
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ACIN POWER ON TIMING
ACIN
5VPCU/3VPCU
NBSWON#
PWRBTN#
RCVV_ON
C C
PWROK/IMVP_PWRGD
D D
RSMRST#
SUSB#,SUSC#
SUSON
MAINON
VSUS,VCC
VR_ON
GMCH_VTT/1.05V
VCORE_CPU
CK410_PWRGD
PLTRST#\PCIRST#
H_PWRGD
H_CPURST#
99ms < t 214
1
2
To ICH6
To ICH6
From ICH6
From 87591
From 87591
From 87591
To clock generator
To GMCH/other
PCI device
From ICH6 to CPU
2ms
Form GMCH to CPU
3
SUSON
SUSD
SUSD
VL
X
VL
X
5VPCU
X
Hub interface "CPU
Reset Complete"
message
STPCLK#,CPUSLP#,
STP_CPU#,STP_PCI#
SLP_S1#,C3_STAT#
Frequency
Straps
PCIRST#
SUS_STAT#
PWROK,
VGATE
Vcc3_3, Vcc1_5,
VCCHI, V_CPU_IO
LAN_PWROK
VccLAN3_3,
VccLAN1_5
SLP_S3#
SLP_S4#
SLP_S5#
SUSCLK
RSMRST#
VccSus3_3,
VccSus1_5
V5RefSus
RTCRST#
VccRTC
Power Sequencing and Reset Signal Timings
Strap Values Normal
2~3RTC
32~38RTC
99ms
0ms
0ms
10ms
0ms
1~2RTC
1~2RTC
V5Ref
0ms
0ms
5ms
4
110ms
110ms
10ms
5
6
Operation]
CPU Power On Sequence
VR_ON
Vcc-core
CPU_UP
Vccp
Vccp_UP
Vccgmch
GMCHPWRGD
CLK_ENABLE#
IMVP4_PWRGD
Tsft_star_vcc
Tboot
Tcpu_up
Tvccp_up
Tgmch_pwrgd
QUANTA
Title
Size Document Number Re v
Custom
Date: Sheet
COMPUTER
System Block Diagram
AW3
7
Vboot
Tboot-vid-tr
Tcpu_pwrgd
2
of
8
1A
41Tuesday, March 15, 2005
A
B
C
D
E
FSC FSB FSA CPU SRC PCI
1 0 1 100 100 33
CLKVDD
C193
0.047U
R126 2.2
1 2
R174 2.2
1 2
R113 1
Default
CLK_VDDA
CLKVDD1
CLK_VDD48
CLK_VDDREF
EC1
CLK48_741122
CLK48_USB12
ICS FAE Recommend.
R140 4.7K for isolation pin53 REF1 CLK output.
Iref=5mA,
Ioh=4*Iref
C303
0.047U
C325
0.047U
C329
0.047U
C194
0.047U
C326
0.047U
C327
0.047U
C195
0.047U
C165
33P
C166
33P
CLK_EN#32
STP_PCI#12
STP_CPU#12,32
SMbus address D2
R176 12.1/F
R177 12.1/F
CG_BSEL2
R124 4.7K
R102 475/F
C286
4.7U
C238
4.7U
C356
4.7U
C385
4.7U
C192
0.047U
B
VCC34,10,11,12,13,14,15,16,17,20,21,22,23,24,25,26,27,29,30,31,32,33,36
GMCH_VTT4,5,6,7,8,9,11,13,33
U18
50
XTAL_IN
49
XTAL_OUT
10
Vtt_PwrGd#/PD
55
PCI/SRC_STOP#
54
CPU_STOP#
46
SCLK
47
SDATA
12
FSA/USB_48MHz
16
FSB/TEST_MODE
53
FSC/REF1
48
VDD_REF
42
VDD_CPU
1
VDD_PCI_1
7
VDD_PCI_2
21
VDD_SRC0
28
VDD_SRC1
34
VDD_SRC2
11
VDD_48
39
IREF
14
DOT96MHz
15
DOT96MHz#
ICS954201
R143 *10K
CLK_VDDA
GND_48
13
R151 0
R132 0
37
VDDA
CPU2#_ITP/SRC7#
CK-410M
SRC0/DREFSSCLK
SRC0#/DREFSSCLK#
GND_REF
GND_PCI_26GND_SRC29GND_CPU
GND_PCI_1
2
51
45
CG_BSEL0
38
REF0
GNDA
CPU0
CPU0#
CPU1
CPU1#
CPU2_ITP/SRC7
SRC6
SRC6#
SRC5
SRC5#
SRC4_SATA
SRC4#_SATA
SRC3
SRC3#
SRC2
SRC2#
SRC1
SRC1#
PCI5
PCI4
PCI3
PCI2
PCIF1/100_96M#
PCIF0/ITP_EN
250mA ( MAX. )
GMCH_VTT
R135
R138
*1K
*1K
CG_BSEL1
CG_BSEL2
R157
R129
*0
*0
R172 10K
CG_XIN
21
Y1
14.318MHZ
CL=20p
CG_XOUT RHCLK_CPU
CLK_EN#
CGCLK_SMB
CGDAT_SMB
CG_BSEL0
CG_BSEL1
R_CG_BSEL2
CLK_VDDREF
CLKVDD
CLKVDD1
CLKVDD
CLK_VDD48
IREF
SELPSB1_CLK4
SELPSB0_CLK4
CPU Type R129R132 R151
Dothan-A PSB400
Dothan-A PSB533
Dothan-B (Default)
Pentium M 730-770
C
52
44
43
41
40
36
35
33
32
31
30
26
27
24
25
22
23
19
20
17
18
R_PCLK_591
5
R_PCLK_7411
4
R_PCLK_LAN
3
R_PCLK_MINI
56
R_PCLK_ICH
9
R_PCLK_SIO
8
R142 1K
R127 1K
R157
14M_REF
RHCLK_CPU#
RHCLK_MCH
RHCLK_MCH#
RSRC_MCH
RSRC_MCH#
RSRC_ICH
RSRC_ICH#
RSRC_SATA
RSRC_SATA#
RSRC_NEW
RSRC_NEW#
RSRC_PEG
RSRC_PEG#
VCC3
Place these termination
to close CK410M.
R98 49.9/F
R99 49.9/F
R100 49.9/F
R101 49.9/F
RP9
RP10
RP11
RP26
RP25
RP24
RP23
R145 33
R169 33
R144 33
R122 33
R175 33
R170 10K
DREFSSCLK Frequency Select.
"0" : 96MHz
"1" : 100MHz
1
3
1
3
1
3
3
1
3
1
3
1
3
1
R171 10K
R146 *10K
MCH_BSEL1 6
MCH_BSEL2 6
2
4
33X2
2
4
33X2
2
4
33X2
4
2
33X2
4
2
33X2
4
2
33X2
4
2
33X2
VCC3
VCC3
SRC_MCH 7
SRC_MCH# 7
SRC_ICH 12
SRC_ICH# 12
SRC_SATA 11
SRC_SATA# 11
SRC_NEW 22
SRC_NEW# 22
SRC_PEG 14
SRC_PEG# 14
PCLK_591 31
PCLK_7411 22
PCLK_LAN 24
PCLK_MINI 26
PCLK_ICH 11
PDAT_SMB10,12
PCLK_SMB10,12
D
ICS FAE Recommend.
R117 22/F
HCLK_CPU 4
HCLK_CPU# 4
HCLK_MCH 6
HCLK_MCH# 6
SRC_MCH
SRC_MCH#
SRC_ICH
SRC_ICH#
SRC_SATA
SRC_SATA#
SRC_NEW
SRC_NEW#
SRC_PEG
SRC_PEG#
Place these termination
to close CK410M.
VCC3
2
3
Q23 RHU002N06
VCC3
2
3
Q20 RHU002N06
These are for backdrive issue
Title
Size Document Number Re v
Custom
Date: Sheet
14M_ICH 12
C223
*10P
R103 49.9/F
R104 49.9/F
R167 49.9/F
R168 49.9/F
R165 49.9/F
R166 49.9/F
R163 49.9/F
R164 49.9/F
R161 49.9/F
R162 49.9/F
R112
10K
1
1
R108
10K
CGDAT_SMB
CGCLK_SMB
QUANTA
COMPUTER
System Block Diagram
AW3
3
E
3
1A
41Tuesday, March 15, 2005
of
0 0 1 133 100 33
0 1 1 166 100 33
0 1 0 200 100 33
0 0 0 266 100 33
1 0 0 333 100 33
4 4
1 1 0 400 100 33
1 1 1 RESERVED
3 3
L34
1 2
VCC3
ACB2012L-120
120 ohms@100Mhz
2 2
L37
1 2
VCC3
ACB2012L-120
120 ohms@100Mhz
1 1
A
A
B
C
D
E
4
H_D#[0..63]6 H_D#[0..63] 6
H_DSTBN#06
H_DSTBP#06
H_DINV#06
H_D#[0..63]6
H_DSTBN#16
H_DSTBP#16
H_DINV#16
SELPSB0_CLK3
SELPSB1_CLK3
R64 47
U14
1
VCC
DXP3SDA
2
GND
7
R361 1K/F
SCLK
ALERT#
GND
MAX6642ATT98-T
4
5
6
THCLK_SMB
THDAT_SMB
CPU_TH_ALERT#
GMCH_VTT
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
PM_PSI#
T53
SELPSB0_CLK
SELPSB1_CLK
T54
T4
T50
T49
T52
H_GTLREF
Layout note: 0.5" max length.
R358
2K/F
R14
10K
1
W1
W2
AA3
AA2
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1
AE5
U59
7SH08
VCC3
P4
U4
V3
R3
V2
T4
Y4
Y1
U1
Y3
U3
R2
P3
T2
P1
T1
C2
D3
A3
C6
D1
D4
B4
4
U38A
A3#
A4#
ADDR GROUP 0 ADDR GROUP 1
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
ADSTB#0
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
ADSTB#1
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
Dothan_478P
XDP_TDI
XDP_TMS
XDP_TDO
H_CPURST#
XDP_DBR#
XDP_PREQ#
PM_THRMTRIP#
XDP_TCK
XDP_TRST#
R563 10K
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROLXTP/ITP SIGNALS
RESET#
RS0#
RS1#
RS2#
TRDY#
HITM#
BPM#0
BPM#1
BPM#2
BPM#3
PRDY#
PREQ#
TRST#
DBR#
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
THERM
ITP_CLK1
ITP_CLK0
BCLK1
BCLK0
H CLK
R46 150
R48 39.2/F
R38 54.9/F
R45 54.9/F
R37 150
R47 56
R68 75
R40 27.4/F
R39 680
1999RESET_1#
3
Q19
2
RHU002N06
C1062
1U
1
HIT#
TCK
TDO
TMS
H_ADS#
N2
H_BNR#
L1
H_BPRI#
J3
H_DEFER#
L4
H_DRDY#
H2
H_DBSY#
M2
H_BREQ#0
N4
H_IERR#
A4
CPUINIT#
B5
H_LOCK#
J2
H_CPURST#
B11
H_RS#0
H1
H_RS#1
K1
H_RS#2
L2
H_TRDY#
M3
H_HIT#
K3
H_HITM#
K4
C8
B8
A9
C9
A10
XDP_PREQ#
B10
XDP_TCK
A13
XDP_TDI
C12
TDI
XDP_TDO
A12
XDP_TMS
C11
XDP_TRST#
B13
XDP_DBR#
A7
H_PROCHOT#
B17
H_THERMDA
B18
H_THERMDC
A18
PM_THRMTRIP#
C17
A15
A16
HCLK_CPU#
B14
HCLK_CPU
B15
GMCH_VTT
GMCH_VTT
GMCH_VTT
GMCH_VTT
3VSUS
GMCH_VTT
GMCH_VTT
R57 0
H_ADS# 6
H_BNR# 6
H_BPRI# 6
H_DEFER# 6
H_DRDY# 6
H_DBSY# 6
H_BREQ#0 6
CPUINIT# 11
H_LOCK# 6
H_CPURST# 6
H_RS#0 6
H_RS#1 6
H_RS#2 6
H_TRDY# 6
H_HIT# 6
H_HITM# 6
PM_THRMTRIP# 6,11
T5
T6
HCLK_CPU# 3
HCLK_CPU 3
SYS_SHDN# 36
H_THERMDA
H_THERMDC
C Close to MAX6642
GMCH_VTT
R43
56
GMCH_VTT
R49
56
V_EE
C141
0.1U
C147
2200P
H_A#[3..31]6
4 4
H_ADSTB#06
H_REQ#06
H_REQ#16
H_REQ#26
H_REQ#36
H_REQ#46
H_A#[3..31]6
3 3
H_ADSTB#16
2 2
H_A#[3..16]
H_A#[17..31]
A20M#11
FERR#11
IGNNE#11
STPCLK#11
INTR11
SMI#11
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADSTB#1
A20M#
FERR#
IGNNE#
STPCLK#
INTR
NMI
NMI11
SMI#
EC 55
VCC3
PM_THRMTRIP#
1 1
R50 470
PCIRST#11,12,22,23,24,26,31
2
R565 0
R54
4.7K
Q18
MMBT3904
1 3
R562 *0
3VSUS
2
1
3 5
R564 *10K
M26
H24
G24
M23
N24
M25
H26
N25
C16
C14
AF7
AC1
AD26
A19
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
C23
C22
D25
H23
G25
L23
F25
L26
K25
K24
L24
E26
J23
J25
J26
E1
B2
C3
2
U38B
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#
PSI#
BSEL0
BSEL1
RSVD
RSVD
RSVD
RSVD
RSVD
GTLREF
Dothan_478P
VCC3
Q13
H_THMD_ALERT#
3
RHU002N06
DATA GRP 2 DATA GRP 3
DATA GRP 0DATA GRP 1
MISC
RSVD/DPRSTP#
PWRGOOD
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DSTBN2#
DSTBP2#
DINV2#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DSTBN3#
DSTBP3#
DINV3#
COMP0
COMP1
COMP2
COMP3
DPSLP#
DPWR#
SLP#
TEST1
TEST2
H_D#32
Y26
H_D#33
AA24
H_D#34
T25
H_D#35
U23
H_D#36
V23
H_D#37
R24
H_D#38
R26
H_D#39
R23
H_D#40
AA23
H_D#41
U26
H_D#42
V24
H_D#43
U25
H_D#44
V26
H_D#45
Y23
H_D#46
AA26
H_D#47
Y25
H_DSTBN#2
W25
H_DSTBP#2
W24
H_DINV#2
T24
H_D#48
AB25
H_D#49
AC23
H_D#50
AB24
H_D#51
AC20
H_D#52
AC22
H_D#53
AC25
H_D#54
AD23
H_D#55
AE22
H_D#56
AF23
H_D#57
AD24
H_D#58
AF20
H_D#59
AE21
H_D#60
AD21
H_D#61
AF25
H_D#62
AF22
H_D#63
AF26
H_DSTBN#3
AE24
H_DSTBP#3
AE25
H_DINV#3
AD20
COMP0
P25
COMP1
P26
COMP2
AB2
COMP3
AB1
DPRSLP#
G1
DPSLP#
B7
H_DPWR#
C19
H_PWRGD
E4
CPUSLP#
A6
H_TEST1
C5
H_TEST2
F23
R374
*1K
H_THMD_ALERT# 12
R370 27.4/F
R368 54.9/F
R346 27.4/F
R347 54.9/F
DPRSLP# 11
DPSLP# 11
H_DPWR# 6
CPUSLP# 6,11
G1: NC for Dothan and
DPRSTP# for Yonah
R44
*1K
MBCLK31,38
MBDAT31,38
H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#2 6
H_D#[0..63] 6
H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6
GMCH_VTT
R53
200
CPUPWRGD 11
VCC3
R27 10K
Q16
3
Q14
3
2
VCC5
R15 10K
2
THCLK_SMB
1
1
RHU002N06
MBCLK
RHU002N06
MBDATA THDAT_SMB
THCLK_SMB 14
THDAT_SMB 14
QUANTA
Title
Size Document Number Re v
Custom
A
B
C
D
Date: Sheet
COMPUTER
System Block Diagram
AW3
E
4
1A
41Tuesday, March 15, 2005
of
A
VCORE
4 4
3 3
2 2
VCORE
220U/2.5V(CC7343)
12 mOhm*4
1 1
U38C
AA11
VCC0
AA13
VCC1
AA15
VCC2
AA17
VCC3
AA19
VCC4
AA21
VCC5
AA5
VCC6
AA7
VCC7
AA9
VCC8
AB10
VCC9
AB12
VCC10
AB14
VCC11
AB16
VCC12
AB18
VCC13
AB20
VCC14
AB22
VCC15
AB6
VCC16
AB8
VCC17
AC11
VCC18
AC13
VCC19
AC15
VCC20
AC17
VCC21
AC19
VCC22
AC9
VCC23
AD10
VCC24
AD12
VCC25
AD14
VCC26
AD16
VCC27
AD18
VCC28
AD8
VCC29
AE11
VCC30
AE13
VCC31
AE15
VCC32
AE17
VCC33
AE19
VCC34
AE9
VCC35
AF10
VCC36
AF12
VCC37
AF14
VCC38
AF16
VCC39
AF18
VCC40
AF8
VCC41
D18
VCC42
D20
VCC43
D22
VCC44
D6
VCC45
D8
VCC46
E17
VCC47
E19
VCC48
E21
VCC49
E5
VCC50
E7
VCC51
E9
VCC52
F18
VCC53
F20
VCC54
F22
VCC55
F6
VCC56
F8
VCC57
G21
VCC58
Dothan_478P
C67
+
220U
CPU_CORE
GMCH_VTT 3,4,6,7,8,9,11,13,33
VCC1.5 6,7,9,12,13,15,25,34,36
A
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCCA0
VCCA1/RSVD
VCCA2/RSVD
VCCA3/RSVD
VCCP0
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCQ0
VCCQ1
VCCSENSE
VSSSENSE
C44
+
220U
VID0
VID1
VID2
VID3
VID4
VID5
G5
H22
H6
J21
J5
K22
U5
V22
V6
W21
W5
Y22
Y6
F26
B1
N1
AC26
D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L21
L5
M22
M6
N21
N5
P22
P6
R21
R5
T22
T6
U21
P23
W4
E2
F2
F3
G3
G4
H4
AE7
AF6
C840
+
220U
VCORE
TP_VCCA1
TP_VCCA2
TP_VCCA3
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
TP_VCCSENSE
TP_VSSSENSE
R349
*54.9/F
CPU_VCCA
GMCH_VTT
+
T55
T3
T51
CPU_VID0 32
CPU_VID1 32
CPU_VID2 32
CPU_VID3 32
CPU_VID4 32
CPU_VID5 32
R348
*54.9/F
C854
220U
C780
0.01U
GMCH_VTT
R379 0
C782
10U
B
VCC1.5
VCC1.5 6,7,9,12,13,15,25,34,36
C77
C90
+
0.1U
150U
VCORE
C59
C53
0.1U
0.1U
C37
C36
0.1U
0.1U
10U/6.3V/X5R(CC0805)
5 mOhm*35
---> 10U/4V/X5R(CC0603)
VCORE
C42
C45
10U
10U
VCORE
C95
C89
10U
10U
VCORE VCORE
C62
C69
10U
10U
B
C81
0.1U
C49
0.1U
C39
0.1U
C46
10U
C80
10U
C74
10U
C112
0.1U
C33
0.1U
C43
0.1U
Murata
C47
10U
C71
10U
C79
10U
C103
0.1U
C38
0.1U
C114
0.1U
C34
10U
C58
10U
C88
10U
C104
0.1U
GMCH_VTTGMCH_VTT
VCORE
VCOREVCORE
C
C85
0.1U
C97
0.1U
C54
0.1U
C75
10U
C111
10U
C61
10U
C93
10U
C
C76
0.1U
C96
0.1U
C109
0.1U
C70
10U
C99
10U
C55
10U
C87
10U
VCORE
VCORE
VCORE
C72
0.1U
C102
0.1U
C108
0.1U
C63
10U
C110
10U
C91
10U
C78
10U
C66
0.1U
C101
0.1U
C107
0.1U
C56
10U
C100
10U
C98
10U
C73
10U
C113
0.1U
C65
0.1U
C50
0.1U
C60
10U
C94
10U
C92
10U
C68
10U
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24
C10
C13
C15
C18
C21
C24
D11
A2
A5
A8
A11
A14
A17
A20
A23
A26
B3
B6
B9
B12
B16
B19
B22
B25
C1
C4
C7
D2
D5
D7
D9
D
U38D
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
Dothan_478P
D
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
E
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
R6
R22
R25
T3
T5
T21
T23
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
QUANTA
Title
Size Document Number Re v
Custom
Date: Sheet
COMPUTER
System Block Diagram
AW3
5
E
of
5
1A
41Tuesday, March 15, 2005
A
H_D#[0..63] H_A#[3..31]
4 4
3 3
2 2
GMCH_VTT GMCH_VTT GMCH_VTT GMCH_VTT
H_XRCOMP H_XSCOMP
R109
24.9/F
1 1
R105
54.9/F
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2
C1
C2
D1
T1
L1
P1
R119
221/F
R115
100/F
U42A
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING
ALVISO_1257P
H_XSWING
C191
0.1U
HOST
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HADS#
HADSTB#0
HADSTB#1
HVREF
HBNR#
HBPRI#
HBREQ0#
HCPURST#
HCLKINN
HCLKINP
HDBSY#
HDEFER#
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HDPWR#
HDRDY#
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HEDRDY#
HHIT#
HHITM#
HLOCK#
HPCREQ#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HRS0#
HRS1#
HRS2#
HSLPCPU#
HTRDY#
R425
54.9/F
H_YSCOMP
H_A#3
G9
H_A#4
C9
H_A#5
E9
H_A#6
B7
H_A#7
A10
H_A#8
F9
H_A#9
D8
H_A#10
B10
H_A#11
E10
H_A#12
G10
H_A#13
D9
H_A#14
E11
H_A#15
F10
H_A#16
G11
H_A#17
G13
H_A#18
C10
H_A#19
C11
H_A#20
D11
H_A#21
C12
H_A#22
B13
H_A#23
A12
H_A#24
F12
H_A#25
G12
H_A#26
E12
H_A#27
C13
H_A#28
B11
H_A#29
D13
H_A#30
A13
H_A#31
F13
H_ADS#
F8
H_ADSTB#0
B9
H_ADSTB#1
E13
H_VREF
J11
H_BNR#
A5
H_BPRI#
D5
H_BREQ#0
E7
H_CPURST#
H10
HCLK_MCH#
AB1
HCLK_MCH
AB2
H_DBSY#
C6
H_DEFER#
E6
H_DINV#0
H8
H_DINV#1
K3
H_DINV#2
T7
H_DINV#3
U5
H_DPWR#
G6
H_DRDY#
F7
H_DSTBN#0
G4
H_DSTBN#1
K1
H_DSTBN#2
R3
H_DSTBN#3
V3
H_DSTBP#0
G5
H_DSTBP#1
K2
H_DSTBP#2
R2
H_DSTBP#3
W4
TP_H_EDRDY#
F6
H_HIT#
D4
H_HITM#
D6
H_LOCK#
B3
TP_H_PCREQ#
A11
H_REQ#0
A7
H_REQ#1
D7
H_REQ#2
B8
H_REQ#3
C7
H_REQ#4
A8
H_RS#0
A4
H_RS#1
C5
H_RS#2
B4
H_CPUSLP#_GMCH
G8
H_TRDY#
B5
B
H_A#[3..31] 4H_D#[0..63]4
H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BREQ#0 4
H_CPURST# 4
HCLK_MCH# 3
HCLK_MCH 3
H_DBSY# 4
H_DEFER# 4
H_DINV#0 4
H_DINV#1 4
H_DINV#2 4
H_DINV#3 4
H_DPWR# 4
H_DRDY# 4
H_DSTBN#0 4
H_DSTBN#1 4
H_DSTBN#2 4
H_DSTBN#3 4
H_DSTBP#0 4
H_DSTBP#1 4
H_DSTBP#2 4
H_DSTBP#3 4
T18
H_HIT# 4
H_HITM# 4
H_LOCK# 4
T59
H_REQ#0 4
H_REQ#1 4
H_REQ#2 4
H_REQ#3 4
H_REQ#4 4
H_RS#0 4
H_RS#1 4
H_RS#2 4
R97 0
H_TRDY# 4
Do not install R416 for Dothan-A and install for Dothan-B
R136
221/F
R140
100/F
H_YSWING
C315
0.1U
H_YRCOMP
R156
24.9/F
GMCH_VTT
R96
100/F
C256
R95
0.1U
200/F
EC2
R183
*40.2/F
Route as short
as possible.
1.8VSUS
R186
80.6/F
R206
80.6/F
R184
*40.2/F
CPUSLP# 4,11
M_RCOMPN
M_RCOMPP
C
DMI_TXN012
DMI_TXN112
DMI_TXN212
DMI_TXN312
DMI_TXP012
DMI_TXP112
DMI_TXP212
DMI_TXP312
DMI_RXN012
DMI_RXN112
DMI_RXN212
DMI_RXN312
DMI_RXP012
DMI_RXP112
DMI_RXP212
DMI_RXP312
CLK_SDRAM010
CLK_SDRAM110
T34
CLK_SDRAM310
CLK_SDRAM410
T31
CLK_SDRAM0#10
CLK_SDRAM1#10
T37
CLK_SDRAM3#10
CLK_SDRAM4#10
T32
CKE010
CKE110
CKE210
CKE310
SM_CS0#10
SM_CS1#10
SM_CS2#10
SM_CS3#10
M_ODT010
M_ODT110
M_ODT210
M_ODT310
SMDDR_VREF10,35
It's point to point,
55ohm trace, keep as
short as possible.
PM_EXTTS#0
PM_EXTTS#1
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
CLK_SDRAM0
CLK_SDRAM1
CLK_SDRAM2
CLK_SDRAM3
CLK_SDRAM4
CLK_SDRAM5
CLK_SDRAM0#
CLK_SDRAM1#
CLK_SDRAM2#
CLK_SDRAM3#
CLK_SDRAM4#
CLK_SDRAM5#
CKE0
CKE1
CKE2
CKE3
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
M_OCDCOMP0
M_OCDCOMP1
M_ODT0
M_ODT1
M_ODT2
M_ODT3
M_RCOMPN
M_RCOMPP
SMXSLEW
SMYSLEW
R81 10K
R82 10K
Alviso Strapping Signals and Configuration
CFG[17:3] have internal pullup resistors.
CFG[19:18] have internal pulldown resistors.
U42B
AA31
AB35
AC31
AD35
Y31
AA35
AB31
AC35
AA33
AB37
AC33
AD37
Y33
AA37
AB33
AC37
AM33
AL1
AE11
AJ34
AF6
AC10
AN33
AK1
AE10
AJ33
AF5
AD10
AP21
AM21
AH21
AK21
AN16
AM14
AH15
AG16
AF22
AF16
AP14
AL15
AM11
AN10
AK10
AK11
AF37
AD1
AE27
AE28
AF9
AF10
VCC2.5
DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3
DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3
DMITXN0
DMITXN1
DMITXN2
DMITXN3
DMITXP0
DMITXP1
DMITXP2
DMITXP3
SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5
SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT
ALVISO_1257P
DMID DR MUXING
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
CFG/RSVD
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
BM_BUSY#
EXT_TS0#
EXT_TS1#
THRMTRIP#
PMCLKNC
PWROK
RSTIN#
DREF_CLKN
DREF_CLKP
DREF_SSCLKN
DREF_SSCLKP
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
D
GMCH_VTT
R67
CFG0
G16
MCH_BSEL1
H13
MCH_BSEL2
G14
CFG3
F16
CFG4
F15
CFG5
G15
CFG6
E16
CFG7
D17
CFG8
J16
CFG9
D15
CFG10
E15
CFG11
D14
CFG12
E14
CFG13
H12
CFG14
C14
CFG15
H15
CFG16
J15
CFG17
H14
CFG18
G22
CFG19
G23
CFG20
D23
G25
G24
J17
A31
A30
D26
D25
J23
J21
H22
F5
AD30
MCHRST#
AE29
A24
A23
C37
D37
AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37
Low=FSB Dynamic ODT Disabled
High=FSB Dynamic ODT Enabled
Low=CPU core VCC 1.05V
High=CPU core VCC 1.5V
10K
PM_EXTTS#0
PM_EXTTS#1
R187 100
TP_NC1
TP_NC2
TP_NC3
TP_NC4
TP_NC5
TP_NC6
TP_NC7
TP_NC8
TP_NC9
TP_NC10
TP_NC11
CFG16
VCC2.5 VCC2.5
CFG18
MCH_BSEL1 3
MCH_BSEL2 3
T21
T27
T26
T12
T24
T23
T17
T22
T20
T57
T58
T15
T10
PM_BMBUSY# 12
PM_THRMTRIP# 4,11
VCC1.5
T77
T73
T78
T75
T76
T74
T70
T68
T65
T56
T66
R85
*4.7K
R83
*1K
Low=CPU VTT 1.05V
High=CPU VTT 1.2V
T25
C263
0.1U
IMVP_PWG 12,32
PLTRST# 11,12,14,29
CFG11
R93
4.7K
Low=FSB533
R84
*1K
CFG19
E
CFG3
R88
*4.7K
Low=DDR533
CFG5
EC3
R65
*4.7K
Low=DMIx2
High=DMIx4
CFG6
R90
2.2K
Low=DDR II
High=DDR
CFG7
R89
*4.7K
Low=Mobile Prescott
High=Dothan
CFG9
EC4
R91
*4.7K
Low=PCIE Reserve Lanes
High=PCIE Normal Operation
CFG12
CFG13
R94
R92
*4.7K
*4.7K
00 : Reserved
01 : XOR Mode Enabled
10 : All Z Mode Enabled
11 : Normal Operation
6
QUANTA
Title
Size Document Number Re v
Custom
A
B
C
D
Date: Sheet
COMPUTER
System Block Diagram
AW3
E
6
1A
41Tuesday, March 15, 2005
of
A
B
C
D
E
7
U42G
H24
SDVOCTRL_DATA
H25
SDVOCTRL_CLK
SRC_MCH#3 PEG_RXN[0..15] 14
SRC_MCH3
4 4
GMCH_VTT
3 3
2 2
AB29
AC29
C16
D21
C20
H21
G21
C23
C22
C33
C31
C25
C24
C29
D28
C27
C28
D27
C26
A15
A17
J18
B15
B16
B17
E24
E23
E21
B20
A19
B19
J20
E25
F25
F23
F22
F26
F28
F27
B30
B29
B34
B33
B32
A34
A33
B31
GCLKN
GCLKP
TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC
DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET
LBKLT_CRTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL
LACLKN
LACLKP
LBCLKN
LBCLKP
LADATAN0
LADATAN1
LADATAN2
LADATAP0
LADATAP1
LADATAP2
LBDATAN0
LBDATAN1
LBDATAN2
LBDATAP0
LBDATAP1
LBDATAP2
ALVISO_1257P
EXP_COMPI
EXP_ICOMPO
EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
VGA TV MISC
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
PCI-EXPREESS GRAPHICS
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
LVDS
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
D36
D34
E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34
D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34
E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36
D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36
PEG_COMP
R424 24.9/F
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
A_MD[0..63]10
VCC3G_PCIE
PEG_RXP[0..15] 14
A_MD0
A_MD1
A_MD2
A_MD3
A_MD4
A_MD5
A_MD6
A_MD7
A_MD8
A_MD9
A_MD10
A_MD11
A_MD12
A_MD13
A_MD14
A_MD15
A_MD16
A_MD17
A_MD18
A_MD19
A_MD20
A_MD21
A_MD22
A_MD23
A_MD24
A_MD25
A_MD26
A_MD27
A_MD28
A_MD29
A_MD30
A_MD31
A_MD32
A_MD33
A_MD34
A_MD35
A_MD36
A_MD37
A_MD38
A_MD39
A_MD40
A_MD41
A_MD42
A_MD43
A_MD44
A_MD45
A_MD46
A_MD47
A_MD48
A_MD49
A_MD50
A_MD51
A_MD52
A_MD53
A_MD54
A_MD55
A_MD56
A_MD57
A_MD58
A_MD59
A_MD60
A_MD61
A_MD62
A_MD63
AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AP7
AP11
AP10
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AM3
AK2
AK3
AG2
AG1
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5
AL9
AL6
AL7
AL4
AL3
U42C
SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63
ALVISO_1257P
SA_BS0
SA_BS1
SA_BS2
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
DDR SYSTEM MEMORY A
SA_MA11
SA_MA12
SA_MA13
SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
AK15
AK16
AL21
AJ37
AP35
AL29
AP24
AP9
AP4
AJ2
AD3
AK36
AP33
AN29
AP23
AM8
AM4
AJ1
AE5
AK35
AP34
AN30
AN23
AN8
AM5
AH1
AE4
AL17
AP17
AP18
AM17
AN18
AM18
AL19
AP20
AM19
AL20
AM16
AN20
AM20
AM15
AN15
AP16
SA_RCVENIN#
AF29
SA_RCVENOUT#
AF28
AP15
A_BS0#
A_BS1#
A_BS2#
A_DM0
A_DM1
A_DM2
A_DM3
A_DM4
A_DM5
A_DM6
A_DM7
A_DQS0
A_DQS1
A_DQS2
A_DQS3
A_DQS4
A_DQS5
A_DQS6
A_DQS7
A_DQS#0
A_DQS#1
A_DQS#2
A_DQS#3
A_DQS#4
A_DQS#5
A_DQS#6
A_DQS#7
A_MA0
A_MA1
A_MA2
A_MA3
A_MA4
A_MA5
A_MA6
A_MA7
A_MA8
A_MA9
A_MA10
A_MA11
A_MA12
A_MA13
A_SCASA#
A_SRASA#
A_BMWEA#
B_MD[0..63]10
A_BS0# 10
A_BS1# 10
A_BS2# 10
A_DM[0..7] 10
A_DQS[0..7] 10
A_DQS#[0..7] 10
A_MA[0..13] 10 B_MA[0..13] 10
A_SCASA# 10
A_SRASA# 10
T36
T33
A_BMWEA# 10
B_MD0
B_MD1
B_MD2
B_MD3
B_MD4
B_MD5
B_MD6
B_MD7
B_MD8
B_MD9
B_MD10
B_MD11
B_MD12
B_MD13
B_MD14
B_MD15
B_MD16
B_MD17
B_MD18
B_MD19
B_MD20
B_MD21
B_MD22
B_MD23
B_MD24
B_MD25
B_MD26
B_MD27
B_MD28
B_MD29
B_MD30
B_MD31
B_MD32
B_MD33
B_MD34
B_MD35
B_MD36
B_MD37
B_MD38
B_MD39
B_MD40
B_MD41
B_MD42
B_MD43
B_MD44
B_MD45
B_MD46
B_MD47
B_MD48
B_MD49
B_MD50
B_MD51
B_MD52
B_MD53
B_MD54
B_MD55
B_MD56
B_MD57
B_MD58
B_MD59
B_MD60
B_MD61
B_MD62
B_MD63
AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AK9
AK6
AH5
AK8
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5
AJ9
AJ7
AJ4
AJ8
AJ5
U42D
SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63
ALVISO_1257P
SB_BS0
SB_BS1
SB_BS2
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
DDR SYSTEM MEMORY B
SB_MA11
SB_MA12
SB_MA13
SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#
AG17
AG21
AF32
AK34
AK27
AK24
AJ10
AK5
AE7
AB7
AF34
AK32
AJ28
AK23
AM10
AH6
AF8
AB4
AF35
AK33
AK28
AJ23
AL10
AH7
AF7
AB5
AH17
AK17
AH18
AJ18
AK18
AJ19
AK19
AH19
AJ20
AH20
AJ16
AG18
AG20
AG15
AH14
AK14
SB_RCVENIN#
AF15
SB_RCVENOUT#
AF14
AH16
B_BS1#
B_BS2#
B_DM0
B_DM1
B_DM2
B_DM3
B_DM4
B_DM5
B_DM6
B_DM7
B_DQS0
B_DQS1
B_DQS2
B_DQS3
B_DQS4
B_DQS5
B_DQS6
B_DQS7
B_DQS#0
B_DQS#1
B_DQS#2
B_DQS#3
B_DQS#4
B_DQS#5
B_DQS#6
B_DQS#7
B_MA0
B_MA1
B_MA2
B_MA3
B_MA4
B_MA5
B_MA6
B_MA7
B_MA8
B_MA9
B_MA10
B_MA11
B_MA12
B_MA13
B_SCASA#
B_SRASA#
B_BMWEA#
B_BS0#
AJ15
B_BS0# 10
B_BS1# 10
B_BS2# 10
B_SCASA# 10
B_SRASA# 10
T35
T38
B_BMWEA# 10
B_DM[0..7] 10
B_DQS[0..7] 10
B_DQS#[0..7] 10
PEG_TXN0
C820 0.1U
PEG_TXN1
C821 0.1U
PEG_TXN2
C829 0.1U
PEG_TXN3
C831 0.1U
PEG_TXN4
C837 0.1U
PEG_TXN5
C838 0.1U
PEG_TXN6
C843 0.1U
PEG_TXN7
C845 0.1U
PEG_TXN8
C853 0.1U
PEG_TXN9
C855 0.1U
C861 0.1U
PEG_TXN11
C862 0.1U
PEG_TXN12
C867 0.1U
PEG_TXN13
PEG_TXN14
PEG_TXN15
C868 0.1U
C874 0.1U
C876 0.1U
1 1
PEG_TXN_C0
PEG_TXN_C1
PEG_TXN_C2
PEG_TXN_C3
PEG_TXN_C4
PEG_TXN_C5
PEG_TXN_C6
PEG_TXN_C7
PEG_TXN_C8
PEG_TXN_C9
PEG_TXN_C10PEG_TXN10
PEG_TXN_C11
PEG_TXN_C12
PEG_TXN_C13
PEG_TXN_C14
PEG_TXN_C15
PCIE x16 AC Coupling CAP.
PEG_TXN_C[0..15] 14 PEG_TXP_C[0..15] 14
PEG_TXP0 PEG_TXP_C0
C816 0.1U
PEG_TXP1
C817 0.1U
PEG_TXP2
C826 0.1U
PEG_TXP3
C827 0.1U
PEG_TXP4
C833 0.1U
PEG_TXP5
C835 0.1U
PEG_TXP6
C841 0.1U
PEG_TXP7
C842 0.1U
PEG_TXP8 PEG_TXP_C8
C847 0.1U
PEG_TXP9
C852 0.1U
PEG_TXP10
C857 0.1U
PEG_TXP11
C858 0.1U
PEG_TXP12
C863 0.1U
PEG_TXP13
C865 0.1U
PEG_TXP14
C872 0.1U
PEG_TXP15
C873 0.1U
PEG_TXP_C1
PEG_TXP_C2
PEG_TXP_C3
PEG_TXP_C4
PEG_TXP_C5
PEG_TXP_C6
PEG_TXP_C7
PEG_TXP_C9
PEG_TXP_C10
PEG_TXP_C11
PEG_TXP_C12
PEG_TXP_C13
PEG_TXP_C14
PEG_TXP_C15
QUANTA
Title
Size Document Number Re v
Custom
A
B
C
D
Date: Sheet
COMPUTER
System Block Diagram
AW3
E
7
1A
41Tuesday, March 15, 2005
of
A
B
C
D
E
8
4 4
GMCH_VTT 1.8VSUS
W26
V26
U26
T26
R26
P26
N26
M26
L26
W25
V25
U25
T25
R25
P25
N25
M25
L25
W24
V24
U24
T24
R24
P24
N24
M24
L24
W23
V23
U23
T23
R23
P23
N23
M23
L23
W22
V22
U22
T22
R22
P22
N22
M22
L22
W21
V21
U21
T21
P21
N21
M21
L21
Y20
R20
P20
N20
M20
L20
Y19
R19
P19
N19
M19
L19
Y18
R18
P18
N18
M18
L18
W17
V17
U17
T17
P17
N17
M17
L17
AD26
AC26
AD25
AC25
AD24
AC24
AD23
AC23
AD22
AC22
AD21
AC21
AD20
AC20
AD19
AC19
AD18
AC18
AD17
AC17
AD16
AC16
AD15
AC15
AD14
AC14
AD13
AC13
AB13
AD12
AC12
AB12
U42H
ALVISO_1257P
VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72
VCC_NCTF73
VCC_NCTF74
VCC_NCTF75
VCC_NCTF76
VCC_NCTF77
VCC_NCTF78
VCCSM_NCTF0
VCCSM_NCTF1
VCCSM_NCTF2
VCCSM_NCTF3
VCCSM_NCTF4
VCCSM_NCTF5
VCCSM_NCTF6
VCCSM_NCTF7
VCCSM_NCTF8
VCCSM_NCTF9
VCCSM_NCTF10
VCCSM_NCTF11
VCCSM_NCTF12
VCCSM_NCTF13
VCCSM_NCTF14
VCCSM_NCTF15
VCCSM_NCTF16
VCCSM_NCTF17
VCCSM_NCTF18
VCCSM_NCTF19
VCCSM_NCTF20
VCCSM_NCTF21
VCCSM_NCTF22
VCCSM_NCTF23
VCCSM_NCTF24
VCCSM_NCTF25
VCCSM_NCTF26
VCCSM_NCTF27
VCCSM_NCTF28
VCCSM_NCTF29
VCCSM_NCTF30
VCCSM_NCTF31
NCTF
3 3
VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VSS_NCTF13
VSS_NCTF14
VSS_NCTF15
VSS_NCTF16
VSS_NCTF17
VSS_NCTF18
VSS_NCTF19
VSS_NCTF20
VSS_NCTF21
VSS_NCTF22
VSS_NCTF23
VSS_NCTF24
VSS_NCTF25
VSS_NCTF26
VSS_NCTF27
VSS_NCTF28
VSS_NCTF29
VSS_NCTF30
VSS_NCTF31
VSS_NCTF32
VSS_NCTF33
VSS_NCTF34
VSS_NCTF35
VSS_NCTF36
VSS_NCTF37
VSS_NCTF38
VSS_NCTF39
VSS_NCTF40
VSS_NCTF41
VSS_NCTF42
VSS_NCTF43
VSS_NCTF44
VSS_NCTF45
VSS_NCTF46
VSS_NCTF47
VSS_NCTF48
VSS_NCTF49
VSS_NCTF50
VSS_NCTF51
VSS_NCTF52
VSS_NCTF53
VSS_NCTF54
VSS_NCTF55
VSS_NCTF56
VSS_NCTF57
VSS_NCTF58
VSS_NCTF59
VSS_NCTF60
VSS_NCTF61
VSS_NCTF62
VSS_NCTF63
VSS_NCTF64
VSS_NCTF65
VSS_NCTF66
VSS_NCTF67
VSS_NCTF68
VTT_NCTF0
VTT_NCTF1
VTT_NCTF2
VTT_NCTF3
VTT_NCTF4
VTT_NCTF5
VTT_NCTF6
VTT_NCTF7
VTT_NCTF8
VTT_NCTF9
VTT_NCTF10
VTT_NCTF11
VTT_NCTF12
VTT_NCTF13
VTT_NCTF14
VTT_NCTF15
VTT_NCTF16
VTT_NCTF17
AB26
AA26
Y26
Y25
Y24
Y23
Y22
AB25
AA25
AB24
AA24
AB23
AA23
AB22
AA22
AB21
AA21
Y21
R21
AB20
AA20
AB19
AA19
AB18
AA18
AB17
AA17
Y17
R17
AB16
AA16
T16
Y16
V16
P16
Y15
W16
U16
R16
N16
M16
AB15
AA15
W15
V15
L16
L15
T15
P15
Y14
M15
AB14
AA14
W14
V14
U15
R15
N15
L14
T14
P14
Y13
U14
R14
Y12
N14
M14
AA13
AA12
W13
V13
L13
T13
P13
U13
V12
R13
N13
M13
W12
L12
T12
P12
U12
R12
N12
M12
GMCH_VTT
AJ24
AG24
J24
F24
D24
B24
AF23
H23
AL22
AH22
J22
E22
D22
A22
AN21
AF21
F21
C21
AK20
V20
G20
F20
E20
D20
A20
AN19
AG19
W19
T19
J19
H19
C19
AL18
U18
B18
A18
AN17
AJ17
AF17
G17
C17
AL16
K16
H16
D16
A16
K15
C15
AN14
AL14
AJ14
AG14
K14
J14
F14
B14
A14
J12
D12
B12
AN11
AL11
AJ11
AG11
AF11
AA11
Y11
H11
F11
AA10
Y10
L10
D10
AN9
AH9
AE9
AC9
AA9
AL8
AN7
AK7
AG7
AA7
AJ6
AE6
AC6
AA6
AP5
AL5
AN4
AF4
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208V9VSS209T9VSS210K9VSS211H9VSS212A9VSS213
VSS214Y8VSS215P8VSS216L8VSS217E8VSS218C8VSS219
VSS220
VSS221
VSS222
VSS223V7VSS224G7VSS225
VSS226
VSS227
VSS228
VSS229T6VSS230P6VSS231L6VSS232J6VSS233B6VSS234
VSS235
VSS236W5VSS237E5VSS238
VSS239
2 2
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
J35
T37
Y37
V37
P37
K37
E37
H37
M37
AJ36
AL36
AF36
AE36
AG37
1 1
AN36
AD36
AC36
AB36
AA36
Y35
V35
C36
W35
AE35
L35
T35
P35
U35
R35
N35
M35
F35
K35
E35
B35
H35
G35
D35
AN34
AH34
AD34
AC34
AB34
AA34
C34
AL33
AF33
AD33
W33
T33
V33
U33
J33
L33
P33
K33
R33
N33
H33
M33
G33
VSS60
VSS61
F33
E33
VSS62
VSS63
D33
AN32
VSS64
VSS65
AJ32
VSS
VSS66
VSS67
AD32
AC32
VSS68
AB32
VSS69
AA32
VSS70
Y32
VSS71
C32
VSS72
A32
VSS73
AL31
VSS74
AG31
VSS75
AD31
VSS76
W31
VSS77
V31
VSS78
U31
VSS79
T31
VSS80
R31
VSS81
P31
VSS82
N31
VSS83
M31
VSS84
L31
VSS85
K31
VSS86
J31
VSS87
H31
VSS88
G31
VSS89
F31
E31
VSS90
VSS91
D31
VSS92
AP30
VSS93
AE30
VSS94
AC30
VSS95
AB30
VSS96
AA30
VSS97
Y30
VSS98
C30
VSS99
AM29
VSS100
VSS101
AJ29
AG29
VSS102
AD29
VSS103
W29
AA29
VSS104
VSS105
V29
VSS106
P29
U29
VSS107
VSS108
L29
H29
VSS109
AJ3
AC3
VSS240Y4VSS241U4VSS242P4VSS243L4VSS244H4VSS245C4VSS246
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
F29
E29
A29
D29
G29
AB28
AA28
AC28
AB3
AA3
VSS247
VSS248
VSS117
VSS118
E28
W28
AN2
VSS249
VSS250C3VSS251A3VSS252
VSS119
VSS120
VSS121
AJ27
AL27
AN27
AL2
AH2
VSS253
VSS122
VSS123
AF27
AG27
AE2
AD2
VSS254
VSS255
VSS124
VSS125
AB27
AA27
VSS256
VSS126
Y1
VSS257V2VSS258T2VSS259P2VSS260L2VSS268J2VSS269G2VSS270D2VSS271
VSS127
VSS128
VSS129
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
J26
E27
B27
E26
A26
G27
G26
W27
AN24
B36
VSSALVDS
VSS267
AL24
U42F
ALVISO_1257P
QUANTA
Title
Size Document Number Re v
Custom
A
B
C
D
Date: Sheet
COMPUTER
System Block Diagram
AW3
E
8
1A
41Tuesday, March 15, 2005
of
5
4
3
2
1
VCC1.5VCC1.5
VSSA_3GBG
U42E
ALVISO_1257P
C224
0.22U
C344
0.22U
C184
0.47U
C171
0.47U
L43
BLM18PG181SN1
C403
0.1U
C484
+
150U
EC 94
VCC_DDRDLL
L41
BLM18PG181SN1
D D
1.8VSUS
C888
C164
10U
C188
0.1U
A21
VCCHV2
VCC21
VCC22
P27
R27
AM37
AH37
VCCSM0
VCC23
N27
M27
VCC1.5
AP29
AD28
VCCSM1
VCCSM2
VCCSM3
VCC24
VCC25
VCC26
L27
K27
C891
0.1U
V1.8_DDR_CAP1
AD27
VCCSM4
VCC27
J27
VCC2.5
C C
B B
GMCH_VTT
F17
E17
VCCA_TVDACA0
VCCA_TVDACA1
VCC0
VCC1
T29
R29
F18
E18
H18
D18
C18
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
VCC2
VCC3
VCC4
VCC5
VCC6
J29
K29
V28
N29
U28
M29
C244
10U
C301
10U
C245
10U
C272
0.1U
C306
0.1U
C310
0.1U
G18
D19
H17
VSSA_TVBG
VCCA_TVBG
VCCD_TVDAC
VCC7
VCC8
VCC9
VCC10
T28
P28
R28
N28
B26
B25
A25
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
VCCDQ_TVDAC
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
J28
L28
K28
H28
M28
A35
B22
B21
VCCHV0
VCCA_LVDS
VCC17
VCC18
VCC19
T27
V27
U27
G28
VCCHV1
VCC20
AC27
AP26
VCCSM5
VCCSM6
VCC28
VCC29
K26
H27
0.1U
V1.8_DDR_CAP2
AN26
AM26
AL26
AK26
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCC30
VCC31
VCC32
VCC33
J25
K25
K24
H26
C392
0.1U
C391
0.1U
C461
0.1U
V1.8_DDR_CAP5
AJ26
AH26
AG26
AF26
AE26
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCC34
VCC35
VCC36
VCC37
K23
K22
K21
U20
W20
V_DPLLA
AP25
AN25
AM25
VCCSM15
VCCSM16
VCCSM17
VCC38
VCC39
VCC40
T20
K20
V19
C187
0.1U
C139
+
470U
L30
BLM11A05S
AL25
AK25
AJ25
VCCSM18
VCCSM19
VCCSM20
VCC41
VCC42
VCC43
K19
U19
W18
AH25
AG25
AF25
VCCSM21
VCCSM22
VCCSM23
VCC44
VCC45
VCC46
T18
V18
K18
V_DPLLB
Note: All VCCSM
pins shorted
internally.
AE25
AE24
AE23
VCCSM24
VCCSM25
VCCSM26
VCC47
VCC48
K17
AC2
C203
0.1U
C163
+
470U
L31
BLM11A05S
AE22
VCCSM27
VCCSM28
POWER
VCCD_HMPLL1
VCCD_HMPLL2
AC1
AE21
AE20
AE19
AE18
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
B23
C35
AA1
AA2
1.8VSUS 6,8,10,25,33,35
C463
10U
C456
10U
C384
0.047U
C377
0.047U
AE17
AE16
AE15
AE14
AP13
AN13
AM13
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
VCC_SYNC
F19
E19
H20
G19
C364
0.1U
C866
470U
L39
BLM11A05S
C485
330U
C404
0.047U
C378
0.047U
C380
0.047U
AL13
AK13
AJ13
VCCSM40
VCCSM41
VTT0
J13
K13
+
+
AH13
AG13
VCCSM42
VCCSM43
VCCSM44
VTT1
VTT2
VTT3
K12
W11
AF13
AE13
AP12
VCCSM45
VCCSM46
VTT4
VTT5
T11
V11
U11
GMCH_VTT
C383
0.047U
C382
0.047U
C379
0.047U
C359
0.047U
AN12
AM12
AL12
VCCSM47
VCCSM48
VCCSM49
VTT6
VTT7
VTT8
P11
R11
N11
C375
0.1U
C877
V_MPLL
470U
L38
BLM11A05S
AK12
AJ12
AH12
VCCSM50
VCCSM51
VCCSM52
VTT9
VTT10
VTT11
L11
K11
M11
+
2 1
RB751V-40
AG12
AF12
AE12
VCCSM53
VCCSM54
VCCSM55
VTT12
VTT13
VTT14
V10
U10
W10
D5
C462
0.1U
AD11
AC11
AB11
VCCSM56
VCCSM57
VCCSM58
VTT15
VTT16
VTT17
T10
P10
R10
VCC_CRTDAC
GM_VTT
VCC_DDRDLL
AF20
AP19
AF19
VCCA_SM0
VCCA_SM1
C170
10U
60mil
VCC1.5
AF18
VCCA_SM2
VCCA_SM3
GMCH_VTT
GMCH_VTT
VCC3G_PCIE
AE37
W37
VCC3G0
EC 94
C886
+
150U
C882
10U
C880
0.1U
U37
R37
VCC3G1
VCC3G2
VCCP_GMCH_CAP1
N37
L37
VCC3G3
VCC3G4
J37
VCC3G5
VCC3G6
Note: All VCCSM
pins shorted
internally.
C442
C411
0.1U
0.1U
VCC3G_PCIE
V1.8_DDR_CAP4
V1.8_DDR_CAP3
V1.8_DDR_CAP6
AB10
AB9
AP8
AM1
AE1
B28
A28
A27
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64
VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23Y9VTT24W9VTT25U9VTT26R9VTT27P9VTT28N9VTT29M9VTT30L9VTT31J9VTT32N8VTT33M8VTT34N7VTT35M7VTT36N6VTT37M6VTT38A6VTT39N5VTT40M5VTT41N4VTT42M4VTT43N3VTT44M3VTT45N2VTT46M2VTT47B2VTT48V1VTT49N1VTT50M1VTT51
J10
K10
N10
M10
C229
0.022U
C221
0.1U
L29
BLM18PG181SN1
R66
VCC2.5
10
V_3GPLL
R181
0.5/F
C387
10U
C363
0.1U
VCC2.5
VCCA_3GPLL
VCCA_3GBG
F37
Y29
Y28
Y27
VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2
VCCP_GMCH_CAP2
C243
4.7U
C832
2.2U
C225
0.1U
G37
VSSA_3GBG
VCCA_3GBG
G1
VCCP_GMCH_CAP4
VCCP_GMCH_CAP3
9
A A
QUANTA
Title
Size Document Number Re v
Custom
5
4
3
2
Date: Sheet
COMPUTER
System Block Diagram
AW3
9
1
1A
41Tuesday, March 15, 2005
of
A
1.8VSUS 1.8VSUS 1.8VSUS 1.8VSUS
SMDDR_VREF
A_MD0
A_MD1
A_DQS#0
A_DQS0
4 4
3 3
A_BS2#7
A_BS0#7 B_BS0#7
A_BMWEA#7 B_BMWEA#7SM_CS0# 6 SM_CS2# 6
A_SCASA#7 B_SCASA#7
SM_CS1#6 SM_CS3#6
M_ODT16 M_ODT36
2 2
1 1
A_MD2
A_MD3
A_MD8
A_MD9
A_DQS#1
A_DQS1
A_MD10 B_MD14
A_MD11
A_MD16
A_MD17
A_DQS#2
A_DQS2
A_MD18
A_MD19
A_MD24
A_MD25
A_DM3
A_MD26
A_MD27
CKE0
A_BS2#
A_MA12
A_MA9
A_MA8
A_MA5
A_MA3
A_MA1
A_MA10
A_BS0#
A_BMWEA#
A_SCASA#
SM_CS1#
M_ODT1
A_MD32
A_MD33
A_DQS#4
A_DQS4
A_MD34
A_MD35
A_MD40
A_MD41
A_DM5
A_MD42 A_MD46
A_MD43
A_MD48
A_MD49
A_DQS#6
A_DQS6
A_MD50
A_MD51
A_MD56
A_MD57
A_DM7
A_MD58
A_MD59
PDAT_SMB
PCLK_SMB
JDIM2
1
VREF
3
VSS47
5
DQ0
7
DQ1
9
VSS37
11
DQS#0
13
DQS0
15
VSS48
17
DQ2
19
DQ3
21
VSS38
23
DQ8
25
DQ9
27
VSS49
29
DQS#1
31
DQS1
33
VSS39
35
DQ10
37
DQ11
39
VSS50
41
VSS18
43
DQ16
45
DQ17
47
VSS1
49
DQS#2
51
DQS2
53
VSS19
55
DQ18
57
DQ19
59
VSS22
61
DQ24
63
DQ25
65
VSS23
67
DM3
69
NC4
71
VSS9
73
DQ26
75
DQ27
77
VSS4
79
CKE0
81
VDD7
83
NC1
85
A16_BA2
87
VDD9
89
A12
91
A9
93
A8
95
VDD5
97
A5
99
A3
101
A1
103
VDD10
105
A10/AP
107
BA0
109
WE#
111
VDD2
113
CAS#
115
S1#
117
VDD3
119
ODT1
121
VSS11
123
DQ32
125
DQ33
127
VSS26
129
DQS#4
131
DQS4
133
VSS2
135
DQ34
137
DQ35
139
VSS27
141
DQ40
143
DQ41
145
VSS29
147
DM5
149
VSS51
151
DQ42
153
DQ43
155
VSS40
157
DQ48
159
DQ49
161
VSS52
163
NCTEST
165
VSS30
167
DQS#6
169
DQS6
171
VSS31
173
DQ50
175
DQ51
177
VSS33
179
DQ56
181
DQ57
183
VSS3
185
DM7
187
VSS34
189
DQ58
191
DQ59
193
VSS14
195
SDA
197
SCL
199
VDD(SPD)
PC4800 DDR2
CLOCK 0,1 CLOCK 3,4
( Channel A ) ( Channel B )
SMbus address A0 SMbus address A1
A
2
VSS46
4
DQ4
6
DQ5
8
VSS15
10
DM0
12
VSS5
14
DQ6
16
DQ7
18
VSS16
20
DQ12
22
DQ13
24
VSS17
26
DM1
28
VSS53
CK0
CK0#
VSS41
DQ14
DQ15
VSS54
VSS20
DQ20
DQ21
VSS6
NC3
DM2
VSS21
DQ22
DQ23
VSS24
DQ28
DQ29
VSS25
DQS#3
DQS3
VSS10
DQ30
DQ31
VSS8
CKE1
VDD8
A15
A14
VDD11
A11
A7
A6
VDD4
A4
A2
A0
VDD12
BA1
RAS#
S0#
VDD1
ODT0
A13
PC4800 DDR2 SDRAM
SO-DIMM (200P)
VDD6
NC2
VSS12
DQ36
DQ37
VSS28
DM4
VSS42
DQ38
DQ39
VSS55
DQ44
DQ45
VSS43
DQS#5
DQS5
VSS56
DQ46
DQ47
VSS44
DQ52
DQ53
VSS57
CK1
CK1#
VSS45
DM6
VSS32
DQ54
DQ55
VSS35
DQ60
DQ61
VSS7
DQS#7
DQS7
VSS36
DQ62
DQ63
VSS13
SA0
SA1
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
CLK_SDRAM0
CLK_SDRAM0#
CLK_SDRAM1
CLK_SDRAM1#
R278 10K
R279 10K
A_MD4
A_MD5
A_DM0
A_MD6
A_MD7
A_MD12
A_MD13
A_DM1
A_MD14
A_MD15
A_MD20
A_MD21
A_DM2
A_MD22
A_MD23
A_MD28
A_MD29
A_DQS#3
A_DQS3
A_MD30
A_MD31
CKE1
A_MA11
A_MA7
A_MA6
A_MA4
A_MA2
A_MA0
A_BS1#
A_SRASA#
SM_CS0#
M_ODT0
A_MA13
A_MD36
A_MD37
A_DM4
A_MD38
A_MD39
A_MD44
A_MD45
A_DQS#5
A_DQS5
A_MD47
A_MD52
A_MD53
A_DM6
A_MD54
A_MD55
A_MD60
A_MD61
A_DQS#7
A_DQS7
A_MD62
A_MD63
B
A_DM[0..7] 7
A_MD[0..63] 7
A_DQS[0..7] 7
A_DQS#[0..7] 7
A_MA[0..13] 7
CLK_SDRAM0 6
CLK_SDRAM0# 6
CKE1 6 CKE3 6CKE06 CKE26
A_BS1# 7 B_BS1# 7
M_ODT0 6
CLK_SDRAM1 6 CLK_SDRAM4 6
CLK_SDRAM1# 6
B
SMDDR_VREF6,35
B_BS2#7
PDAT_SMB3,12
PCLK_SMB3,12
SMDDR_VREF
B_MD0
B_MD1
B_DQS#0
B_DQS0
B_MD2
B_MD3
B_MD8
B_MD9
B_DQS#1
B_DQS1
B_MD10
B_MD11
B_MD16
B_MD17
B_DQS#2
B_DQS2
B_MD18
B_MD19
B_MD24
B_MD25
B_DM3
B_MD26
B_MD27
CKE2
B_BS2#
B_MA12
B_MA9
B_MA8
B_MA5
B_MA3
B_MA1
B_MA10
B_BS0#
B_BMWEA#
B_SCASA#
SM_CS3#
M_ODT3
B_MD32
B_MD33
B_DQS#4
B_DQS4
B_MD34
B_MD35
B_MD40
B_MD41
B_DM5
B_MD42 B_MD46
B_MD43
B_MD48
B_MD49
B_DQS#6
B_DQS6
B_MD50
B_MD56
B_MD57
B_DM7
B_MD58
B_MD59
PDAT_SMB
PCLK_SMB
VCC33,4,11,12,13,14,15,16,17,20,21,22,23,24,25,26,27,29,30,31,32,33,36
1.8VSUS6,8,9,25,33,35
SMDDR_VTERM25,35,36
SMDDR_VREF6,35
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
JDIM1
VREF
VSS47
DQ0
DQ1
VSS37
DQS#0
DQS0
VSS48
DQ2
DQ3
VSS38
DQ8
DQ9
VSS49
DQS#1
DQS1
VSS39
DQ10
DQ11
VSS50
VSS18
DQ16
DQ17
VSS1
DQS#2
DQS2
VSS19
DQ18
DQ19
VSS22
DQ24
DQ25
VSS23
DM3
NC4
VSS9
DQ26
DQ27
VSS4
CKE0
VDD7
NC1
A16_BA2
VDD9
A12
A9
A8
VDD5
A5
A3
A1
VDD10
A10/AP
BA0
WE#
VDD2
CAS#
S1#
VDD3
ODT1
VSS11
DQ32
DQ33
VSS26
DQS#4
DQS4
VSS2
DQ34
DQ35
VSS27
DQ40
DQ41
VSS29
DM5
VSS51
DQ42
DQ43
VSS40
DQ48
DQ49
VSS52
NCTEST
VSS30
DQS#6
DQS6
VSS31
DQ50
DQ51
VSS33
DQ56
DQ57
VSS3
DM7
VSS34
DQ58
DQ59
VSS14
SDA
SCL
VDD(SPD)
PC4800 DDR2
CKE 2,3CKE 0,1
High=5.2mmHigh=9.2mm
C
2
VSS46
4
DQ4
6
DQ5
8
VSS15
10
DM0
12
VSS5
14
DQ6
16
DQ7
18
VSS16
20
DQ12
22
DQ13
24
VSS17
26
DM1
28
VSS53
CK0
CK0#
VSS41
DQ14
DQ15
VSS54
VSS20
DQ20
DQ21
VSS6
NC3
DM2
VSS21
DQ22
DQ23
VSS24
DQ28
DQ29
VSS25
DQS#3
DQS3
VSS10
DQ30
DQ31
VSS8
CKE1
VDD8
A15
A14
VDD11
A11
A7
A6
VDD4
A4
A2
A0
VDD12
BA1
RAS#
S0#
VDD1
ODT0
A13
PC4800 DDR2 SDRAM
SO-DIMM (200P)
VDD6
NC2
VSS12
DQ36
DQ37
VSS28
DM4
VSS42
DQ38
DQ39
VSS55
DQ44
DQ45
VSS43
DQS#5
DQS5
VSS56
DQ46
DQ47
VSS44
DQ52
DQ53
VSS57
CK1
CK1#
VSS45
DM6
VSS32
DQ54
DQ55
VSS35
DQ60
DQ61
VSS7
DQS#7
DQS7
VSS36
DQ62
DQ63
VSS13
SA0
SA1
C
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
CLK_SDRAM3
CLK_SDRAM3#
CLK_SDRAM4
CLK_SDRAM4#
R268 10K
R269 10K
B_MD4
B_MD5
B_DM0
B_MD6
B_MD7
B_MD12
B_MD13
B_DM1
B_MD15
B_MD20
B_MD21
B_DM2
B_MD22
B_MD23
B_MD28
B_MD29
B_DQS#3
B_DQS3
B_MD30
B_MD31
CKE3
B_MA11
B_MA7
B_MA6
B_MA4
B_MA2
B_MA0
B_BS1#
B_SRASA#
SM_CS2#
M_ODT2
B_MA13
B_MD36
B_MD37
B_DM4
B_MD38
B_MD39
B_MD44
B_MD45
B_DQS#5
B_DQS5
B_MD47
B_MD52
B_MD53
B_DM6
B_MD54
B_MD55B_MD51
B_MD60
B_MD61
B_DQS#7
B_DQS7
B_MD62
B_MD63
B_DM[0..7] 7
B_MD[0..63] 7
B_DQS[0..7] 7
B_DQS#[0..7] 7
B_MA[0..13] 7
CLK_SDRAM3 6
CLK_SDRAM3# 6
B_SRASA# 7A_SRASA# 7
M_ODT2 6
CLK_SDRAM4# 6
VCC3VCC3VCC3
D
1.8VSUS 1.8VSUS
C524
C548
0.1U
0.1U
1.8VSUS
C611
C585
0.1U
0.1U
VCC3 VCC3
C894
C895
2.2U
0.1U
SMDDR_VREF SMDDR_VREF
C573
C575
2.2U
0.1U
SMDDR_VTERM
C602
0.1U
SMDDR_VTERM
C565
0.1U
C608
0.1U
C561
0.1U
C531
0.1U
C610
0.1U
C899
2.2U
C556
2.2U
C600
0.1U
C549
0.1U
C569
0.1U
C609
0.1U
C900
0.1U
C544
0.1U
C562
0.1U
C576
0.1U
1.8VSUS
C559
0.1U
C551
0.1U
C526
2.2U
C584
2.2U
Place these Caps near So-Dimm1.Place these Caps near So-Dimm1.
Place these Caps near So-Dimm2.Place these Caps near So-Dimm2.
SM_CS0#
A_BS1#
A_MA8
A_MA5
A_MA1
A_MA3
A_MA11
CKE1
A_BS0#
A_MA10
A_MA6
A_MA7
A_MA4
A_MA2
A_SRASA#
A_MA0
A_MA12
A_MA9
A_SCASA#
A_BMWEA#
B_BS1#
B_MA2
B_MA1
B_MA3
B_MA5
B_MA8
B_MA0
B_MA4
B_MA9
B_MA12
B_MA7
B_MA6
B_BS2#
CKE2
B_MA13
B_SRASA#
B_SCASA#
B_BMWEA#
B_BS0#
B_MA10
M_ODT0
A_MA13
M_ODT2
SM_CS2#
M_ODT3
SM_CS3#
M_ODT1
SM_CS1#
B_MA11
CKE3
A_BS2#
CKE0
C591
0.1U
C590
0.1U
C529
C525
2.2U
2.2U
C612
C615
2.2U
2.2U
RP78 56X2
RP69 56X2
RP70 56X2
RP74 56X2
RP71 56X2
RP75 56X2
RP76 56X2
RP77 56X2
RP68 56X2
RP72 56X2
RP64 56X2
RP57 56X2
RP56 56X2
RP63 56X2
RP55 56X2
RP62 56X2
RP54 56X2
RP65 56X2
RP59 56X2
RP58 56X2
RP79 56X2
RP66 56X2
RP60 56X2
RP73 56X2
RP61 56X2
RP67 56X2
C577
C558
0.1U
0.1U
C589
C563
0.1U
0.1U
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
C560
0.1U
C566
0.1U
C567
2.2U
C616
2.2U
C574
0.1U
C593
0.1U
E
C568
2.2U
C582
2.2U
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
10
C570
2.2U
C583
2.2U
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
C557
C601
0.1U
0.1U
C578
C592
0.1U
0.1U
C588
0.1U
C564
0.1U
Layout note: Place one cap close to every 2 pullup resistors terminated to SMDDR_VTERM
QUANTA
Title
Size Document Number Re v
Custom
D
Date: Sheet
COMPUTER
System Block Diagram
AW3
10
E
of
1A
41Tuesday, March 15, 2005
A
B
C
D
E
CLK_32KX1
5
4
3
2
1
5
4
3
2
1
5
4
3
2
1
GMCH_VTT
GMCH_VTT
GMCH_VTT
VCC3
E
11
IRQ14
REQ0#
FRAME#
REQ2#
PIRQD#
STOP#
REQ1#
DEVSEL#
PLOCK#
REQ5#
SATA_RXN0 29
SATA_RXP0 29
SATA_TXN0 29
SATA_TXP0 29
11
of
VCC3
VCC3
VCC3
1A
41Tuesday, March 15, 2005
23
CLK_32KX2
NMI4
A20M#4
FERR#4
IGNNE#4
INTR4
CPUINIT#4
RCIN#31
GATEA2031
AD[0..31]22,24,26
PCI_PME#22,24,26
PCLK_ICH3
PCIRST#4,12,22,23,24,26,31
CLKRUN#22,24,26,31
VCC3
PDD[0..15]12
PDCS1#12
PDCS3#12
PDA012
PDA112
PDA212
PDIOR#12
PDIOW#12
PIORDY12
IRQ1412
PDDREQ12
PDDACK#12
R317
10M
RTC_RST#
SM_INTRUDER#
R300 56
R302 10K
PDCS1#
PDCS3#
PDA0
PDA1
PDA2
PDIOR#
PDIOW#
PIORDY
IRQ14
PDDREQ
PDDACK#
R_FERR#
RCIN#
GATEA20
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PCLK_ICH
PCIRST#
PLTRST1_#
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
AA2
AA3
AA5
AF25
AF23
AF24
AG26
AG24
AF27
AD23
AF22
AF19
AD14
AF15
AF14
AD12
AE14
AC11
AD11
AB11
AE13
AF13
AB12
AB13
AC13
AE15
AG15
AD13
AD16
AE17
AC16
AB17
AC17
AE16
AC14
AF16
AB16
AB14
AB15
Y1
Y2
E2
E5
C2
F5
F3
E9
F2
D6
E6
D3
A2
D2
D5
H3
B4
J5
K2
K5
D4
L6
G3
H4
H2
H5
B3
M6
B2
K6
K3
A5
L1
K4
P6
G6
R2
R5
U34A
RTCX1
RTCX2
RTCRST#
INTRUDER#
INTVRMEN
NMI
A20M#
FERR#
IGNNE#
INTR
INIT#
RCIN#
A20GATE
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PME#
PCICLK
PCIRST#
PLTRST#
CLKRUN#/GPIO32
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
DCS1#
DCS3#
DA0
DA1
DA2
DIOR#
DIOW#
IORDY
IDEIRQ
DDREQ
DDACK#
ICH6-M
C
RTC
CPU
PCI
IDE
LAD0
LAD1/FB1
LAD2/FB2
LAD3/FB3
LDRQ0#
LDRQ1#/GPI41
LFRAME#
LPC
CPUPWRGD/GPO49
INIT3_3V#
THRMTRIP#
SMI#
STPCLK#
CPUSLP#
DPSLP#/TP[2]
DPRSLP#/TP[4]
C/BE0#
C/BE1#
C/BE2#
C/BE3#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PAR
SERR#
PERR#
PLOCK#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#/GPI40
REQ5#/GPI1
REQ6#/GPI0
GNT0#
GNT1#
GNT2#
GNT3#
GNT4#/GPO48
GNT5#/GPO17
GNT6#/GPO16
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPI2
PIRQF#/GPI3
PIRQG#/GPI4
PIRQH#/GPI5
SATALED#
SATA0_RXN
SATA0_RXP
SATA0_TXN
SATA0_TXP
SATA2_RXN
SATA2_RXP
SATA2_TXN
SATA2_TXP
SATA_CLKN
SATA
SATA_CLKP
SATARBIAS#
SATARBIAS
ACZ_BIT_CLK
ACZ_SYNC
ACZ_RST#
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
ACZ_SDO
AC-97/
AZALIA
HD_BCLK
P2
N3
N5
N4
LPC_DRQ0#
N6
LPC_DRQ1#
P4
P3
AG25
AE22
THERMTRIP#_ICH
AE23
AG27
AE26
R_CPUSLP#
AE27
AD27
AE24
J6
H6
G4
G2
J3
A3
J2
C3
J1
E1
G5
E3
C5
REQ0#
L5
REQ1#
B5
REQ2#
M5
REQ3#
B8
REQ4#
F7
REQ5#
E8
REQ6# DPRSLP#
B7
GNT0#
C1
GNT1#
B6
GNT2#
F1
GNT3#
C8
GNT4#
E7
GNT5#
F6
GNT6#
D8
PIRQA#
N2
PIRQB#
L2
PIRQC#
M1
PIRQD#
L3
ICH_GPI2
D9
ICH_GPI3
C7
ICH_GPI4
C6
ICH_GPI5
M3
ICHSATALED#
R293 10K
AC19
SATA_RXN0_C
AE3
SATA_RXP0_C
AD3
SATA_TXN0_C
AG2
SATA_TXP0_C
AF2
SATA_RXN1_C
AD7
SATA_RXP1_C
AC7
AF6
AG6
AC2
AC1
AG11
R297 24.9/F
AF11
Place within 500mils
of ICH6 ball
HD_BCLK
C10
IAC_SYNC
B9
IAC_RESET#
A10
F11
F10
B10
IAC_SDATAO
C9
LAD0/FWH0 31
LAD1/FWH1 31
LAD2/FWH2 31
LAD3/FWH3 31
LPC_DRQ0#
LPC_DRQ1# 31
LFRAME#/FWH4 31
CPUPWRGD 4
R291 56
SMI# 4
STPCLK# 4
DPSLP# 4
C/BE0# 22,24,26
C/BE1# 22,24,26
C/BE2# 22,24,26
C/BE3# 22,24,26
FRAME# 22,24,26
IRDY# 22,24,26
TRDY# 22,24,26
DEVSEL# 22,24,26
STOP# 22,24,26
PAR 22,24,26
SERR# 22,24,26
PERR# 22,24,26
PLOCK# 22
REQ0# 22
REQ1# 24
REQ2# 26
GNT0# 22
GNT1# 24
GNT2# 26
T86
T92
T90
T89
PIRQB# 22,26
PIRQC# 22,26
PIRQD# 22,24
VCC3
SRC_SATA# 3
SRC_SATA 3
HD_SDIN0 27
HD_SDIN1 26
T48
GMCH_VTT
Depop for Dothan-B,Populate for Dothan-A
R306 *0
R307 0
Depop for Dothan-A,Populate for Dothan-B
R290
75
PM_THRMTRIP# 4,6
CPUSLP# 4,6
DPRSLP# 4
PCI Pullups
SERIRQ12,22,31
IAC_SDATAO
IAC_RESET#
IAC_SYNC
VCC3
VCC3
VCC3
R369 39
R449 39
R463 39
R462
R458
SERIRQ
PERR#
REQ4#
SERR#
IRDY#
REQ6#
REQ3#
Close to ICH6-M
R367 39
EC 71
R569
R570
39
39
HD_BCLK_MDC 26
HD_BCLK_Audio 27
D
Title
Size Document Number Re v
Custom
Date: Sheet
FERR#
DPSLP#
6
7
8
9
10
6
7
8
9
10
6
7
8
9
10
R299 56
R289 *56
R298 *56
39
39
RP84
RP85
RP87
RP88
1
3
5
7
8.2KX4
C653 3900P
C659 3900P
C651 3900P
C652 3900P
C739
*10P
C740
*10P
C741
*10P
PIRQA#
PIRQC#
PIRQB#
TRDY#
ICH_GPI5
ICH_GPI4
ICH_GPI3
ICH_GPI2
SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_C
SATA_TXP0_C
QUANTA
COMPUTER
System Block Diagram
AW3
8.2KX8
8.2KX8
8.2KX8
2
4
6
8
HD_SDO_MDC 26
HD_SDO_Audio 27
HD_RST#_MDC 26
HD_RST#_Audio 27
HD_SYNC_MDC 26
HD_SYNC_Audio 27
R311
0
CL2
CL1
C673 15P
Y4
32.768KHZ
C667 15P
B
4 1
C658
0.1U
RTC
2 1
3VPCU
EC 74
30mil
CON20
4 4
Check Trace width
BIOS_CRISIS_REC31
BIOS_HDD_CLEAR31
3 3
2 2
1 1
R438 1K
1
2
85204-0200L
BIOS_CRISIS_REC
BIOS_HDD_CLEAR
VCC3
BL2
HL2
PLTRST#6,12,14,29
C728 18P
A
2 1
VCC3
BL1
HL1
PCLK_ICHRC
R282 4.7K
VCCRTC
D8
RB500H
C700
0.1U
D7
RB500H
R301 10K
C297
0.1U
R310 240K
R314
1M
SM_INTRUDER#
RCIN#
CMOS Clear
Place close to DIMM or MiniPCI door.
BIOS CRISIS RECOVERY
Place close to DIMM or MiniPCI door.
BIOS AND HDD PASSWORD CLEAR
Place close to DIMM or MiniPCI door.
VCC3
C6440.01U
53
U31
PIORDY
1
2
PCLK_ICH
PLTRST1_#
4
NC7SZ32P5X
R323 33
EC5
Z0815
A
B
C
D
E
Primary HDD Connector
R574 0
HDD1LED#CD_LED#
PDDREQ
4 4
HDD1VCC VCC5
3 3
60mil
2 2
1 1
VCC5
Pin 47 Cable select:
"H" = Slave
"L" = Master
R281 *4.7K
IRQ14
IDERST1#
PDD7
PDD6
PDD4
PDD3
PDD2
PDD1
PDD0
PDDREQ
PDIOW#
PDIOR#
PIORDY
PDDACK#
IRQ14
PDA1
PDA0
PDCS1#
HDD1LED#
C634
*100P
R238 470
RP82
1
3
*4P2R-S-10K
CON24
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
HDD
PDD[0..15]11
PDCS1#11
PDCS3#11
PDA011
PDA111
PDA211
PDIOR#11
PDIOW#11
PIORDY11
IRQ1411
PDDREQ11
PDDACK#11
IDERST1#
PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0
PDIOW#
IRQ14
PDA1
PDA0 PDA2
PDCS1#
CD_LED#
VCC5_CD
A
ODDCSEL
45
46
47
48
R566 *0
EC13
2
4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
CON22
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
CDR-50RUX-50P
D16
RB500H
PDD8
PDD9
PDD10PDD5
PDD11
PDD12
PDD13
PDD14
PDD15
HDDCSEL
PDIAG#
PDA2
PDCS3#
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
EC 56
21
R283 470
R284 *10K
C631
.1U
ODD_LED# 20,29
HDD1VCC
C627
10U/10V
F5 2A
1 2
C626
10U/10V
60mil 60mil
C630
C629
1000P
.1U
CD ROM Connector
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
PDDREQ
PDIOR#
PDDACK#PIORDY
PDIAG#
PDCS3#
R248 *10K
C502
.1U
CD_LED#
C503
.1U
IDERST1#
C505
.1U
R318
33
R567 *0
D15
*RB500H
VCC5
VCC5_CD
C504
.1U
IDERST1#R
21
4
C624
10U/10V
R322
33
C727
10P
U33
EC 57
F4 2A
RC1206
C506
10U/10V
B
VCC5
TC7SH08FU
3 5
12
CLK48_USB
ICHCLK48RC
14M_ICH
14M_ICHRC
80 mils80 mils
R326
10
C730
10P
ICHEXP_RXP022
ICHEXP_RXN022
ICHEXP_TXN022
ICHEXP_TXP022
EC12
2
1
ODD_LED# 20,29
VCC5
USBP0+30
USBP0-30
OC0#30
USBP2+30
USBP2-30
OC2#30
USBP4+30
USBP4-30
USBP6+22 USBP7+ 30
USBP6-22
CLK48_USB3
DMI_RXN06
DMI_RXP06
DMI_TXN06
DMI_TXP06
DMI_RXN16
DMI_RXP16
DMI_TXN16
DMI_TXP16
SRC_ICH#3
SRC_ICH3
C684 0.1U
PCLK_SMB3,10
PDAT_SMB3,10
H_THMD_ALERT#4
NPWROK20,31
DPRSLPVR32
DNBSWON#31
IMVP_PWG6,32
PM_BMBUSY#6
T81
14M_ICH3
PCSPK27
KBSMI#31
SCI#31
SWI#31
LCD_ON20
DEV_OFF_LAN24
DEV_OFF_MINI26
RF_SW#26,30
EC 95
PCIRST# 4,11,22,23,24,26,31
CLK48_USB
C686 0.1U
PCLK_SMB
PDAT_SMB
SMBALERT#
RI#
NPWROK
BATLOW#
DNBSWON#
RSMRST#
IMVP_PWG
SUSCLK
ICH6_GPI7
KBSMI#
SCI#
SWI#
T87
T47
T91
T88
OC0#
OC2#
OC4#
ICHEXPTXN0C
RVCC3
D21
USBP0P
C21
USBP0N
C27
OC0#
C19
USBP2P
D19
USBP2N
B26
OC2#
D17
USBP4P
E17
USBP4N
C23
OC4#/GPI9
D15
USBP6P
C15
USBP6N
C25
OC6#/GPI14
A27
CLK48
T25
DMI0_RXN
T24
DMI0_RXP
R27
DMI0_TXN
R26
DMI0_TXP
V25
DMI1_RXN
V24
DMI1_RXP
U27
DMI1_TXN
U26
DMI1_TXP
AD25
DMI_CLKN
AC25
DMI_CLKP
H25
HSIN0
H24
HSIP0
G27
HSON0
G26
HSOP0
K25
HSIN1
K24
HSIP1
J27
HSON1
J26
HSOP1
Y4
SMBCLK
W5
SMBDATA
W6
SMBALERT#/GPI11
T2
RI#
AC20
THRM#
AA1
PWROK
AE20
DPRSLPVR/TP1
V2
BATLOW#/TP0
U1
PWRBTN#
Y3
RSMRST#
AF21
VRMPWRGD
AD19
BM_BUSY#/GPIO6
W3
SUS_STAT#/LPCPD#
V6
SUSCLK
E10
CLK14
F8
SPKR
AE19
GPI7
R1
GPI8
M2
GPI12
R6
GPI13
AB21
GPO19
AD20
GPO21
AD21
GPO23
V3
GPIO24
D12
EE_CS
B12
EE_SHCLK
D11
EE_DOUT
F13
EE_DIN
AC5
RSVD1
AD5
RSVD2
AF4
RSVD3
AG4
RSVD4
AC9
RSVD5
C
U34B
PCI-EXPRESS
SM&SMI
MISC&GPIO
RESERVED
ICH6-M
R308 22K
USB
DMI
PM
LAN
1 6
C657
1U
STP_PCI#/GPO18
STP_CPU#/GPO20
SATA0GP/GPIO26
SATA1GP/GPIO29
SATA2GP/GPIO30
SATA3GP/GPIO31
5
U32A
7WZ14
USBP1P
USBP1N
OC1#
USBP3P
USBP3N
OC3#
USBP5P
USBP5N
OC5#/GPI10
USBP7P
USBP7N
OC7#/GPI15
USBRBIAS
USBRBIAS#
DMI2_RXN
DMI2_RXP
DMI2_TXN
DMI2_TXP
DMI3_RXN
DMI3_RXP
DMI3_TXN
DMI3_TXP
DMI_ZCOMP
DMI_IRCOMP
HSIN2
HSIP2
HSON2
HSOP2
HSIN3
HSIP3
HSON3
HSOP3
SMLINK0
SMLINK1
LINKALERET#
SLP_S3#
SLP_S4#
SLP_S5#
LAN_RST#
SYS_RESET#
WAKE#
MCH_SYNC#
SERIRQ
GPIO25
GPIO27
GPIO28
GPIO33
GPIO34
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
LAN_CLK
LAN_RSTSYNC
RSVD6
RSVD7
RSVD8
RSVD9
ICHRSMRSTRSMRSTRC
B20
A20
OC1#
B27
B18
A18
OC3#
C26
A16
B16
OC5#
D23
B14
A14
OC7#OC6#
C24
B22
R325 22.6/F
A22
Place within 500mils of ICH-6
Y25
Y24
W27
W26
AB24
AB23
AA27
AA26
ICHDMICOMP
F24
R319 24.9/F
F23
Place within 500mils of ICH-6
M25
M24
L27
L26
P24
P23
N27
N26
SMLINK0
W4
SMLINK1
U6
SMB_LINK_ALERT#
Y5
T4
T5
T6
V5
SYS_RESET#
U2
PCIE_WAKE#
U5
MCH_SYNC#
AG21
AC21
AD22
AB20
P5
SATA0GP
AF17
R3
T3
SATA1GP
AE18
SATA2GP
AF18
SATA3GP
AG18
AF20
AC18
E12
E11
C13
C12
C11
E13
F12
B11
AD9
AF8
AG8
U3
5
U32B
3 4
7WZ14
RSMRST#
D
USBP1+ 30
USBP1- 30
OC1# 30
USBP3+ 30
USBP3- 30
OC3# 30
USBP5+ 30
USBP5- 30
USBP7- 30
SUSB# 31
SUSC# 31
PCIE_WAKE# 22
STP_PCI# 3
STP_CPU# 3,32
SERIRQ 11,22,31
FPID0# 30
SATA_EN#
KBID0# 30
KBID1# 30
EC 95
DMI_RXN2 6
DMI_RXP2 6
DMI_TXN2 6
DMI_TXP2 6
DMI_RXN3 6
DMI_RXP3 6
DMI_TXN3 6
DMI_TXP3 6
VCC1.5
PLTRST# 6,11,14,29
T83
12
OC2#
OC1#
OC3#
OC0#
3VSUS
EC6
VCC3
EC7
EC8
EC9
VCC3
VCC3
EC10
VCC3
EC11
RVCC3
RVCC3
RVCC3
Title
Size Document Number Re v
Custom
Date: Sheet
RP86
6
7
8
9
10
10KX8
RVCC3
RP81
1
2
3
4
5
6
7
8
10KX4
RVCC3
RP80
1
2
3
4
5
6
7
8
10KX4
RVCC3
RP83
1
2
3
4
5
6
7
8
10KX4
EC 88
R551 100K
R294 8.2K
R295 8.2K
R286 10K
R285 10K
R287 680
R292 100K
R312 10K
R288 10K
R305 100
R296 100
R303 100
R304 100C648 .1U
QUANTA
COMPUTER
System Block Diagram
AW3
5
4
3
2
1
SMB_LINK_ALERT#
SMLINK0
BATLOW#
MCH_SYNC#
SWI#
SCI#
SMBALERT#
SMLINK1
KBSMI#
RI#
DNBSWON#
SYS_RESET#
FPID0#
ICH6_GPI7
H_THMD_ALERT#
PCLK_SMB
PDAT_SMB
PCIE_WAKE#
DPRSLPVR
NPWROK
RSMRST#
SATA0GP
SATA1GP
SATA2GP
SATA3GP
E
OC4#
OC7#
OC6#
OC5#
12
3VSUS
1A
41Tuesday, March 15, 2005
of
A
L47
VCC5
VCC3
5VPCU
3VPCU
VCC3
1 2
BLM41P600SPG
R330 10
R321 10
C719
0.1U
2 1
2 1
ICHDMIPLL
VCC1.5
VCC1.5
4 4
3 3
VCC1.5
R316 1
C656
10U
2 2
EC18
VCC3
RVCC3
RVCC3
1 1
C717
0.1U
C715
0.1U
+1_5V_PCIE
C677
+
220U
D20
C639
0.1U
C716
0.1U
C674
0.1U
C713
0.1U
C731
1U
C699
1U
VCC1.5
VCC1.5
VCC3
C714
0.1U
C712
0.1U
A
RB751V-40
D18
RB751V-40
L46 BLM11A05S
C676
0.1U
V5REF
C709
0.1U
V5REF_SUS
C701
0.1U
+1_5V_SATA_RX
C650
0.1U
+1_5V_SATA_TX
C649
0.1U
C669
0.01U
C645
0.1U
C718
0.1U
C642
0.1U
C641
0.1U
C678
0.1U
V_DMIPLL
C680
0.1U
C643
0.1U
C640
0.1U
U34C
AA22
VCC1_5_1
AA23
VCC1_5_2
AA24
VCC1_5_3
AA25
VCC1_5_4
AB25
VCC1_5_5
AB26
VCC1_5_6
AB27
VCC1_5_7
F25
VCC1_5_8
F26
VCC1_5_9
F27
VCC1_5_10
G22
VCC1_5_11
G23
VCC1_5_12
G24
VCC1_5_13
G25
VCC1_5_14
H21
VCC1_5_15
H22
VCC1_5_16
J21
VCC1_5_17
J22
VCC1_5_18
K21
VCC1_5_19
K22
VCC1_5_20
L21
VCC1_5_21
L22
VCC1_5_22
M21
VCC1_5_23
M22
VCC1_5_24
N21
VCC1_5_25
N22
VCC1_5_26
N23
VCC1_5_27
N24
VCC1_5_28
N25
VCC1_5_29
P21
VCC1_5_30
P25
VCC1_5_31
P26
VCC1_5_32
P27
VCC1_5_33
R21
VCC1_5_34
R22
VCC1_5_35
T21
VCC1_5_36
T22
VCC1_5_37
U21
VCC1_5_38
U22
VCC1_5_39
V21
VCC1_5_40
V22
VCC1_5_41
W21
VCC1_5_42
W22
VCC1_5_43
Y21
VCC1_5_44
Y22
VCC1_5_45
AA6
VCC1_5_46
AB4
VCC1_5_47
AB5
VCC1_5_48
AB6
VCC1_5_49
AC4
VCC1_5_50
AD4
VCC1_5_51
AE4
VCC1_5_52
AE5
VCC1_5_53
AF5
VCC1_5_54
AG5
VCC1_5_55
AA7
VCC1_5_56
AA8
VCC1_5_57
AA9
VCC1_5_58
AB8
VCC1_5_59
AC8
VCC1_5_60
AD8
VCC1_5_61
AE8
VCC1_5_62
AE9
VCC1_5_63
AF9
VCC1_5_64
AG9
VCC1_5_65
AC27
VCCDMIPLL
E26
VCC3_3_1
AE1
VCCSATAPLL
AG10
VCC3_3_22
A13
VCCLAN3_3/VCCSUS3_3_1
F14
VCCLAN3_3/VCCSUS3_3_2
G13
VCCLAN3_3/VCCSUS3_3_3
G14
VCCLAN3_3/VCCSUS3_3_4
A11
VCCSUS3_3_1
U4
VCCSUS3_3_2
V1
VCCSUS3_3_3
V7
VCCSUS3_3_4
W2
VCCSUS3_3_5
Y7
VCCSUS3_3_6
A17
VCCSUS3_3_7
B17
VCCSUS3_3_8
C17
VCCSUS3_3_9
F18
VCCSUS3_3_10
G17
VCCSUS3_3_11
G18
VCCSUS3_3_12
ICH6-M
B
VCC1_5_79
VCC1_5_80
VCC1_5_81
VCC1_5_82
VCC1_5_83
VCC1_5_84
VCC1_5_85
VCC1_5_86
VCC1_5_87
VCC1_5_88
VCC1_5_89
VCC1_5_90
VCC1_5_91
B
VCC1_5_92
VCC1_5_93
VCC1_5_94
VCC1_5_95
VCC1_5_96
VCC1_5_97
VCC1_5_98
VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6
VCC3_3_7
VCC3_3_8
VCC3_3_9
VCC3_3_10
VCC3_3_11
VCC3_3_12
VCC3_3_13
VCC3_3_14
VCC3_3_15
VCC3_3_16
VCC3_3_17
VCC3_3_18
VCC3_3_19
VCC3_3_20
VCC3_3_21
VCCSUS1_5_1
VCCSUS1_5_2
VCCSUS1_5_3
VCC1_5_67
VCC1_5_68
VCC1_5_69
VCC1_5_70
VCC1_5_71
VCC1_5_72
VCC1_5_73
VCC1_5_74
VCC1_5_75
VCC1_5_76
VCC1_5_77
VCC1_5_78
VCC2_5_2
VCC2_5_4
V5REF1
V5REF2
V5REF_SUS
VCCUSBPLL
VCCSUS3_3_20
VCCRTC
V_CPU_IO1
V_CPU_IO2
V_CPU_IO3
VCCSUS3_3_13
VCCSUS3_3_14
VCCSUS3_3_15
VCCSUS3_3_16
VCCSUS3_3_17
VCCSUS3_3_18
VCCSUS3_3_19
VCC
VCCLAN1_5/VCCSUS1_5_1
VCCLAN1_5/VCCSUS1_5_2
AA19
AA20
AA21
L11
L12
L14
L16
L17
M11
M17
P11
P17
T11
T17
U11
U12
U14
U16
U17
F9
A6
B1
E4
H1
H7
J7
L4
L7
M7
P1
AA12
AA14
AA15
AA17
AC15
AD17
AG13
AG16
AG19
AA10
G19
R7
U7
G8
D24
D25
D26
D27
E20
E21
E22
E23
E24
F20
G20
P7
AB18
A8
AA18
F21
A25
A24
AB3
G10
G11
AB22
AD26
AG23
C16
D16
E16
F15
F16
G15
G16
VCC1.5
V5REF
V5REF_SUS
VCCRTC
VCC1.5
EC17
C689
0.1U
C703
0.1U
C697
0.1U
C661
0.1U
+3_3V_PCI
+3_3V_ICH
VCCRTC
C660
0.1U
C688
0.1U
C724
0.1U
C647
0.1U
C664
1U
C711
0.1U
C692
0.1U
C666
0.1U
C682
1U
C725
0.1U
C707
0.1U
C687
0.1U
C694
0.1U
C662
0.1U
VCC1.5
VCC1.5
C654
0.1U
C723
1U
VCC3
C726
0.1U
C691
0.1U
C663
0.1U
C
C655
C693
0.01U
VCC3
EC14
RVCC1.5
C696
10U
10U
AA11
AA13
AA16
AB10
AB19
AC10
AC12
AC22
AC23
AC24
AC26
AD10
AD15
AD18
AD24
AE10
AE11
AE12
AE21
AE25
EC15
RVCC1.5
AG12
AG14
AG17
AG20
VCC1.5
VCC2.5
AG22
EC16
VCC1.5
C708
0.01U
GMCH_VTT
C646
0.1U
AA4
AB1
AB2
AB7
AB9
AC3
AC6
AD1
AD2
AD6
AE2
AE6
AE7
AF1
AF10
AF12
AF26
AF3
AF7
AG1
AG3
AG7
C14
C18
C20
C22
D10
D13
D14
D18
D20
D22
D
U34D
A1
VSS001
A12
VSS002
A15
VSS003
A19
VSS004
A21
VSS005
A23
VSS006
A26
VSS007
A4
VSS008
A7
VSS009
A9
VSS010
VSS011
VSS012
VSS013
VSS014
VSS015
VSS016
VSS017
VSS018
VSS019
VSS020
VSS021
VSS022
VSS023
VSS024
VSS025
VSS026
VSS027
VSS028
VSS029
VSS030
VSS031
VSS032
VSS033
VSS034
VSS035
VSS036
VSS037
VSS038
VSS039
VSS040
VSS041
VSS042
VSS043
VSS044
VSS045
VSS046
VSS047
VSS048
VSS049
VSS050
VSS051
VSS052
VSS053
VSS054
VSS055
VSS056
VSS057
B13
VSS058
B15
VSS059
B19
VSS060
B21
VSS061
B23
VSS062
B24
VSS063
B25
VSS064
VSS065
VSS066
VSS067
VSS068
C4
VSS069
D1
VSS070
VSS071
VSS072
VSS073
VSS074
VSS075
VSS076
D7
VSS077
E14
VSS078
E15
VSS079
E18
VSS080
E19
VSS081
E25
VSS082
F17
VSS083
F19
VSS084
F22
VSS085
F4
VSS086
ICH6-M
GND
VSS087
VSS088
VSS089
VSS090
VSS091
VSS092
VSS093
VSS094
VSS095
VSS096
VSS097
VSS098
VSS099
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
G1
G12
G21
G7
G9
H23
H26
H27
J23
J24
J25
J4
K1
K23
K26
K27
K7
L13
L15
L23
L24
L25
M12
M13
M14
M15
M16
M23
M26
M27
M4
N1
N11
N12
N13
N14
N15
N16
N17
N7
P12
P13
P14
P15
P16
P22
R11
R12
R13
R14
R15
R16
R17
R23
R24
R25
R4
T1
T12
T13
T14
T15
T16
T23
T26
T27
T7
U13
U15
U23
U24
U25
V23
V26
V27
V4
W1
W23
W24
W25
W7
Y23
Y26
Y27
Y6
E27
E
13
QUANTA
Title
Size Document Number Re v
Custom
C
D
Date: Sheet
COMPUTER
System Block Diagram
AW3
E
13
1A
41Tuesday, March 15, 2005
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