Quanta AK3 Schematic
5
4
3
2
1
01
AK3
BlOCK DIAGRAM
D D
Dual channel Memory DDRII 667/800
DDR II CHANNEL A
SO-DIMM
STANDARD
SO-DIMM
STANDARD
C C
PRIMARY HDD
ODD
MINI CARD
WLAN
MINI CARD
1-SegTV
USB
B B
4x connector
FELICA
Logitec Camera /MIC
Bluetooth
A A
13,14
13,14
DDR II CHANNEL B
SATA<PORT0>
27
PATA 66/100MHz
27
PCI-E<PORT3>
USBX1<PORT7>
26
PCI-E<PORT4>
USBX1<PORT8>
26
USBX4<PORT0-3>
29
USBX1<PORT4>
29
USBX1<PORT5>
29
USBX1<PORT6>
33
USB2.0
CPU
Merom
u-FCPGA 478PIN
FSB 800 MHZ
NB
GM965
1201-pin FCBGA
6,7,8,9,10,11
DMI LINK
SB
ICH-8M
16,17,18,19
LPC
4,5
CPU Thermal Sensor
FAN Control
PCI-E<PORT6>
PCI-E<PORT1>
USBX1<PORT9>
PCI 2.3
Azalia
Azalia
12
28
CRT DDC2B
Broadcom
BCM5787
10/100/1000BASE-T
CARDBUS
RICOH R5C804
CARDBUS
RICOH R5C837
HD_ AUDIO
ALC262
HD_MDC
TPM1.2
DC/DC &
DC In
Charge
Battery
CRT
2x LVDS
S- Vedio
1x D-SUB 15-Pin
LCD
15" W 2-CH LVDS
S-Vedio
RJ-45
31 32
1x 8P8C
Express Card
PC Card
20
Media card reader
22
type-I/II
MIC-In Jack
24
25
29
AMP
AMP
MAX4411
MAX9710
WIRE
Headphone Jack
Int. Speaker
RJ-11 X1
1x 6P2C
15
15
29
33
21
23
25
25
24
Key Board
Touch Pad
1x D-SUB 9-PinSerial
5
28
28
30
EC
Quanta Computer Inc.
Quanta Computer Inc.
ITE IT8513E
34 34
4
SPI
Size Document Number Rev
Size Document Number Rev
FLASH
3
BIOS
2
Size Document Number Rev
BLACK DRAGRAM
BLACK DRAGRAM
BLACK DRAGRAM
Date: Sheet
Date: Sheet
Date: Sheet of
Quanta Computer Inc.
PROJECT : AK3
PROJECT : AK3
PROJECT : AK3
142Tuesday, October 30, 2007
142Tuesday, October 30, 2007
142Tuesday, October 30, 2007
of
1
of
2A
2A
2A
5
4
3
2
1
1. PAGE LIST
01 --BLOCK DIAGRAM
02 --PAGE LIST
03 --CLOCK G_ICS363
04 --Merom (HOST BUS)
05 --Merom (POWER/NC)
D D
06 --Crestline_A (HOST)
07 --Crestline_B (VGA,DMI)
08 --Crestline_C (DDR2)
09 --Crestline_D (VCC,NCTF)
10 --Crestline_E (POWER)
11 --Crestline_F (VSS)
12 --Thermal Sensor
13 --DDR2 SO-DIMM(200P)
14 --DDR2 RES. ARRAY
15 --CRT & LCD
16 --ICH8-M HOST (1 of 4)
17 --ICH8-M PCI E (2 of 4)
18 --ICH8-M GPIO (3 of 4)
19 --ICH8-M Power (4 of 4)
20 --R5C804_PCI
C C
21 --R5C804_CARDBUS
22 --R5C837_ PCI
23 --R5C837_4 IN 1
24 --HD_ALC262
25 --AUDIO JACK/MODEM/BUZZER
26 --MINI PCI-E
27 --SATA(HDD)/PATA(ODD)
28 --INT.KB/TOUCH-PAD/FAN
29 --USB/TPM/FELICA/CAMERA
30 --SERIAL PORT
31 --LAN (BCM5787M/5784M)
32 --LAN (TR & CONNECTOR)
33 --NEW CARD/BLUETOOTH
34 --EC_ITE8513
35 --CPU CORE (MAX8770)
37 --VCCP/INV5VPCU
38 --1.8VSUS/DDR/VCC1.5/VCC1.25
39 --Battery charger
40 --Battery connector
41 --DISCHARGE
42 --Change list
4.Power rails
Voltage Rails
Voltage Rails
CPU_CORE
VCCP
SMDDR_VTERM
RVCC3
+3.3ALW 3VSTD_D
VCC1.25 MAINON
VCC1.5
VCC3
VCC5
1.8VSUS
3VSUS
5VSUS
3VPCU
5VPCU
15VPCU
VR_ON
MAINON
MAINON
RVCCD
MAINON
MAIND_2
MAIND_2
SUSON
SUSD
SUSD
LDO5
LDO5
5VPCU
ON S0~S2Ctl Signal
ON S3 ON S4 ON S5
ON
ON
ON
ON ON
ON
ON ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
5.POWER ON SEQUENCE
02
Power On Sequence
ACIN
5VPCU/3VPCU
2. PCI Description :
CHIPPCIINT
B B
IDSEL CHIP
AD17
AD20
BUSMASTER
REQ
REQ0 / GNT0
REQ1 / GNT1
CardBus( R5C804)
Media card(R5C837)
CHIP
CardBus( R5C804)
Media card(R5C837)
INTA#
CardBus( R5C804)
INTA#
Media card(R5C837)
3. PCI_E Description :
A A
Port 1
Port 3 Mini-PCIE (Wireless card)
Port 4 Mini-PCIE (1-seg TV)
Port 6 LAN(BCM5787M)
CHIP
PCI-EXPRESS Card
5
4
NBSWON#
DNBSWON#
STBON
RSMRST#
SUSB#,SUSC#
SUSON
MAINON
VSUS,VCC
VCCP
HWPG
VR_ON
VCORE_CPU
CK_PWG
PWROK ICH_PWROK
PLTRST#\PCIRST#
H_PWRGD
H_CPURST#
3
99ms < t 214
2ms
2
To ICH8
To ICH8
From ICH8
From 8512
From 8512
From 8734_PG
From 8512
To clock generator
To GMCH/other
PCI device
From ICH8 to CPU
Form GMCH to CPU
QUANTA
QUANTA
QUANTA
COMPUTER
COMPUTER
C
C
C
Tuesday, October 30, 2007
Tuesday, October 30, 2007
Tuesday, October 30, 2007
COMPUTER
PAGE LIST
PAGE LIST
PAGE LIST
AK23 Main Board
AK23 Main Board
AK23 Main Board
1
242
242
242
of
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
2A
2A
2A
1
VCC3
L14
L14
1 2
BLM21PG600SN1D(60,3A)
BLM21PG600SN1D(60,3A)
A A
VCC3 VDDCPU
L12 BLM21PG600SN1D(60,3A)L12 BLM21PG600SN1D(60,3A)
1 2
VCC3 VDDA
L13
L13
1 2
BLM21PG600SN1D(60,3A)
BLM21PG600SN1D(60,3A)
B B
CPU_MCH_BSEL04
C C
VCCP
CPU_MCH_BSEL14
VCCP
CPU_MCH_BSEL24
VCCP
12
12
C111
C111
C395
C395
0.1U
0.1U
10U
10U
12
12
C95
C95
C96
C96
10U
10U
0.1U
0.1U
12
12
C110
C110
C109
C109
0.1U
0.1U
10U
10U
FSB FREQUNCY SELECTION TABLE
BSEL2 BSEL1 BSEL0 CPU
0
D D
0
0
0
1
1
1
1
FSAFSBFSC
0
0
0
1
0
1
1
1
0
0
0
1
1
0
1
1
1
SRC
266.66
100
133.33
100
200.00
100
100
166.66
100
333.33
100
100.00
100
400.00
200.00 100 33.33
2
12
C112
C112
0.1U
0.1U
VDDCPU
VDDA
R73 0R73 0
R75 *56R75 *56
R71 1K_4R71 1K_4
R89 0R89 0
R83 1K_4R83 1K_4
R85 *0R85 *0
R84 0R84 0 R359 *10KR359 *10K
R69 1K_4R69 1K_4
R76 *0R76 *0
12
C391
C391
0.1U
0.1U
12
C384
C384
0.1U
0.1U
PM_STPCPU#18
PM_STPPCI#18
CGCLK_SMB13,18,26,33
CGDAT_SMB13,18,26,33
CLKUSB_4818
14M_ICH18
CK_PWG18 PCIE_REQ3# 33
DREFCLK7
DREFCLK#7
(96MHz)
CLK_BSEL0
R74 1K_4R74 1K_4
CLK_BSEL1
R88 1K_4R88 1K_4 C91 10PC91 10P
CLK_BSEL2
R86 1K_4R86 1K_4
12
VCC3
VCC3
CLK_3.3V
C418
C418
0.1U
0.1U
3
12
12
C427
C427
C430
C430
0.1U
0.1U
0.1U
0.1U
VCC3
R357
R357
R361
R361
*10K
*10K
*10K
*10K
CLK_BSEL0
CLK_BSEL1
CLK_BSEL2
R374 1K/FR374 1K/F
R375 220/FR375 220/F
RP7 4P2R-S-33RP7 4P2R-S-33
1
3
R378 10KR378 10K
MCH_BSEL0 7
MCH_BSEL1 7
MCH_BSEL2 7
CLK_3.3V
12
C396
C396
0.1U
0.1U
4
R367 33R367 33
R72 2.2KR72 2.2K
R68 2.2KR68 2.2K
R63 33R63 33
2
4
PP-1009-1
C389 30PC389 30P
C393 30PC393 30P
CLK_3.3V
VDDCPU
VDDA
R_DREFCLK
R_DREFCLK#
PWRSAVE#
5
CLK_XIN
21
Y5
Y5
14.318MHZ/20P
14.318MHZ/20P
CLK_XOUT
U25
CLK_XIN
CLK_XOUT
VCC3
U25
58
X1
57
X2
62
CPU_STOP#
63
PCI/PCIEX_STOP#
54
SCLK
55
SDATA
12
FSA/USB_48MHZ
16
FSB/TEST_MODE
61
FSC/REF1/TEST_SEL
60
REF0
1
VDDPCI
7
VDDPC1
11
VDD48
56
VDDREF
21
VDDPCIEX
28
VDDPCIEX
42
VDDPCIEX
50
VDDCPU
47
VREF
45
VDDA
10
VTTPWR_GD/PD#
14
PCIET_L9/DOTT_96MHZ
15
PCIEC_L9/DOTC_96MHZL
34
*PWRSAVE#
37
GND
2
GND
6
GND
13
GND
29
GND
53
GND
59
GND
46
GNDA
ICS9PR363DGLF
ICS9PR363DGLF
LATCH SELECTION INPUT-PIN
R65 *10KR65 *10K
R362 10KR362 10K
R351 10KR351 10K
R57 *10KR57 *10K
RPCLK_R5C804
RPCLK_ICH
REQ_SEL
R_PCI_CLK_8513
CPUT_L0
CPUC_L0
CPUT_L1F
CPUC_L1F
CPUITPT_L2/PCIET_L8
CPUITPC_L2/PCIEC_L8
27FIX/LCD_SSCGT/PCIET_L0
27SS/LCD_SSCGC/PCIEC_L0
SATACLKT_L
SATACLKC_L
PCIET_L1
PCIEC_L1
PCIET_L2
PCIEC_L2
PCIET_L3
PCIEC_L3
PCIET_L4
PCIEC_L4
PCIET_L5
PCIEC_L5
PCIET_L6
PCIEC_L6
PEREQ1#/PCIET_L7
PEREQ2#/PCIEC_L7
*PEREQ3#
*PEREQ4#
**REQ_SEL/PCICLK0
PCICLK1
*SELPCIEX0_LCD#/PCICLK3
*SELLCD_27#/PCICLK_F5
* Internal pull up to VDD
**Internal pull down to GND
PCICLK2
ITP_EN/PCICLK_F4
R62 10KR62 10K
R350 *10KR350 *10K
R55 10KR55 10K
LATCH SELECTION TABLE
PCI
REF
USB48DOT
33.33
14.318
33.33 14.318 48 96
33.33 14.318 48 96
33.33 14.318 48 96
33.33 14.318 48 96
33.33 14.318 48 96
33.33 14.318 48 96
14.318 48 96
2
96
Spread
%
0.5 Down
0.5 Down
0.5 Down
0.5 Down
0.5 Down
0.5 Down
0.5 Down
0.5 Down
PIN 5 PIN 9 Pin 14/15
LO
HI
HI
LO
HI
DOT(96MHZ)
PCIEX9
DOT(96MHZ)
PCIEX9
LO
PIN 64 Pin40/41
LO PCIEX7
HI
PEREQ#
3
4
5
Pin 17/18
27M
LCD
PCIEX0
PCIEX0
PIN 8 Pin 43/44
LO
HI
SRC
CPU_ITP
6
7
Byte 4 to program CPU CLK Free Run
RHCLK_MCH
52
RHCLK_MCH#
51
RHCLK_CPU
49
RHCLK_CPU#
48
44
43
R_DREFSSCLK
17
R_DREFSSCLK#
18
RSRC_SATA
26
RSRC_SATA#
27
RSRC_TV
19
RSRC_TV#
20
RSRC_XCARD
22
RSRC_XCARD#
23
RSRC_ICH
24
RSRC_ICH#
25
RSRC_LAN
30
RSRC_LAN#
31
RSRC_MCH
36
RSRC_MCH#
35
RSRC_WLAN
39
RSRC_WLAN#
38
R_PCIE_REQ1#
41
R_PCIE_REQ2#
40
R_PCIE_REQ3#
32
R_PCIE_REQ4#
33
REQ_SEL PCLK_DEBUG
64
R_PCLK_R5C837
3
R_PCLK_TPM PCLK_TPM
4
RPCLK_R5C804
5
R_PCI_CLK_8513 PCI_CLK_8513
8
RPCLK_ICH PCLK_ICH
9
PIN 5
PIN 9
PIN 64
PIN 8
RP8 4P2R-S-33RP8 4P2R-S-33
4
2
RP10 4P2R-S-33RP10 4P2R-S-33
4
2
RP9 4P2R-S-33RP9 4P2R-S-33
2
4
RP16 4P2R-S-33RP16 4P2R-S-33
2
4
RP11 4P2R-S-33RP11 4P2R-S-33
2
4
RP12 4P2R-S-33RP12 4P2R-S-33
2
4
RP14 4P2R-S-33RP14 4P2R-S-33
2
4
RP18 4P2R-S-33RP18 4P2R-S-33
2
4
RP17 4P2R-S-33RP17 4P2R-S-33
4
2
RP15 4P2R-S-33RP15 4P2R-S-33
4
2
R376 475/FR376 475/F
R377 475/FR377 475/F
R379 475/FR379 475/F
R380 475/FR380 475/F
R352 22R352 22
R355 33R355 33
R358 33R358 33
R64 22R64 22
R59 22R59 22
R365 22R365 22
EMI
14M_ICH
CLKUSB_48
PCLK_DEBUG
PCLK_R5C837
PCLK_TPM
PCLK_R5C804
PCLK_ICH
PCI_CLK_8513
CLKREQ# CONTROL TABLE
PCIE_REQ1#
PCIE_REQ2#
PCIE_REQ4# PCIE_L5
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
CLOCK G_ICS363
CLOCK G_ICS363
CLOCK G_ICS363
Date: Sheet of
Date: Sheet of
6
Date: Sheet
7
3
1
3
1
1
3
1
3
1
3
1
3
1
3
1
3
3
1
3
1
PCLK_R5C837
PCLK_R5C804
C399 10PC399 10P
C382 10PC382 10P
C385 10PC385 10P
C388 10PC388 10P
C89 10PC89 10P
C394 10PC394 10P
C84 10PC84 10P
PCIE_L6
PCIE_L1
PCIE_L2PCIE_REQ3#
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
DREFSSCLK 7
DREFSSCLK# 7
CLK_PCIE_SATA 16
CLK_PCIE_SATA# 16
CLK_PCIE_MINI_TV 26
CLK_PCIE_MINI_TV# 26
CLK_PCIE_NEW_C 33
CLK_PCIE_NEW_C# 33
CLK_PCIE_ICH 17
CLK_PCIE_ICH# 17
CLK_PCIE_LAN 31
CLK_PCIE_LAN# 31
CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7
CLK_PCIE_MINI_WLAN 26
CLK_PCIE_MINI_WLAN# 26
PCIE_REQ1# 26
PCIE_REQ2# 26
PCIE_REQ4# 7
PCLK_DEBUG 26
PCLK_R5C837 22
PCLK_TPM 29
PCLK_R5C804 20
PCI_CLK_8513 34
PCLK_ICH 17
PCIE_L0
PCIE_L4
PCIE_L8
PCIE_L3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : AK3
PROJECT : AK3
PROJECT : AK3
8
PCIE_L7
of
342Tuesday, October 30, 2007
342Tuesday, October 30, 2007
342Tuesday, October 30, 2007
8
03
FREE RUN
WLAN
TV
NEWCARD
3GPLL
FREE RUN
FREE RUN
2A
2A
2A
1
H_A#[3..35]6
A A
H_ADSTB#06
H_REQ#06
H_REQ#16
H_REQ#26
H_REQ#36
H_REQ#46
H_A#[3..35]6
B B
H_ADSTB#16
H_A20M#16
H_FERR#16
H_IGNNE#16
H_STPCLK#16
H_INTR16
H_NMI16
H_SMI#16
C C
D D
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
ITP_TMS
ITP_TDI
ITP_TDO
ITP_BPM#5
ITP_TCK
ITP_TRST#
Layout Note:
Place these
resistor close
to CPU
2
U3A
U3A
J4
A[3]#
L5
A[4]#
L4
A[5]#
K5
A[6]#
M3
A[7]#
N2
A[8]#
J1
A[9]#
N3
A[10]#
P5
A[11]#
P2
A[12]#
L2
A[13]#
P4
A[14]#
P1
A[15]#
R1
A[16]#
M1
ADSTB[0]#
K3
REQ[0]#
H2
REQ[1]#
K2
REQ[2]#
J3
REQ[3]#
L1
REQ[4]#
Y2
A[17]#
U5
A[18]#
R3
A[19]#
W6
A[20]#
U4
A[21]#
Y5
A[22]#
U1
A[23]#
R4
A[24]#
T5
A[25]#
T3
A[26]#
W2
A[27]#
W5
A[28]#
Y4
A[29]#
U2
A[30]#
V4
A[31]#
W3
A[32]#
AA4
A[33]#
AB2
A[34]#
AA3
A[35]#
V1
ADSTB[1]#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD[01]
N5
RSVD[02]
T2
RSVD[03]
V3
RSVD[04]
B2
RSVD[05]
C3
RSVD[06]
D2
RSVD[07]
D22
RSVD[08]
D3
RSVD[09]
F6
RSVD[10]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
R232 39/F_4R232 39/F_4
1 2
R14 150_4R14 150_4
1 2
R233 *54.9/F_4R233 *54.9/F_4
1 2
R13 51/F_4R13 51/F_4
1 2
R237 27_4R237 27_4
1 2
R242 649_4R242 649_4
1 2
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
ADDR GROUP 0
ADDR GROUP 0
BR0#
IERR#
LOCK#
CONTROLXDP/ITP SIGNALS
CONTROLXDP/ITP SIGNALS
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HITM#
BPM[0]#
ADDR GROUP 1
ADDR GROUP 1
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TRST#
DBR#
THERMAL
THERMAL
PROCHOT#
THERMDA
THERMDC
ICH
ICH
THERMTRIP#
H CLK
H CLK
BCLK[0]
BCLK[1]
RESERVED
RESERVED
INIT#
HIT#
TCK
TDO
TMS
3
H1
E2
G5
H5
F21
E1
F1
H_IERR#
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
ITP_BPM#0
AD4
ITP_BPM#1
AD3
ITP_BPM#2
AD1
ITP_BPM#3
AC4
ITP_BPM#4
AC2
ITP_BPM#5
AC1
ITP_TCK
AC5
ITP_TDI
AA6
TDI
AB3
AB5
AB6
C20
D21
A24
B25
C7
A22
A21
VCCP
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#
R303 56_4R303 56_4
H_ADS# 6
H_BNR# 6
H_BPRI# 6
H_DEFER# 6
H_DRDY# 6
H_DBSY# 6
H_BR0# 6
R295 56/F_4R295 56/F_4
1 2
H_INIT# 16
H_LOCK# 6
H_RS#0 6
H_RS#1 6
H_RS#2 6
H_TRDY# 6
H_HIT# 6
H_HITM# 6
R310 0_4R310 0_4
12
H_PROCHOT# 35
H_THERMDA 12
H_THERMDC 12
H_THERMTRIP# 7,16
CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3
VCCP
VCCP
T49PAD T49PAD
T45PAD T45PAD
T48PAD T48PAD
T44PAD T44PAD
T47PAD T47PAD
4
VCCP
12
R22
R22
*51/F
*51/F
SYS_RST# 18
5
H_D#[0..63]6
H_RESET# 6
Layout Note:
Place voltage
divider within
0.5" of GTLREF
pin
VCCP
R40
R40
1K/F
1K/F
1 2
R39
R39
2K/F
2K/F
1 2
T6T6
T46T46
T7T7
For the purpose of testability, route these signals
through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.
H_DSTBN#06
H_DSTBP#06
H_DINV#06
H_D#[0..63]6
H_DSTBN#16
H_DSTBP#16
H_DINV#16
CPU_MCH_BSEL03
CPU_MCH_BSEL13
CPU_MCH_BSEL23
BCLK
133
166
200
1 2
1 2
12
BSEL2 BSEL1 BSEL0
0
FSB
533 0 0
667
800
R314 *1K/F_4R314 *1K/F_4
R43 *1K/F_4R43 *1K/F_4
C60 *0.1U/10V_4C60 *0.1U/10V_4
Place C close to the
CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other noisy signal.
CPU_TEST3
CPU_TEST5
CPU_TEST6
V_CPU_GTLREF
CPU_TEST1
CPU_TEST2
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST6
1
1
CPU_TEST1
CPU_TEST2
CPU_TEST4
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
6
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
AD26
C23
D25
C24
AF26
AF1
A26
B22
B23
C21
1
1
00
U3B
U3B
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
DATA GRP 0 DATA GRP 1
DATA GRP 0 DATA GRP 1
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
GTLREF
MISC
MISC
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
BSEL[0]
BSEL[1]
BSEL[2]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
7
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
DATA GRP 2DATA GRP 3
DATA GRP 2DATA GRP 3
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
COMP0
COMP1
COMP2
COMP3
Comp0,2 connect with Zo=27.4ohm,Comp1,3
connect with Zo=55ohm, make those traces
length shorter than 0.5".Trace should be
at least 25 mils away from any other
toggling signal.
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
1 2
R240
R240
54.9/F_4
54.9/F_4
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0
COMP1
COMP2
COMP3
1 2
R239
R239
27.4/F_4
27.4/F_4
H_D#32
Y22
H_D#[0..63] 6
H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#2 6
H_D#[0..63] 6
H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6
Note:
H_DPRTSTP need to daisy chain
from ICH8 to IMVP6 to CPU.
H_DPRSTP# 7,16,35
H_DPSLP# 16
H_DPWR# 6
H_PWRGOOD 16
H_CPUSLP# 6
H_PSI# 35
R41
R41
54.9/F_4
54.9/F_4
1 2
1 2
R42
R42
27.4/F_4
27.4/F_4
8
04
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : AK3
PROJECT : AK3
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Merom(HOST BUS)
Merom(HOST BUS)
Merom(HOST BUS)
Date: Sheet of
Date: Sheet of
1
2
3
4
5
6
Date: Sheet
7
PROJECT : AK3
2A
2A
2A
of
442Tuesday, October 30, 2007
442Tuesday, October 30, 2007
442Tuesday, October 30, 2007
8
1
2
3
4
5
6
7
8
All use 10U 4V(+-20%,X6S,0805)Pb-Free.
CPU_CORE
C286
C286
C330
C330
12
10U/4V/X6S_8
10U/4V/X6S_8
12
10U/4V/X6S_8
10U/4V/X6S_8
12
10U/4V/X6S_8
A A
10U/4V/X6S_8
CPU_CORE
12
10U/4V/X6S_8
10U/4V/X6S_8
C287
C287
C320
C320
12
C281
C281
10U/4V/X6S_8
10U/4V/X6S_8
12
C323
C323
10U/4V/X6S_8
10U/4V/X6S_8
12
C288
C288
10U/4V/X6S_8
10U/4V/X6S_8
12
C292
C292
10U/4V/X6S_8
10U/4V/X6S_8
12
C297
C297
10U/4V/X6S_8
10U/4V/X6S_8
12
C328
C328
10U/4V/X6S_8
10U/4V/X6S_8
CPU_CORE CPU_CORE
8 inside cavity, north side, secondary layer.
CPU_CORE
C293
C293
C308
C308
12
10U/4V/X6S_8
10U/4V/X6S_8
12
10U/4V/X6S_8
10U/4V/X6S_8
12
10U/4V/X6S_8
10U/4V/X6S_8
B B
CPU_CORE
12
10U/4V/X6S_8
10U/4V/X6S_8
C289
C289
C301
C301
12
C309
C309
10U/4V/X6S_8
10U/4V/X6S_8
12
C282
C282
10U/4V/X6S_8
10U/4V/X6S_8
12
C302
C302
10U/4V/X6S_8
10U/4V/X6S_8
12
C329
C329
10U/4V/X6S_8
10U/4V/X6S_8
12
C298
C298
10U/4V/X6S_8
10U/4V/X6S_8
12
C319
C319
10U/4V/X6S_8
10U/4V/X6S_8
8 inside cavity, south side, secondary layer.
CPU_CORE
12
C26
C26
10U/4V/X6S_8
10U/4V/X6S_8
12
C28
C28
10U/4V/X6S_8
10U/4V/X6S_8
12
10U/4V/X6S_8
10U/4V/X6S_8
C30
C30
12
C40
C40
10U/4V/X6S_8
10U/4V/X6S_8
12
C33
C33
10U/4V/X6S_8
10U/4V/X6S_8
12
C37
C37
10U/4V/X6S_8
10U/4V/X6S_8
6 inside cavity, north side, primary layer.
CPU_CORE
C C
12
10U/4V/X6S_8
10U/4V/X6S_8
C25
C25
12
10U/4V/X6S_8
10U/4V/X6S_8
C27
C27
12
10U/4V/X6S_8
10U/4V/X6S_8
C29
C29
12
10U/4V/X6S_8
10U/4V/X6S_8
C32
C32
12
C36
C36
10U/4V/X6S_8
10U/4V/X6S_8
12
C39
C39
10U/4V/X6S_8
10U/4V/X6S_8
6 inside cavity, south side, primary layer.
VCCP
12
C283
C283
0.1U/10V/X7R_4
0.1U/10V/X7R_4
12
0.1U/10V/X7R_4
0.1U/10V/X7R_4
C327
C327
12
C284
C284
0.1U/10V/X7R_4
0.1U/10V/X7R_4
12
C325
C325
0.1U/10V/X7R_4
0.1U/10V/X7R_4
12
C285
C285
0.1U/10V/X7R_4
0.1U/10V/X7R_4
12
C326
C326
0.1U/10V/X7R_4
0.1U/10V/X7R_4
>=X5R
Layout out:
D D
Place these inside socket cavity on North side secondary.
U3C
U3C
A7
VCC[001]
A9
VCC[002]
A10
VCC[003]
A12
VCC[004]
A13
VCC[005]
A15
VCC[006]
A17
VCC[007]
A18
VCC[008]
A20
VCC[009]
B7
VCC[010]
B9
VCC[011]
B10
VCC[012]
B12
VCC[013]
B14
VCC[014]
B15
VCC[015]
B17
VCC[016]
B18
VCC[017]
B20
VCC[018]
C9
VCC[019]
C10
VCC[020]
C12
VCC[021]
C13
VCC[022]
C15
VCC[023]
C17
VCC[024]
C18
VCC[025]
D9
VCC[026]
D10
VCC[027]
D12
VCC[028]
D14
VCC[029]
D15
VCC[030]
D17
VCC[031]
D18
VCC[032]
E7
VCC[033]
E9
VCC[034]
E10
VCC[035]
E12
VCC[036]
E13
VCC[037]
E15
VCC[038]
E17
VCC[039]
E18
VCC[040]
E20
VCC[041]
F7
VCC[042]
F9
VCC[043]
F10
VCC[044]
F12
VCC[045]
F14
VCC[046]
F15
VCC[047]
F17
VCC[048]
F18
VCC[049]
F20
VCC[050]
AA7
VCC[051]
AA9
VCC[052]
AA10
VCC[053]
AA12
VCC[054]
AA13
VCC[055]
AA15
VCC[056]
AA17
VCC[057]
AA18
VCC[058]
AA20
VCC[059]
AB9
VCC[060]
AC10
VCC[061]
AB10
VCC[062]
AB12
VCC[063]
AB14
VCC[064]
AB15
VCC[065]
AB17
VCC[066]
AB18
VCC[067]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
.
.
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
VCCP
Before VCORE stable : 4.5A
After VCORE stable : 2.5A
12
+
+
C2
C2
ESR = 12mohm
220U/4V
220U/4V
130mA
12
C58
CPU_VID0 35
CPU_VID1 35
CPU_VID2 35
CPU_VID3 35
CPU_VID4 35
CPU_VID5 35
CPU_VID6 35
VCCSENSE 35
VSSSENSE 35
C58
0.01U/25V/X7R_4
0.01U/25V/X7R_4
>=X5R
Layout Note:
Place C105 near PIN
B26.
VCCSENSE
VSSSENSE
Route VCCSENSE and VSSSENSE
traces at 27.4ohms and
length matched to within 25
mil. Place PU and PD within
2 inch of CPU.
CPU_CORE
12
12
VCC1.5
R267
R267
100/F
100/F
R260
R260
100/F
100/F
12
C64
C64
10U/4V/X6S_8
10U/4V/X6S_8
U3D
U3D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080]
VSS[081]P3VSS[162]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[163]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
.
.
05
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : AK3
PROJECT : AK3
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Merom(POWER/NC)
Merom(POWER/NC)
Merom(POWER/NC)
Date: Sheet of
Date: Sheet of
1
2
3
4
5
6
Date: Sheet
7
PROJECT : AK3
2A
2A
2A
of
542Tuesday, October 30, 2007
542Tuesday, October 30, 2007
542Tuesday, October 30, 2007
8
1
2
3
4
5
6
7
8
06
U4A
M10
N12
W10
AD12
AE3
AD9
AC9
AC7
AC14
AD11
AC11
AB2
AD7
AB1
AC6
AE2
AC5
AG3
AH8
AJ14
AE9
AE11
AH12
AH5
AE7
AE5
AH2
AH13
E2
G2
G7
M6
H7
H3
G4
F3
N8
H2
N9
H5
P13
K9
M2
Y8
V4
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
W3
N1
Y3
AJ9
AJ5
AJ6
AJ7
AJ2
AJ3
B3
C2
W1
W2
B6
E5
B9
A9
U4A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
CRESTLINE_1p0
CRESTLINE_1p0
H_ADSTB#_0
H_ADSTB#_1
HOST
HOST
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
H_D#[0..63]4
A A
VCCP
12
R32
R32
221/F
221/F
H_SWING
12
R33
R33
100/F
100/F
B B
VCCP
12
R308
R308
54.9/F
54.9/F
12
R31
R31
24.9/F
24.9/F
Layout Note:
H_RCOMP trace should be
10-mil wide with 20-mil
C C
spacing.
12
R302
R302
54.9/F
54.9/F
1 2
H_SCOMP
H_SCOMP#
H_RCOMP
C21
C21
0.1U/10V/X7R_4
0.1U/10V/X7R_4
VCCP
1 2
12
R30
R30
1K/F
1K/F
R29
R29
2K/F
2K/F
H_RESET#4
H_CPUSLP#4
12
C20
C20
0.1U/10V/X7R_4
0.1U/10V/X7R_4
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
H_REF
J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19
G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7
K5
L2
AD13
AE13
M7
K3
AD2
AH11
L7
K2
AC2
AJ10
M14
E13
A11
H13
B12
E12
D7
D8
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_BPRI# 4
H_DEFER# 4
CLK_MCH_BCLK 3
CLK_MCH_BCLK# 3
H_LOCK# 4
H_TRDY# 4
H_RS#0 4
H_RS#1 4
H_RS#2 4
H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BR0# 4
H_DBSY# 4
H_DPWR# 4
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_DINV#0 4
H_DINV#1 4
H_DINV#2 4
H_DINV#3 4
H_DSTBN#0 4
H_DSTBN#1 4
H_DSTBN#2 4
H_DSTBN#3 4
H_DSTBP#0 4
H_DSTBP#1 4
H_DSTBP#2 4
H_DSTBP#3 4
H_REQ#0 4
H_REQ#1 4
H_REQ#2 4
H_REQ#3 4
H_REQ#4 4
H_A#[3..35] 4
Layout Note:
Place the 0.1 uF
D D
1
2
decoupling capacitor
within 100 mils from
GMCH pins.
3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : AK3
PROJECT : AK3
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Crestline_A(HOST)
Crestline_A(HOST)
Crestline_A(HOST)
Date: Sheet of
Date: Sheet of
4
5
6
Date: Sheet
7
PROJECT : AK3
2A
2A
2A
of
642Tuesday, October 30, 2007
642Tuesday, October 30, 2007
642Tuesday, October 30, 2007
8
1
1.8VSUS
12
R342
R342
1K/F
12
12
12
12
12
12
12
PM_EXTTS#0
PM_EXTTS#1
RSTIN#_MCH
1 2
R272 0R272 0
PM_EXTTS#0
PM_EXTTS#1
PCIE_REQ4#
12
12
1K/F
R345
R345
3.01K/F
3.01K/F
R343
R343
1K/F
1K/F
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
DPRSLPVR_MCH
R329 100R329 100
SM_RCOMP_VOH
12
C375
C375
A A
0.01U/25V/X7R_4
0.01U/25V/X7R_4
SM_RCOMP_VOL
12
C378
C378
0.01U/25V/X7R_4
0.01U/25V/X7R_4
Santa Rosa Platform MOW WW15
For 4Gb DRAM support,
change Pin-BJ29 to DDR_A_MA14,
change Pin-BE24 to DDR_B_MA14.
B B
Layout Note:
Location of all MCH_CFG strap
resistors needs to be close to
minmize stub.
C C
VCC3
DELAY_VR_PWRGOOD18,35
VCC3
D D
12
C374
C374
2.2U/10V
2.2U/10V
12
C379
C379
2.2U/10V
2.2U/10V
DDR_A_MA1413,14
DDR_B_MA1413,14
MCH_BSEL03
MCH_BSEL13
MCH_BSEL23
T50T50
T4T4
R278 *4.02K/FR278 *4.02K/F
T63T63
T53T53
T54T54
R259 *4.02K/FR259 *4.02K/F
T61T61
T62T62
R280 *4.02K/FR280 *4.02K/F
R268 *4.02K/FR268 *4.02K/F
T52T52
T58T58
R291 *4.02K/FR291 *4.02K/F
T60T60
T59T59
R292 *4.02K/FR292 *4.02K/F
R279 *4.02K/FR279 *4.02K/F
PM_BMBUSY#18
H_DPRSTP#4,16,35
PM_EXTTS#013
PM_EXTTS#113
H_THERMTRIP#4,16
DPRSLPVR18,35
R287 10KR287 10K
1 2
R276 10KR276 10K
1 2
R270 10KR270 10K
1 2
PLT_RST-R#17
1
P36
P37
R35
N35
AR12
AR13
AM12
AN13
J12
AR37
AM36
AL36
AM37
D20
H10
B51
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23
BG23
BC23
BD24
BJ29
BE24
BH39
AW20
BK20
C48
D47
B44
C44
A35
B37
B36
B34
C34
P27
N27
N24
C21
C23
F23
N23
G23
J20
C20
R24
L23
J23
E23
E20
K23
M20
M24
L32
N33
L35
G41
L39
L36
J36
AW49
AV20
N20
G36
BJ51
BK51
BK50
BL50
BL49
BL3
BL2
BK1
BJ1
E1
A5
C51
B50
A50
A49
BK2
CRESTLINE_1p0
CRESTLINE_1p0
12
2
U4B
U4B
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
RSTIN#_MCH
2
DDR MUXINGCLKDMI
DDR MUXINGCLKDMI
CFGRSVD
CFGRSVD
PM
PM
GRAPHICS VIDME
GRAPHICS VIDME
NC
NC
MISC
MISC
3
SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4
SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4
SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF_0
SM_VREF_1
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
PEG_CLK
PEG_CLK#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VR_EN
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
SDVO_CTRL_CLK
SDVO_CTRL_DATA
CLK_REQ#
ICH_SYNC#
TEST_1
TEST_2
3
AV29
BB23
BA25
AV23
AW30
BA23
AW25
AW23
BE29
AY32
BD39
BG37
BG20
BK16
BG16
BE13
BH18
BJ15
BJ14
BE16
BL15
BK14
BK31
BL31
AR49
AW4
B42
C42
H48
H47
K44
K45
AN47
AJ38
AN42
AN46
AM47
AJ39
AN41
AN45
AJ46
AJ41
AM40
AM44
AJ47
AJ42
AM39
AM43
E35
A39
C38
B39
E36
AM49
AK50
AT43
AN49
AM50
H35
K36
G39
G40
A37
R32
M_CLK_DDR0 13
M_CLK_DDR1 13
M_CLK_DDR3 13
M_CLK_DDR4 13
M_CLK_DDR#0 13
M_CLK_DDR#1 13
M_CLK_DDR#3 13
M_CLK_DDR#4 13
DDR_CKE0_DIMMA 13,14
DDR_CKE1_DIMMA 13,14
DDR_CKE3_DIMMB 13,14
DDR_CKE4_DIMMB 13,14
DDR_CS0_DIMMA# 13,14
DDR_CS1_DIMMA# 13,14
DDR_CS2_DIMMB# 13,14
DDR_CS3_DIMMB# 13,14
M_ODT0 13,14
M_ODT1 13,14
M_ODT2 13,14
M_ODT3 13,14
SMRCOMPP
SMRCOMPN
SM_RCOMP_VOH
SM_RCOMP_VOL
DREFCLK 3
DREFCLK# 3
DREFSSCLK 3
DREFSSCLK# 3
CLK_MCH_3GPLL 3
CLK_MCH_3GPLL# 3
DMI_MRX_ITX_N0 17
DMI_MRX_ITX_N1 17
DMI_MRX_ITX_N2 17
DMI_MRX_ITX_N3 17
DMI_MRX_ITX_P0 17
DMI_MRX_ITX_P1 17
DMI_MRX_ITX_P2 17
DMI_MRX_ITX_P3 17
DMI_MTX_IRX_N0 17
DMI_MTX_IRX_N1 17
DMI_MTX_IRX_N2 17
DMI_MTX_IRX_N3 17
DMI_MTX_IRX_P0 17
DMI_MTX_IRX_P1 17
DMI_MTX_IRX_P2 17
DMI_MTX_IRX_P3 17
CL_CLK0 18
CL_DATA0 18
ECPWROK 15,18,34
CL_RST0# 18
PCIE_REQ4#
R296
R296
20K
20K
1 2
4
R341 20/F_4R341 20/F_4
R60 20/F_4R60 20/F_4
1 2
R328 0R328 0
R325 *1KR325 *1K
R324 *1KR324 *1K
T51 PADT51 PAD
T2 PADT2 PAD
T1 PADT1 PAD
T3 PADT3 PAD
T5 PADT5 PAD
CRT_B15
CRT_G15
CRT_R15
MCH_CLVREF
T55
T55
PAD
PAD
T64
T64
PAD
PAD
PCIE_REQ4# 3
MCH_ICH_SYNC# 18
R270R27
0
1 2
4
12
SMDDR_VREF
1.8VSUS
12
C620
C620
*22P_4
*22P_4
12
C619
C619
*22P_4
*22P_4
1.8VSUS
12
*22P_4
*22P_4
TV_COMP29
TV_LUMA29
TV_CHROMA29
VCC3
DDCCLK15
DDCDATA15
HSYNC15
VSYNC15
R263 0R263 0
R275 0R275 0
R271 0R271 0
C618
C618
C341
C341
0.1U/10V/X7R_4
0.1U/10V/X7R_4
1 2
5
BLON15
VCC3
EDIDCLK15
EDIDDATA15
DIGON15
LA_CLK#15
LA_CLK15
LB_CLK#15
LB_CLK15
LA_DATAN015
LA_DATAN115
LA_DATAN215
LA_DATAP015
LA_DATAP115
LA_DATAP215
LB_DATAN015
LB_DATAN115
LB_DATAN215
LB_DATAP015
LB_DATAP115
LB_DATAP215
R286 150/FR286 150/F
R274 150/FR274 150/F
R256 150/FR256 150/F
R288 2.2KR288 2.2K
R294 2.2KR294 2.2K
R264 150/FR264 150/F
R281 150/FR281 150/F
R277 150/FR277 150/F
R261 30.1R261 30.1
R25 1.3K/FR25 1.3K/F
R265 30.1R265 30.1
<check list>
HSYNC/VSYNC serial R
place close to NB
CRT_BLUE1
CRT_GREEN1
CRT_RED1
VCC1.25
12
R318
R318
1K/F
1K/F
12
R317
R317
392/F
392/F
5
R273 0R273 0
R262 10KR262 10K
R266 10KR266 10K
R251 0R251 0
R257 0R257 0
R290 0R290 0
R289 2.4KR289 2.4K
CRT_BLUE1
CRT_GREEN1
CRT_RED1
CRT_BLUE1
CRT_GREEN1
CRT_RED1
12
12
C615
C615
*22P_4
*22P_4
*22P_4
*22P_4
PP-1025-2
T56T56
T57T57
TV_DCONSEL_0
TV_DCONSEL_1
HSYNC11
CRTIREF
VSYNC11
12
C616
C616
*22P_4
*22P_4
6
LVDS_IBG
C617
C617
6
U4C
U4C
J40
L_BKLT_CTRL
H39
L_BKLT_EN
E39
L_CTRL_CLK
E40
L_CTRL_DATA
C37
L_DDC_CLK
D35
L_DDC_DATA
K40
L_VDD_EN
L41
LVDS_IBG
L43
LVDS_VBG
N41
LVDS_VREFH
N40
LVDS_VREFL
D46
LVDSA_CLK#
C45
LVDSA_CLK
D44
LVDSB_CLK#
E42
LVDSB_CLK
G51
LVDSA_DATA#_0
E51
LVDSA_DATA#_1
F49
LVDSA_DATA#_2
G50
LVDSA_DATA_0
E50
LVDSA_DATA_1
F48
LVDSA_DATA_2
G44
LVDSB_DATA#_0
B47
LVDSB_DATA#_1
B45
LVDSB_DATA#_2
E44
LVDSB_DATA_0
A47
LVDSB_DATA_1
A45
LVDSB_DATA_2
E27
TVA_DAC
G27
TVB_DAC
K27
TVC_DAC
F27
TVA_RTN
J27
TVB_RTN
L27
TVC_RTN
M35
TV_DCONSEL_0
P33
TV_DCONSEL_1
H32
CRT_BLUE
G32
CRT_BLUE#
K29
CRT_GREEN
J29
CRT_GREEN#
F29
CRT_RED
E29
CRT_RED#
K33
CRT_DDC_CLK
G35
CRT_DDC_DATA
F33
CRT_HSYNC
C32
CRT_TVO_IREF
E33
CRT_VSYNC
CRESTLINE_1p0
CRESTLINE_1p0
CFG5
CFG9
CFG16
CFG19
CFG20
SDVO_CRTL_DATA
7
PEG_COMPI
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
LVDS
LVDS
TV VGA
TV VGA
DMI X2 Select
PCI Express
Graphic Lane
FSB Dynamic
ODT
DMI Lane
Reversal
SDVO/PCIE
Concurrent
Operation
SDVO Present.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Crestline_B(VGA/DMI)
Crestline_B(VGA/DMI)
Crestline_B(VGA/DMI)
Date: Sheet of
Date: Sheet of
Date: Sheet
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
Low=DMIx2
High=DMIx4(Default)
Low= Reveise Lane
High=Normal operation
Low=Dynamic ODT Disable
High=Dynamic ODT Enable(default).
Low=Normal(default).
High=Lane Reversed
Low=Only SDVO or PCIEx1 is
operational (defaults)
High=SDVO and PCIEx1 are operating
simultaneously via PEG port
Low=No SDVO Device Present
(default)
High=SDVO Device Present
7
N43
M43
J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41
J50
PEG_RX_0
L50
PEG_RX_1
M47
PEG_RX_2
U44
PEG_RX_3
T49
PEG_RX_4
T41
PEG_RX_5
W45
PEG_RX_6
W41
PEG_RX_7
AB50
PEG_RX_8
Y48
PEG_RX_9
AC45
AC41
AH47
AG49
AH45
AG42
N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44
M45
PEG_TX_0
T38
PEG_TX_1
T46
PEG_TX_2
N50
PEG_TX_3
R51
PEG_TX_4
U43
PEG_TX_5
W42
PEG_TX_6
Y47
PEG_TX_7
Y39
PEG_TX_8
AC38
PEG_TX_9
AD47
AC50
AD43
AG39
AE50
AH43
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : AK3
PROJECT : AK3
PROJECT : AK3
8
R297
R297
24.9/F_4
24.9/F_4
742Tuesday, October 30, 2007
742Tuesday, October 30, 2007
742Tuesday, October 30, 2007
8
07
+VCC_PEG
12
of
2A
2A
2A
1
2
3
4
5
6
7
8
08
DDR_A_D[0..63]13
A A
B B
C C
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BF48
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BG10
AW9
AM8
AN10
AN9
AM9
AN11
BD8
AY9
BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AT9
U4D
U4D
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
CRESTLINE_1p0
CRESTLINE_1p0
SA_BS_0
SA_BS_1
SA_BS_2
SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_RAS#
SA_RCVEN#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_WE#
BK19
BF29
BL17
AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6
AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2
BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16
BE18
AY20
BA19
DDR_A_BS1
DDR_A_BS2
DDR_A_CAS#
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_RAS#
DDR_A_WE#
DDR_A_BS0 13,14
DDR_A_BS1 13,14
DDR_A_BS2 13,14
DDR_A_CAS# 13,14
DDR_A_DM[0..7] 13
DDR_A_DQS[0..7] 13
DDR_A_DQS#[0..7] 13
DDR_A_MA[0..13] 13,14
DDR_A_RAS# 13,14
T65 PADT65 PAD
DDR_A_WE# 13,14
DDR_A_BS0
BB19
DDR_B_D[0..63]13
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BK5
BK9
BK10
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2
BL9
BL5
BJ8
BJ6
BJ2
U4E
U4E
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
CRESTLINE_1p0
CRESTLINE_1p0
SB_BS_0
SB_BS_1
SB_BS_2
SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_RAS#
SB_RCVEN#
SB_WE#
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
BG18
BG36
BE17
AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2
AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3
BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
AV16
AY18
BC17
DDR_B_BS1
DDR_B_BS2
DDR_B_CAS#
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_RAS#
DDR_B_WE#
DDR_B_BS0 13,14
DDR_B_BS1 13,14
DDR_B_BS2 13,14
DDR_B_CAS# 13,14
DDR_B_DM[0..7] 13
DDR_B_DQS[0..7] 13
DDR_B_DQS#[0..7] 13
DDR_B_MA[0..13] 13,14
DDR_B_RAS# 13,14
T66 PADT66 PAD
DDR_B_WE# 13,14
DDR_B_BS0
AY17
D D
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : AK3
PROJECT : AK3
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Crestline_C(DDRII)
Crestline_C(DDRII)
Crestline_C(DDRII)
Date: Sheet of
Date: Sheet of
1
2
3
4
5
6
Date: Sheet
7
PROJECT : AK3
2A
2A
2A
of
842Tuesday, October 30, 2007
842Tuesday, October 30, 2007
842Tuesday, October 30, 2007
8
5
VCCP
1572mA
D D
1.8VSUS
C C
+VGFX_CORE_INT
B B
A A
3.3A
AT35
AT34
AH28
AC32
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32
AU32
AU33
AU35
AV33
AW33
AW35
AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33
AU30
W13
W14
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14
R30
R20
T14
Y12
U4G
U4G
VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC CORE
VCC CORE
POWER
POWER
VCC SMVCC GFX
VCC SMVCC GFX
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC GFX NCTF
VCC GFX NCTF
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC SM LF
VCC SM LF
T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31
AW45
BC39
BE39
BD17
BD4
AW8
AT6
4
Layout Note:
370 mils from edge.
GMCH 1.05V
VCCR_RX_DMI
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
VCCP
Layout Note:
308 mils from edge.
12
+
+
C23
C23
330U/2.5V
330U/2.5V
R249*0R249
*0
ES2-0919-4
Layout Note:
Inside GMCH cavity for VCC_AXG.
12
12
12
12
C322
C322
0.1U
0.1U
VCC Core
VCC_AXG
VCC_AXD
VTT
VCC_PEG
VCC_AXM
12
C356
C356
0.1U/10V
0.1U/10V
C334
C334
0.1U
0.1U
current(A)
1.573
7.7
0.2
0.85
1.2
0.54
0.25
12.313SUM
12
C355
C355
0.1U/10V
0.1U/10V
C271
C271
0.47U/10V
0.47U/10V
C3371UC337
1U
Remark
( 1.3A for
external GFX )
for integrated
Gfx
FSB VCCP
for PCIEG
for IAMT
function
DMI
12
12
C369
C369
0.22U/10V
0.22U/10V
12
+
+
C11
C11
220U/2.5V
220U/2.5V
+VGFX_CORE_INT
12
10U/10V/X5R_8
10U/10V/X5R_8
C370
C370
0.22U/10V
0.22U/10V
3
12
C311
C311
22U/4V
22U/4V
Layout Note:
Inside GMCH cavity.
12
C272
C272
C273
C273
22U/6.3V
22U/6.3V
VCCP
12
C367
C367
0.47U/10V
0.47U/10V
+3V_VCCSYNC
R247 10R247 10
1 2
12
C315
C315
0.22U/10V
0.22U/10V
R269 0R269 0
R258 0R258 0
12
0.1U/10V/X7R_4
0.1U/10V/X7R_4
12
Layout Note:
Place close to GMCH edge.
12
12
C368
C368
1U/10V
1U/10V
VCCGFPLLOW
12
C317
C317
0.22U/10V
0.22U/10V
VCCP
7.7A
Layout Note:
Inside GMCH cavity.
12
C339
C339
0.1U/10V/X7R_4
0.1U/10V/X7R_4
12
C53
C53
22U/4V
22U/4V
C363
C363
1U/10V
1U/10V
C342
C342
C354
C354
0.22U/10V
0.22U/10V
2
D33
D33
21
SDMK0340L-7-F
SDMK0340L-7-F
12
C336
C336
0.1U/10V/X7R_4
0.1U/10V/X7R_4
12
C343
C343
0.1U/10V/X7R_4
0.1U/10V/X7R_4
12
C349
C349
0.22U/10V
0.22U/10V
1.8VSUS
12
C80
C80
0.1U/10V
0.1U/10V
Layout Note:
Place C233 where LVDS
and DDR2 taps.
AB33
AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37
AJ33
AJ35
AK33
AK35
AK36
AK37
AD33
AJ36
AM35
AL33
AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36
AL24
AL26
AL28
AM26
AM28
AM29
AM31
AM32
AM33
AP29
AP31
AP32
AP33
AL29
AL31
AL32
AR31
AR32
AR33
Y32
Y33
Y35
Y36
Y37
U29
U31
U32
U33
U35
U36
V32
V33
V36
V37
T30
T34
T35
U4F
U4F
CRESTLINE_1p0
CRESTLINE_1p0
+
+
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50
VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19
12
C88
C88
330U/2.5V
330U/2.5V
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS NCTF
VSS NCTF
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VCC NCTF
VCC NCTF
POWER
POWER
VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6
VSS SCBVCC AXM
VSS SCBVCC AXM
VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7
VCC AXM NCTF
VCC AXM NCTF
VCC_SM
12
12
C78
C78
C79
C79
22U/4V
22U/4V
22U/4V
22U/4V
Layout Note:
Place on the edge.
1
09
T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28
A3
B2
C1
BL1
BL51
A51
VCCP
540mA
AT33
AT31
AK29
AK24
AK23
AJ26
AJ23
CRESTLINE_1p0
CRESTLINE_1p0
5
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : AK3
PROJECT : AK3
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Crestline_D(VCC/NCTF)
Crestline_D(VCC/NCTF)
Crestline_D(VCC/NCTF)
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet
PROJECT : AK3
1
2A
2A
2A
of
942Tuesday, October 30, 2007
942Tuesday, October 30, 2007
942Tuesday, October 30, 2007
5
L1
L1
BLM18PG181SN1
BLM18PG181SN1
R23 0_6R23 0_6
C304
C304
0.1U
0.1U
C316
C316
0.1U
0.1U
Enable
+VCCA_CRTDAC
R26*0R26
+VCCA_DAC_BG
12
VCC1.25
VCC1.25
VCC1.25
+1.5V_VCCD_TVDAC
R306*0R306
*0
1.5V
3.3V
3.3V
3.3VVCCD_CRT
GND
12
C18
C18
0.1U
0.1U
12
C19
C19
0.1U
0.1U
L31
L31
BLM11A121S
BLM11A121S
L32
L32
BLM11A121S
BLM11A121S
R327
R327
0.5/F/0603
0.5/F/0603
1 2
+VCCA_MPLL_L
12
C47
C47
22U/10V
22U/10V
735mA
VCC1.25
1.8VSUS
Disable
1.5V
GND
GND
GND
GND
70mA
*0
5mA
R28*0R28
*0
+VCCA_HPLL
50mA
12
12
C43
C43
22U/10V
22U/10V
+VCCA_MPLL
+VCCA_MPLL
12
150mA
12
C59
C59
+
+
100U/6.3V
100U/6.3V
12
35mA
12
12
C364
C364
*1U/10V
*1U/10V
R330 0_6R330 0_6
R293 0_6R293 0_6
LVDS Disable/Enable guideline
External VGA with EV@part,Internal VGA with IV@ part
Signal
VCCD_LVDS
VCCA_LVDS
VCC_TX_LVDS
VCC3
1 2
+3V_TV_DAC
D D
VCC1.25
L30
L30
10uH/100mA
10uH/100mA
12
12
+
+
L2
L2
10uH/100mA
10uH/100mA
12
12
+
12
C12
C12
0.1U
0.1U
VCC1.5
R313 100/F_6R313 100/F_6
1 2
Enable
+
12
C13
C13
0.1U
0.1U
R309 0_6R309 0_6
1 2
0.1Caps should be
placed 200 mils
with in its pins.
VCC3
12
C C
L26
L26
BLM18PG181SN1
BLM18PG181SN1
+3V_TV_DAC
12
C270
C270
10U
10U
B B
CRT/TV Disable/Enable guideline
External VGA with EV@part,Internal VGA with IV@ part
Ball
VCCSYNC 3.3V
VCCA_CRT_DAC
VCCA_DAC_BG
3.3V
3.3V
1.5V
VCCD_QDAC
A A
1.5V
100mA
C306
C306
470U/4V
470U/4V
100mA
C41
C41
470U/4V
470U/4V
Disable
GND
GND
GND
GND
GND
12
C22
C22
0.1U
0.1U
0.5mA
12
C307
C307
0.1U
0.1U
VCCD_TVDAC
VCCA_TVA_DAC
VCCA_TVB_DAC
VCCA_TVC_DAC
VSS_DAC_BG
+1.25V_VCCA_DPLLA
12
C24
C24
0.1U
0.1U
+1.25V_VCCA_DPLLB
12
C38
C38
0.1U
0.1U
R245*0R245
*0
12
12
Ball
R250 0_6R250 0_6
<FAE>
INT VGA disable
VCCSYNC connect
to GND
12
C338
C338
0.1U/10V
0.1U/10V
12
C348
C348
0.1U/10V
0.1U/10V
C362
C362
*22U/4V
*22U/4V
1 2
12
C365
C365
*1U/10V
*1U/10V
R285 *0R285 *0
R284 0R284 0
12
C350
C350
0.1U
0.1U
If SDVO Disable
LVDS Disable
4
+1.8VSUS_VCC_TX_LVDS
VCC3
400uA
12
C291
C291
0.1U/10V
0.1U/10V
C345
C345
4.7U/6.3V
4.7U/6.3V
C371
C371
22U/4V
22U/4V
120mA
60mA
60mA
250mA
+VCCA_PEG_PLL
12
C303
C303
0.1U
0.1U
150mA
C2991UC299
1U
GND
GND
GND
+3V_VCCSYNCVCC3
C274
C274
0.1U
0.1U
+1.25V_VCCA_DPLLA
+1.25V_VCCA_DPLLB
+VCCA_HPLL
+VCCA_MPLL
+VCCA_PEG_PLL
12
12
C366
C366
22U/4V
22U/4V
12
C372
C372
0.1U/10V
0.1U/10V
+1.5V_VCCD_CRT
+1.5V_VCCD_QDAC
VCCD_HPLL
90mA
+1.8V_VCCD_LVDS
C295
C295
R282*0R282
*0
*10U_8
*10U_8
If LVDS
enable
1.8V
1.8V
1.8V
C344
C344
1U/10V
1U/10V
R248*0R248
*0
10mA
90mA
VCC1.25
10mA
C15
C15
1000P
1000P
U4H
U4H
J32
A33
B33
A30
B32
B49
H49
AL2
AM2
A41
B41
K50
K49
U51
AW18
AV19
AU19
AU18
AU17
AT22
AT21
AT19
AT18
AT17
AR17
AR16
BC29
BB29
C25
B25
C27
B27
B28
A28
M32
L29
N28
AN2
U48
J41
H42
L28
L28
1 2
BLM21PG221SN1D
BLM21PG221SN1D
VCCSYNC
VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
VCCA_DAC_BG
VSSA_DAC_BG
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCA_LVDS
VSSA_LVDS
VCCA_PEG_BG
VSSA_PEG_BG
VCCA_PEG_PLL
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2
VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2
VCCD_CRT
VCCD_TVDAC
VCCD_QDAC
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS_1
VCCD_LVDS_2
CRTPLLA PEGA SMTV
CRTPLLA PEGA SMTV
POWER
POWER
A CK A LVDS
A CK A LVDS
D TV/CRTLVDS
D TV/CRTLVDS
+VCCA_PEG_PLL
12
R307
R307
1/F/0603
1/F/0603
12
C313
C313
10U/6.3V
10U/6.3V
3
AXD
AXD
VCC_AXD_NCTF
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
SM CK
SM CK
VCC_TX_LVDS
HV
HV
VCC_RXR_DMI_1
VCC_RXR_DMI_2
DMI
DMI
CRESTLINE_1p0
CRESTLINE_1p0
VTT
VTT
VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
AXF
AXF
VCC_DMI
VCC_HV_1
VCC_HV_2
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
PEG
PEG
VTTLF
VTTLF
12
C318
C318
0.1U/10V
0.1U/10V
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTTLF1
VTTLF2
VTTLF3
VCCP
U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1
AT23
AU28
AU24
AT29
AT25
AT30
AR29
B23
B21
A21
AJ50
BK24
BK23
BJ24
BJ23
A43
C40
B40
AD51
W50
W51
V49
V50
AH50
AH51
A7
F2
AH1
+VTTLF3
2 1
Place on the edge.
12
C310
C310
4.7U/10V
4.7U/10V
12
C361
C361
1U/10V
1U/10V
+3V_VCC_HV
100mA
+VCC_RXR_DMI
+VTTLF1
+VTTLF2
12
C332
C332
0.47U/10V
0.47U/10V
D34
D34
+VCC_HV_L
+3V_VCC_HV
C279
C279
0.1U/10V
0.1U/10V
12
+VCC_AXD_L
12
12
12
R24*0R24
*0
12
12
FSB=800MHZ , 850mA
12
C312
C312
C31
C31
4.7U/10V
4.7U/10V
2.2U/6.3V
2.2U/6.3V
L10 0_6L10 0_6
1 2
C77
C77
*22U/10V
*22U/10V
12
C278
C278
C277
C277
10U/6.3V
10U/6.3V
1U/10V
1U/10V
C324
C324
0.1U/10V
0.1U/10V
+VCC_SM_CK
12
C82
C82
0.1U/10V
0.1U/10V
12
C16
C16
1000P
1000P
+VCC_PEG
12
C17
C17
C14
C14
0.47U/10V
0.47U/10V
0.47U/10V
0.47U/10V
R24410_4 R24410_4
1 2
R2520_6 R2520_6
1 2
12
12
+
+
C268
C268
220U/6.3V
220U/6.3V
12
C76
C76
22U/10V
22U/10V
C314
C314
10U/6.3V
10U/6.3V
VCC3
2
12
C300
C300
0.47U/6.3V
0.47U/6.3V
515mA
495mA
100mA
12
C333
C333
10U/6.3V
10U/6.3V
VCCP
VCC1.25
VCC1.25
VCC1.25
L11
L11
1uH/300mA
1uH/300mA
12
R66
R66
1/F/0603
1/F/0603
+VCC_SM_CK_L
100mA
1310mA
12
+
+
C42
C42
220U/4V
220U/4V
260mA
12
+
+
12
+
+
C34
C34
220U/4V
220U/4V
C57
C57
220U/4V
220U/4V
12
C87
C87
1 2
10U/6.3V
10U/6.3V
L25
L25
1uH/300mA
1uH/300mA
L3
91nH/1.5AL391nH/1.5A
L4
91nH/1.5AL491nH/1.5A
200mA
12
12
12
VCCP
VCCP
1.8VSUS
1.8VSUS+1.8VSUS_VCC_TX_LVDS
1
10
110mA
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : AK3
PROJECT : AK3
SDMK0340L-7-F_NC
SDMK0340L-7-F_NC
5
4
3
2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Crestline_E(POWER)
Crestline_E(POWER)
Crestline_E(POWER)
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT : AK3
1
2A
2A
10 42Tuesday, October 30, 2007
10 42Tuesday, October 30, 2007
10 42Tuesday, October 30, 2007
2A
of
of
of
5
4
3
2
1
U4I
U4I
A13
VSS_1
A15
VSS_2
A17
VSS_3
A24
VSS_4
AA21
VSS_5
AA24
VSS_6
AA29
VSS_7
D D
C C
B B
A A
5
AB20
AB23
AB26
AB28
AB31
AC10
AC13
AC3
AC39
AC43
AC47
AD1
AD21
AD26
AD29
AD3
AD41
AD45
AD49
AD5
AD50
AD8
AE10
AE14
AE6
AF20
AF23
AF24
AF31
AG2
AG38
AG43
AG47
AG50
AH3
AH40
AH41
AH7
AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AK31
AK51
AM11
AM13
AM3
AM4
AM41
AM45
AN1
AN38
AN39
AN43
AN5
AN7
AP4
AP48
AP50
AR11
AR2
AR39
AR44
AR47
AR7
AT10
AT14
AT41
AT49
AU1
AU23
AU29
AU3
AU36
AU49
AU51
AV39
AV48
AW1
AW12
AW16
AL1
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
CRESTLINE_1p0
CRESTLINE_1p0
VSS
VSS
4
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41
3
U4J
U4J
C46
VSS_199
C50
VSS_200
C7
VSS_201
D13
VSS_202
D24
VSS_203
D3
VSS_204
D32
VSS_205
D39
VSS_206
D45
VSS_207
D49
VSS_208
E10
VSS_209
E16
VSS_210
E24
VSS_211
E28
VSS_212
E32
VSS_213
E47
VSS_214
F19
VSS_215
F36
VSS_216
F4
VSS_217
F40
VSS_218
F50
VSS_219
G1
VSS_220
G13
VSS_221
G16
VSS_222
G19
VSS_223
G24
VSS_224
G28
VSS_225
G29
VSS_226
G33
VSS_227
G42
VSS_228
G45
VSS_229
G48
VSS_230
G8
VSS_231
H24
VSS_232
H28
VSS_233
H4
VSS_234
H45
VSS_235
J11
VSS_236
J16
VSS_237
J2
VSS_238
J24
VSS_239
J28
VSS_240
J33
VSS_241
J35
VSS_242
J39
VSS_243
K12
VSS_245
K47
VSS_246
K8
VSS_247
L1
VSS_248
L17
VSS_249
L20
VSS_250
L24
VSS_251
L28
VSS_252
L3
VSS_253
L33
VSS_254
L49
VSS_255
M28
VSS_256
M42
VSS_257
M46
VSS_258
M49
VSS_259
M5
VSS_260
M50
VSS_261
M9
VSS_262
N11
VSS_263
N14
VSS_264
N17
VSS_265
N29
VSS_266
N32
VSS_267
N36
VSS_268
N39
VSS_269
N44
VSS_270
N49
VSS_271
N7
VSS_272
P19
VSS_273
P2
VSS_274
P23
VSS_275
P3
VSS_276
P50
VSS_277
R49
VSS_278
T39
VSS_279
T43
VSS_280
T47
VSS_281
U41
VSS_282
U45
VSS_283
U50
VSS_284
V2
VSS_285
V3
VSS_286
CRESTLINE_1p0
CRESTLINE_1p0
VSS
VSS
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28
AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : AK3
PROJECT : AK3
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Crestline_F(VSS)
Crestline_F(VSS)
Crestline_F(VSS)
Date: Sheet of
Date: Sheet of
2
Date: Sheet
PROJECT : AK3
1
11
11 42Tuesday, October 30, 2007
11 42Tuesday, October 30, 2007
11 42Tuesday, October 30, 2007
2A
2A
2A
of
5
Thermal Senser (CPU)
C73
C73
THERM_VCC
0.1U
0.1U
D D
2200P
2200P
4.7K_4
4.7K_4
C67
C67
R51
R51
VCC3
H_THERMDAH_THERMDA
H_THERMDCH_THERMDC
-SYS_SHDN-1
3
R50
R50
10K
10K
VCC3
R52 200R52 200
U7
U7
1
VCC
2
DXP
3
DXN
4
-OVT
G781-1
G781-1
MSOP8-4_9-65
MSOP8-4_9-65
P/N:AL000781039
3
VCC3
C74
C74
0.1U
0.1U
SMCLK
SMDATA
-ALT
GND
SYS_SHDN# 36
8
7
6
5
4
THMCLK 34
THMDAT 34
THERM_ALERT# 18,28
H_THERMDA
H_THERMDC
SMBUS SLAVE ADDRESS
G781
G781-1
98 (NB)
9A (CPU)
H_THERMDA 4
H_THERMDC 4
3
2
1
12
-SYS_SHDN-1
C C
B B
Q7
Q7
2N7002E-T1-E3
2N7002E-T1-E3
H-r315x323c394d118p2
H-r315x323c394d118p2
H-TC295D39PT
H-TC295D39PT
2
1
H4
H4
H-C315D177P2
H-C315D177P2
1
H22
H22
1
H15
H15
1
2
C68
C68
0.01U
0.01U
H5
H5
H-C315D177P2
H-C315D177P2
1
H23
H23
H-C315D118P2
H-C315D118P2
1
H9
H9
H-TC295D39PT
H-TC295D39PT
1
H14
H14
H-TC256D47PT
H-TC256D47PT
Q8
Q8
2N7002E-T1-E3
2N7002E-T1-E3
1
H11
H11
H-C315D177P2
H-C315D177P2
1
H3
H3
H-C315D118P2
H-C315D118P2
1
H18
H18
H-TC295D39PT
H-TC295D39PT
1
H16
H16
H-TC256D39PT
H-TC256D39PT
H12
H12
H-C315D177P2
H-C315D177P2
1
H21
H21
H-r315x323c394d118p2
H-r315x323c394d118p2
1
H8
H8
H-TC295D39PT
H-TC295D39PT
1
H17
H17
H-TC256D39PT
H-TC256D39PT
H13
H13
H-rt11x11rb8x8d3p2
H-rt11x11rb8x8d3p2
1
H1
H1
H-TC425X350BC315D110P2
H-TC425X350BC315D110P2
1
GND_LAN
H24
H25
H25
H-TC256D39PT
H-TC256D39PT
H24
H-TC256D39PT
H-TC256D39PT
1
1
H2
H2
H-TC315X345BC315D118P2
H-TC315X345BC315D118P2
1
H6
H6
H-TC447X527BC315D110P2
H-TC447X527BC315D110P2
1
PP-1024-2
H19
H19
H-rt323b315d118p2
H-rt323b315d118p2
1
H7
H7
H-TS1BC315D110P2
H-TS1BC315D110P2
1
H26
H26
H-C217D118P2
H-C217D118P2
1
H20
H20
H-RT315B323D118P2
H-RT315B323D118P2
1
H10
H10
h-tc118bc315d118pb
h-tc118bc315d118pb
1
VCC5
VCCP
1.8VSUS
VCC3
C621
C621
*0.01U_6
*0.01U_6
C633
C633
*0.01U_6
*0.01U_6
VCC3
VCCP
1.8VSUS
VIN
C632
C632
*0.01U_6
*0.01U_6
C634
C634
*0.01U_6
*0.01U_6
VCC3
VCC5
VCCP
VIN
C625
C625
*0.01U_6
*0.01U_6
C635
C635
*0.01U_6
*0.01U_6
VCC5
VIN
C630
C630
*0.01U_6
*0.01U_6
VCC3
VIN
C631
C631
*0.01U_6
*0.01U_6
A A
5
1
1
1
PP-1022-2
4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : AK3
PROJECT : AK3
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Thermal Sensor
Thermal Sensor
Thermal Sensor
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet
PROJECT : AK3
1
2A
2A
2A
of
12 42Tuesday, October 30, 2007
12 42Tuesday, October 30, 2007
12 42Tuesday, October 30, 2007
1
1.8VSUS
DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
VCC3
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
M_ODT1
DDR_A_D36
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D41
DDR_A_D40
DDR_A_DM5
DDR_A_D42
DDR_A_D46
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D61 DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
CGCLK_SMB
A A
B B
DDR_CKE0_DIMMA7,14
DDR_A_BS28,14
DDR_A_BS08,14
DDR_A_WE#8,14
DDR_A_CAS#8,14
DDR_CS1_DIMMA#7,14
M_ODT17,14
C C
D D
CGDAT_SMB3,18,26,33
CGCLK_SMB3,18,26,33
SMbus address A0
1
2
SMDDR_VREF
JDIM1
JDIM1
1
VREF
3
VSS47
5
DQ0
7
DQ1
9
VSS37
11
DQS#0
13
DQS0
15
VSS48
17
DQ2
19
DQ3
21
VSS38
23
DQ8
25
DQ9
27
VSS49
29
DQS#1
31
DQS1
33
VSS39
35
DQ10
37
DQ11
39
VSS50
41
VSS18
43
DQ16
45
DQ17
47
VSS1
49
DQS#2
51
DQS2
53
VSS19
55
DQ18
57
DQ19
59
VSS22
61
DQ24
63
DQ25
65
VSS23
67
DM3
69
NC4
71
VSS9
73
DQ26
75
DQ27
77
VSS4
79
CKE0
81
VDD7
83
NC1
85
A16_BA2
87
VDD9
89
A12
91
A9
93
A8
95
VDD5
97
A5
99
A3
101
A1
103
VDD10
105
A10/AP
107
BA0
109
WE#
111
VDD2
113
CAS#
115
S1#
117
VDD3
119
ODT1
121
VSS11
123
DQ32
125
DQ33
127
VSS26
129
DQS#4
131
DQS4
133
VSS2
135
DQ34
137
DQ35
139
VSS27
141
DQ40
143
DQ41
145
VSS29
147
DM5
149
VSS51
151
DQ42
153
DQ43
155
VSS40
157
DQ48
159
DQ49
161
VSS52
163
NCTEST
165
VSS30
167
DQS#6
169
DQS6
171
VSS31
173
DQ50
175
DQ51
177
VSS33
179
DQ56
181
DQ57
183
VSS3
185
DM7
187
VSS34
189
DQ58
191
DQ59
193
VSS14
195
SDA
197
SCL
199
VDD(SPD)
DDR2_SODIMM(1-1734074-1)
DDR2_SODIMM(1-1734074-1)
CLOCK 0,1
2
3
1.8VSUS
2
VSS46
4
DQ4
6
DQ5
8
VSS15
10
DM0
12
VSS5
14
DQ6
16
DQ7
18
VSS16
20
DQ12
22
DQ13
24
VSS17
26
DM1
28
VSS53
30
CK0
32
CK0#
34
VSS41
36
DQ14
38
DQ15
40
VSS54
42
VSS20
44
DQ20
46
DQ21
48
VSS6
50
NC3
52
DM2
54
VSS21
56
DQ22
58
DQ23
60
VSS24
62
DQ28
64
DQ29
66
VSS25
68
DQS#3
70
DQS3
72
VSS10
74
DQ30
76
DQ31
78
VSS8
80
CKE1
82
VDD8
84
A15
86
A14
88
VDD11
90
PC4800 DDR2 SDRAM
SO-DIMM (200P)
PC4800 DDR2 SDRAM
SO-DIMM (200P)
A11
92
A7
94
A6
96
VDD4
98
A4
100
A2
102
A0
104
VDD12
106
BA1
108
RAS#
110
S0#
112
VDD1
114
ODT0
116
A13
118
VDD6
120
NC2
122
VSS12
124
DQ36
126
DQ37
128
VSS28
130
DM4
132
VSS42
134
DQ38
136
DQ39
138
VSS55
140
DQ44
142
DQ45
144
VSS43
146
DQS#5
148
DQS5
150
VSS56
152
DQ46
154
DQ47
156
VSS44
158
DQ52
160
DQ53
162
VSS57
164
CK1
166
CK1#
168
VSS45
170
DM6
172
VSS32
174
DQ54
176
DQ55
178
VSS35
180
DQ60
182
DQ61
184
VSS7
186
DQS#7
188
DQS7
190
VSS36
192
DQ62
194
DQ63
196
VSS13
198
SA0
200
SA1
H 5.2 H 9.2
DDR_A_D4
DDR_A_D5
DDR_A_DM0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR_A_DM1
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
PM_EXTTS#0_R PM_EXTTS#1_R
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA 7,14
DDR_A_MA14 7,14 DDR_B_MA14 7,14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA# 7,14
M_ODT0
DDR_A_MA13
DDR_A_D37
DDR_A_D32
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D43
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
R392
R392
10K
10K
1 2
1 2
3
M_CLK_DDR0 7
M_CLK_DDR#0 7
R390 *0R390 *0
1 2
DDR_A_BS1 8,14
DDR_A_RAS# 8,14
M_ODT0 7,14
M_CLK_DDR1 7
M_CLK_DDR#1 7
R391
R391
10K
10K
DDR_A_DM[0..7] 8
DDR_A_D[0..63] 8
DDR_A_DQS[0..7] 8
DDR_A_DQS#[0..7] 8
DDR_A_MA[0..13] 8,14
SMDDR_VREF
12
C434
C434
0.1U_10V
0.1U_10V
PM_EXTTS#0 7
VCC3
12
C448
C448
2.2U_6.3V
2.2U_6.3V
12
C443
C443
0.1U_10V
0.1U_10V
4
12
C435
C435
2.2U_6.3V
2.2U_6.3V
DDR_CKE3_DIMMB7,14
DDR_B_BS08,14
DDR_B_WE#8,14
DDR_CS3_DIMMB#7,14
4
DDR_B_BS28,14
DDR_B_CAS#8,14
DDR_B_D5
DDR_B_D0
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D2
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D11
DDR_B_D10
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D22
DDR_B_D29
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
M_ODT37,14
M_ODT3
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42 DDR_B_D46
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
CGDAT_SMBCGDAT_SMB
CGCLK_SMB
VCC3
SMbus address A4
5
1.8VSUS 1.8VSUS
SMDDR_VREF
JDIM2
JDIM2
1
VREF
3
VSS47
5
DQ0
7
DQ1
9
VSS37
11
DQS#0
13
DQS0
15
VSS48
17
DQ2
19
DQ3
21
VSS38
23
DQ8
25
DQ9
27
VSS49
29
DQS#1
31
DQS1
33
VSS39
35
DQ10
37
DQ11
39
VSS50
41
VSS18
43
DQ16
45
DQ17
47
VSS1
49
DQS#2
51
DQS2
53
VSS19
55
DQ18
57
DQ19
59
VSS22
61
DQ24
63
DQ25
65
VSS23
67
DM3
69
NC4
71
VSS9
73
DQ26
75
DQ27
77
VSS4
79
CKE0
81
VDD7
83
NC1
85
A16_BA2
87
VDD9
89
A12
91
A9
93
A8
95
VDD5
97
A5
99
A3
101
A1
103
VDD10
105
A10/AP
107
BA0
109
WE#
111
VDD2
113
CAS#
115
S1#
117
VDD3
119
ODT1
121
VSS11
123
DQ32
125
DQ33
127
VSS26
129
DQS#4
131
DQS4
133
VSS2
135
DQ34
137
DQ35
139
VSS27
141
DQ40
143
DQ41
145
VSS29
147
DM5
149
VSS51
151
DQ42
153
DQ43
155
VSS40
157
DQ48
159
DQ49
161
VSS52
163
NCTEST
165
VSS30
167
DQS#6
169
DQS6
171
VSS31
173
DQ50
175
DQ51
177
VSS33
179
DQ56
181
DQ57
183
VSS3
185
DM7
187
VSS34
189
DQ58
191
DQ59
193
VSS14
195
SDA
197
SCL
199
VDD(SPD)
DDR2_SODIMM(2-1734073-2)
DDR2_SODIMM(2-1734073-2)
CLOCK 2,3
CKE 2,3CKE 0,1
5
6
2
VSS46
4
DQ4
6
DQ5
8
VSS15
10
DM0
12
VSS5
14
DQ6
16
DQ7
18
VSS16
20
DQ12
22
DQ13
24
VSS17
26
DM1
28
VSS53
30
CK0
32
CK0#
34
VSS41
36
DQ14
38
DQ15
40
VSS54
42
VSS20
44
DQ20
46
DQ21
48
VSS6
50
NC3
52
DM2
54
VSS21
56
DQ22
58
DQ23
60
VSS24
62
DQ28
64
DQ29
66
VSS25
68
DQS#3
70
DQS3
72
VSS10
74
DQ30
76
DQ31
78
VSS8
80
CKE1
82
VDD8
84
A15
86
A14
88
VDD11
90
A11
92
A7
94
A6
96
VDD4
98
PC4800 DDR2 SDRAM
SO-DIMM (200P)
PC4800 DDR2 SDRAM
SO-DIMM (200P)
A4
100
A2
102
A0
104
VDD12
106
BA1
108
RAS#
110
S0#
112
VDD1
114
ODT0
116
A13
118
VDD6
120
NC2
122
VSS12
124
DQ36
126
DQ37
128
VSS28
130
DM4
132
VSS42
134
DQ38
136
DQ39
138
VSS55
140
DQ44
142
DQ45
144
VSS43
146
DQS#5
148
DQS5
150
VSS56
152
DQ46
154
DQ47
156
VSS44
158
DQ52
160
DQ53
162
VSS57
164
CK1
166
CK1#
168
VSS45
170
DM6
172
VSS32
174
DQ54
176
DQ55
178
VSS35
180
DQ60
182
DQ61
184
VSS7
186
DQS#7
188
DQS7
190
VSS36
192
DQ62
194
DQ63
196
VSS13
198
SA0
200
SA1
DDR_B_D4
DDR_B_D1
DDR_B_DM0
DDR_B_D6
DDR_B_D3
DDR_B_D12
DDR_B_D13
DDR_B_DM1
DDR_B_D14
DDR_B_D15
DDR_B_D16DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D18DDR_B_D19
DDR_B_D23
DDR_B_D28
DDR_B_D24
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D31
DDR_B_D30
DDR_CKE4_DIMMB 7,14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB# 7,14
M_ODT2
DDR_B_MA13
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_DM6
DDR_B_D54
DDR_B_D55DDR_B_D51
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
R121 10KR121 10K
R122
R122
10K
10K
1 2
6
M_CLK_DDR3 7
M_CLK_DDR#3 7
DDR_B_BS1 8,14
DDR_B_RAS# 8,14
M_ODT2 7,14
M_CLK_DDR4 7
M_CLK_DDR#4 7
12
DDR_B_DM[0..7] 8
DDR_B_D[0..63] 8
DDR_B_DQS[0..7] 8
DDR_B_DQS#[0..7] 8
DDR_B_MA[0..13] 8,14
R119 *0R119 *0
1 2
VCC3
7
8
13
SMDDR_VREF
12
PM_EXTTS#1 7
1.8VSUS
12
C143
C143
2.2U_6.3V
2.2U_6.3V
1.8VSUS
12
C115
C115
2.2U_6.3V
2.2U_6.3V
1.8VSUS
12
C469
C469
0.1U_10V
0.1U_10V
1.8VSUS
12
C119
C119
0.1U_10V
0.1U_10V
VCC3
12
C480
C480
2.2U_6.3V
2.2U_6.3V
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
SO-DIMM
SO-DIMM
SO-DIMM
Date: Sheet of
Date: Sheet of
Date: Sheet
7
12
C470
C472
C472
0.1U_10V
0.1U_10V
C470
2.2U_6.3V
2.2U_6.3V
Place these Caps near So-DimmB.
12
C140
C140
2.2U_6.3V
2.2U_6.3V
C144
C144
2.2U_6.3V
2.2U_6.3V
C142
C142
2.2U_6.3V
2.2U_6.3V
12
12
Place these Caps near So-DimmA.
12
12
C117
C117
2.2U_6.3V
2.2U_6.3V
C118
C118
2.2U_6.3V
2.2U_6.3V
12
C114
C114
2.2U_6.3V
2.2U_6.3V
Place these Caps near So-DimmB.
12
C141
C141
0.1U_10V
0.1U_10V
C139
C139
0.1U_10V
0.1U_10V
C466
C466
0.1U_10V
0.1U_10V
12
12
Place these Caps near So-DimmA.
12
12
C463
C463
0.1U_10V
0.1U_10V
12
C479
C479
0.1U_10V
0.1U_10V
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT : AK3
PROJECT : AK3
PROJECT : AK3
C461
C461
0.1U_10V
0.1U_10V
12
C459
C459
0.1U_10V
0.1U_10V
of
13 42Tuesday, October 30, 2007
13 42Tuesday, October 30, 2007
13 42Tuesday, October 30, 2007
8
12
C467
C467
2.2U_6.3V
2.2U_6.3V
12
C116
C116
2.2U_6.3V
2.2U_6.3V
2A
2A
2A
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