QUANTA AJ2 Schematics
5
4
3
2
1
AJ2 BLOCK DIAGRAM
AJ2 BLOCK DIAGRAM
AJ2 BLOCK DIAGRAMAJ2 BLOCK DIAGRAM
Penryn / Cantiga / ICH9-M
Penryn / Cantiga / ICH9-M
Penryn / Cantiga / ICH9-MPenryn / Cantiga / ICH9-M
D D
CPU THERMAL
SENSOR
+3.3V
+5V
PG 5
CPU Penryn
CPU Penryn
CPU PenrynCPU Penryn
(479 Micro-FCPGA)
+1.5V
+1.05V_VCCP
+VCC_CORE
PG 3,4
(Montevina Platform)
X'TAL
14.318MHz
CPU CLK_ 200MHz
GMCH CLK_ 200MHz
DREFCLK_96MHz
PCIE MCH CLK_100MHz
CLOCK GEN
ICS9LPRS365/RTM875T-606
64pins
+3.3V
PG 2
+3V_S5/+5V_S5
CPU CORE POWER
ISL6260C+ISL6208
PG 39
PG 38
+1.5V & +1.05VCCP
PCIE MINICARD CLK_100MHz
SATA ICH CLK_100MHz
PCIE LAN CLK_100MHz
FSB
667/800 MHz
PG 18
PG 29
PG 28
PG 27
PG 27
DDRII 667 MHz
USB 2.0
SATA
SATA
NORTH BRIDGE
NORTH BRIDGE
NORTH BRIDGENORTH BRIDGE
Cantiga
1299 uFCBGA
+1.05V_VCCP
+1.8V_SUS
+1.5V
+3.3V
V_DDR_MCH_REF
X'TAL
32.768KHz
+1.5V
+1.05V_VCCP
+1.25V
+3.3V
+3.3V_ALW
+3.3V_S5
+3.3V_SUS
+3V_VCCLAN
+5V
+5V_ALW
+5V_S5
VCCRTC_(1~4)
DMI LINK
4X PCI-E
ICH9-M
ICH9-M
ICH9-MICH9-M
652 BGA
PG 14~17
LPC
X'TAL
32.768KHz
PG 6~11
SDVO
PCI
PCI-E
Azalia
MODEM CONN.
MXM
PG 22
PARADE
PS8101
+3.3V
PG 19
Azalia
Codec
CX20561-15Z
+3.3V
SWITCH
PG 22
HDMI
PG 24
DDRII-SODIMM1
DDRII-SODIMM2
+0.9V_DDR_VTT
+1.8V_SUS
+3.3V
V_DDR_MCH_REF
C C
Web Cam
USB8
+5V
PG 12,13
Bluetooth
USB9
+3.3V_SUS
USB PORT X4
USB0,1,2,5
+5V_SUS
B B
ODD(fixed)
+5V
Internal HDD
+5V
+3.3V
(MDC)
+3.3V_SUS
IT8502E
+3.3V_ALW
+3.3V
RTC_VCC
A A
PG5
Touchpad
PG 31 PG 31 PG 30 PG 24
SWITCH BOARD
+3.3V +3.3V_ALW
PG 31
5
FAN
+5V
LQFP 128PIN
Keyboard
+3.3V_ALW+5V
4
PG30
SPI FLASH
RJ11/USB X 2
B to B CONN.
USB2,USB5
+5V_SUS
WIRE
PG 25
PG 25
AMP
TPA6017A2
+5V
PG 24
JACK
HEADPHONE/SPDIF
INT. DMIC
INT. SPEAKERS
3
DMIC/
LightSensor
+3.3V
LCD Panel
VIN_BLIGHT
+3.3V
CRT port
+5V
+3.3V
HDMI port
+3.3V
+5V
LAN(1000)
Marvell 88E8057
LANVCC
LANVCC_L
+2.5V_1.8V_LAN
+1.2V_LAN
X'TAL
25MHz
PG 21
RJ45
JACK
PG 30
PG 18
PG 20
PG 19
PG 21
PCIE ICH CLK_100MHz
MINI-PCI-E Card
X2
USB4,USB7
+3.3V_SUS
+3.3V
+1.5V
PG 26
2
PCIE NEW CARD CLK_100MHz
EXPRESS CARD
(NEW CARD)
USB3
+3.3V
+1.5V
Custom BLOCK DIAGRAM
Custom BLOCK DIAGRAM
Custom BLOCK DIAGRAM
Date: Sheet of
Date: Sheet of
Date: Sheet of
(RT8204)
PCI OZ126T CLK_33MHz
DDR2
+1.8V_SUS & +0.9V
D/D POWER
+5_ALW & +3.3V_ALW
CHARGER
ISL6251A
RUN POWER SW
& DISCHARGE
PG 32
PROJECT : AJ2
PROJECT : AJ2
PROJECT : AJ2
Quanta Computer Inc.
Quanta Computer Inc.
Document Number
Document Number
Document Number
Tuesday, September 16, 2008
Tuesday, September 16, 2008
Tuesday, September 16, 2008
Quanta Computer Inc.
PG 37
PG 36
PG 35
PG 34
PG 33
CARDREADER
CONTROLLER
OZ126T
+3.3V
+1.8V
PG 23
4 IN 1
XD
SD/MMC
MS/MSPRO
+3.3V
PG 23
1 43
1 43
1 43
1
RevSize
RevSize
RevSize
1A
1A
1A
5
L51
L51
BLM21PG600SN1D
+3.3V
D D
C C
BLM21PG600SN1D
L52
L52
BLM21PG600SN1D
BLM21PG600SN1D
1 2
SATA_CLKREQ#16
MINI1CLK_REQ#26
PCLK_LPC_DEBUG26
OZ126TCLK23
PCI_CLK_851230
CLK_ICH_48M16
CPU_MCH_BSEL03,7
CPU_MCH_BSEL13,7
CPU_MCH_BSEL23,7
CLK_ICH_14M16
L23
L23
*LQG15HS5N6S02D
*LQG15HS5N6S02D
1 2
C187
C187
*15P/50V_4
*15P/50V_4
CLK_PCI_ICH15
40 mil
C478
C478
22U/6.3V/X5R_8
22U/6.3V/X5R_8
40 mil
C480
C480
22U/6.3V/X5R_8
22U/6.3V/X5R_8
SATA_CLKREQ#
PCLK_LPC_DEBUG
CLK_PCI_ICH
CLK_ICH_48M
CLK_ICH_14M
C188 27P/50V/NPO_4C188 27P/50V/NPO_4
C189 27P/50V/NPO_4C189 27P/50V/NPO_4
Modify for RAMP
use 080401
C484
C484
C471
C471
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
R151
R151
*1M/F_6
*1M/F_6
4
C207
C207
C485
C485
0.1U/16V/X7R_4
0.1U/16V/X7R_4
C473
C473
C472
C472
0.1U/16V/X7R_4
0.1U/16V/X7R_4
R182
R182
R183
R183
R185 33_4R185 33_4
R192 22_4R192 22_4
R186 33_4R186 33_4
R188 22_4R188 22_4
R195 33_4R195 33_4
R189 2.2K_4R189 2.2K_4
R163 10K_4R163 10K_4
R162 33_4R162 33_4
21
CK_VDD_MAIN1
C475
C475
0.1U/16V/X7R_4
0.1U/16V/X7R_4
CK_VDD_MAIN2
C481
C481
0.1U/16V/X7R_4
0.1U/16V/X7R_4
475/F_4
475/F_4
475/F_4
475/F_4
Y3
Y3
14.318MHZ
14.318MHZ
C474
C474
0.1U/16V/X7R_4
0.1U/16V/X7R_4
C482
C482
0.1U/16V/X7R_4
0.1U/16V/X7R_4
SATACLKREQ#_R
MINI1CLK_REQ#_RMINI1CLK_REQ#
PCI2/TME
PCI3OZ126TCLK
FCTSEL1PCI_CLK_8512
PCI_F5/ITP_EN
FSLA
FSLC
XIN
XOUT
3
U9
U9
2
VDDPCI
9
VDD48
16
VDDPLL3
61
VDDREF
39
VDDSRC
55
C190
C190
0.1U/16V/X7R_4
0.1U/16V/X7R_4
C483
C483
0.1U/16V/X7R_4
0.1U/16V/X7R_4
VDDCPU
0.1U/16V/X7R_4
0.1U/16V/X7R_4
12
VDD96_IO
20
VDDPLL3_IO
26
VDDSRC_IO
36
VDDSRC_IO
49
VDDCPU_IO
45
VDDSRC_IO
0.1U/16V/X7R_4
0.1U/16V/X7R_4
1
PCI0/CR#_A
3
PCI1/CR#_B
4
PCI2/TME
5
PCI3
6
PCI4/27_Select
7
PCI_F5/ITP_EN
10
USB_48MHz/FSLA
57
FSLB/TEST_MODE
62
REF0/FSLC/TEST_SEL
60
X1
59
X2
8
GNDPCI
11
GND48
15
GND
19
GND
52
GNDCPU
23
GNDSRC
29
GNDSRC
42
GNDSRC
58
GNDREF
ICS9LPRS365BGLFT / RTM875T-606
ICS9LPRS365BGLFT / RTM875T-606
CK505
CK505
PCI_STOP#
CPU_STOP#
CPUT2_ITP/SRCT8
CPUC2_ITP/SRCC8
SRCT11/CR#_H
SRCC11/CR#_G
SRCT7/CR#_F
SRCC7/CR#_E
CR#_C/SRC-3
SRCC3/CR#_C
SRCT2/SATAT
SRCC2/SATAC
27MHz_NonSS/SRCT1/SE1
27MHz_SS/SRCC1/SE2
SRCT0/DOTT_96
SRCC0/DOTC_96
CK_PWRGD/PD#
SCLK
SDATA
CPUT0
CPUC0
CPUT1_F
CPUC1_F
SRCC10
SRCT10
SRCT9
SRCC9
SRCT6
SRCC6
SRCT4
SRCC4
NC
48
CGCLK_SMB_M
64
CGDAT_SMB_M
63
38
37
54
53
51
50
47
46
35
34
33
32
30
31
44
SRCC7
43
41
40
27
28
24
25
21
22
DREFSSCLK_R
17
DREFSSCLK#_R
18
13
14
56
T30T30
T32T32
DREFSSCLK_R
DREFSSCLK#_R
R176 475/F_4R176 475/F_4
R180 475/F_4R180 475/F_4
R164 475/F_4R164 475/F_4
2
CLK_3GPLLREQ#CLK_3GPLLREQ#_R
MINI2CLK_REQ#MINI2CLK_REQ#_R
NEW-CARD_CLK_REQ#NEW-CARD_CLK_REQ#_R
RP24 *I@0X2RP24 *I@0X2
RP48 E@0X2RP48 E@0X2
4
3
2
1
4
3
2
1
CGCLK_SMB_M 12,13,26
CGDAT_SMB_M 12,13,26
H_STP_PCI# 16
H_STP_CPU# 16
CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
CLK_PCIE_NEW_C 32
CLK_PCIE_NEW_C# 32
CLK_MCH_3GPLL# 7
CLK_MCH_3GPLL 7
CLK_3GPLLREQ# 7
MINI2CLK_REQ# 26
CLK_PCIE_MINI2 26
CLK_PCIE_MINI2# 26
NEW-CARD_CLK_REQ# 32
CLK_PCIE_ICH 15
CLK_PCIE_ICH# 15
CLK_PCIE_MINI1 26
CLK_PCIE_MINI1# 26
CLK_PCIE_LAN 21
CLK_PCIE_LAN# 21
CLK_PCIE_SATA 14
CLK_PCIE_SATA# 14
MCH_DREFCLK 7
MCH_DREFCLK# 7
CLK_PWRGD 16
DREF_SSCLK 7
DREF_SSCLK# 7
CLK_MXM 22
CLK_MXM# 22
1
+3.3V
To NB
To MXMEC Add in For SA6 EMI
02
C205 0.1U/16V/X7R_4C205 0.1U/16V/X7R_4
C203 0.1U/16V/X7R_4C203 0.1U/16V/X7R_4
C174 0.1U/16V/X7R_4C174 0.1U/16V/X7R_4
+3.3V +3.3V
R191
R191
10K_4
10K_4
B B
PCI2/TME PCI_F5/ITP_EN
R196
R196
*10K_4
*10K_4
CPU Clock select
FSC FSB
1 330
0
0
0
0 0
A A
1 100
1
1
R194
R194
*4.7K_4
*4.7K_4
R423
R423
4.7K_4
4.7K_4
PCI2/TME
FSA CPU SRC PCI
1 100.00
10
1
1
1
0
0
0 33
0
1
0
1
1
5
133.33
166.66
200.00
266.66
333.33
400.00
200.00
100
100
100
100
100
100
100
PULL HIGH PULL LOW
SRC8/SRC8#ITP/ITP#PCI_F5/ITP_EN
Overclocking of CPU
and SRC not allowed
MINI2CLK_REQ#
CLK_3GPLLREQ#
SATA_CLKREQ#
MINI1CLK_REQ#
33
NEW-CARD_CLK_REQ#
Overclocking of CPU
and SRC allowed
R179 10K_4R179 10K_4
R178 10K_4R178 10K_4
R181 10K_4R181 10K_4
R190 10K_4R190 10K_4
R150 10K_4R150 10K_4
+3.3V
33
33
33
33
33
EMI CAP
C503 *15P/50V_4C503 *15P/50V_4
C502 15P/50V_4C502 15P/50V_4
C181 15P/50V_4C181 15P/50V_4
C488 15P/50V_4C488 15P/50V_4
C206 15P/50V_4C206 15P/50V_4
C487 15P/50V_4C487 15P/50V_4
4
OZ126TCLK
CLK_ICH_48M
CLK_ICH_14M
PCI_CLK_8512
PCLK_LPC_DEBUG
CLK_PCI_ICH
GCLK_SEL = FCTSEL1
FCTSEL1
(PIN6)
0=UMA
1 = External VGA
PCI3
R187
R187
*10K_4
*10K_4
PIN13
SRC-0 SRC-0# 27Mout-NSS 27Mout-SS
PCI3
3
PIN14 PIN17 PIN18
SRC-1#/LCDT_100DOT96
+3.3V
SRC-1/LCDT_100DOT96#
R193
R193
*10K_4
*10K_4
FCTSEL1
R424
R424
10K_4
10K_4
PULL HIGH PULL LOW
PIN37/38 is
CPU_STOP/PCI_STOP
PIN37/38 IS SRC5.
**SRC5_EN/PCI-3
(Internal Pull Low)
CGDAT_SMB_M
CGCLK_SMB_M
Document Number
Document Number
Document Number
Custom CLOCK GENERATOR
Custom CLOCK GENERATOR
Custom CLOCK GENERATOR
Date: Sheet of
Tuesday, September 16, 2008
Date: Sheet of
Tuesday, September 16, 2008
Date: Sheet of
2
Tuesday, September 16, 2008
+3.3V
R167
R167
10K_4
10K_4
2
Q20
Q20
1
2N7002E/CH2507SPT
2N7002E/CH2507SPT
R170
R170
10K_4
10K_4
1
2N7002E/CH2507SPT
2N7002E/CH2507SPT
3
ICH_SMBDATA 16,32
+3.3V
2
Q19
Q19
3
PROJECT : AJ2
PROJECT : AJ2
PROJECT : AJ2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
1
ICH_SMBCLK 16,32
2 43
2 43
2 43
RevSize
RevSize
RevSize
1A
1A
1A
1
2
3
4
5
6
7
8
H_A#[3..16]6
A A
H_ADSTB#06
H_REQ#[0..4]6
H_A#[17..35]6
B B
H_ADSTB#16
H_A20M#14
H_FERR#14
H_IGNNE#14
H_STPCLK#14
H_INTR14
H_NMI14
H_SMI#14
C C
H_A#[3..16]
H_REQ#[0..4]
H_A#[17..35]
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
Populate ITP700Flex for bringup
H_RESET#
ITP_TMS
ITP_TDI
ITP_TDO
ITP_TCK
ITP_TRST#
D D
ITP_DBRESET#
1
R17 *51/F_4R17 *51/F_4
C17
C17
*0.1U/16V/X7R_4
*0.1U/16V/X7R_4
R22 54.9/F_4R22 54.9/F_4
R21 54.9/F_4R21 54.9/F_4
R23
R23
R25 54.9/F_4R25 54.9/F_4
R24 54.9/F_4R24 54.9/F_4
C16
C16
*0.1U/16V/X7R_4
*0.1U/16V/X7R_4
R74 10K/F_4R74 10K/F_4
C71
C71
*0.1U/16V/X7R_4
*0.1U/16V/X7R_4
*54.9/F_4
*54.9/F_4
+3.3V_S5
U18A
U18A
J4
A[3]#
L5
A[4]#
L4
A[5]#
K5
A[6]#
M3
A[7]#
N2
A[8]#
J1
A[9]#
N3
A[10]#
P5
A[11]#
P2
A[12]#
L2
A[13]#
P4
A[14]#
P1
A[15]#
R1
A[16]#
M1
ADSTB[0]#
K3
REQ[0]#
H2
REQ[1]#
K2
REQ[2]#
J3
REQ[3]#
L1
REQ[4]#
Y2
A[17]#
U5
A[18]#
R3
A[19]#
W6
A[20]#
U4
A[21]#
Y5
A[22]#
U1
A[23]#
R4
A[24]#
T5
A[25]#
T3
A[26]#
W2
A[27]#
W5
A[28]#
Y4
A[29]#
U2
A[30]#
V4
A[31]#
W3
A[32]#
AA4
A[33]#
AB2
A[34]#
AA3
A[35]#
V1
ADSTB[1]#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD[01]
N5
RSVD[02]
T2
RSVD[03]
V3
RSVD[04]
B2
RSVD[05]
C3
RSVD[06]
D2
RSVD[07]
D22
RSVD[08]
D3
RSVD[09]
F6
RSVD[10]
Penryn Ball-out Rev 1a
Penryn Ball-out Rev 1a
+1.05V_VCCP
04/17 jack hsu
2
ADDR GROUP 0
ADDR GROUP 0
ADDR GROUP 1
ADDR GROUP 1
XDP/ITP SIGNALS
XDP/ITP SIGNALS
THERMAL
THERMAL
PROCHOT#
THERMDA
THERMDC
ICH
ICH
THERMTRIP#
H CLK
H CLK
RESERVED
RESERVED
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
DBR#
BCLK[0]
BCLK[1]
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
TDI
AB3
AB5
AB6
C20
D21
A24
B25
C7
A22
A21
R73 56_4R73 56_4
H_IERR#
1 2
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#
R75 47_4R75 47_4
H_PROCHOT#
H_THERMDA
H_THERMDC
H_THERMTRIP_R#
C375
H_THERMDA H_THERMDC
C375
*2200P/50V/X7R_4
*2200P/50V/X7R_4
R27 0_4R27 0_4
1 2
12
R29 0_4R29 0_4
R28 *56.2/F_4R28 *56.2/F_4
1 2
H_ADS# 6
H_BNR# 6
H_BPRI# 6
H_DEFER# 6
H_DRDY# 6
H_DBSY# 6
H_BR0# 6
+1.05V_VCCP
H_INIT# 14
H_LOCK# 6
H_RESET#H_RESET_R#
H_RS#0 6
H_RS#1 6
H_RS#2 6
H_TRDY# 6
H_HIT# 6
H_HITM# 6
T3*PAD T3*PAD
T4*PAD T4*PAD
T95*PAD T95*PAD
T1*PAD T1*PAD
T2*PAD T2*PAD
T94*PAD T94*PAD
ITP_DBRESET# 16
+1.05V_VCCP
T8*PAD T8*PAD
H_THERMDA 5
H_THERMDC 5
CLK_CPU_BCLK 2
CLK_CPU_BCLK# 2
H_PROCHOT#
+1.05V_VCCP
12
R18
R18
*51/F
*51/F
H_THERMTRIP# 7,14
+1.05V_VCCP
+1.05V_VCCP
Q38
Q38
*2N7002W-7-F
*2N7002W-7-F
R391 0_4R391 0_4
1 2
ITP700 layout guidelines
Signal Resistor Value Connect To Resistor Placement
150 ohm ± 5%
TDI
39 ohm ± 1%
TMS
500 to 680
TRST#
ohm ± 5%
27 ohm ± 1%
TCK
TDO
51 ohm ± 5% Place the pull-up near ITP
22.6 ohm ± 1%
series resistor
RESET# VCCP
and pullup 51
ohm ± 1%.
3
Place the pull-up near CPU
VCCP
Within 200ps of ITP connector
VCCP
GND
Place the pull-down near CPU
Connect to TCK pin of CPU and then
connect it to FBO pin of ITP connector
GND
in daisy chain. Place the pull-down
near TCK0 pin of ITP connector
VCCP
Connect to CPURST# pin of GMCH through
the series resistor placed within
200ps of ITP connector. Place the
pull-up after the series resistor from
ITP connector.
4
Layout Note:
Place R288
close to
CPU.
H_RESET# 6
Layout Note:
Place voltage
divider within
0.5" of GTLREF
pin
+1.05V_VCCP
1 2
1 2
+3.3V_ALW
R390
R390
*2.2K_4
*2.2K_4
2
1 2
31
R382
R382
1K/F_4
1K/F_4
R377
R377
2K/F_4
2K/F_4
CPU_MCH_BSEL02,7
CPU_MCH_BSEL12,7
CPU_MCH_BSEL22,7
Voltage Level shift
IMVP6_PROCHOT# 38
H_D#[0..63]6
H_DSTBN#06
H_DSTBP#06
H_DINV#06
H_D#[0..63]6
H_D#[0..63] H_D#[0..63]
H_D#[0..63]
H_DSTBN#16
H_DSTBP#16
H_DINV#16
Place C close to the
CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other noisy signal.
5
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_GTLREF
CPU_TEST1
CPU_TEST2
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST6
CPU_TEST7
R82 *1K/F_4R82 *1K/F_4
1 2
R72 *1K/F_4R72 *1K/F_4
1 2
C378 *0.1U/16V/X7R_4C378 *0.1U/16V/X7R_4
12
R76 *0_4R76 *0_4
1 2
R30 *0_4R30 *0_4
1 2
U18B
U18B
E22
D[0]#
F24
D[1]#
E26
D[2]#
G22
D[3]#
F23
D[4]#
G25
D[5]#
E25
D[6]#
E23
D[7]#
K24
D[8]#
G24
D[9]#
J24
D[10]#
J23
D[11]#
H22
D[12]#
F26
D[13]#
K22
D[14]#
H23
D[15]#
J26
DSTBN[0]#
H26
DSTBP[0]#
H25
DINV[0]#
N22
D[16]#
K25
D[17]#
P26
D[18]#
R23
D[19]#
L23
D[20]#
M24
D[21]#
L22
D[22]#
M23
D[23]#
P25
D[24]#
P23
D[25]#
P22
D[26]#
T24
D[27]#
R24
D[28]#
L25
D[29]#
T25
D[30]#
N25
D[31]#
L26
DSTBN[1]#
M26
DSTBP[1]#
N24
DINV[1]#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
C3
TEST7
B22
BSEL[0]
B23
BSEL[1]
C21
BSEL[2]
Penryn Ball-out Rev 1a
Penryn Ball-out Rev 1a
CPU_TEST1
CPU_TEST2
CPU_TEST4
CPU_TEST6
CPU_TEST7
6
Y22
D[32]#
AB24
D[33]#
V24
D[34]#
V26
D[35]#
V23
D[36]#
T22
D[37]#
U25
D[38]#
DATA GRP 0 DATA GRP 1
DATA GRP 0 DATA GRP 1
MISC
MISC
PWRGOOD
For the purpose of testability, route these signals
through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.
FSB
533 0 0
667
800
U23
D[39]#
Y25
D[40]#
W22
D[41]#
Y23
D[42]#
W24
D[43]#
W25
D[44]#
AA23
D[45]#
DATA GRP 2DATA GRP 3
DATA GRP 2DATA GRP 3
AA24
D[46]#
AB25
D[47]#
Y26
DSTBN[2]#
AA26
DSTBP[2]#
U22
DINV[2]#
AE24
D[48]#
AD24
D[49]#
AA21
D[50]#
AB22
D[51]#
AB21
D[52]#
AC26
D[53]#
AD20
D[54]#
AE22
D[55]#
AF23
D[56]#
AC25
D[57]#
AE21
D[58]#
AD21
D[59]#
AC22
D[60]#
AD23
D[61]#
AF22
D[62]#
AC23
D[63]#
AE25
DSTBN[3]#
AF24
DSTBP[3]#
AC20
DINV[3]#
R26
COMP[0]
U26
COMP[1]
AA1
COMP[2]
Y1
COMP[3]
E5
DPRSTP#
B5
DPSLP#
D24
DPWR#
D6
D7
SLP#
AE6
PSI#
T7
*PADT7*PAD
T96
T96
*PAD
*PAD
BCLK
133
166
200
Document Number
Document Number
Document Number
Custom Penryn Processor (HOST BUS)
Custom Penryn Processor (HOST BUS)
Custom Penryn Processor (HOST BUS)
Date: Sheet of
Tuesday, September 16, 2008
Date: Sheet of
Tuesday, September 16, 2008
Date: Sheet of
Tuesday, September 16, 2008
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0
COMP1
COMP2
COMP3
CPU_TEST3
CPU_TEST5
H_D#[0..63]
Note:
H_DPRTSTP need to daisy chain
from ICH9 to IMVP6 to CPU.
H_D#[0..63] 6
03
H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#2 6
H_D#[0..63] 6
H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6
H_DPRSTP# 7,14,38
H_DPSLP# 14
H_DPWR# 6
H_PWRGOOD 14
H_CPUSLP# 6
H_PSI# 38
BSEL2 BSEL1 BSEL0
1
1
1
0
COMP0
COMP1
COMP2
COMP3
Comp0,2 connect with Zo=27.4ohm,Comp1,3
connect with Zo=55ohm, make those traces
length shorter than 0.5".Trace should be
at least 25 mils away from any other
toggling signal.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
7
00
1
R20
R20
R380
1 2
27.4/F_4
27.4/F_4
R380
54.9/F_4
54.9/F_4
1 2
3 43
3 43
3 43
8
R31
R31
54.9/F_4
54.9/F_4
1 2
PROJECT : AJ2
PROJECT : AJ2
PROJECT : AJ2
R381
R381
27.4/F_4
27.4/F_4
1 2
RevSize
RevSize
RevSize
1A
1A
1A
1
2
3
4
5
6
7
8
All use 22U 10V(+-20%,X5R,1210)Pb-Free.
+VCC_CORE
C350
C350
10U/4V/X6S_8
10U/4V/X6S_8
C337
C337
10U/4V/X6S_8
10U/4V/X6S_8
12
12
12
A A
+VCC_CORE
12
C353
C353
10U/4V/X6S_8
10U/4V/X6S_8
C344
C344
10U/4V/X6S_8
10U/4V/X6S_8
12
C50
C50
10U/4V/X6S_8
10U/4V/X6S_8
12
C339
C339
10U/4V/X6S_8
10U/4V/X6S_8
12
C345
C345
10U/4V/X6S_8
10U/4V/X6S_8
12
C349
C349
10U/4V/X6S_8
10U/4V/X6S_8
12
C341
C341
10U/4V/X6S_8
10U/4V/X6S_8
12
C59
C59
10U/4V/X6S_8
10U/4V/X6S_8
8 inside cavity, north side, secondary layer.
+VCC_CORE
C340
C340
10U/4V/X6S_8
10U/4V/X6S_8
C36
C36
10U/4V/X6S_8
10U/4V/X6S_8
12
12
12
B B
+VCC_CORE
12
C33
C33
10U/4V/X6S_8
10U/4V/X6S_8
C51
C51
10U/4V/X6S_8
10U/4V/X6S_8
12
C45
C45
10U/4V/X6S_8
10U/4V/X6S_8
12
C58
C58
10U/4V/X6S_8
10U/4V/X6S_8
12
C38
C38
10U/4V/X6S_8
10U/4V/X6S_8
12
C44
C44
10U/4V/X6S_8
10U/4V/X6S_8
12
C354
C354
10U/4V/X6S_8
10U/4V/X6S_8
12
C348
C348
10U/4V/X6S_8
10U/4V/X6S_8
8 inside cavity, south side, secondary layer.
+VCC_CORE
12
C29
C29
10U/4V/X6S_8
10U/4V/X6S_8
12
C57
C57
10U/4V/X6S_8
10U/4V/X6S_8
12
C26
C26
10U/4V/X6S_8
10U/4V/X6S_8
12
C27
C27
10U/4V/X6S_8
10U/4V/X6S_8
12
C60
C60
10U/4V/X6S_8
10U/4V/X6S_8
12
C31
C31
10U/4V/X6S_8
10U/4V/X6S_8
6 inside cavity, north side, primary layer.
+VCC_CORE
C28
C28
10U/4V/X6S_8
10U/4V/X6S_8
12
C C
12
C30
C30
10U/4V/X6S_8
10U/4V/X6S_8
12
C32
C32
10U/4V/X6S_8
10U/4V/X6S_8
12
C35
C35
10U/4V/X6S_8
10U/4V/X6S_8
12
C351
C351
10U/4V/X6S_8
10U/4V/X6S_8
12
C37
C37
10U/4V/X6S_8
10U/4V/X6S_8
6 inside cavity, south side, primary layer.
+1.05V_VCCP
C336
C336
0.1U/16V/X7R_4
0.1U/16V/X7R_4
12
12
Layout out:
Place these inside socket cavity on North side secondary.
D D
C338
C338
0.1U/16V/X7R_4
0.1U/16V/X7R_4
12
C355
C355
0.1U/16V/X7R_4
0.1U/16V/X7R_4
12
C335
C335
0.1U/16V/X7R_4
0.1U/16V/X7R_4
12
C357
C357
0.1U/16V/X7R_4
0.1U/16V/X7R_4
12
C356
C356
0.1U/16V/X7R_4
0.1U/16V/X7R_4
+VCC_CORE
+PWR_SRC
12
C314
C314
+
+
*100U/25V
*100U/25V
Layout Note:
Need to add 100uF cap on PWR_SRC for cap singing.
Place on PWR_SRC near +VCC_CORE.
U18C
U18C
A7
VCC[001]
A9
VCC[002]
A10
VCC[003]
A12
VCC[004]
A13
VCC[005]
A15
VCC[006]
A17
VCC[007]
A18
VCC[008]
A20
VCC[009]
B7
VCC[010]
B9
VCC[011]
B10
VCC[012]
B12
VCC[013]
B14
VCC[014]
B15
VCC[015]
B17
VCC[016]
B18
VCC[017]
B20
VCC[018]
C9
VCC[019]
C10
VCC[020]
C12
VCC[021]
C13
VCC[022]
C15
VCC[023]
C17
VCC[024]
C18
VCC[025]
D9
VCC[026]
D10
VCC[027]
D12
VCC[028]
D14
VCC[029]
D15
VCC[030]
D17
VCC[031]
D18
VCC[032]
E7
VCC[033]
E9
VCC[034]
E10
VCC[035]
E12
VCC[036]
E13
VCC[037]
E15
VCC[038]
E17
VCC[039]
E18
VCC[040]
E20
VCC[041]
F7
VCC[042]
F9
VCC[043]
F10
VCC[044]
F12
VCC[045]
F14
VCC[046]
F15
VCC[047]
F17
VCC[048]
F18
VCC[049]
F20
VCC[050]
AA7
VCC[051]
AA9
VCC[052]
AA10
VCC[053]
AA12
VCC[054]
AA13
VCC[055]
AA15
VCC[056]
AA17
VCC[057]
AA18
VCC[058]
AA20
VCC[059]
AB9
VCC[060]
AC10
VCC[061]
AB10
VCC[062]
AB12
VCC[063]
AB14
VCC[064]
AB15
VCC[065]
AB17
VCC[066]
AB18
VCC[067]
Penryn Ball-out Rev 1a
Penryn Ball-out Rev 1a
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
+VCC_CORE
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
VCCSENSE
AF7
VSSSENSE
AE7
.
.
+1.05V_VCCP
12
+
+
C346
C346
330U/2.5V_7343
330U/2.5V_7343
VID0 38
VID1 38
VID2 38
VID3 38
VID4 38
VID5 38
VID6 38
VCCSENSE 38
VSSSENSE 38
+1.5V
C72
C72
0.01U/25V/X7R_4
0.01U/25V/X7R_4
+VCC_CORE
12
12
12
C73
C73
10U/4V/X6S_8
10U/4V/X6S_8
R350
R350
100/F_4
100/F_4
R347
R347
100/F_4
100/F_4
12
Layout Note:
Place C424 near PIN
B26.
VCCSENSE
VSSSENSE
Route VCCSENSE and VSSSENSE
traces at 27.4ohms and
length matched to within 25
mil. Place PU and PD within
2 inch of CPU.
U18D
U18D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080]
VSS[081]P3VSS[162]
Penryn Ball-out Rev 1a
Penryn Ball-out Rev 1a
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[163]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
.
.
04
PROJECT : AJ2
PROJECT : AJ2
PROJECT : AJ2
Quanta Computer Inc.
Quanta Computer Inc.
Document Number
Quanta Computer Inc.
Document Number
Document Number
Custom Penryn Processor (POWER)
Custom Penryn Processor (POWER)
Custom Penryn Processor (POWER)
Date: Sheet of
Tuesday, September 16, 2008
Date: Sheet of
Tuesday, September 16, 2008
Date: Sheet of
1
2
3
4
5
6
Tuesday, September 16, 2008
7
4 43
4 43
4 43
8
RevSize
RevSize
RevSize
1A
1A
1A
5
CPU Thermal monitor
4
3
2
1
05
D D
2N7002W-7-F
2N7002W-7-F
ABCLK30,31
ABCLK
TO MMB/ EC
2N7002W-7-F
2N7002W-7-F
ABDATA30,31
THERM_ALERT#16,22
SYS_SHDN#35,39
C C
ABDATA
CPU FAN
R39
R39
100K_4
100K_4
PWM_FAN130
B B
1 2
Q40
Q40
3 1
Q39
Q39
3 1
2N7002W-7-F
2N7002W-7-F
+5V_FAN
+3.3V
2
+3.3V
2
Q37
Q37
3 1
FANSET
C24
C24
0.1U/16V/X7R_4
0.1U/16V/X7R_4
+3.3V
2
+5V
THM_CLK
THM_DAT
6648OVERT#
U1
U1
1
2
3
R395 *0_4R395 *0_4
70 mil
VEN
GND
VIN
GND
VO
GND
SET4GND
G993P1U
G993P1U
+3.3V
R398
R398
R397
R397
R394
10K_4
10K_4
C22
C22
1U/10V/X5R_6
1U/10V/X5R_6
R394
10K_4
10K_4
+3.3V
13
R352
R352
100K_4
100K_4
10K_4
10K_4
Layout Note:
Layout Note:Routing 10:10 mils and
away from noise source with ground
gard
8
7
6
5
FANSIG130
R387 0_6R387 0_6
R383
R383
*10K_4
*10K_4
U20
U20
8
SCLK
7
SDA
6
ALERT#
4
OVERT#
G780P81
G780P81
40 mil
C23
C23
0.1U/16V/X7R_4
0.1U/16V/X7R_4
2
Q32
Q32
PDTA124EU
PDTA124EU
ADDRESS:
98H
+5V_FAN
25 mil
+3.3V_THM
1
VCC
2
DXP
3
DXN
5
GND
C330
C330
10U/10V/X5R_8
10U/10V/X5R_8
FANSIG
C382
C382
0.1U/16V/X7R_4
0.1U/16V/X7R_4
H_THERMDA
C381
C381
100P/50V_4
100P/50V_4
H_THERMDC
CN17
CN17
1
234
5
FAN
FAN
C333
C333
1000P/16V/X7R_4
1000P/16V/X7R_4
H_THERMDA 3
H_THERMDC 3
Thermistor_CTRL 39
A A
PROJECT : AJ2
PROJECT : AJ2
PROJECT : AJ2
Quanta Computer Inc.
Quanta Computer Inc.
Document Number
Quanta Computer Inc.
Document Number
Document Number
Custom Thermal IC
Custom Thermal IC
Custom Thermal IC
Date: Sheet of
Tuesday, September 16, 2008
Date: Sheet of
Tuesday, September 16, 2008
Date: Sheet of
5
4
3
2
Tuesday, September 16, 2008
5 43
5 43
5 43
1
RevSize
RevSize
RevSize
1A
1A
1A
1
2
3
4
5
6
7
8
06
U21A
M11
N12
P13
AD14
AA8
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6
E11
A11
B11
N10
Y10
Y12
Y14
C12
G8
G2
H6
H2
D4
H3
M9
R2
N9
M5
N2
R1
N5
N6
N8
M3
W2
C5
U21A
F2
H_D#_0
H_D#_1
F8
H_D#_2
E6
H_D#_3
H_D#_4
H_D#_5
H_D#_6
F6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
J1
H_D#_12
J2
H_D#_13
H_D#_14
J6
H_D#_15
P2
H_D#_16
L2
H_D#_17
H_D#_18
H_D#_19
L6
H_D#_20
H_D#_21
J3
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
L7
H_D#_29
H_D#_30
H_D#_31
Y3
H_D#_32
H_D#_33
Y6
H_D#_34
H_D#_35
H_D#_36
H_D#_37
Y7
H_D#_38
H_D#_39
H_D#_40
Y9
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
E3
H_RCOMP
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
CANTIGA_1p0
CANTIGA_1p0
HOST
HOST
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20
H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9
J8
L3
Y13
Y1
L10
M7
AA5
AE6
L9
M8
AA6
AE5
B15
K13
F13
B13
B14
B6
F12
C8
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_RESET#3
H_CPUSLP#3
12
H_D#[0..63]
C435
C435
0.1U/16V/X7R_4
0.1U/16V/X7R_4
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWING
H_RCOMP
H_REF
H_D#[0..63]3
A A
+1.05V_VCCP
12
R392
B B
C C
R392
221/F
221/F
H_SWING
12
R389
R389
100/F_4
100/F_4
12
R388
R388
24.9/F_4
24.9/F_4
Layout Note:
H_RCOMP trace should be
10-mil wide with 20-mil
spacing.
H_RCOMP
C424
C424
0.1U/16V/X7R_4
0.1U/16V/X7R_4
1 2
<--close pin C5
+1.05V_VCCP
R400
R400
1K/F_4
1K/F_4
1 2
12
R401
R401
2K/F_4
2K/F_4
H_A#[3..35]
H_ADS# 3
H_ADSTB#0 3
H_ADSTB#1 3
H_BNR# 3
H_BPRI# 3
H_BR0# 3
H_DEFER# 3
H_DBSY# 3
CLK_MCH_BCLK 2
CLK_MCH_BCLK# 2
H_DPWR# 3
H_DRDY# 3
H_HIT# 3
H_HITM# 3
H_LOCK# 3
H_TRDY# 3
H_DINV#0 3
H_DINV#1 3
H_DINV#2 3
H_DINV#3 3
H_DSTBN#0 3
H_DSTBN#1 3
H_DSTBN#2 3
H_DSTBN#3 3
H_DSTBP#0 3
H_DSTBP#1 3
H_DSTBP#2 3
H_DSTBP#3 3
H_REQ#0 3
H_REQ#1 3
H_REQ#2 3
H_REQ#3 3
H_REQ#4 3
H_RS#0 3
H_RS#1 3
H_RS#2 3
H_A#[3..35] 3
<--CLK
Layout Note:
Place the 0.1 uF
D D
1
2
decoupling capacitor
within 100 mils from
GMCH pins.
3
PROJECT : AJ2
PROJECT : AJ2
PROJECT : AJ2
Quanta Computer Inc.
Quanta Computer Inc.
Document Number
Quanta Computer Inc.
Document Number
Document Number
Custom Cantiga (HOST)
Custom Cantiga (HOST)
Custom Cantiga (HOST)
Date: Sheet of
Tuesday, September 16, 2008
Date: Sheet of
Tuesday, September 16, 2008
Date: Sheet of
4
5
6
Tuesday, September 16, 2008
7
6 43
6 43
6 43
8
RevSize
RevSize
RevSize
1A
1A
1A
1
M36
N36
R141
R141
1K/F_4
1K/F_4
R153
R153
3.01K/F_4
3.01K/F_4
R158
R158
1K/F_4
1K/F_4
MCH_CFG3
MCH_CFG4
MCH_CFG5
MCH_CFG6
MCH_CFG7
MCH_CFG8
MCH_CFG9
MCH_CFG10
MCH_CFG11
MCH_CFG12
MCH_CFG13
MCH_CFG14
MCH_CFG15
MCH_CFG16
MCH_CFG17
MCH_CFG18
MCH_CFG19
MCH_CFG20
H_THERMTRIP#
TP_NC1
TP_NC2
TP_NC3
TP_NC4
TP_NC5
TP_NC6
TP_NC7
TP_NC8
TP_NC9
TP_NC10
TP_NC11
TP_NC12
TP_NC13
TP_NC14
TP_NC15
TP_NC16
AH10
AH12
AH13
AL34
AK34
AN35
AM35
AY21
BG23
BF23
BH18
BF18
AT40
AT11
BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
R33
T33
AH9
K12
T24
B31
AJ6
M1
A47
T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28
R29
B7
N33
P32
T20
R32
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
pull up/down
impedance
compensation
For Memory
SM_RCOMP_VOH
12
C171
C171
0.01U/25V/X7R_4
0.01U/25V/X7R_4
A A
SM_RCOMP_VOL
12
C179
C179
0.01U/25V/X7R_4
0.01U/25V/X7R_4
Layout Note:
Location of all MCH_CFG strap
resistors needs to be close to
minmize stub.
B B
CPU_MCH_BSEL02,3
CPU_MCH_BSEL12,3
CPU_MCH_BSEL22,3
MCH_CFG[3..20]8
PM_SYNC#16
H_DPRSTP#3,14,38
PM_EXTTS#012,13
PM_EXTTS#112
DELAY_VR_PG
PLTRST#_NB15
H_THERMTRIP#3,14
PM_DPRSLPVR16,38
C C
+3.3V
R173 10K_4R173 10K_4
1 2
R169 10K_4R169 10K_4
1 2
12
C180
C180
2.2U/10V/X5R_8
2.2U/10V/X5R_8
12
C173
C173
2.2U/10V/X5R_8
2.2U/10V/X5R_8
R85 100/F_4R85 100/F_4
+1.8V_SUS
12
12
12
PM_EXTTS#0
PM_EXTTS#1
Modify for C-TEST
T117T117
T113T113
T118T118
T111T111
T109T109
T120T120
T114T114
T112T112
T110T110
T116T116
T119T119
T33T33
T97T97
T99T99
T100T100
T98T98
PM_EXTTS#0
PM_EXTTS#1
U21B
U21B
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
CANTIGA_1p0
CANTIGA_1p0
2
SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
SA_CKE_0
SA_CKE_1
RSVD
RSVD
CFG
CFG
PM
PM
NC
NC
SB_CKE_0
SB_CKE_1
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF
DDR CONTROL/COMPENSATIONCLK
DDR CONTROL/COMPENSATIONCLK
SM_PWROK
SM_REXT
SM_DRAMRST#
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
PEG_CLK
PEG_CLK#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI
DMI
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VR_EN
GRAPHICS VIDMEHDA
GRAPHICS VIDMEHDA
CL_PWROK
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
MISC
MISC
HDA_BCLK
HDA_RST#
HDA_SDO
HDA_SYNC
CL_CLK
CL_DATA
CL_RST#
CL_VREF
TSATN
HDA_SDI
3
AP24
AT21
AV24
AU20
AR24
AR21
AU24
AV20
BC28
AY28
AY36
BB36
BA17
AY16
AV16
AR13
BD17
AY17
BF15
AY13
BG22
BH21
BF28
BH28
AV42
AR36
BF17
BC36
B38
A38
E41
F41
F43
E43
AE41
AE37
AE47
AH39
AE40
AE38
AE48
AH40
AE35
AE43
AE46
AH42
AD35
AE44
AF46
AH43
INTEL FAE Suggest PD for Ext graphics
B33
B32
G33
F33
E33
C34
AH37
AH36
AN36
AJ35
AH34
N28
M28
G36
E36
K36
H36
B12
B28
B30
B29
C29
A28
SMRCOMPP
SMRCOMPN
SM_RCOMP_VOH
SM_RCOMP_VOL
V_DDR_MCH_REF
SM_PWROK
SM_DRAMRST#
MCH_DREFCLK
MCH_DREFCLK#
DREF_SSCLK
DREF_SSCLK#
MCH_DREFCLK
MCH_DREFCLK#
DREF_SSCLK
DREF_SSCLK#
MCH_CLVREF
DDPC_CTRLCLK
DDPPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
R399 56.2/F_4R399 56.2/F_4
MCH_TSATN
ACZ_BITCLK_MCH
ACZ_RST#_MCH
ACZ_SDIN3_MCH
ACZ_SDOUT_MCH
ACZ_SYNC_MCH
M_CLK_DDR0 13
M_CLK_DDR1 13
M_CLK_DDR3 13
M_CLK_DDR4 13
M_CLK_DDR#0 13
M_CLK_DDR#1 13
M_CLK_DDR#3 13
M_CLK_DDR#4 13
DDR_CKE0_DIMMA 12,13
DDR_CKE1_DIMMA 12,13
DDR_CKE3_DIMMB 12,13
DDR_CKE4_DIMMB 12,13
DDR_CS0_DIMMA# 12,13
DDR_CS1_DIMMA# 12,13
DDR_CS2_DIMMB# 12,13
DDR_CS3_DIMMB# 12,13
M_ODT0 12,13
M_ODT1 12,13
M_ODT2 12,13
M_ODT3 12,13
R175 0_4R175 0_4
R108 499/F_4R108 499/F_4
TP3TP3
MCH_DREFCLK 2
MCH_DREFCLK# 2
DREF_SSCLK 2
DREF_SSCLK# 2
CLK_MCH_3GPLL 2
CLK_MCH_3GPLL# 2
DMI_MRX_ITX_N0 15
DMI_MRX_ITX_N1 15
DMI_MRX_ITX_N2 15
DMI_MRX_ITX_N3 15
DMI_MRX_ITX_P0 15
DMI_MRX_ITX_P1 15
DMI_MRX_ITX_P2 15
DMI_MRX_ITX_P3 15
DMI_MTX_IRX_N0 15
DMI_MTX_IRX_N1 15
DMI_MTX_IRX_N2 15
DMI_MTX_IRX_N3 15
DMI_MTX_IRX_P0 15
DMI_MTX_IRX_P1 15
DMI_MTX_IRX_P2 15
DMI_MTX_IRX_P3 15
R197 E@0_4R197 E@0_4
R198 E@0_4R198 E@0_4
R199 E@0_4R199 E@0_4
R200 E@0_4R200 E@0_4
T108 *PADT108 *PAD
T106 *PADT106 *PAD
T29 *PADT29 *PAD
T31 *PADT31 *PAD
T28 *PADT28 *PAD
Layout Note:
T107 *PADT107 *PAD
HSYNC/VSYNC serial R
place close to NB
CL_CLK0 16
CL_DATA0 16
PWROK 16,30
ICH_CL_RST0# 16
TP1TP1
TP2TP2
SDVO_CTRLCLK 19
SDVO_CTRLDATA 19
CLK_3GPLLREQ# 2
MCH_ICH_SYNC# 16
+1.05V_VCCP
ACZ_BITCLK_MCH 14
ACZ_RST#_MCH 14
R413 0_4R413 0_4
ACZ_SDOUT_MCH 14
ACZ_SYNC_MCH 14
12
4
IV&EV Dis/Enable setting
If LVDS no use,all signal can NC
L_BKLT_CTRL18
INT_LVDS_BLON18
+3.3V
INT_LVDS_EDIDCLK18
INT_LVDS_EDIDDATA18
Layout Note:
Place 150 ohm
termination resistors
close to GMCH.
R155 E@0_4R155 E@0_4
R160 E@0_4R160 E@0_4
R64 *I@150/F_4R64 *I@150/F_4
R68 *I@150/F_4R68 *I@150/F_4
R70 *I@150/F_4R70 *I@150/F_4
R159 *I@1K/F_4R159 *I@1K/F_4
R156 E@0_4R156 E@0_4
INT_CRT_DDCCLK22
INT_CRT_DDCDAT22
INT_HSYNC22
INT_VSYNC22
ACZ_SDIN3 14
INT_LVDS_DIGON18
INT_TXLCLKOUT-22
INT_TXLCLKOUT+22
INT_TXUCLKOUT-22
INT_TXUCLKOUT+22
INT_TXLOUT0-22
INT_TXLOUT1-22
INT_TXLOUT2-22
INT_TXLOUT0+22
INT_TXLOUT1+22
INT_TXLOUT2+22
INT_TXUOUT0-22
INT_TXUOUT1-22
INT_TXUOUT2-22
INT_TXUOUT0+22
INT_TXUOUT1+22
INT_TXUOUT2+22
HSYNC_G
VSYNC_G
INT_CRT_BLU
INT_CRT_GRN
INT_CRT_RED
ACZ_BITCLK_MCH
EMC
reserved
(Near to pin B28)
R172 *I@10K_4R172 *I@10K_4
R168 *I@10K_4R168 *I@10K_4
R418 *I@2.4K/F_4R418 *I@2.4K/F_4
INT_TXLCLKOUTÂINT_TXLCLKOUT+
INT_TXUCLKOUTÂINT_TXUCLKOUT+
INT_TXLOUT0ÂINT_TXLOUT1ÂINT_TXLOUT2-
INT_TXLOUT0+
INT_TXLOUT1+
INT_TXLOUT2+
INT_TXUOUT0ÂINT_TXUOUT1ÂINT_TXUOUT2-
INT_TXUOUT0+
INT_TXUOUT1+
INT_TXUOUT2+
R143 E@0_4R143 E@0_4
R139 *I@75/F_4R139 *I@75/F_4
INT_CRT_BLU22
INT_CRT_GRN22
INT_CRT_RED22
CRTIREF
R154 *I@24.9/F_4R154 *I@24.9/F_4
R157 *I@24.9/F_4R157 *I@24.9/F_4
R412
R412
*33_4
*33_4
Non-iAMT
C462
C462
*0.1U/16V/X7R_4
*0.1U/16V/X7R_4
1 2
For ME
Management Engine
5
L_CTRL_CLK
L_CTRL_DATA
INT_CRT_BLU
INT_CRT_GRN
INT_CRT_RED
HSYNC_G
CRTIREF
VSYNC_G
MCH_CLVREF
C184
C184
0.1U/16V/X7R_4
0.1U/16V/X7R_4
L32
G32
M32
M33
K33
J33
M29
C44
B43
E37
E38
C41
C40
B37
A37
H47
E46
G40
A40
H48
D45
F40
B40
A41
H38
G37
J37
B42
G38
F37
K37
F25
H25
K25
H24
C31
E32
E28
G28
J28
G29
H32
J32
J29
E29
L29
+1.05V_VCCP
12
R148
R148
1K/F_4
1K/F_4
12
R161
R161
511/F_4
511/F_4
U21C
U21C
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3
TVA_DAC
TVB_DAC
TVC_DAC
TV_RTN
TV_DCONSEL_0
TV_DCONSEL_1
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_IRTN
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC
CANTIGA_1p0
CANTIGA_1p0
+1.8V_SUS
R134
R134
80.6/F_4
80.6/F_4
SMRCOMPP
SMRCOMPN
R135
R135
80.6/F_4
80.6/F_4
For Memory
install 80.6 fo r Cantiga.
install 20 for Teenah.
6
7
8
07
49.9 ohm for cantiga
EXP_A_COMPX
T37
PEG_COMPI
T36
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
LVDS
LVDS
TV
TV
12
12
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
VGA
VGA
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39
H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40
J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46
J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
C_PEG_TXN0
C_PEG_TXN1
C_PEG_TXN2
C_PEG_TXN3
C_PEG_TXN4
C_PEG_TXN5
C_PEG_TXN6
C_PEG_TXN7
C_PEG_TXN8
C_PEG_TXN9
C_PEG_TXN10
C_PEG_TXN11
C_PEG_TXN12
C_PEG_TXN13
C_PEG_TXN14
C_PEG_TXN15
C_PEG_TXP0
C_PEG_TXP1
C_PEG_TXP2
C_PEG_TXP3
C_PEG_TXP4
C_PEG_TXP5
C_PEG_TXP6
C_PEG_TXP7
C_PEG_TXP8
C_PEG_TXP9
C_PEG_TXP10
C_PEG_TXP11
C_PEG_TXP12
C_PEG_TXP13
C_PEG_TXP14
C_PEG_TXP15
+VCC_PEG
R177 49.9/FR177 49.9/F
1 2
PEG_RXN[15:0] 22
Can support reversal routing.If CFG9=1, PCI
Express is normal operation. If CFG9=0,
then PEG_TXP0 becomes PEG_TXP15, PEG_TXP1
becomes PEG_TXP14, PEG_TXP2 becomes
PEG_TXP13, etc. similarly for PEG_RXP[15:0]
and PEG_RXN[15:0]
PEG_RXP[15:0] 22
C367 0.1U/16V/X7R_4C367 0.1U/16V/X7R_4
C371 0.1U/16V/X7R_4C371 0.1U/16V/X7R_4
C376 0.1U/16V/X7R_4C376 0.1U/16V/X7R_4
C384 0.1U/16V/X7R_4C384 0.1U/16V/X7R_4
C391 E@.1U/16V_4C391 E@.1U/16V_4
C403 E@.1U/16V_4C403 E@.1U/16V_4
C406 E@.1U/16V_4C406 E@.1U/16V_4
C414 E@.1U/16V_4C414 E@.1U/16V_4
C417 E@.1U/16V_4C417 E@.1U/16V_4
C425 E@.1U/16V_4C425 E@.1U/16V_4
C428 E@.1U/16V_4C428 E@.1U/16V_4
C431 E@.1U/16V_4C431 E@.1U/16V_4
C436 E@.1U/16V_4C436 E@.1U/16V_4
C440 E@.1U/16V_4C440 E@.1U/16V_4
C443 E@.1U/16V_4C443 E@.1U/16V_4
C446 E@.1U/16V_4C446 E@.1U/16V_4
C364 0.1U/16V/X7R_4C364 0.1U/16V/X7R_4
C368 0.1U/16V/X7R_4C368 0.1U/16V/X7R_4
C372 0.1U/16V/X7R_4C372 0.1U/16V/X7R_4
C380 0.1U/16V/X7R_4C380 0.1U/16V/X7R_4
C386 E@.1U/16V_4C386 E@.1U/16V_4
C393 E@.1U/16V_4C393 E@.1U/16V_4
C404 E@.1U/16V_4C404 E@.1U/16V_4
C407 E@.1U/16V_4C407 E@.1U/16V_4
C415 E@.1U/16V_4C415 E@.1U/16V_4
C421 E@.1U/16V_4C421 E@.1U/16V_4
C426 E@.1U/16V_4C426 E@.1U/16V_4
C429 E@.1U/16V_4C429 E@.1U/16V_4
C432 E@.1U/16V_4C432 E@.1U/16V_4
C437 E@.1U/16V_4C437 E@.1U/16V_4
C441 E@.1U/16V_4C441 E@.1U/16V_4
C445 E@.1U/16V_4C445 E@.1U/16V_4
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
PEG_TXN[15:0] 22
SDVOB_REDÂSDVOB_GREENÂSDVOB_BLUEÂSDVOB_CLK-
PEG_TXP[15:0] 22
SDVOB_RED+
SDVOB_GREEN+
SDVOB_BLUE+
SDVOB_CLK+
Modify for C-TEST
D D
PROJECT : AJ2
PROJECT : AJ2
PROJECT : AJ2
Quanta Computer Inc.
Quanta Computer Inc.
Document Number
Document Number
Document Number
Custom Cantiga (VGA,DMI)
Custom Cantiga (VGA,DMI)
Custom Cantiga (VGA,DMI)
Date: Sheet of
Tuesday, September 16, 2008
Date: Sheet of
Tuesday, September 16, 2008
Date: Sheet of
1
2
3
4
5
6
Tuesday, September 16, 2008
7
Quanta Computer Inc.
7 43
7 43
7 43
8
RevSize
RevSize
RevSize
1A
1A
1A
1
2
3
4
5
6
7
8
DDR2
DDR_A_D[0..63]13
A A
B B
C C
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
AU10
BA11
AN10
AM11
AM5
AN12
AM13
AJ11
AJ12
BB9
BA9
AV9
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AJ9
AJ8
U21D
U21D
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
CANTIGA_1p0
CANTIGA_1p0
DDR_A_BS0
BD21
SA_BS_0
SA_BS_1
SA_BS_2
SA_RAS#
SA_CAS#
SA_WE#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_MA_14
BG18
AT25
BB20
BD20
AY20
AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5
AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8
BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25
DDR_A_BS1
DDR_A_BS2
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_BS0 12,13
DDR_A_BS1 12,13
DDR_A_BS2 12,13
DDR_A_RAS# 12,13
DDR_A_CAS# 12,13
DDR_A_WE# 12,13
DDR_A_DM[0..7] 13
DDR_A_DQS[0..7] 13
DDR_A_DQS#[0..7] 13
DDR_A_MA[0..14] 12,13
DDR_B_D[0..63]13
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3
U21E
U21E
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
CANTIGA_1p0
CANTIGA_1p0
DDR_B_BS0
BC16
SB_BS_0
SB_BS_1
SB_BS_2
SB_RAS#
SB_CAS#
SB_WE#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_MA_14
BB17
BB33
AU17
BG16
BF14
AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
DDR_B_BS1
DDR_B_BS2
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_BS0 12,13
DDR_B_BS1 12,13
DDR_B_BS2 12,13
DDR_B_RAS# 12,13
DDR_B_CAS# 12,13
DDR_B_WE# 12,13
DDR_B_DM[0..7] 13
DDR_B_DQS[0..7] 13
DDR_B_DQS#[0..7] 13
DDR_B_MA[0..14] 12,13
08
STRAPPING
CFG5
DMI X2 Select
CFG6 iTPM Host Interface
CFG7
CFG9
Intel Management Engine Crypto
Strap
PCI Express Graphic Lane
CFG10 PCIe Loopback Enable
CFG16
D D
CFG19
CFG20
FSB Dynamic ODT
DMI Lane Reversal
Digital Display Port(SDVO/DP/iHDMI)
and PCIe Concurrent Operation.
CFG13 CFG12 XOR / ALLZ / Clock Un-gating
1
2
3
Low=DMIx2
High=DMIx4(Default)
Low= Enable
High=Disable(Default)
Low= Intel Management Engine Crypto TLS
cipher suite with no Confidentiality
High=Intel Management Engine Crypto TLS
cipher suite with Confidentiality(Default)
Low= Reveise Lane
High=Normal operation
Low= Enable
High=Disable(Default)
Low=Dynamic ODT Disable
High=Dynamic ODT Enable(default).
Low=Normal(default).
High=Lane Reversed
Low=Only DP or inly PCIe is operational (defaults)
High=DP and PCIe x1 are operating simultaneously.
00=Reserved.
10=XOR Mode Enabled.
01=All-Z Mode Enabled.
11=Normal Operation (Default).
4
5
R144 *2.21K/F_4R144 *2.21K/F_4
R132 *2.21K/F_4R132 *2.21K/F_4
R140 *2.21K/F_4R140 *2.21K/F_4
R130 *2.21K/F_4R130 *2.21K/F_4
R138 *2.21K/F_4R138 *2.21K/F_4
R127 *2.21K/F_4R127 *2.21K/F_4
R133 *2.21K/F_4R133 *2.21K/F_4
R131 *2.21K/F_4R131 *2.21K/F_4
+3.3V
R146 *4.02K/FR146 *4.02K/F
R145 2.21K/FR145 2.21K/F
6
*PAD
*PAD
*PAD
*PAD
12
12
12
*PAD
*PAD
12
12
*PAD
*PAD
12
12
*PAD
*PAD
*PAD
*PAD
12
*PAD
*PAD
*PAD
*PAD
12
12
Custom Cantiga (DDR2,STRAPPING)
Custom Cantiga (DDR2,STRAPPING)
Custom Cantiga (DDR2,STRAPPING)
Date: Sheet of
Date: Sheet of
Date: Sheet of
MCH_CFG3
T20
T20
MCH_CFG4
T26
T26
MCH_CFG5
MCH_CFG6
MCH_CFG7
MCH_CFG8
T22
T22
MCH_CFG9
MCH_CFG10
MCH_CFG11
T25
T25
MCH_CFG12
MCH_CFG13
MCH_CFG14
T21
T21
MCH_CFG15
T19
T19
MCH_CFG16
MCH_CFG17
T24
T24
MCH_CFG18
T27
T27
MCH_CFG19
MCH_CFG20
Quanta Computer Inc.
Quanta Computer Inc.
Document Number
Document Number
Document Number
Tuesday, September 16, 2008
Tuesday, September 16, 2008
Tuesday, September 16, 2008
Quanta Computer Inc.
7
MCH_CFG[3..20] 7
PROJECT : AJ2
PROJECT : AJ2
PROJECT : AJ2
8 43
8 43
8 43
8
RevSize
RevSize
RevSize
1A
1A
1A
5
U21G
AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29
BA36
BB24
BD16
BB21
AW16
AW13
AT13
AE25
AB25
AA25
AE24
AC24
AA24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
AH20
AF20
AE20
AC20
AB20
AA20
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
AN14
AM14
AJ14
AH14
V15
U15
U14
T14
Y26
Y24
Y21
T17
T16
Y15
U21G
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
VCC_AXG_SENSE
VSS_AXG_SENSE
POWER
POWER
VCC SMVCC GFX
VCC SMVCC GFX
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC GFX NCTF
VCC GFX NCTF
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC SM LF
VCC SM LF
+1.8V_SUS
D D
C C
+1.05V_AXG
B B
A A
W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
AV44
BA37
AM40
AV21
AY5
AM10
BB13
4
+1.05V_AXG
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
+1.05V_VCCP
Layout Note:
Place close to GMCH.
+1.05V_VCCP
12
+
+
C75
C75
*I@330U/2.5V_7343
*I@330U/2.5V_7343
Place close to the MCH
+1.8V_SUS
12
C196
C196
0.1U/16V/X7R_4
0.1U/16V/X7R_4
Layout Note:
Place C411 where LVDS
and DDR2 taps.
C130
C130
0.1U/16V/X7R_4
0.1U/16V/X7R_4
12
C123
C123
0.1U/16V/X7R_4
0.1U/16V/X7R_4
12
12
+
+
R87 *I@0_8R87 *I@0_8
12
+
+
C76
C76
*I@330U/2.5V_7343
*I@330U/2.5V_7343
R174
R174
0.002/F
0.002/F
1 2
12
12
C104
C104
C157
C157
0.22U/10V
0.22U/10V
0.22U/10V
0.22U/10V
3
C77
C77
330U/2.5V_7343
330U/2.5V_7343
+1.05V_AXG
E@0_6
E@0_6
12
+
+
12
12
C192
C192
22U/4V_8
22U/4V_8
Layout Note:
Inside GMCH cavity.
E@0_6
E@0_6R88 *I@0_8R88 *I@0_8
R91
R91
R93
R93
+1.05V_AXG
12
C198
C198
330U/6.3V
330U/6.3V
C201
C201
0.47U/10V
0.47U/10V
12
C152
C152
*I@0.47U/10V
*I@0.47U/10V
12
Layout Note:
Place on the edge.
12
C197
C197
1U/10V/X5R_6
1U/10V/X5R_6
12
C178
C178
0.22U/10V
0.22U/10V
12
C139
C139
*I@1U/10V/X5R_6
*I@1U/10V/X5R_6
VCC_SM
12
C186
C186
22U/4V_8
22U/4V_8
12
C202
C202
1U/10V/X5R_6
1U/10V/X5R_6
12
C191
C191
0.22U/10V
0.22U/10V
12
C156
C156
C165
C165
*I@22U/4V_8
*I@22U/4V_8
*I@10U/6.3V/X5R_6
*I@10U/6.3V/X5R_6
C185
C185
22U/4V_8
22U/4V_8
2
12
C195
C195
0.1U/16V/X7R_4
0.1U/16V/X7R_4
Cavity Capactors
12
C145
C145
*I@0.1U/16V/X7R_4
*I@0.1U/16V/X7R_4
R152 0_4R152 0_4
1 2
12
C167
C167
*I@0.1U/16V/X7R_4
*I@0.1U/16V/X7R_4
AG34
AC34
AB34
AA34
Y34
V34
U34
AM33
AK33
AJ33
AG33
AF33
AE33
AC33
AA33
Y33
W33
V33
U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
T32
U21F
U21F
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
CANTIGA_1p0
CANTIGA_1p0
1
09
VCC CORE
VCC CORE
+1.05V_VCCP
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
POWER
POWER
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC NCTF
VCC NCTF
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
5
CANTIGA_1p0
CANTIGA_1p0
PROJECT : AJ2
PROJECT : AJ2
PROJECT : AJ2
Quanta Computer Inc.
Quanta Computer Inc.
Document Number
Quanta Computer Inc.
Document Number
Document Number
Custom Cantiga (VCC,NCTF)
Custom Cantiga (VCC,NCTF)
Custom Cantiga (VCC,NCTF)
Date: Sheet of
Tuesday, September 16, 2008
Date: Sheet of
Tuesday, September 16, 2008
Date: Sheet of
4
3
2
Tuesday, September 16, 2008
9 43
9 43
9 43
1
RevSize
RevSize
RevSize
1A
1A
1A
5
4
3
2
1
L48
L48
20 mil
+1.05V_VCCP
L50 *I@10uH/100MA_8L50 *I@10uH/100MA_8
D D
L53 *I@10uH/100MA_8L53 *I@10uH/100MA_8
+1.05V_VCCP
L47 BLM11A121S_6L47 BLM11A121S_6
C C
+1.5V
L46 BLM11A121S_6L46 BLM11A121S_6
+V1.05M_MCH_PLL
C394
C394
10U/6.3V/X5R_8
10U/6.3V/X5R_8
20 mil
C497
*I@470U/4V_ESR15_7343
*I@470U/4V_ESR15_7343
C497
20 mil
C496
*I@470U/4V_ESR15_7343
*I@470U/4V_ESR15_7343
C496
20 mil
C388
C388
4.7U/6.3V_6
4.7U/6.3V_6
20 mil
R386 0.5/F_6R386 0.5/F_6
40 mil
C169
C169
5
+VCCD_TVDAC_R
20 mil
C166
C166
R142 0_6R142 0_6
20 mil
B B
20 mil
BLM18PG181SN1
BLM18PG181SN1
A A
C162
C162
0.1U/16V/X7R_4
0.1U/16V/X7R_4
L22
L22
0.01U/16V/X7R_4
0.01U/16V/X7R_4
+1.05V_VCCP
L54 BLM18PG181SN1L54 BLM18PG181SN1
20 mil 20 mil
12
+
+
*I@0.1U/16V/X7R_4
*I@0.1U/16V/X7R_4
12
+
+
*I@0.1U/16V/X7R_4
*I@0.1U/16V/X7R_4
C401
C401
0.1U/16V/X7R_4
0.1U/16V/X7R_4
15 mil
C168
C168
+VCCQ_QDAC_R
.022U/16V_4
.022U/16V_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
+VCCA_DPLLA
C479
C479
+VCCA_DPLLB
C486
C486
+VCCA_HPLL
+VCCA_MPLL
C402
C402
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.01U/16V/X7R_4
0.01U/16V/X7R_4
C172
C172
1U/6.3V/X5R_4
1U/6.3V/X5R_4
+VCCA_PEG_PLL
R419
R419
E@0_4
E@0_4
des
des
R420
R420
E@0_4
E@0_4
des
des
C175
C175
10mil
R425
R425
1/F_6
1/F_6
+V1.05S_PEGPLL_FB
C504
C504
10U/6.3V/X5R_8
10U/6.3V/X5R_8
+3.3V
+3.3V
80 mil
+3.3V
1 2
*I@BLM18PG181SN1_6
*I@BLM18PG181SN1_6
*I@0.1U/16V/X7R_4
20 mil
R409 *I@0_6R409 *I@0_6
*I@0.1U/16V/X7R_4
*I@0.1U/16V/X7R_4
*I@0.1U/16V/X7R_4
AB total 64.8mA
For Teenah
R422 *0_6R422 *0_6
+3.3V
R421 0_6R421 0_6
+1.5V
+1.05V_VCCP
+1.05V_VCCP
For Cantiga
R96 0_6R96 0_6
+
+
C96
C96
220U/2.5V_3528
220U/2.5V_3528
R147 0_6R147 0_6
R406 *I@0_6R406 *I@0_6
20 mil 20 mil
+1.5V
2.2U/6.3V/X5R_6
2.2U/6.3V/X5R_6
int
int
*10U/6.3V/X5R_8
*10U/6.3V/X5R_8
R415 *I@0_6
R415 *I@0_6
20 mil
C153
C153
int
int
20 mil
C396
C396
0.1U/16V/X7R_4
0.1U/16V/X7R_4
R184 *I@0_6
+1.8V_SUS
4
R184 *I@0_6
20 mil
+VCCA_CRTDAC
C460
C460
int
int
*I@0.01U/16V/X7R_4
*I@0.01U/16V/X7R_4
+VCC_TVBG
C454
C454
*I@0.01U/16V/X7R_4
*I@0.01U/16V/X7R_4
int
int
20 mil
414uA
C489 0.1U/16V/X7R_4C489 0.1U/16V/X7R_4
480mA
C121
C121
10U/6.3V/X5R_8
10U/6.3V/X5R_8
C147
C147
10U/6.3V/X5R_8
10U/6.3V/X5R_8
C164
C164
10U/6.3V/X5R_8
10U/6.3V/X5R_8
C447
C447
*0.1U/16V/X7R_4
*0.1U/16V/X7R_4
C469
C469
*I@0.1U/16V/X7R_4
*I@0.1U/16V/X7R_4
int
int
157.2mA
int
int
*I@1U/6.3V/X5R_4
*I@1U/6.3V/X5R_4
73mA
C459
C459
int
int
2.68mA
C455
C455
int
int
24mA
139.2mA
13.2mA
C492
C492
*I@1000P/50V/X7R_4
*I@1000P/50V/X7R_4
+V1.05M_A_SM
C134
C134
10U/6.3V/X5R_8
10U/6.3V/X5R_8
C155
C155
4.7U/6.3V_6
4.7U/6.3V_6
24mA
+VCCA_SM_CK
C170
C170
10U/6.3V/X5R_8
10U/6.3V/X5R_8
87.78mA
+VCC_TVDACA_R
C449
C449
20 mil
R414
R414
E@0_4
E@0_4
des
des
48.363mA
50mA
C495
C495
0.1U/16V/X7R_4
0.1U/16V/X7R_4
20 mil
+VCCD_LVDS
C200
C200
*I@10U/6.3V/X5R_8
*I@10U/6.3V/X5R_8
int
int
R411
R411
E@0_4
E@0_4
des
des
R408
R408
E@0_4
E@0_4
des
des
+VCCA_DPLLA
+VCCA_DPLLB
+VCCA_HPLL
+VCCA_MPLL
+VCC_TX_LVDS
+VCC_PEG_BG
C494
C494
0.1U/16V/X7R_4
0.1U/16V/X7R_4
50mA
+VCCA_PEG_PLL
C111
C111
10U/6.3V/X5R_8
10U/6.3V/X5R_8
C146
C146
1U/6.3V/X5R_4
1U/6.3V/X5R_4
C176
C176
0.1U/16V/X7R_4
0.1U/16V/X7R_4
R407
R407
E@0_4
E@0_4
des
des
50mA
+VCC_HDA
56.87mA
+VCCD_TVDAC_R
+VCCQ_QDAC_R
+V1.05M_MCH_PLL
+VCCA_PEG_PLL
20 mil
60.31mA
C204
C204
des
des
int
int
R171
R171
E@0_4
E@0_4
U21H
U21H
B27
VCCA_CRT_DAC_1
A26
VCCA_CRT_DAC_2
A25
VCCA_DAC_BG
B25
VSSA_DAC_BG
F47
VCCA_DPLLA
L48
VCCA_DPLLB
AD1
VCCA_HPLL
AE1
VCCA_MPLL
J48
VCCA_LVDS
J47
VSSA_LVDS
AD48
VCCA_PEG_BG
AA48
VCCA_PEG_PLL
AR20
VCCA_SM_1
AP20
VCCA_SM_2
AN20
VCCA_SM_3
AR17
VCCA_SM_4
AP17
VCCA_SM_5
AN17
VCCA_SM_6
AT16
VCCA_SM_7
AR16
VCCA_SM_8
AP16
VCCA_SM_9
AP28
VCCA_SM_CK_1
AN28
VCCA_SM_CK_2
AP25
VCCA_SM_CK_3
AN25
VCCA_SM_CK_4
AN24
VCCA_SM_CK_5
AM28
VCCA_SM_CK_NCTF_1
AM26
VCCA_SM_CK_NCTF_2
AM25
VCCA_SM_CK_NCTF_3
AL25
VCCA_SM_CK_NCTF_4
AM24
VCCA_SM_CK_NCTF_5
AL24
VCCA_SM_CK_NCTF_6
AM23
VCCA_SM_CK_NCTF_7
AL23
VCCA_SM_CK_NCTF_8
B24
VCCA_TV_DAC_1
A24
VCCA_TV_DAC_2
A32
VCC_HDA
M25
VCCD_TVDAC
L28
VCCD_QDAC
AF1
VCCD_HPLL
AA47
VCCD_PEG_PLL
M38
VCCD_LVDS_1
L37
VCCD_LVDS_2
CANTIGA_1p0
CANTIGA_1p0
3
+VTTLF1
+VTTLF2
+VTTLF3
CRTPLLA PEGA SM
CRTPLLA PEGA SM
A LVDS
A LVDS
POWER
POWER
A CK
A CK
TV
TV
HDA
HDA
D TV/CRT
D TV/CRT
LVDS
LVDS
C395
C395
.47U/6.3V_4
.47U/6.3V_4
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
AXF
AXF
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
SM CK
SM CK
VCC_TX_LVDS
VCC_HV_1
VCC_HV_2
VCC_HV_3
HV
HV
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
PEG
PEG
VCC_PEG_5
VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4
DMI
DMI
VTTLF
VTTLF
C400
C400
.47U/6.3V_4
.47U/6.3V_4
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT
VTT
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VTTLF1
VTTLF2
VTTLF3
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1
B22
B21
A21
119.85mA
BF21
BH20
BG20
BF20
K47
C35
B35
A35
V48
U48
V47
U47
U46
AH48
AF48
AH47
AG47
A8
L1
AB2
C430
C430
.47U/6.3V_4
.47U/6.3V_4
2
118.8mA
+3V_VCC_HV
+VCC_RXR_DMI
+VTTLF1
+VTTLF2
+VTTLF3
852mA
C399
C399
.47U/6.3V_4
.47U/6.3V_4
C387
C387
2.2U/6.3V/X5R_6
2.2U/6.3V/X5R_6
+VCC_AXF
C444
C444
1U/6.3V/X5R_4
1U/6.3V/X5R_4
+VCC_SM_CK
C74
4.7U/6.3V_6
4.7U/6.3V_6
R403 0_6R403 0_6
C442
C442
10U/6.3V/X5R_8
10U/6.3V/X5R_8
L21 1uH/300mA_8L21 1uH/300mA_8
C392
C392
4.7U/6.3V_6
4.7U/6.3V_6
20 mil20 mil
+1.05V_VCCP
C74
1uH+-20%_300mA
R107
R107
1/F_6
C148
C148
0.1U/16V/X7R_4
0.1U/16V/X7R_4
12
C493
C493
*I@1000P/50V/X7R_4
*I@1000P/50V/X7R_4
R416 0_6R416 0_6
C477
C477
0.1U/16V/X7R_4
0.1U/16V/X7R_4
12
C509
C509
+
+
220U/2.5V_7343
220U/2.5V_7343
1/F_6
+VCC_SM_CK_L
C137
C137
10U/6.3V/X5R_8
10U/6.3V/X5R_8
C491
C491
*I@10U/6.3V/X5R_8
*I@10U/6.3V/X5R_8
int
int
+1.05V_VCCP
21
D23
D23
CH501H-40PT
CH501H-40PT
R417
R417
10_4
10_4
20 mil
Modify for C-TEST
R559 0_12R559 0_12
C499
C499
10U/6.3V/X5R_8
10U/6.3V/X5R_8
R560 0_12R560 0_12
EC C-7 /7 Del L56,L57 Add
R560,R559 1206 0 ohm.
PROJECT : AJ2
PROJECT : AJ2
PROJECT : AJ2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
C158
C158
10U/6.3V/X5R_8
10U/6.3V/X5R_8
+VCC_TX_LVDS
R426
R426
E@0_4
E@0_4
des
des
+3V_VCC_HV
105.3mA
C476
C476
0.1U/16V/X7R_4
0.1U/16V/X7R_4
1782mA
C490
C490
4.7U/6.3V_6
4.7U/6.3V_6
456mA
C498
C498
0.1U/16V/X7R_4
0.1U/16V/X7R_4
Document Number
Document Number
Document Number
Custom Cantiga (POWER)
Custom Cantiga (POWER)
Custom Cantiga (POWER)
Date: Sheet of
Tuesday, September 16, 2008
Date: Sheet of
Tuesday, September 16, 2008
Date: Sheet of
Tuesday, September 16, 2008
+VCCP_GMCH
10
R81 0_8R81 0_8
12
+
+
C79
C79
330U/2.5V_7343
330U/2.5V_7343
+1.8V_SUS
1uH+-20%_300mA
L55
L55
int
int
*I@1uH/300mA_8
*I@1uH/300mA_8
C500
C500
*I@10U/6.3V/X5R_8
*I@10U/6.3V/X5R_8
+3.3V
90 mil
90 mil
10 43
10 43
10 43
1
+1.05V_VCCP
+1.8V_SUS
20 mil
+1.05V_VCCP+VCC_PEG
+1.05V_VCCP
RevSize
RevSize
RevSize
1A
1A
1A
5
4
3
2
1
U21I
U21I
AU48
VSS_1
AR48
VSS_2
AL48
VSS_3
BB47
VSS_4
AW47
VSS_5
AN47
VSS_6
AJ47
VSS_7
D D
C C
B B
A A
5
AF47
AD47
AB47
N47
G47
BD46
BA46
AY46
AV46
AR46
AM46
V46
R46
P46
H46
F46
BF44
AH44
AD44
AA44
Y44
U44
T44
M44
F44
BC43
AV43
AU43
AM43
C43
BG42
AY42
AT42
AN42
AJ42
AE42
N42
BD41
AU41
AM41
AH41
AD41
AA41
Y41
U41
T41
M41
G41
B41
BG40
BB40
AV40
AN40
H40
E40
AT39
AM39
AJ39
AE39
N39
B39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
Y38
U38
T38
F38
C38
BF37
BB37
AW37
AT37
AN37
AJ37
H37
C37
BG36
BD36
AK15
AU36
Y47
T47
L47
J43
L42
L39
J38
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
CANTIGA_1p0
CANTIGA_1p0
VSS
VSS
4
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
3
BG21
L12
AW21
AU21
AP21
AN21
AH21
AF21
AB21
R21
M21
J21
G21
BC20
BA20
AW20
AT20
AJ20
AG20
Y20
N20
K20
F20
C20
A20
BG19
A18
BG17
BC17
AW17
AT17
R17
M17
H17
C17
BA16
AU16
AN16
N16
K16
G16
E16
BG15
AC15
W15
A15
BG14
AA14
C14
BG13
BC13
BA13
AN13
AJ13
AE13
N13
L13
G13
E13
BF12
AV12
AT12
AM12
AA12
J12
A12
BD11
BB11
AY11
AN11
AH11
Y11
N11
G11
C11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BF9
BC9
AN9
AM9
AD9
BH8
BB8
AV8
AT8
U21J
U21J
G9
B9
CANTIGA_1p0
CANTIGA_1p0
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_235
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS
VSS
VSS NCTF
VSS NCTF
VSS SCB
VSS SCB
NC
NC
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5
VSS_SCB_6
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4
BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1
U24
U28
U25
U29
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
BH48
BH1
A48
C1
B2
A3
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
PROJECT : AJ2
PROJECT : AJ2
PROJECT : AJ2
Quanta Computer Inc.
Quanta Computer Inc.
Document Number
Document Number
Document Number
Custom Cantiga (VSS)
Custom Cantiga (VSS)
Custom Cantiga (VSS)
Date: Sheet of
Tuesday, September 16, 2008
Date: Sheet of
Tuesday, September 16, 2008
Date: Sheet of
2
Tuesday, September 16, 2008
Quanta Computer Inc.
1
11
11 43
11 43
11 43
RevSize
RevSize
RevSize
1A
1A
1A
1
2
3
4
5
6
7
8
DDR2 Dual channel A/B PU
+0.9V_DDR_VTT
C141
C141
A A
0.1U/16V/X7R_4
0.1U/16V/X7R_4
Layout note: Place 1 cap close to every 1 R-pack terminated to SMDDR_VTERM.
C405
C405
C136
C136
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
DDRII A CHANNEL
C408
C408
C161
C161
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
C87
C87
C160
C160
C109
C416
C416
C448
C448
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
C109
C100
C100
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
C112
C112
C94
C94
0.1U/16V/X7R_4
0.1U/16V/X7R_4
12
+0.9V_DDR_VTT
C106
C106
C90
C90
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
B B
C C
C131
C131
0.1U/16V/X7R_4
0.1U/16V/X7R_4
DDRII B CHANNEL
C118
C118
C154
C154
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
C124
C124
C89
C83
C83
C97
C97
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
C89
C451
C451
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
Please these resistor
closely DIMMA,all
trace length<750 mil.
C150
C150
C133
C86
C86
0.1U/16V/X7R_4
0.1U/16V/X7R_4
C133
0.1U/16V/X7R_4
0.1U/16V/X7R_4
DDR_A_MA[0..13]8,13 DDR_B_MA[0..13] 8,13
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_BS18,13
DDR_A_RAS#8,13
M_ODT07,13
DDR_A_BS28,13
DDR_A_BS08,13
DDR_A_WE#8,13
DDR_A_CAS#8,13
DDR_CS0_DIMMA#7,13
DDR_CS1_DIMMA#7,13
DDR_CKE0_DIMMA7,13
DDR_CKE1_DIMMA7,13
DDR_A_MA13
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_BS0
DDR_A_MA10
DDR_A_MA2
DDR_A_MA0
DDR_A_MA1
RP47 56X2RP47 56X2
1
3
RP46 56X2RP46 56X2
1
3
RP44 56X2RP44 56X2
1
3
RP43 56X2RP43 56X2
1
3
RP17 56X2RP17 56X2
1
3
RP15 56X2RP15 56X2
1
3
RP12 56X2RP12 56X2
1
3
RP6 56X2RP6 56X2
1
3
RP4 56X2RP4 56X2
1
3
RP45 56X2RP45 56X2
1
3
R97 56_4R97 56_4
R102 56_4R102 56_4
R396 56_4R396 56_4
R100 56_4R100 56_4
R123 56_4R123 56_4
R405 56_4R405 56_4
R404 56_4R404 56_4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
+0.9V_DDR_VTT
RP16 56X2RP16 56X2
RP11 56X2RP11 56X2
RP5 56X2RP5 56X2
RP2 56X2RP2 56X2
RP13 56X2RP13 56X2
RP14 56X2RP14 56X2
RP9 56X2RP9 56X2
RP7 56X2RP7 56X2
RP3 56X2RP3 56X2
RP8 56X2RP8 56X2
R95 56_4R95 56_4
R105 56_4R105 56_4
R101 56_4R101 56_4
R98 56_4R98 56_4
R109 56_4R109 56_4
R126 56_4R126 56_4
R125 56_4R125 56_4
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA2
DDR_B_MA13
DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
DDR_B_MA12
DDR_B_MA1
DDR_B_MA3
DDR_B_MA10
DDR_B_MA4
DDR_B_MA0
SWAP
SWAP
+0.9V_DDR_VTT 33,36
DDR_B_BS1 8,13
DDR_B_RAS# 8,13
M_ODT2 7,13
Please these resistor
closely DIMMB,all
trace length<750 mil.
DDR_B_BS0 8,13
DDR_B_WE# 8,13
DDR_B_CAS# 8,13
M_ODT3 7,13M_ODT17,13
DDR_B_BS2 8,13
DDR_CS2_DIMMB# 7,13
DDR_CS3_DIMMB# 7,13
DDR_CKE3_DIMMB 7,13
DDR_CKE4_DIMMB 7,13
DDR_B_MA14 8,13DDR_A_MA148,13
DDR2 Thermal Sensor SO-DIMM 0 & 1
U4
D D
CGCLK_SMB_M2,13,26
CGDAT_SMB_M2,13,26
PM_EXTTS#07,13
PM_EXTTS#17
1
R62 *0_4R62 *0_4
U4
8
SCLK
7
SDA
6
ALERT#
4
OVERT#
*LM86CIMM
*LM86CIMM
2
VCC
DXP
DXN
GND
1
2
3
5
20 mil
R48
R48
*220_6
*220_6
LM86_3V
+3.3V
30 mil
DDR_THERMDA
DDR_THERMDC
3
Uninstall
C42
C42
*0.1U/16V/X7R_4
*0.1U/16V/X7R_4
2
+3.3V 2,5,7,8,10,13,14,15,16,17,18,19,20,21,22,23,24,26,27,30,31,32,33
13
*MMBT3904
*MMBT3904
Q14
Q14
4
PROJECT : AJ2
PROJECT : AJ2
PROJECT : AJ2
Quanta Computer Inc.
Quanta Computer Inc.
Document Number
Quanta Computer Inc.
Document Number
Document Number
Custom DDR RES. ARRAY
Custom DDR RES. ARRAY
Custom DDR RES. ARRAY
Date: Sheet of
Tuesday, September 16, 2008
Date: Sheet of
Tuesday, September 16, 2008
Date: Sheet of
5
6
Tuesday, September 16, 2008
7
12 43
12 43
12 43
8
RevSize
RevSize
RevSize
1A
1A
1A
1
A is required to route to Top
SoDIMM for AMT to
function.This will need to
change for M08
A A
DDR_CKE0_DIMMA7,12
B B
DDR_A_BS28,12
DDR_A_BS08,12
DDR_A_WE#8,12
DDR_A_CAS#8,12
DDR_CS1_DIMMA#7,12
M_ODT17,12
C C
+3.3V
D D
+1.8V_SUS
C119 0.1U/16V/X7R_4C119 0.1U/16V/X7R_4
C117 0.1U/16V/X7R_4C117 0.1U/16V/X7R_4
1
DDR2 Dual channel A/B CONN
V_DDR_MCH_REF
+1.8V_SUS
DDR_A_D0
DDR_A_D4
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D3
DDR_A_D12
DDR_A_D13
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D14
DDR_A_D11
DDR_A_D21
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DM3
DDR_A_D30
DDR_A_D31
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_D36
DDR_A_D37
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D39
DDR_A_D35
DDR_A_D41
DDR_A_D40
DDR_A_DM5
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D53
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D51
DDR_A_D50
DDR_A_D57
DDR_A_D61
DDR_A_DM7
DDR_A_D62
DDR_A_D59
CGDAT_SMB_M
CGCLK_SMB_M
CN23
CN23
1
VREF
3
VSS47
5
DQ0
7
DQ1
9
VSS37
11
DQS#0
13
DQS0
15
VSS48
17
DQ2
19
DQ3
21
VSS38
23
DQ8
25
DQ9
27
VSS49
29
DQS#1
31
DQS1
33
VSS39
35
DQ10
37
DQ11
39
VSS50
41
VSS18
43
DQ16
45
DQ17
47
VSS1
49
DQS#2
51
DQS2
53
VSS19
55
DQ18
57
DQ19
59
VSS22
61
DQ24
63
DQ25
65
VSS23
67
DM3
69
NC4
71
VSS9
73
DQ26
75
DQ27
77
VSS4
79
CKE0
81
VDD7
83
NC1
85
A16_BA2
87
VDD9
89
A12
91
A9
93
A8
95
VDD5
97
A5
99
A3
101
A1
103
VDD10
105
A10/AP
107
BA0
109
WE#
111
VDD2
113
CAS#
115
S1#
117
VDD3
119
ODT1
121
VSS11
123
DQ32
125
DQ33
127
VSS26
129
DQS#4
131
DQS4
133
VSS2
135
DQ34
137
DQ35
139
VSS27
141
DQ40
143
DQ41
145
VSS29
147
DM5
149
VSS51
151
DQ42
153
DQ43
155
VSS40
157
DQ48
159
DQ49
161
VSS52
163
NCTEST
165
VSS30
167
DQS#6
169
DQS6
171
VSS31
173
DQ50
175
DQ51
177
VSS33
179
DQ56
181
DQ57
183
VSS3
185
DM7
187
VSS34
189
DQ58
191
DQ59
193
VSS14
195
SDA
197
SCL
199
VDD(SPD)
DIMM1_9.2
DIMM1_9.2
CKE 0,1
CLOCK 0,1
2
+1.8V_SUS
2
VSS46
4
DQ4
6
DQ5
8
VSS15
10
DM0
12
VSS5
14
DQ6
16
DQ7
18
VSS16
20
DQ12
22
DQ13
24
VSS17
26
DM1
28
VSS53
30
CK0
32
CK0#
34
VSS41
36
DQ14
38
DQ15
40
VSS54
42
VSS20
44
DQ20
46
DQ21
48
VSS6
50
NC3
52
DM2
54
VSS21
56
DQ22
58
DQ23
60
VSS24
62
DQ28
64
DQ29
66
VSS25
68
DQS#3
70
DQS3
72
VSS10
74
DQ30
76
DQ31
78
VSS8
80
CKE1
82
VDD8
84
A15
86
A14
88
VDD11
90
A11
92
A7
94
A6
96
VDD4
98
PC4800 DDR2 SDRAM
SO-DIMM (200P)
PC4800 DDR2 SDRAM
SO-DIMM (200P)
A4
100
A2
102
A0
104
VDD12
106
BA1
108
RAS#
110
S0#
112
VDD1
114
ODT0
116
A13
118
VDD6
120
NC2
122
VSS12
124
DQ36
126
DQ37
128
VSS28
130
DM4
132
VSS42
134
DQ38
136
DQ39
138
VSS55
140
DQ44
142
DQ45
144
VSS43
146
DQS#5
148
DQS5
150
VSS56
152
DQ46
154
DQ47
156
VSS44
158
DQ52
160
DQ53
162
VSS57
164
CK1
166
CK1#
168
VSS45
170
DM6
172
VSS32
174
DQ54
176
DQ55
178
VSS35
180
DQ60
182
DQ61
184
VSS7
186
DQS#7
188
DQS7
190
VSS36
192
DQ62
194
DQ63
196
VSS13
198
SA0
200
SA1
3
DDR_A_DM[0..7] 8
DDR_A_D[0..63] 8
DDR_A_DQS[0..7] 8
DDR_A_DQS#[0..7] 8
DDR_A_MA[0..13] 8,12 DDR_B_MA[0..13] 8,12
DDR_A_D5
DDR_A_D1
DDR_A_DM0
DDR_A_D7
DDR_A_D2
DDR_A_D8
DDR_A_D9
DDR_A_DM1
M_CLK_DDR0 7
DDR_A_D15
DDR_A_D10
DDR_A_D20
DDR_A_D16
PM_EXTTS#0
DDR_A_DM2
DDR_A_D22
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D26
DDR_A_D27
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_MA13
DDR_A_D33
DDR_A_D32
DDR_A_DM4
DDR_A_D34
DDR_A_D38
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D43
DDR_A_D42
DDR_A_D52
DDR_A_D49
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D56
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D58
DDR_A_D63
R363
R363
10K_4
10K_4
M_CLK_DDR#0 7
DDR_CKE1_DIMMA 7,12
DDR_A_MA14 8,12 DDR_B_MA14 8,12
DDR_A_BS1 8,12
DDR_A_RAS# 8,12
DDR_CS0_DIMMA# 7,12
M_ODT0 7,12
M_CLK_DDR1 7
M_CLK_DDR#1 7
CGDAT_SMB_M2,12,26
CGCLK_SMB_M2,12,26
R365
R365
10K_4
10K_4
+3.3V
4
DDR_B_D0
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D3
DDR_B_D2
DDR_B_D9
DDR_B_D8
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D14
DDR_B_D21
DDR_B_D20
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D22
DDR_B_D23
DDR_B_D29
DDR_B_DM3
DDR_B_D26
DDR_CKE3_DIMMB7,12
DDR_B_BS28,12
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS08,12
DDR_B_WE#8,12
DDR_B_CAS#8,12
DDR_CS3_DIMMB#7,12
M_ODT37,12
DDR_B_D36
DDR_B_D34
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D38
DDR_B_D35
DDR_B_D41
DDR_B_D40
DDR_B_DM5
DDR_B_D47
DDR_B_D43
DDR_B_D53
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D55
DDR_B_D50
DDR_B_D57
DDR_B_D61
DDR_B_DM7
DDR_B_D62
DDR_B_D63
CGDAT_SMB_M
CGCLK_SMB_M
V_DDR_MCH_REF
+1.8V_SUS
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
V_DDR_MCH_REF 7,36
CN24
CN24
1
VREF
3
VSS47
5
DQ0
7
DQ1
9
VSS37
DQS#0
DQS0
VSS48
DQ2
DQ3
VSS38
DQ8
DQ9
VSS49
DQS#1
DQS1
VSS39
DQ10
DQ11
VSS50
VSS18
DQ16
DQ17
VSS1
DQS#2
DQS2
VSS19
DQ18
DQ19
VSS22
DQ24
DQ25
VSS23
DM3
NC4
VSS9
DQ26
DQ27
VSS4
CKE0
VDD7
NC1
A16_BA2
VDD9
A12
A9
A8
VDD5
A5
A3
A1
VDD10
A10/AP
BA0
WE#
VDD2
CAS#
S1#
VDD3
ODT1
VSS11
DQ32
DQ33
VSS26
DQS#4
DQS4
VSS2
DQ34
DQ35
VSS27
DQ40
DQ41
VSS29
DM5
VSS51
DQ42
DQ43
VSS40
DQ48
DQ49
VSS52
NCTEST
VSS30
DQS#6
DQS6
VSS31
DQ50
DQ51
VSS33
DQ56
DQ57
VSS3
DM7
VSS34
DQ58
DQ59
VSS14
SDA
SCL
VDD(SPD)
DIMM2_5.2
DIMM2_5.2
5
+1.8V_SUS
2
VSS46
DQ4
DQ5
VSS15
DM0
VSS5
DQ6
DQ7
VSS16
DQ12
DQ13
VSS17
DM1
VSS53
CK0
CK0#
VSS41
DQ14
DQ15
VSS54
VSS20
DQ20
DQ21
VSS6
NC3
DM2
VSS21
DQ22
DQ23
VSS24
DQ28
DQ29
VSS25
DQS#3
DQS3
VSS10
DQ30
DQ31
VSS8
CKE1
VDD8
A15
A14
VDD11
A11
A7
A6
VDD4
PC4800 DDR2 SDRAM
SO-DIMM (200P)
PC4800 DDR2 SDRAM
SO-DIMM (200P)
A4
A2
A0
VDD12
BA1
RAS#
S0#
VDD1
ODT0
A13
VDD6
NC2
VSS12
DQ36
DQ37
VSS28
DM4
VSS42
DQ38
DQ39
VSS55
DQ44
DQ45
VSS43
DQS#5
DQS5
VSS56
DQ46
DQ47
VSS44
DQ52
DQ53
VSS57
CK1
CK1#
VSS45
DM6
VSS32
DQ54
DQ55
VSS35
DQ60
DQ61
VSS7
DQS#7
DQS7
VSS36
DQ62
DQ63
VSS13
SA0
SA1
GND
202
DDR_B_D4
4
DDR_B_D1
6
8
DDR_B_DM0
10
12
DDR_B_D7
14
DDR_B_D6
16
18
DDR_B_D12
20
DDR_B_D13
22
24
DDR_B_DM1
26
28
30
32
34
DDR_B_D11
36
DDR_B_D15
38
40
42
DDR_B_D17
44
DDR_B_D16
46
48
50
DDR_B_DM2
52
54
DDR_B_D19
56
DDR_B_D18
58
60
DDR_B_D24DDR_B_D28
62
DDR_B_D25
64
66
DDR_B_DQS#3
68
DDR_B_DQS3
70
72
DDR_B_D27DDR_B_D30
74
DDR_B_D31
76
78
80
82
84
86
88
DDR_B_MA11
90
DDR_B_MA7
92
DDR_B_MA6
94
96
DDR_B_MA4
98
DDR_B_MA2
100
DDR_B_MA0
102
104
106
108
110
112
114
DDR_B_MA13
116
118
120
122
DDR_B_D37
124
DDR_B_D32
126
128
DDR_B_DM4
130
132
DDR_B_D39
134
DDR_B_D33
136
138
DDR_B_D45
140
DDR_B_D44
142
144
DDR_B_DQS#5
146
DDR_B_DQS5
148
150
DDR_B_D42
152
DDR_B_D46
154
156
DDR_B_D48
158
DDR_B_D52
160
162
164
166
168
DDR_B_DM6
170
172
DDR_B_D54
174
DDR_B_D51
176
178
DDR_B_D56
180
DDR_B_D60
182
184
DDR_B_DQS#7
186
DDR_B_DQS7
188
190
DDR_B_D59
192
DDR_B_D58
194
196
198
200
R53 10K_4R53 10K_4
R54
R54
10K_4
10K_4
6
DDR_B_DM[0..7] 8
DDR_B_D[0..63] 8
DDR_B_DQS[0..7] 8
DDR_B_DQS#[0..7] 8
M_CLK_DDR3 7
M_CLK_DDR#3 7
PM_EXTTS#0 7,12
DDR_CKE4_DIMMB 7,12
DDR_B_BS1 8,12
DDR_B_RAS# 8,12
DDR_CS2_DIMMB# 7,12
M_ODT2 7,12
M_CLK_DDR4 7
M_CLK_DDR#4 7
+3.3V
7
+1.8V_SUS
Place these Caps near So-Dimm1.
C144
C144
C103
C103
+
C182
+
C182
2.2U/6.3V/X5R_6
2.2U/6.3V/X5R_6
2.2U/6.3V/X5R_6
*330U/2.5V_7343
*330U/2.5V_7343
+1.8V_SUS
C127
C127
0.1U/16V/X7R_4
0.1U/16V/X7R_4
V_DDR_MCH_REF
C505
C505
C508
C508
0.1U/16V/X7R_4
0.1U/16V/X7R_4
+1.8V_SUS
Place these Caps near So-Dimm2.
C138
C138
C149
C149
2.2U/6.3V/X5R_6
2.2U/6.3V/X5R_6
+1.8V_SUS
C142
C142
C129
C129
0.1U/16V/X7R_4
0.1U/16V/X7R_4
V_DDR_MCH_REF
C501
C501
C507
C507
0.1U/16V/X7R_4
0.1U/16V/X7R_4
2.2U/6.3V/X5R_6
C151
C151
C95
C95
0.1U/16V/X7R_4
0.1U/16V/X7R_4
+3.3V
C47
C47
2.2U/6.3V/X5R_6
2.2U/6.3V/X5R_6
2.2U/6.3V/X5R_6
2.2U/6.3V/X5R_6
C110
C110
2.2U/6.3V/X5R_6
2.2U/6.3V/X5R_6
2.2U/6.3V/X5R_6
2.2U/6.3V/X5R_6
C99
C99
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
0.1U/16V/X7R_4
C40
C40
2.2U/6.3V/X5R_6
2.2U/6.3V/X5R_6
C101
C101
0.1U/16V/X7R_4
0.1U/16V/X7R_4
C125
C125
C132
C132
+3.3V
8
13
C113
C113
C122
C122
2.2U/6.3V/X5R_6
2.2U/6.3V/X5R_6
2.2U/6.3V/X5R_6
2.2U/6.3V/X5R_6
2.2U/6.3V/X5R_6
C107
C107
0.1U/16V/X7R_4
0.1U/16V/X7R_4
C48
C48
0.1U/16V/X7R_4
0.1U/16V/X7R_4
C140
C140
2.2U/6.3V/X5R_6
2.2U/6.3V/X5R_6
0.1U/16V/X7R_4
0.1U/16V/X7R_4
C43
C43
2.2U/6.3V/X5R_6
2.2U/6.3V/X5R_6
2.2U/6.3V/X5R_6
2.2U/6.3V/X5R_6
2.2U/6.3V/X5R_6
0.1U/16V/X7R_4
0.1U/16V/X7R_4
CKE 2,3
SMbus address A0
2
3
4
CLOCK 3,4
+3.3V 2,5,7,8,10,12,14,15,16,17,18,19,20,21,22,23,24,26,27,30,31,32,33
5
SMbus address A4
PROJECT : AJ2
PROJECT : AJ2
PROJECT : AJ2
Quanta Computer Inc.
Quanta Computer Inc.
Document Number
Quanta Computer Inc.
Document Number
Document Number
Custom DDR SO-DIMM(200P)
Custom DDR SO-DIMM(200P)
Custom DDR SO-DIMM(200P)
Date: Sheet of
Tuesday, September 16, 2008
Date: Sheet of
Tuesday, September 16, 2008
Date: Sheet of
6
Tuesday, September 16, 2008
7
13 43
13 43
13 43
8
RevSize
RevSize
RevSize
1A
1A
1A
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