Q-Tech’s flat pack crystal oscillators consist of a source
clock square wave generator, logic output buffers
and/or logic divider stages, and a round AT highprecision quartz crystal built in an all metal flat
package.
The Tristate function on pin 1 has a built-in pull-up resistor typical 50kΩ, so it
can be left floating or tied to Vdd without deteriorating the electrical performance.
Frequency vs. Temperature Curve
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tec h.com
Flat Pack (Revision F, August 2010 ) (ECO# 9934)
4
Q-TECH
45º45º
Hybrid Case
Substrate
Die
D/A epoxy
D/A epoxy
Heat
Die
R1
D/A epoxy
Substrate
D/A epoxy
Hybrid Case
R2R3R4R5
JAJCCA
Die
T
T
T
C
A
J
CA
JC
COR PORATI ON
Thermal Characteristics
The heat transfer model in a hybrid package is described in
figure 1.
Heat spreading occurs when heat flows into a material layer of
increased cross-sectional area. It is adequate to assume that
spreading occurs at a 45° angle.
The total thermal resistance is calculated by summing the
thermal resistances of each material in the thermal path
between the device and hybrid case.
FLAT PACK
CRYSTAL CLOCK OSCILLATORS
-5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.12Hz to 200MHz
RT = R1 + R2 + R3 + R4 + R5
(Figure 1)
The total thermal resistance RT (see figure 2) between the heat
source (die) to the hybrid case is the Theta Junction to Case
(Theta JC) in°C/W.
• Theta junction to case (Theta JC) for this product is 30°C/W.
• Theta case to ambient (Theta CA) for this part is 100°C/W.
• Theta Junction to ambient (Theta JA) is 130°C/W.
Maximum power dissipation PD for this package at 25°C is:
• PD(max) = (TJ (max) – TA)/Theta JA
• With TJ = 175°C (Maximum junction temperature of die)
• PD(max) = (175 – 25)/130 = 1.15W
(Figure 2)
Environmental Specifications
Q-Tech Standard Screening/QCI (MIL-PRF55310) is available for all of our Flat Packs. Q-Tech can also customize screening and test
procedures to meet your specific requirements. The Flat Packs are designed and processed to exceed the following test conditions:
Environmental TestTest Conditions
Temperature cyclingMIL-STD-883, Method 1010, Cond. B
Constant accelerationMIL-STD-883, Method 2001, Cond. A, Y1
Seal: Fine and Gross LeakMIL-STD-883, Method 1014, Cond. A and C
Burn-in160 hours, 125°C with load
Aging30 days, 70°C, ± 1.5ppm max
Vibration sinusoidalMIL-STD-202, Method 204, Cond. D
Shock, non operatingMIL-STD-202, Method 213, Cond. I
Thermal shock, non operatingMIL-STD-202, Method 107, Cond. B
Ambient pressure, non operatingMIL-STD-202, 105, Cond. C, 5 minutes dwell time minimum
Resistance to solder heatMIL-STD-202, Method 210, Cond. C
Moisture resistanceMIL-STD-202, Method 106
Terminal strengthMIL-STD-202, Method 211, Cond. C
Resistance to solventsMIL-STD-202, Method 215
SolderabilityMIL-STD-202, Method 208
ESD ClassificationMIL-STD-883, Method 3015, Class 1HBM 0 to 1,999V
Moisture Sensitivity LevelJ-STD-020, MSL=1
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tec h.com
Flat Pack (Revision F, August 2010 ) (ECO# 9934)
Please contact Q-Tech for higher shock requirements
5
Q-TECH
COR PORATI ON
Period Jitter
As data rates increase, effects of jitter become critical with
its budgets tighter. Jitter is the deviation of a timing event
of a signal from its ideal position. Jitter is complex and
is composed of both random and deterministic jitter
components. Random jitter (RJ) is theoretically unbounded and Gaussian in distribution. Deterministic jitter
(DJ) is bounded and does not follow any predictable
distribution. DJ is also referred to as systematic jitter. A
technique to measure period jitter (RMS) one standard
deviation (1σ) and peak-to-peak jitter in time domain is
to use a high sampling rate (>8G samples/s) digitizing
oscilloscope. Figure shows an example of peak-to-peak
jitter and RMS jitter (1σ) of a QT24L-20MHz, at 3.3Vdc.
FLAT PACK
CRYSTAL CLOCK OSCILLATORS
-5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.12Hz to 200MHz
Phase Noise and Phase Jitter Integration
RMS jitter (1σ): 5.75ps Peak-to-peak jitter: 60ps
Phase noise is measured in the frequency domain, and is expressed as a ratio of signal power to noise power measured in a 1Hz
bandwidth at an offset frequency from the carrier, e.g. 10Hz, 100Hz, 1kHz, 10kHz, 100kHz, etc. Phase noise measurement is made
with an Agilent E5052A Signal Source Analyzer (SSA) with built-in outstanding low-noise DC power supply source. The DC source
is floated from the ground and isolated from external noise to ensure accuracy and repeatability.
In order to determine the total noise power over a certain frequency range (bandwidth), the time domain must be analyzed in the
frequency domain, and then reconstructed in the time domain into an rms value with the unwanted frequencies excluded. This may be
done by converting L(f) back to Sφ(f) over the bandwidth of interest, integrating and performing some calculations.
Symbol
∫L(f)
Sφ (f)=(180/Π)x√2 ∫L(f)df
RMS jitter = Sφ (f)/(fosc.360°)Jitter(in seconds) due to phase noise. Note Sφ (f) in degrees.
Integrated single side band phase noise (dBc)
Spectral density of phase modulation, also known as RMS phase error (in degrees)
Definition
The value of RMS jitter over the bandwidth of interest, e.g. 10kHz to 20MHz, 10Hz to 20MHz, represents 1 standard deviation of
phase jitter contributed by the noise in that defined bandwidth.
Figure below shows a typical Phase Noise/Phase jitter of a QT24HC, 5.0Vdc, 24MHz and QT24L, 3.3Vdc, 24MHz clock at offset frequencies 10Hz to 5MHz, and phase jitter integrated over the bandwidth of 12kHz to 1MHz.
QT24HC, 5.0Vdc, 24MHz
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tec h.com
Flat Pack (Revision F, August 2010 ) (ECO# 9934)
QT24L, 3.3Vdc, 24 MHz
6
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