QPROX QT301-D, QT301-IS Datasheet

jfbkLQ QT301

RELIMINARY

 Capacitance to Analog Converter (CAC) IC

 Patented charge-transfer conversion method

 Sub-ranging Direct-to-Analog conversion

 Rescaleable PWM: wide dynamic range

 End-to-end calibration (gain, span) via CAL pins

 100 kHz PWM

 Spread spectrum acquisition bursts for low noise

 Sample on demand via Sync pin

 Only one external sample capacitor

APPLICATIONS

APACITANCE TO

CAL_DN

NALOG

SYNC 1

SNS1

 Transducer driver Moisture detection Fluid level sensors  Material sensors Position sensing Proximity sensors

ONVERTER

VDD

QT301

CAL_UP

PWM

SNS2VSS

The QT301 charge-transfer (QT) IC is a self-contained Capacitance-to-Analog-Converter (CAC) capable of detecting femotofarad level changes in capacitance. This part is designed primarily for stand-alone instrumentation applications.

Primary applications include fluid level sensors, distance sensors, material detectors, transducer amplifiers for pressure and humidity sensing functions, and other uses requiring quantified capacitance data.

Unlike other Quantum products, the QT301 does not process its acquired data. Its only output is raw, unprocessed data in filterable PWM form that can be translated into an analog voltage by a simple RC network. This allows the designer to treat the device as a CAC for measurement applications.

The PWM range is set via two inputs that control the starting and ending point of the conversion range. For example, if the capacitance range of Cx is from 27pF to 38pF, the QT301 can be calibrated so that the PWM zero point occurs at 27pF, and the endpoint (255) occurs at 38pF. In this way, the PWM range is optimized for the zone of interest. These calibration points are stored in internal EEPROM and do not have to be reacquired after a power reset. This means that the resolution of the part can be compared easily to other methods that might otherwise require 12 or more bits of overall resolution.

The device operates on demand via a sync input pin. The sync input can also be used to avoid external noise sources and cross-interference from adjacent QRG capacitive sensors. Unique among capacitance sensors, this device features spread-spectrum burst modulation, permitting extremely high noise rejection characteristics for very robust signals even in high EMI environments.

The device requires only a single sampling capacitor (Cs) to acquire signals. The value of this capacitor controls the gain of the sensor, and it can be adjusted over 2½ decades of range from 1nF to 500nF. No external switches, opamps, or other components are required.

AVAILABLE OPTIONS

8-PIN DIPSOICT

QT301-D-00C to +700C

-QT301-IS-400C to +850C

1 - Overview

3 to 5.5V

The QT301 is a digital burst mode charge-transfer (QT) capacitance-to-analog converter (CAC). It has a PWM output designed for applications such as fluid level sensing and distance gauging; the PWM signal is eight bits in resolution. The IC features two calibration inputs for end-to-end span calibration. The output depends on load (Cx) and sampling capacitor (Cs) values.

1.1 Basic Operation

The QT301 has internal EEPROM to store the two calibration points. The sensor acquires the signal from the electrode and calculates the PWM result using the two calibration points. The sensor can be calibrated via the two calibration inputs (see Section 4). The signal can be acquired either continuously or it can be synchronized on an external signal. The response time of the PWM depends largely on the acquisition burst spacing.

Figure 1-1 Basic Circuit Diagram

0.1uF

SYNC

CAL_UP

CAL_DN

PWM

166%10

VDD

VSS

SNS1

SNS2

Uppe r Cal

Lowe r Cal

PWM Out

R2R3

1.2 Basic Circuit

Figure 1-1 shows a basic circuit diagram for the QT301. The pin layout of the QT301 is as explained in Table 1-1. In this particular circuit, C1 should be 100nF and R1, R2 and R3 should all be 10K.

R1 is only required if the synchronization feature is not used and can be connected to either VDD or VSS.

Cs is recommended between 1nF and 500nF but this depends on the sensitivity required. Use either NPO or PPS capacitors for best results.

Rs is calculated with the following formula:

Rs <

where Cx is expressed in pF.

Table 1-1 Pin Description

FunctionNamePin

Sync InputSYNC1 Lower Calibration inputCAL_DN2 Sense 1 line (to electrode)SNS13 Negative supply (ground)VSS4 Sense 2 lineSNS25 PWM outputPWM6 Upper Calibration inputCAL_UP7 Positive supplyVDD8

2 - Signal Acquisition

The QT301 has a power-up delay of 200ms. During this interval it does aquire signals or generate a PWM result; it also ignores calibration inputs. This delay helps to prevent

false calibrations due to signal noise on Vdd during startup.

Figure 2-1 shows the basic QT301 acquisition timing parameters. Tbd is the burst duration, Tbs is the burst spacing from the start of one burst to the start of the next burst; when there is no Sync signal Tbs = Tbd+2.5ms.

Electrode

provides direct ADC conversion. The ADC is designed to dynamically optimize the QT burst length according to the rate of charge buildup on Cs, which in turn depends on the values of Cs, Cx, and VDD. VDD is used as the charge reference voltage.

2.1 Burst Properties

The QT301 employs bursts of charge-transfer cycles to acquire its signal. Burst mode dramatically reduces RF emissions and lowers susceptibility to EMI.

The acquisition burst operates in a band between

230kHz and 305khz. The burst is spread-spectrum modulated within this band to suppress interference from external noise sources.

The QT switches and charge measurement hardware functions are all internal to the QT301. A 16-bit single-slope switched capacitor, analog to digital converter (ADC), includes both the required QT charge and transfer switches in a configuration that

Figure 2-1 Acquisition Burst: No Sync Pulse

Tbd

Tbs

2 QT301 R1.04 21/09/03

2.2 CS / CX Dependency

The signal value is a direct function of Cs and Cx, where Cs is the fixed sample capacitor, and Cx is the unknown capacitance. These two values influence device sensitivity, resolution and response time, making them very important parameters.

Sensitivity and resolution are also a function of the size, shape, and composition of the electrode, the composition and thickness of any dielectric overlaying the electrode, the composition and aspect of the object being sensed, and the degree of mutual coupling between the electrode and the object being sensed.

2.3 Burst Length

The burst length is described by the following formula:

BL =

Where ‘k’ is a constant, typical -0.51 (this may vary slightly from device to device).

The response is thus a logarithmic curve; each doubling of Cs increases the signal level and differential sensitivity by a factor of two. Likewise, doubling Cx reduces the signal level and differential sensitivity by a factor of two (Figures 6-1, 6-2, page 8).

ln(

Cs+Cx

)

2.4 Sync Input

Bursts can be synchronized to external noise sources such as mains frequency to suppress the effects of interference coupled from such sources using a circuit such as that shown in Figure 2-6. By synchronizing with noise sources, the noise itself becomes highly correlated with the acquired data, and AC alias components effectively disappear from the signal. Sync works best on low frequency, highly repeatable signals, such as mains frequency (50/60 Hz).

Figure 2-2 shows the effect of sync pulses on the burst rate. A sync signal triggers a burst on the rising edge.

There is a Sync timeout of 100ms as shown in Figure 2-3. If Sync pulses cease for >100ms, the Sync signal will be treated as being lost and the device will start to acquire at its own default rate again. When using the Sync feature it is important that the Sync pulses are spaced less than 100ms apart.

Figure 2-2 shows the acquisition burst in relation to Sync pulses. If no rising edge is detected for 100ms, the QT301 will revert to the default timing shown in Figure 2-1. Figure 2-4 shows the sudden start of a train of Sync pulses and the effect on the acquisition bursts.

Should the sync signal overclock the acquisition bursts (Figure 2-5), the device will trigger on the next rising edge after a delay of Tbd+2.5ms.

The 2.5ms is the minimum gap between bursts is to allow Cs to properly discharge; Sync is not possible during this interval nor is it possible to re-sync during a burst.

Figure 2-2 Acquisition Burst with Sync Signal

Sync Signal

Acquisition Burst

Figure 2-3 Acquisition Burst: Sync Lost

Sync Signal

Acquisition Burst

100ms

Figure 2-4 Acquisition Burst: Sync Reacquired

Sync Signal

Acquisition Burst

Figure 2-5 Sync Overclocked

Sync Signal

Acquisition Burst

3 QT301 R1.04 21/09/03

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