QPROX QT300-D, QT300-IS Datasheet

LQ QT300

APACITANCE TO

 Capacitance to Digital Converter (CDC) IC

 Direct-to-digital conversion, 16 bits

 Log response: Wide dynamic range

 Outputs raw data to a host device

 Single wire UART interface

 Master or Slave mode SPI interface

 Programmable clock speed

 Turns objects into intrinsic touch sensors

 One external sample capacitor to control gain

 Multiple QT300’s possible on one SPI bus

The QT300 charge-transfer (“QT’”) IC is a self-contained Capacitance-toDigital-Converter (CDC) capable of detecting femotofarad level changes in capacitance. While designed primarily for instrumentation applications, it can be used also for touch control applications where signal processing is best handled by a host MCU.

Primary applications include fluid level sensors, distance sensors, transducer ‘amplifiers’ for pressure and humidity sensing functions, material detectors, and other uses requiring quantified capacitance data.

DRDY 1

SCK

SNS1

IGITAL

ONVERTER

Vdd

QT300

SDO

REQ / 1W

SNS2Vss

APPLICATIONS

 Fluid level sensors  Prox sensors  Moisture detection  Position sensing  Transducer driver  Material sensors

Unlike other Quantum products, the QT300 does not process its acquired data. Its only result is raw, unprocessed binary data which can be transmitted to a host via either a bidirectional SPI interface or a simple polled single wire UART type interface. This allows the designer to treat the device as a capacitance-to-digital-converter (CDC) for measurement applications. It is ideal for situations where there are unique signal processing requirements.

The device requires only a single sampling capacitor to function. The value of this capacitor controls the gain of the sensor, and it can be adjusted over 2½ decades of range from 1nF to 500nF. No external switches, opamps, or other components are required.

The device operates on demand, and can be synchronized to allow several QT300’s to operate near each other without cross-interference.

AVAILABLE OPTIONS

C to +700C

8-PIN DIPSOICT

QT300-D-0

-QT300-IS-400C to +850C

Table 1-1 SPI Mode Pin Description

FunctionNamePin

Data Ready/DRDY1

Serial data clockSCK2

Sense 1 lineSNS13

Negative supply (ground)VSS4

Sense 2 lineSNS25

Request input/REQ6

Serial data outSDO7

Positive supplyVDD8

Table 1-2 1W UART Mode Pin Description

FunctionNamePin

Connect to Vdd or Vss-1 Connect to Vdd or Vss-2

Sense 1 lineSNS13

Negative supply (ground)VSS4

Sense 2 lineSNS25

1W UART Line1W6

Connect to Vdd or Vss-7

Positive supplyVDD8

Table 1-3 Alternate Cloning Pin Functions

FunctionNamePin

Serial clone data clockSCK2

Serial clone data inSDI6

Serial clone data outSDO7

1 - OVERVIEW

The QT300 is a digital burst mode charge-transfer (QT) capacitance-to-digital converter (CDC) designed for applications requiring raw signal information such as fluid level sensing and distance gauging; it outputs raw digital signal data over a serial interface. The output data is in a 16-bit format; signal levels depend on load (Cx) and the sampling capacitor value (Cs).

1.1 Basic Operation

The QT300 does no internal signal processing; data is simply returned via one of two serial port types.

There are two basic types of serial interface: 4-wire SPI and a simple single wire (‘1W’) UART. The SPI interface allows multiple devices to be connected on one SPI bus, while the1W UART requires that the controller have one dedicated pin for each QT300. There are two types of SPI mode, master and slave.

The type of serial port and its mode can be selected via the cloning process using a QTM300CA programming adapter.

The QT300 operates only on request from a host device. After initiation via a trigger signal, the QT300 generates an acquisition burst and sends the resulting raw signal data back via one of the serial modes.

Vdd

SCK

SDO

Vcc

GND 4

SNS 1

SNS 2

100nF

SENSOR

DRDY

SCK

Host Micro

REQ REQ

SDI

QT 300

DRDY

Figure 1-1 Basic QT300 Circuit in SPI mode.

QT300

8 Vdd

Host Micro

(1W UART)

Vss

SNS1

SNS2

Electrode

Figure 1-2 Basic QT300 Circuit in UART mode.

1.2 CS / CX Dependency

The value returned is a direct function of Cs, the fixed sample capacitor and Cx, the unknown or variable capacitance. These two values influence device sensitivity and response time, making them very important parameters.

Sensitivity is also a function of electrode size, shape, orientation, the composition and aspect of the object being sensed, the thickness and composition of any dielectric overlaying the electrode, and the degree of mutual coupling between the electrode and the object being sensed.

The response follows a logarithmic curve (Figures 7-4, 7-5, Page 10); each doubling of Cs increases the signal level and differential sensitivity by a factor of 2. Likewise, doubling Cx reduces the signal level and differential sensitivity by a factor of 2.

2 - Timing

Figure 2-1 shows the basic QT300 acquisition timing parameters. The basic timing parameters are:

Tbd Burst duration (2.1) Tacq Acquire response time (2.2) Tbs Burst Spacing (2.3)

2.1 Tbd - Burst duration

The burst duration depends on the values of Cs and Cx and to a lesser extent, Vdd. The burst is composed of charge-transfer cycles operating at about 240kHz.

QT300 R1.01 21/09/03

The length of this burst is an important parameter as it is directly related to the signal value. The burst duration also affects the response time of the sensor; the larger Cs is, the longer the burst, the slower the possible acquisition rate.

2.2 Tacq - Acquire Response Time

The time from the /REQ or 1W line going low until the completion of data transmission is Tacq. Tacq depends on the acquisition burst length as well as the serial transmission time.

SPI Mode: In SPI mode Tacq depends in part on the serial clock speed and the space between the returned high and low bytes. In SPI slave mode the clock speed and the inter-byte spacing time Tbdly is determine by the host. In SPI Master mode these timings are set by Setup parameters SCD and MLS.

1W mode: Tacq depends in part on the Baud rate as well as the inter-byte spacing. The Baud rate is auto-set by the trigger pulse width; the inter-byte spacing is set by the MLS parameter. See Section 4.

2.3 Tbs - Burst Spacing

Burst spacing is the time from the start of one acquisition burst to the start of the next burst. It depends on the host’s trigger rate on the /REQ or 1W pin. The QT300 only acquires when the host requests it.

While waiting for a new request the part is in a low power mode.

3 - SPI Port

3.1 SPI Specifications

The QT300 can operate in master or slave mode, and thus is compatible with virtually all SPI-capable microcontrollers. The SPI interface has the following specifications:

Max clock rate, Fckm 40KHz (master mode) Max clock rate, Fcks 40KHz (slave mode) Data length 2 bytes (16 bits total) Inter-byte delay ≥8µs (master mode)*

≥12µs (slave mode) Clock idle logic level Low or High* Clock edge Data out on rising or falling edge* Data sequence High byte first, MSB first

*Determined by Setups

The host can clock the SPI at any rate up to and including the maximum. The maximum clock rate of the part in Master mode is determined in Setups via cloning.

3.2 Protocol Overview

The QT300 only transmits data on request, after an acquisition burst. The host requests an acquire by setting the /REQ line low for at least 30µs; the device then acquires. When finished, the DRDY line is pulled low by the QT300 to indicate it is ready to send data. (Figure 2-1). The transfer is done as two bytes, with the highest byte transferred first.

Figure 2-1 Signal Acquisition - Slave SPI Mode

In master mode, /DRDY goes high between bytes for the period determined by Setup parameter MLS; this is a multiple of 6µs.

When not communicating, all SPI lines float to allow multiple chips to connect over the same SPI lines. A pullup or pulldown resistor is required on SCK depending on the selected clock phase, determined by Setups. A pullup resistor is required on /DRDY. /REQ may require a pullup if the host ever allows this line to float.

3.3 SPI Bus Sharing

All SPI float transfers making it possible to have several QT300 devices (or other unrelated devices) share the SPI control signals (Figure 3-1).

Each part needs an individual /REQ line, but /DRDY, SCK and SDO can be connected together.

3.4 SPI Slave Mode

Refer to Figure 7-1 and Table 7-1, page 8.

In SPI Slave mode, /DRDY is used to let the host know when data is ready for collection in response to a request so that the host can clock over the data.

SPI Slave mode uses 4 signals:

/REQ - Request Acquisition Input; Active low input-only.

When /REQ is pulled low, the QT300 wakes and starts an acquire. The IC will transmit the resulting data only when the acquire has finished.

/REQ should return high before the end of the burst. If /REQ is still low at the end of the burst the part will go into Setup mode. The minimum duration of /REQ is 30µs.

QT300 R1.01 21/09/03

Figure 3-1 Multiple QT300's on the same SPI port

Vdd

100nF

QT 300

Vcc

QT 300

DRDY

SCK

REQ

SDO

DRDY

SCK

REQ

SDO

DRDY

SCK

REQ

SDO

100nF

SENSOR

SNS 1

SNS 2

GND 4

Vdd

Vcc

SNS 1

SNS 2

GND 4

Vdd

Vcc

SNS 1

SNS 2

GND 4

Host Micro

REQ1

REQ2

DRDY

REQ3

SCK

SDI

SDO - Serial Data Output; Output-only. This is the data

output to the host during an SPI transfer. When not in use, this pin floats. This pin should be connected to the SDI input pin of the host device.

SCK - SPI clock; Idle high or idle low; input-only SPI clock

from the host. The idle state is determined in Setups by the serial mode (SM) parameter.

If SM is set for idle-low SCK: Data is shifted out of the QT300 on the rising edge of SCK and should be shifted into the host on the falling edge of SCK.

If SM is set for idle-high SCK: Data is shifted out of the QT300 on the falling edge of SCK and should be shifted into the host on the rising edge of SCK.

The maximum clock speed is 40kHz, and the timings should obey the parameters Tskh and Tskl in Table 7-1.

/DRDY - Data Ready; active low output only. This indicates to

the host that the device is ready to send data back to the host. During idle times this pin floats and therefore must be connected to a pullup resistor. The host must wait until /DRDY goes low before starting an SPI transfer.

Between the high and low byte clockings, the host should observe a delay of ≥12µs.

A typical SPI slave mode communication sequence is:

1) Host pulses /REQ low for ≥30µs to initiate an acquire.

2) QT300 acquires a signal in response to /REQ.

3) QT300 pulls /DRDY low when ready to send data back.

4) Host detects /DRDY is low.

5) Host clocks out the high byte of data from the QT300.

6) Host waits for ≥12µs.

7) Host clocks out the low byte of data from the QT300.

8) QT300 releases /DRDY to float high.

3.5 SPI Master Mode

Refer to Figure 7-2 and Table 7-2, page 8.

In master SPI mode the QT300 generates the clock signal after an acquire initiated from the host via the /REQ line. The clock speed and the spacing between the two bytes is set via the Setup process (Section 6).

SCD setup parameter determines the master-mode clock rate. The default value is 55 (resulting in a 2.55KHz rate). The relationship is:

Fscd = 1200/(30+ (SCD x 8)) in Khz Where SCD = 0..255

MLS setup parameter determines the spacing between the two return bytes; this can be important to allow a slow host device to recover from receiving the first byte to prevent an overrun. The default value is 148 (resulting in a 500µs gap). The relationship is:

Tmls (in µs) = (10 + MLS x 4) / 1.2 Where MLS = 0..255 (from user setup MLS)

Master SPI mode requires at least 3 signals to operate:

/REQ - Request Acquisition Input; Active low input-only.

When /REQ is pulled low, the QT300 wakes and starts an acquire. The IC will transmit the resulting data only when the acquire has finished.

/REQ must return high before the end of the burst. If /REQ is still low at the end of the burst the part goes into Setup mode. The minimum duration of /REQ is 30µs.

SDO - Serial Data Output; Idle low output-only. This is the

data output to the host during an SPI transfer. When not in use, this pin floats. This pin should be connected to the SDI input pin of the host device.

SCK - SPI clock; Idle high or idle low, output-only. The idle

state is determined in Setups by the serial mode (SM) parameter.

If SM is set for idle-low SCK: Data is shifted out of the QT300 on the rising edge of SCK and should be shifted into the host on the falling edge of SCK.

If SM is set for idle-high SCK: Data is shifted out of the QT300 on the falling edge of SCK and should be shifted into the host on the rising edge of SCK.

The maximum clock speed is 40kHz, and the timings should obey the parameters Tskh and Tskl in Table 7-2.

/DRDY - Data Ready (Optional); active low output only. This

indicates to the host that the device is ready to send data

QT300 R1.01 21/09/03

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