QORVO UF3C120080B7S Datasheet

Preliminary, January 2019

Description

Features

Typical applications

Package

D2PAK-7L

United Silicon Carbide's cascode products co-package its high­performance F3 SiC fast JFETs with a cascode optimized MOSFET to
produce the only standard gate drive SiC device in the market today.

This series exhibits very fast switching using a D2PAK-7L SMD
package and the best reverse recovery characteristics of any device
of similar ratings. These devices are excellent for switching inductive
loads, and any application requiring standard gate drive.

1200V-80mW SiC Cascode

w EV charging

w PV inverters

w Switch mode power supplies

w Power factor correction modules

w Motor drives

w Induction heating

w Typical on-resistance R

DS(on),typ

of 80mW

w Maximum operating temperature of 175°C

w Excellent reverse recovery

w Low gate charge

w Low intrinsic capacitance

w ESD protected, HBM class 2

Part Number

Marking

UF3C120080B7S

UF3C120080B7S

w D2PAK-7L package for faster switching, clean gate waveforms

DATASHEET

UF3C120080B7S

D (Tab)

S (3-7)

G (1)

KS (2)

Tab

1

7

Datasheet: UF3C120080B7S Preliminary, January 2019 1

Maximum Ratings

Symbol Value Units

V

DS

1200 V

V

GS

-25 to +25 V

28.8 A
21 A

I

DM

77 A

E

AS

58.5 mJ

P

tot

190 W

T

J,max

175 °C

TJ, T

STG

-55 to 175 °C

T

L

250 °C

1. Limited by T

J,max

2. Pulse width tp limited by T

J,max

3. Starting TJ = 25°C

Thermal Characteristics

Min Typ Max

R

qJC

0.61 0.79 °C/W

Units

Parameter

Symbol

Test Conditions

Value

Thermal resistance, junction-to-case

Gate-source voltage

DC

Max. lead temperature for soldering,

1/8” from case for 5 seconds

Power dissipation

TC = 25°C

Maximum junction temperature

Operating and storage temperature

TC = 25°C

Pulsed drain current

2

TC = 25°C

Single pulsed avalanche energy

3

L=15mH, IAS =2.8A

I

D

TC = 100°C

Continuous drain current

1

Parameter

Test Conditions

Drain-source voltage

Datasheet: UF3C120080B7S Preliminary, January 2019 2

Electrical Characteristics (TJ = +25°C unless otherwise specified)

Typical Performance - Static

Min Typ Max

BV

DS

1200 V

0.7 75

3

I

GSS

6

20

mA

80 100

172

V

G(th)

3.5 4.5 5.5 V

R

G

4.2

W

Typical Performance - Reverse Diode

Min Typ Max

I

S

28.8 A

I

S,pulse

77 A

1.5 2

2

Q

rr

140 nC

t

rr

23 ns

Q

rr

118 nC

t

rr

19 ns

Reverse recovery charge
Reverse recovery time

VR=800V, IF=20A,

VGS=-5V, R

G_EXT

=22W

di/dt=2800A/ms,

TJ=25°C

Reverse recovery charge

VR=800V, IF=20A,

VGS=-5V, R

G_EXT

=22W

di/dt=2800A/ms,

TJ=150°C

Reverse recovery time

Drain-source on-resistance

R

DS(on)

mW

Parameter

Symbol

Test Conditions

Value

Units

Gate threshold voltage

VDS=5V, ID=10mA

Gate resistance

f=1MHz, open drain

Forward voltage

V

FSD

VGS=0V, IF=10A,

TJ=25°C

V

VGS=0V, IF=10A,

TJ=175°C

Diode continuous forward current

1

TC=25°C

Diode pulse current

2

TC=25°C

VGS=0V, ID=1mA

VDS=1200V,

VGS=0V, TJ=25°C

VDS=1200V,

VGS=0V, TJ=175°C

Parameter

Symbol

Test Conditions

Value

Units

mA

Total drain leakage current

I

DSS

VDS=0V, TJ=25°C,

VGS=-20V / +20V

VGS=12V, ID=20A,

TJ=25°C

VGS=12V, ID=20A,

TJ=175°C

Drain-source breakdown voltage

Total gate leakage current

Datasheet: UF3C120080B7S Preliminary, January 2019 3

Typical Performance - Dynamic

Min Typ Max

C

iss

754

C

oss

97

C

rss

0.8

C

oss(er)

54 pF

C

oss(tr)

122

pF

E

oss

17.3

mJ

Q

G

23

Q

GD

5

Q

GS

11

t

d(on)

33

t

r

7

t

d(off)

30

t

f

9

E

ON

340

E

OFF

48

E

TOTAL

388

t

d(on)

31

t

r

6

t

d(off)

30

t

f

8

E

ON

312

E

OFF

42

E

TOTAL

354

Gate-source charge

Gate-drain charge

VDS=800V, ID=20A,

VGS = -5V to 12V

nC

Total gate charge

Total switching energy

Turn-on delay time

VDS=800V, ID=20A,

Gate Driver =-5V to

+12V,

Turn-on R

G,EXT

=8.5W,

Turn-off R

G,EXT

=22W

Inductive Load,

FWD: same device with

VGS = -5V, RG = 22W,

TJ=150°C

ns

Rise time

Turn-off delay time

Fall time

Turn-on energy

mJ

Turn-off energy

Total switching energy

Effective output capacitance, time
related

VDS=0V to 800V,

VGS=0V

C

OSS

stored energy

VDS=800V, VGS=0V

mJ

ns

Turn-off energy

Fall time

Turn-on energy

VDS=800V, ID=20A,

Gate Driver =-5V to

+12V,

Turn-on R

G,EXT

=8.5W,

Turn-off R

G,EXT

=22W

Inductive Load,

FWD: same device with

VGS = -5V, RG = 22W,

TJ=25°C

Turn-on delay time

Rise time

Turn-off delay time

Value

Units

Reverse transfer capacitance

Effective output capacitance, energy
related

VDS=0V to 800V,

VGS=0V

pF

Parameter

Symbol

Test Conditions

Input capacitance

Output capacitance

VDS=100V, VGS=0V

f=100kHz

Datasheet: UF3C120080B7S Preliminary, January 2019 4

Typical Performance Diagrams

Figure 1. Typical output characteristics at TJ = ­55°C, tp < 250ms

Figure 2. Typical output characteristics at TJ = 25°C,
tp < 250ms

Figure 3. Typical output characteristics at TJ = 175°C,
tp < 250ms

Figure 4. Normalized on-resistance vs. temperature
at VGS = 12V and ID = 20A

0

10

20

30

40

50

60

0 1 2 3 4 5 6 7 8 9 10

Drain Current, I

D

(A)

Drain-Source Voltage, VDS(V)

Vgs = 15V
Vgs = 8V
Vgs = 7V
Vgs = 6.5V
Vgs = 6V

0

10

20

30

40

50

60

0 1 2 3 4 5 6 7 8 9 10

Drain Current, I

D

(A)

Drain-Source Voltage, VDS(V)

Vgs = 15V
Vgs = 8V

Vgs = 7V
Vgs = 6.5V
Vgs = 6V

0

10

20

30

40

50

60

0 1 2 3 4 5 6 7 8 9 10

Drain Current, I

D

(A)

Drain-Source Voltage, VDS(V)

Vgs = 15V
Vgs = 8V
Vgs = 7V
Vgs = 6V
Vgs = 5.5V
Vgs = 5V

0.0

0.5

1.0

1.5

2.0

2.5

-75 -50 -25 0 25 50 75 100 125 150 175

On Resistance, R

DS_ON

(P.U.)

Junction Temperature, TJ(°C)

Datasheet: UF3C120080B7S Preliminary, January 2019 5

Figure 5. Typical drain-source on-resistances at VGS =
12V

Figure 6. Typical transfer characteristics at VDS = 5V

Figure 7. Threshold voltage vs. junction temperature
at VDS = 5V and ID = 10mA

Figure 8. Typical gate charge at VDS = 800V and ID =
20A

0

50

100

150

200

250

300

0 10 20 30 40 50 60

On-Resistance, R

DS(on)

(mW)

Drain Current, ID(A)

Tj = 175°C
Tj = 25°C
Tj = - 55°C

0

10

20

30

40

50

60

0 1 2 3 4 5 6 7 8 9 10

Drain Current, I

D

(A)

Gate-Source Voltage, VGS(V)

Tj = -55°C

Tj = 25°C

Tj = 175°C

0

1

2

3

4

5

6

-100 -50 0 50 100 150 200

Threshold Voltage, V

th

(V)

Junction Temperature, TJ(°C)

-5

0

5

10

15

20

0 10 20 30 40

Gate-Source Voltage, V

GS

(V)

Gate Charge, QG(nC)

Datasheet: UF3C120080B7S Preliminary, January 2019 6

Figure 10. 3rd quadrant characteristics at TJ = 25°C

Figure 11. 3rd quadrant characteristics at TJ = 175°C

Figure 12. Typical stored energy in C

OSS

at VGS = 0V

Figure 9. 3rd quadrant characteristics at TJ = -55°C

-30

-25

-20

-15

-10

-5

0

-4 -3 -2 -1 0

Drain Current, I

D

(A)

Drain-Source Voltage, VDS(V)

Vgs = -5V
Vgs = 0V
Vgs = 5V
Vgs = 8V

-30

-25

-20

-15

-10

-5

0

-4 -3 -2 -1 0

Drain Current, I

D

(A)

Drain-Source Voltage, VDS(V)

Vgs = - 5V
Vgs = 0V
Vgs = 5V
Vgs = 8V

-30

-25

-20

-15

-10

-5

0

-4 -3 -2 -1 0

Drain Current, I

D

(A)

Drain-Source Voltage, VDS(V)

Vgs = - 5V
Vgs = 0V
Vgs = 5V
Vgs = 8V

0

10

20

30

40

0 200 400 600 800 1000 1200

E

OSS

(mJ)

Drain-Source Voltage, VDS(V)

Datasheet: UF3C120080B7S Preliminary, January 2019 7

Figure 13. Typical capacitances at f = 100kHz and
VGS = 0V

Figure 14. DC drain current derating
Figure 15. Total power dissipation

Figure 16. Maximum transient thermal impedance

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

0 200 400 600 800 1000 1200

Capacitance, C (pF)

Drain-Source Voltage, VDS(V)

C

iss

C

oss

C

rss

0

5

10

15

20

25

30

35

-75 -50 -25 0 25 50 75 100 125 150 175

DC Drain Current, I

D

(A)

Case Temperature, TC(°C)

0

50

100

150

200

-75 -50 -25 0 25 50 75 100 125 150 175

Power Dissipation, P

tot

(W)

Case Temperature, TC(°C)

0.001

0.01

0.1

1

1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01

Thermal Impedance, Z

qJC

(°C/W)

Pulse Time, tp(s)

D = 0.5
D = 0.3
D = 0.1
D = 0.05
D = 0.02
D = 0.01
Single Pulse

Datasheet: UF3C120080B7S Preliminary, January 2019 8

Figure 17. Safe operation area at TC = 25°C, D = 0,
Parameter t

p

Figure 18. Clamped inductive switching energy vs.
drain current at TJ = 25°C

Figure 19. Clamped inductive switching turn-on
energy vs. R

G,EXT_ON

Figure 20. Clamped inductive switching turn-off
energy vs. R

G,EXT_OFF

0.1

1

10

100

1 10 100 1000

Drain Current, I

D

(A)

Drain-Source Voltage, VDS(V)

1ms

10ms

100ms

1ms

DC

10ms

0

100

200

300

400

500

0 5 10 15 20 25

Turn-on Energy, E

ON

(mJ)

Total External RG,

RG,EXT_ON

(W)

VDD= 800V, VGS= -5V/12V

ID= 20A, TJ= 25°C
FWD: same device with
VGS= - 5V, RG= 22W

0

20

40

60

80

100

120

0 20 40 60 80 100

Turn-Off Energy, E

OFF

(mJ)

Total External RG,

RG,EXT_OFF

(W)

VDD= 800V, VGS= -5V/12V
ID= 20A, TJ=25°C
FWD: same device with
V

GS

= -5V

0

100

200

300

400

500

600

700

800

0 5 10 15 20 25 30 35

Switching Energy (

mJ)

Drain Current, ID(A)

Etot
Eon
Eoff

VDD= 800V, VGS= -5V/12V

R

G_ON

= 8.5W, R

G_OFF

= 22W

FWD: same device with VGS=

-5V, RG= 22W

Datasheet: UF3C120080B7S Preliminary, January 2019 9

Applications Information

Disclaimer

Like other high performance power switches, proper PCB layout
design to minimize circuit parasitics is strongly recommended due to
the high dv/dt and di/dt rates. An external gate resistor is
recommended when the cascode is working in the diode mode in
order to achieve the optimum reverse recovery performance. For
more information on cascode operation, see www.unitedsic.com.

United Silicon Carbide, Inc. reserves the right to change or modify
any of the products and their inherent physical and technical
specifications without prior notice. United Silicon Carbide, Inc.
assumes no responsibility or liability for any errors or inaccuracies
within.

Figure 21. Clamped inductive switching energy vs.
junction temperature at VDS = 800V and ID = 20A

United Silicon Carbide, Inc. assumes no liability whatsoever relating
to the choice, selection or use of the United Silicon Carbide, Inc.
products and services described herein.

Figure 22. Reverse recovery charge Qrr vs. junction
temperature

SiC cascodes are enhancement-mode power switches formed by a
high-voltage SiC depletion-mode JFET and a low-voltage silicon
MOSFET connected in series. The silicon MOSFET serves as the
control unit while the SiC JFET provides high voltage blocking in the
off state. This combination of devices in a single package provides
compatibility with standard gate drivers and offers superior
performance in terms of low on-resistance (R

DS(on)

), output

capacitance (C

oss

), gate charge (QG), and reverse recovery charge

(Qrr) leading to low conduction and switching losses. The SiC
cascodes also provide excellent reverse conduction capability
eliminating the need for an external anti-parallel diode.

Information on all products and contained herein is intended for
description only. No license, express or implied, to any intellectual
property rights is granted within this document.

0

50

100

150

200

250

300

350

400

0 25 50 75 100 125 150 175

Switching Energy (

mJ)

Junction Temperature, TJ(°C)

Etot
Eon
Eoff

VGS= -5V/12V, R

G_ON

= 8.5W,

R

G_OFF

= 22W, FWD: same device

with VGS= -5V, RG= 22W

0

50

100

150

0 25 50 75 100 125 150 175

Qrr (nC)

Junction Temperature, TJ(°C)

VDD= 800V, IS= 20A,

di/dt = 2800A/ms,

VGS= -5V, RG=22W

Datasheet: UF3C120080B7S Preliminary, January 2019 10