Q MAC Electronics HF90 User Manual
No part of this manual may be copied, transcribed, translated or reproduced in any manner or form
whatsoever, for commercial purposes, without obtaining prior written permission from Q-MAC
Electronics Pty Ltd. However, limited copying is permitted for private use providing authorship is
acknowledged.
© Copyright Q-MAC Electronics Pty Ltd, 2003.
142 Hasler Road
Osborne Park, WA 6017
PO Box 1334
Osborne Park Business Centre, WA 6916
AUSTRALIA
Australia: Phone 08 - 9242 2900, Fax 08 - 9242 3900
International: Phone +618 - 92242 2900, Fax +618 - 9242 3900
Print date: August 1996
Print date: February 1997
Print date: October 2000
Author: Rod Macduff
Literature Reference Number: TECH02C.PUB
Part Number: QM1021
First Edition
Second Edition
Third Edition
Additional Technical Support:
Note that additional technical support is available to Q-MAC Dealers under the “Dealer Support”
section of the Q-MAC website: www.qmac.com
. This site incorporates Technical Bulletins issued by
Q-MAC, plus Technical Notes and Instructions in relation to specif ic produ ct s.
- 1 -
TABLE OF CONTENTS
Section 1 Warnings & advice
..............................................................................................4
Section 2 Introduction
........................................................................................................... 5
Section 3 Product specification
........................................................................................ 6
Section 4 Mechanical assembly
.........................................................................................7
Section 5 Functional overview
...........................................................................................8
Section 6 Block diagrams
Microprocessor..........................................................................................................11
Receiver/exciter.........................................................................................................12
Synthesizers...............................................................................................................13
Power amp & switching P.S.U..................................................................................14
Front panel.................................................................................................................10
Section 7 Circuit description
7.1 Front panel PCB...............................................................................................15
7.2 RXMP PCB ....................................................................................................16
7.3 PASW PCB ....................................................................................................21
Section 8 Tables & diagrams
Diagram 1. Serial link chain ....................................................................................25
Table 2.
Diagram 2. Superhet. mixing scheme......................................................................26
Diagram 3. HF-90 Rx gain distribution...................................................................26
Table 3. HF-90 Tx low pass filters......................................................................27
Table 4. HF-90 connector pinouts.......................................................................28
Diagram 4. Connector positions...............................................................................30
Table 1. HF-90 micro port allocations................................................................24
Section 9 Maintenance
9.2 Replacement of Microprocessor.......................................................................32
9.3 Radio alignment................................................................................................33
9.1 Disassembly & assembly..................................................................................31
Section 10 Fault finding
10.1 No tools fault finding......................................................................................36
Section 11 Diagnostic test sequence
11.2 Transmitter test sequence ...............................................................................43
11.1 Receiver test sequence....................................................................................39
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Section 12 Test point overlays
12.1 RXMP test point voltages...............................................................................45
HF-90 P.A. board alignment - position reference......................................................46
Section 13 Software overview
13.2 Routine description (not frequency hopping).................................................48
13.3 Software releases............................................................................................50
13.1 Program description........................................................................................47
Section 14 Hints & tips
14.2 Servicing warnings.........................................................................................52
14.1 Device removal...............................................................................................51
14.3 Servicing case histories...................................................................................53
Section 15 Parts List
15.1 Front panel PCB parts list (ISSUE N)............................................................60
15.2 RXMP PCB parts list (ISSUE V)...................................................................61
15.3 PASW PCB parts list (ISSUE Q)...................................................................67
Section 16 PCB overlays
Front panel top overlay - issue N (designators).........................................................72
Front panel top overlay - issue N (component values)..............................................73
RXMP top overlay - issue V (designators)................................................................74
RXMP top overlay - issue V (component values).....................................................75
PASW top overlay - issue Q (designators)................................................................76
PASW top overlay - issue Q (component values).....................................................77
Section 17 Schematic diagrams
HF-90 I.F. strip, micro section & synth (90003).......................................................80
HF-90 P.A. & power supply (90002)........................................................................81
HF-90 display (90000)...............................................................................................79
Section 18 External connectors
.........................................................................................82
Section 19 Device pinouts & codes
Device pinouts...........................................................................................................84
19.1 SMD capacitor codes......................................................................................85
- 3 -
1. WARNINGS & ADVICE
1. On no account should the unit be connected directly to 110volt or 240volt AC mains
power. Serious damage or personal injury may result.
2. An approved 12volt or 24volt power supply or battery should be used. The supply
should be capable of sourcing peak currents up to 10ampere. Failure to comply with
this rating will result in severe distortion on transmissions. Please note that some
power supplies labeled as 10ampere peak are not adequate as the voltage collapses
towards the peaks.
3. Use only the approved power cable for installation. Use of thinner conductors or
extensions will result in severe distortion on transmissions.
!
!
4. The system performance is generally only as good as the antenna and ground system
will allow. If unbalanced antennas are being used eg. whips, end-fed broadbands etc,
then it is vital to obtain a good low impedance ground connection either to a vehicle
body, a moist patch of ground or a metal fence with rust removed at the point of
connection.
5. The HF-90 is extremely small. When transmitting, the heatsink and extrusion may get
very hot. Under some circumstances it may be possible to get burned by touching the
heatsink. The radio has been designed and tested to cope with elevated temperatures.
However the user should endeavour to allow free circulation of air around the radio.
6. In order to achieve the high output power, an internal power convertor is used to
supply +55volt to the final amplifier on transmit. The energy stored by this supply is
quite high (2.2joules) and it is wise to WAIT FOR A FULL MINUTE after
transmitting prior to doing any service work on the PASW printed circuit board.
7. Radio Frequency Field Exposure: The HF-90 Packages generate high radio frequency
fields. Their antennas are marked with a safe working distance in accordance with
required Standards. This should be observed.
8. This device complies with Part 90 of the FCC Rules. Operation is subject to the
condition that this device does not cause harmful interference.
- 4 -
2. INTRODUCTION
The HF-90 Compact Transceiver breaks new ground in the following areas:
Size: The volume of the transceiver is approximately one litre. This is less than a tenth of
comparable products. On initial inspection it is often mistaken for a VHF/UHF set.
Weight: At 1 kilogram, the HF-90 is a quarter of the weight of products with a similar
specification.
Ease of use: The HF-90 has quite deliberately been kept simple so that persons unfamiliar
with HF communications may immediately pick it up and use it.
Low cost: The transceiver has been designed using state of the art SMD technology.
Components from cellular telephony, satellite television, and personal computers have been
used wherever possible to keep the cost at a minimum. Also, wherever possible,
functionality has been implemented in software rather than hardware.
Ruggedness: Use of a heavily ribbed aluminium extrusion confers great strength to the
HF-90. Stainless steel handles protect all front panel controls. A ribbed rear heatsink
protects the rear connectors.
Reliability: Use of SMD technology and the delegation of functionality to software has led
to simplicity of design which translates to high reliability. Unreliable parts such as
potentiometers and wiring looms are avoided. All internal connectors have gold to gold
mating surfaces.
Serviceability: The HF-90 was designed with serviceability as a top priority. The radio
consists of three PCBs, all of which plug together. Only four screws need be removed to
access the main PCBs. These PCBs plug together as a ‘sandwich’ with all the essential
components and nodes easily probeable while the radio is operating, without the use of
extenders. All power transistors are easily accessed and use single screw fixing.
Minimised inventory: The design of the HF-90 was implemented with the minimum
number of different types of components. Thus spares inventory is reduced.
Versatility: The high performance and small size allows the HF-90 to be used in portable,
mobile or fixed configurations. The wide power supply range (12 to 24volt) makes it
particularly attractive in multi-role applications.
Receiver performance: Excellent receive sensitivity is combined with a large dynamic
range through the use of four GaAs FETs in the front end mixer.
Transmit ter performance: A very high power to weight ratio and extreme RF ruggedness
is obtained through the use of 500volt MOS FETs in the power amplifier.
Selcall performance: A sophisticated digital signal processing algorithm is capable of
extracting very weak calls in the presence of noise. Successful decodes at down to -132dBm
have been observed.
- 5 -
3. PRODUCT SPECIFICATION
General
Frequency range: 2 ! 30MHz
Modes of operation: USB, LSB (J3E)
Number of channels: 255
Channel resolution: 100Hz
Supply voltage: 12 ! 24V DC nominal
Power consumption:
- Transmit: 2A! 10A
- Receive: 310mA
Frequency stability: ± 1.5ppm
Antenna impedance:
Antenna connector: BNC
Handsets: Speaker microphone
Selcall system: Based on CCIR 493-4
Programming: IBM PC 4800,8,1,N
BITE: Micro, Rx, Tx tests
Environmental
Operating temperature: -30ºC ! 60ºC
Storage temperature: -30ºC ! 80ºC
Humidity: 95% non-condensing
Environmental rating: IP54
Physical characteri st ics
Dimensions (mm): 112(W) x 47(H) x 220(D)
Weight: 1kg (HF-90 only)
Construction: All metal extruded sleeve
Finish: Black anodized aluminium
CW (optional)
Hopping (optional)
AM (Rx only), FSK
(subject to pre-set power
output)
50Ω
DTMF microphone
& telephone handset
(Australian Standard)
with front panel and
heatsink
Transmitter
Power output: 50Wat t PEP
Duty cycle: Normal speech or data
Unwanted sideband: Better than -45dB
Carrier suppression: Better than -50dB
Harmonic suppression: Better than –60dB
Spurious emissions: Better than –60dB
Noise suppression: Better than -35dB
Distortion: Less than 5% @ 70% PEP
Audio response: 270Hz ! 2800Hz
Microphone: Electret insert
Tune: >20W radiated @ +1000Hz
Load protection: ALC
Receiver
Sensitivity: 0.25µV for 10dB S+N/N
Selectivity: 2.3 kHz @ -6dB
Image rejection: Better than -50dB
Intermodulation: Better than -70dB
3rd order intercept: +20dBm (GaAs FET
Blocking: Better than -70dB
Spurious response: Better than -60dB
IF rejection: Better than -60dB
Intermediate freq’s: 83.16MHz, 455kHz
AGC: Less than 3dB
Clarifier range: ± 250Hz
Audio response: 270Hz ! 2800Hz
Audio output: 2Watt
Audio load impedance:
Audio distortion: Less than 5% @ 1W
(with fan option)
6kHz @ -60dB
mixer)
from 3µV ! 1V
8Ω
Specifications are subject to change without notice
- 6 -
4. MECHANICAL ASSEMBLY
Radio construction
The radio shell comprises a 2.5mm aluminium front plate complete with black stainless steel
handles, a 160mm long key-ribbed sleeve extrusion and a 10-fin extruded rear heatsink. This
provides a simple and strong housing for the radio. Four M3x12 screws are used to secure
both front and rear panels. The display PCB is secured to the metal front-plate by the fixing
nuts of three front panel parts. This allows for simple removal. The two main PCBs pug into
each other as a ‘sandwich’, and the whole assembly slides into the extruded sleeve on
keyways. The rear heatsink is part of the PASW board assembly. Rubber gaskets on the
front and rear mating surfaces give some water resistance.
Front panel
The front panel allows manual control of all the radio functions. This is achieved by six
elastomer keys, an incremental shaft encoder (volume) and a toggle switch for power
activation. A high efficiency 6-digit 7-segment LED display indicates the channel number
on receive and frequency on transmit. An 8-pole microphone socket provides all the external
interface requirements for m icrophones , headphon es, D TMF keyp ad, and comput er inte rf ace.
The front panel can be removed by undoing the four screws on the front of the radio and
pulling gently on the handles. It can be further disassembled by simply undoing the two hex
grub screws on the volume knob and unscrewing the volume, on/off switch and microphone
socket n uts. The elastomer ke ys and f ibregl ass key se parat or shoul d be left i n the keyho les.
The gold keyp ad s ar e pl ac ed on a sma ll su b-bo ar d a bove th e di s pla y PCB . S ix p ins hol d t his
small keypad in place.
RXMP board
This board has no direct connections to the outside world. It mates both mechanically and
electrically with the PASW board via four 10-way connectors. It also mates via two of the
10-way connectors with the display PCB. There is one unused 10-way pin field for test use.
When mated with the PASW board it slides into the extruded sleeve on keyways.
PASW board
The PASW board incorporates the rear heatsink extrusion as part of its assembly. The
heatsink contains the BNC antenna connector and the 4-pole power receptacle. The heatsink
is attached to the PCB by virtue of the heavy connections to the power receptacle and the 18
power transistor leads. The PASW board mates with the RXMP board via four 10-way
connectors but has no connection to the display PCB.
- 7 -
Front panel
Refer to the block diagram (FRONT PANEL) in Section 6 of this manual.
The only electronic parts of significance on the display PCB belong to the display register
and multiplexor. All other parts merely route signals from the keys, microphone socket,
volume encoder etc to the main two PCBs via a pair of 10-way connectors.
RXMP PCB
This board incorporates three distinct functional blocks, the Microprocessor, Receiver/
Exciter and Synthesizer.
Microprocessor
Refer to the block diagram (MICROPROCESSOR) in Section 6 of this manual.
This section contains the 8-bit microcontroller along with its address latch, battery backed
RAM, data memory and glue logic. For simpl icity, communi cation wit h peripheral devices
is via a serial 3-wire bus. This bus sends data to the display, volume DAC, transmit low pass
filters and power control. A separate data line feeds the synthesizer. Computer I/O and
Selcall data in, also share the same serial ports. The keypad is read via a 5-wire matrix and
the volume encoder has a 2-line quadrature input plus interrupt. A DTMF decoder handles
tones from the microphone and utilises a memory mapped interface.
Receiver/Exciter
Refer to the block diagram (RECEIVER/EXCITER) in Section 6 of this manual.
The receiver/exciter section is configured as a double superhet with first IF at 83.160MHz
and second IF at 455kHz. The same circuit is used on receive and transmit apart from the
second IF processor. Relays re-route the signal on transmit through the first IF. The other
circuit elements are bi-directional. LO1 and LO2 are synthesizer derived. The carrier
insertion oscillator at 453.6kHz or 456.4kHz is counted down from the LSB or USB crystal.
Synthesizer
Refer to the block diagram (SYNTHESIZER) in Section 6 of this manual.
The first local oscillator uses a high level push-pull circuit. It covers a 30MHz span and is
controlled by one half of the frequency synthesizer running at a high comparison frequency
to obtain low phase noise. The second local oscillator is a simple single ended unit covering
a 20kHz span, controlled by the other half of the frequency synthesizer. The Selcall decoder
uses a PLL and data slicer to demodulate the FSK signal.
PASW PCB
Refer to the block diagram (POWER AMP & SWITCHING PSU) in Section 6 of this manual.
The PASW board contains the main power supplies and the transmitter power train. A
shielded +5volt switching power supply provides power for most of the RX and logic and a
+10volt linear supply is also provided. On transmit a +50volt switching power supply is
active. The transmit power train comprises two RF Op-Amps, the first of which is ALC
controlled, then a driver stage and final amplifier, both of which use MOS FETs. One out of
six harmonic filters is selected by a darlington driver.
5. FUNCTIONAL OVERVIEW
- 8 -
6. BLOCK DIAGRAMS
Please refer to the following pages for block diagrams .....
- 9 -
REFER BLOCK DIAGRAM
“HF-90 RADIO BLOCK DIAGRAM - FRONT PANEL”
IN FILE NAMED “HF90BFP.xxx”
- 10 -
REFER BLOCK DIAGRAM
“HF-90 RADIO BLOCK DIAGRAM - MICROPROCESSOR”
IN FILE NAMED “HF90BMCP.xxx”
- 11 -
REFER BLOCK DIAGRAM
“HF-90 RADIO BLOCK DIAGRAM RECEIVER / EXCITER”
IN FILE NAMED “HF90BRXE.xxx”
- 12 -
REFER BLOCK DIAGRAM
“HF-90 RADIO BLOCK DIAGRAM - SYNTHESIZERS”
IN FILE NAMED “QMAPAPS.xxx”
- 13 -
REFER BLOCK DIAGRAM
“HF-90 RADIO BLOCK DIAGRAM POWER
AMP & SWITCHING P.S.U.”
IN FILE NAMED “HF90BPAP.xxx”
- 14 -
7. CIRCUIT DESCRIPTION
7.1 Front panel PCB
Refer to the schematic diagram (HF-90 DISPLAY 90000) in Section 17 of this manual.
The front panel PCB contains a 6-digit 7-segment LED display, 6-button keypad matrix, on/
off switch, volume control and microphone socket. It measures 35mm x 95mm and contains
eight integrated circuits.
Display data is contained within a 6-byte serial shift register (U1 - U6) and the display is
refreshed at one sixth of the 7kHz clock rate by the multiplex counter (U8 & U25).
The displ ay is updated from t he microproc essor via a 3-wire serial interfa ce (TOC, SCK &
DIS). A fourth line DSIRO allows the microprocessor to check for serial link integrity.
The 7-segment display sections (U18 - U23) are extremely compact and efficient resulting in
excellent readability and endurance.
An incremental shaft encoder (VR1) controls the volume level on the Standard and
Advanced Model HF-90 and allows a flexible user interface for possible future options. It
gives 24 detents (clicks) per revolution.
The computer programming interface utilises D1 and Q2 to achieve compatibility with IBM
PC Clone RS232C ports, operating at 4800N81 (4800 baud, no parity, eight data, one stop).
A simple auxiliary PCB contains the 5-line, 6-button keypad matrix. TR and BR (top and
bottom row) carry negative going key scan pulses at 250Hz repetition rate. RCL, MCL and
LCL (right, middle and bottom column) are inputs allowing the key presses to be read by the
microprocessor.
The microphone socket allows use of an unbalanced electret microphone, telephone style
handset with PTT, a DTMF keypad and an RS232C programming link.
A single pole on/off switch activates the power relay on the PASW PCB (power amplifier
and switch mode power supply PCB), by switch closure to ground.
- 15 -
7.2 RXMP PCB
Refer to the schematic diagram (HF-90 I.F. STRIP , MICRO SECTION & SYNTH. 90003) in Section
17 of this manual. Applies to RXMP boards of issue U and beyond.
The RXMP PCB is the heart of the radio and condenses a high degree of functionality into a
small board area.
The two main functional blocks on this board are the microprocessor and the receiver. Large
sections of the receiver are re-used on transmit to generate the drive for the PASW PCB. This
minimises unnecessary replication of circuitry. The RXMP PCB measures 100mm x 147mm
and contains 30 integrated circuits.
Microprocessor architecture
A minimal number of components are used as a result of the following:
" Delegation of functionality to software, wherever possible.
" Extensive re-use of ports.
" Utilisation of a simple serial interface.
" Use of a microprocessor with embedded code and separate data memory.
The microprocessor core consists of the microprocessor (U1), the non-volatile data memory
(U2), and the low address latch (U3). D24 gates the battery backed RAM enabling it during
RAM reads and writes.
DTMF detector
The DTMF chip (U9) flags data valid on pin 14 when keys on the DTMF microphone are
pushed. The microprocessor activates the DTMFE line when it is ready to read the DTMF
code. The DTMF chip is memory mapped at address #8000H and diode D1 disables the
battery backed RAM when a DTMF read occurs.
A full table of microprocessor port allocations is shown in Table 1 (Section 8 of this manual).
Serial links
There are two separate serial data paths which share a common data and clock signal (TOC
and SCK) but have different enable lines (SYN and DIS).
One of these serial links has been described in Section 7.1 (Front panel PCB), however it
services other registers besides the display. It loops back onto the RXMP PCB and controls
the miscellaneous register and volume control. It then loops through the PASW PCB where
it controls the PA low pass filter selection and power selection. Finally, it loops back to the
microprocessor where it can be sampled to check the link.
The second serial data signal is the synthesizer loader. This is fed to U16 setting the
frequency of LO1 and LO2.
The display enable and clock are also used to increment the signal strength meter ramp
counter, which is active on every display write.
A hardware and software summary of these two serial links is contained in Diagram 1 and
Table 2, respectively (Section 8 of this manual).
- 16 -
Interrupts
The microprocessor runs three interrupts:-
1. The incremental shaft encoder interrupt on INT1 (volume set).
2. An internal software interrupt on Timer 0, TICKINT which wakes up the
microprocessor from an idle state every 2ms (or 666µs in hop mode). This is the
‘heartbeat’ of the radio and it ticks at all times except during computer
communication.
3. An internal software interrupt on Timer 1, TIMER1INT which provides timing for all
tones generated by the radio on receive and transmit.
The RS232 serial I/O programming link is not run as an interrupt driven service. It is
operated as a scheduled polled service.
Although PTT input to the microprocessor is fed into pin INT0, the interrupt on this pin is
disabled and instead the pin is polled. It is also a PTT output.
Shaft encoder
Quadrature drives to the shaft encoder from QUAD1 and QUAD2 allow the detection of
turning direction and velocity, by line INT1. The change in volume is output via the serial
link to the shift register (U11) setting the gain DAC (U13).
Clarifier
The clarifier on receive is implemented entirely in software adjusting the synthesizer in 25Hz
increments over ±250Hz.
Receiver and synthesizers
The receiver architecture comprises a double conversion superheterodyne with intermediate
frequencies of 83.16MHz and 455kHz. Two high-side local oscillators (LO1 and LO2) mix
down to 83.16MHz and 455kHz respectively.
The local oscillators are controlled by a dual frequency synthesizer which allow coverage of
2 - 30MHz in 100Hz steps.
Mixing scheme
Diagram 2 (Section 8 of this manual) shows the HF-90 superheterodyne mixing scheme.
Synthesizer Part 1
Synthesizer Part 1 controls LO1. The synthesizer chip (U16) utilises an internal dual
modulus prescaler to obtain a high operating frequency (85 - 113MHz), along with a high
phase comparison frequency (47 - 202kHz). The synthesizer is designed for low phase noise
and the loop filter (R25, C96, C99) is optimized for low phase comparison sideband level.
The high comparison rate gives the synthesizer a very rapid lock time of 3ms. The nonlinear amplifier (Q10, Q14, Q15, Q16, Q22) linearises the overall system gain to maintain
consistent noise performance across the VCO span.
- 17 -
LO1
LO1 is a high level (+13dBm) low phase noise VCO providing the injection source for Mixer
1. It employs push-pull JFETS (Q6, Q7) and an amplitude stabilisation circuit (D7, D8, Y1,
Y2, Y7, Y8). Fast inverters (U29 E and F) provide hard switching and load isolation.
Synthesizer Part 2
Synthesizer Part 2 (U16) employs a single chip synthesizer to stabilize the injection
frequency of LO2. It has an on-board prescaler and requires only the external loop filter
(C85, C77, R83, R4, C46). The frequency of LO2 is controlled in 200 100Hz steps over a
20kHz span.
LO2
LO2 employs a Vackar circuit with a very narrow span. It provides a +7dBm injection level
for Mixer 2 using a single JFET (Q8). A fast inverter (U30C) and a 3dB pad provide hard
switching and load isolation. Capacitor C212 is a 33p N470 type, to achieve temperature
compensation from -30ºC to +60ºC.
Front end
A 5-element elliptic low pass filter band limits the receiver input signal and suppresses
leakage from LO1 on transmit and receive.
A high-level GaAs FET mixer (Q1, Q2, Q3, Q4) provides a low loss, high 3IP performance
to obtain excellent sensitivity and dynamic range. This mixer incorporates proprietary
architecture. Being essentially a passive element, the mixer is reciprocal and operates in the
reverse direction in transmit mode. Diodes D14 and D27 provide front end protection.
First IF
The first IF chain comprises F1, Q5 & U21, with associated components. The active
components are switched in direction between receive and transmit by a relay pair (RL1 &
RL2). This ensures optimum IMD performance on both receive and transmit.
Saw filter
Selectivity with a bandwidth of 30kHz is provided by the first IF filter (F1). Use of a SAW
device allows very smooth passband performance with deep transmission zeros on the image
frequency of the second IF. The tank circuits associated with L5 and L6 provide impedance
matching for the filter which has a Zo of 800Ω.
Active devices (Q5 and U21) provide the AGC controlled gain in the first IF. The Op-Amp
(U20) stabilises the bias current in the GaAs FET. The GaAs FET is characterised by
excellent linearity and ultra low noise.
Mixer 2
The second mixer uses a diode ring module (M1) to mix to 455 kHz. Because it is passive, it
functions as a reciprocal device, operating in the reverse direction on transmit.
- 18 -
Filter 2
The ultimate selectivity of 2.4kHz @ 3dB points is provided by ceramic filter (F2). This
device has a Zo of 2kΩ. Matching on transmit and receive is performed by 5mm transformer
(T8).
Tx/Rx switch
Bilateral switch (U22) routes the signal through the final IF processor chip (U23) on receive
and direct from the double balanced mixer on transmit. It also handles the transmit and
receive audio paths ensuring correct audio switching to/from the double balanced mixer
(U24).
455 kHz IF processor
The IF processor chip (U23) provides up to 100dB gain at 455kHz and provides 100dB of
AGC range. U19C and Q11 along with C131, C22 and C174, implement hang AGC
appropriate to SSB signals. Two different decay times, fast and slow, are available by
switching MOS FET Q25.
Double balanced mixer
The double balanced mixer (U24) provides greater than 50dB of carrier suppression on
transmit and highly linear demodulation on receive. As previously described, bilateral switch
(U22) performs the signal routing to enable th is to happen.
Carrier insertion oscillator
To generate and receive a single sideband signal a carrier insertion oscillator is required. On
USB this operates at 453.6kHz and on LSB the frequency is 456.4kHz. It is derived from
oscillator (U6), which has selectable crystals (X3 & X4). The oscillator operates on
7257.6kHz or 7302.4kHz for USB and LSB respectively. The CIO frequency emerges from
output Q4 of counter U7, after division by 16. Counter U7 also provides a 7kHz clock to run
the charge pump, 25volt & -5volt supplies and the display multiplex clock.
Gain distribution
Diagram 3 (Section 8 of this manual) shows the HF-90 system gain distribution.
Receive audio chain
The recovered audio of pin 6 of the double balanced modulator (U24) is routed through a
switch (U22) to the gain stage (U25B). This provides 30dB gain, taking AGC level signals
up to 2volt p-p.
The audi o pat h fe eds thr ough th e vo lu me co nt rol DAC o nwa rd t o t he o utp ut amp l ifie r (U 28 ).
The DIL audio amplifier yields 2watt, or more if the radio is operating from higher than
12volt.
The amplifier (U27:B) provides a limiting signal to the Selcall decoder (U18).
- 19 -
Selcall decoder
The Selcall decoder uses an on-frequency PLL with a VCO centre frequency of 1700 Hz. An
XOR phase comparator (PCI) is used for noise rejection. The recovered data signal appears
on the loop filter (R32, R128, C127, C129). It is then fed to a data slicer which has an
adaptive reference level (pin 6 U19:A). This ensures that off-frequency signals will be
satisfactorily recovered since the reference is the mean signal deviation. The data is sent on
its way to the microprocessor as SELD.
The switching transistor (Q12) disables the Selcall output (SELD) when SELE is taken high
by output PL3/Pin 7 on the PASW PCB. This allows the computer the use of the FROMC
line during programming.
Microphone amplifier
The microphone amplifier (U25:A) provides a differential balanced input allowing common
mode rejection. Inputs from TR and BR allow tone modulation for the emergency alarm,
being added at the virtual earth. Input from the microphone is via a 600Ω transformer (T7)
which provides isolation. The microphone amplifier has a feed to DTMF chip U9.
Automatic audio level control
The ALC chip (U26) works on transmit to maintain a near constant output level of 2volt p-p
when the audio output is beyond a certain threshold set by R73. In this way the best radiated
signal to noise ratio is maintained. The transmit audio signal (TXA) is routed through U22 to
pin 4 of the double balanced mixed (U24). A diode clipper (D18,C173) prevents any
transient overshoot.
Receiver voltage supplies
The main +5volt supply is switch mode derived on the PASW PCB. The main +10volt
supply is from a linear regulator on the PASW PCB.
Low current supplies at +25volt and -5volt are derived from a charge pump circuit
(comprising U8, D2, D6, D16, D17 and D19). The charge pump is clocked at 7kHz by the
CIO counter (U7).
Low battery detector
The comparator (U4B and A) detects when the 10volt regulator loses regulation and pulls the
LOBAT line low, signaling low battery level. At present this signal is not used by the radio.
Signal strength meter
The signal strength meter comprises counter U14, DAC U15 and comparator U4:C. The
counter is clocked and enabled by the display serial line. During display write the counter is
clocked and when the DAC ramp crosses the AGC level comparator U4:C, output feeding
RCL is pulled low. In this way the microprocessor can measure signal level.
- 20 -
7.3 PASW PCB
Refer to the schematic diagram (HF-90 P.A. & POWER SUPPLY 90002) in Section 17 of this
manual.
This printed circuit board contains the power stages of the transmitter and all the radio power
supplies. It measures 100mm x 147mm and contains nine integrated circuits. Four MOS
FETS and two power transistors are mounted on the mechanically connec ted rea r heat sink .
The HF-90 breaks new ground in obtaining excellent transmitter intermodulation distortion,
low broadband noise and PA economy, through the use of high voltage MOS FETs in the PA
and driver stages. The necessary supply rails are provided by low EMI switch mode power
supplies.
Power supplies
Tx supply switches
The darlington driver (U8) inverts the PTT / line to switch series pass transistor (Q11) which
keys up the +5 Tx supply.
+5volt supply
A simple switcher chip (U9) along with D10, L2 and C80, provide a high efficiency +5volt
output from a wide range of input voltages (10 - 28volt). Chokes (L1 and L3) with
associated decoupling capacitors minimise electromagnetic emission. The unit is enclosed
by a shield to further reduce interference.
+10volt supply
This relatively low current +10volt supply is obtained by sitting a 5volt regulator (U10) on
the +5volt rail. The regulator is a low dropout type requiring only 0.2volt of headroom.
+15volt supply
This supply should be more correctly designated the +11.4volt limiter since its function is to
maintain an output voltage in the range 10 - 11.4volt, irrespective of input voltage.
The series pass transistor (Q13) is hard on until U3:A detects that its output has risen to
+11.4volt. Thereafter it is held in regulation. It is keyed on only in transmit by using the
+5volt supply as a reference. Its function is to limit supply voltage to U4 and MOSFET
drivers (Q1 & Q2).
+50volt Tx supply
The +50volt Tx supply is a classic boost convertor utilising energy storage choke (L5),
switches (Q5 and Q6), and a rectifier (D5). The switch mode controller chip (U4) monitors
the output voltage via voltage divider (R7 & R8) comparing it against a 5volt reference to
obtain an error duty cycle on the gates of Q5 and Q6. The chokes (L4 & L6) with their
associated decoupling capacitors yield a low EMI design. Some supply droop will occur on
speech peaks.
Tx amplifier (pre-driver)
The current mode Op-Amps (U1 & U11) each provide +16dB of gain with low output
impedance, wide bandwidth and excellent linearity. They drive the driver MOS FET gates
through a balanced transformer (T4). the MOS FET (Q9) in the feedback circuit of U11
controls the stage gain. This permits ALC of the PASW unit.
- 21 -
Bias circuit
Bias for both the driver and PA MOS FETs is derived from a source which is effectively an
amplified thermal junction pedestal (Q8 and Q12). VR1 is the driver bias pot and VR2 is the
PA bias pot. These references are buffered by Op-Amps (U2:A and U3:B) which have gains
of three and five respectively. Device Q12 is in direct thermal contact with PA MOS FET
Q3, and device Q8 is in direct thermal contact with Q4 in order to obtain a thermal
coefficient of bias which is slightly negative, thus ensuring thermal stability.
PA drivers
The PA driver circuit uses MOS FETs (Q1 and Q2) running from the +15volt limited supply
(+11.4volt). Negative feedback networks (C57, R43, R90, C56, R88 & R44) fix the gain of
the stage at 20dB. The 10R input resistors (R37 & R55) suppress parasitics. The bifilar feed
transformer (T1) provides a DC cancelled supply isolation.
The transmission line transformer (T5) yields a 4:1 impedance step-down to provide final
output MOS FETs (Q3 & Q4) with a high current source for gate drive.
PA final output
The final output architecture is similar to that of the drivers, with negative feedback and
parasitic stoppers. The difference lies in the supply voltage and output matching. The PA
transistors operate from a +50volt rail, achieving isolation from supply by a DC cancelled
bifilar choke (T2). An output transmission line transformer (T3) combines the output signals
and provides balance-to-unbalance conversion. Impedance conversion is unnecessary since
the PA matches directly to 50Ω. Polyswitches (Negative TC Thermistors) in series with the
source leads of the output MOS FETs Q3 and Q4, wind back the output power when the
temperature on the heatsink exceeds 80°C.
PA low pass filters
Harmonic attenuation of the transmitter output signal is implemented through the six 5element elliptic low pass filters. Latching relays (RL3 - RL8) select the sub-octave filters
according to Table 3 (Section 7 of this manual).
Relay drive circuit
Selection of the set or reset coil for activation is implemented via seven darlington drivers
(U6). The address information is loaded down the DIS serial data line into a shift register
(U5) and this drives the darlington driver (U6). When a frequency change occurs the
common reset line is pulsed, then the specific set line is pulsed. In the static condition no
current is consumed by the relays. Latching takes place through application of a 5ms pulse.
Tx RF ALC
The forward and reverse current are sampled by a 16:1 current transformer (L19) and
detector diodes (D1 and D2). These provide references for the ALC circuit. Potentiometer
VR3 sets the power level by manipulating the fraction of signal fed to U3:B.
Low power select deactivates the +50V supply by grounding pin 2 on U4.
ALC time constants are determined by C34, R95 and R96. A diode (D3) combines the
- 22 -
forward and reverse signals and the Op-Amp (U2:B) provides system gain in the ALC
feedback loop. The gain controlled RF amplifier (U11) in the first stage of the PASW PCB
is fed with the ALC output signal via Q7.
ATU PSU switch
A software keyed +12 - 28volt supply is provided on the rear 4-pin connector to allow the
interfacing of a TA-90 automatic antenna tun er, a horn ala rm or flashing beacon.
Reverse / over-voltage / under-voltage protection
A tranzorb diode (D7) provides reverse and 33volt clamp protection. An external fuse must
be fitted. Diodes D4 and D6, in series with the power on relay activation coil, ensure that the
radio will not power up if the supply is accidentally reverse polarised. The relay also
guarantees that the radio will switch off completely below 9.5volt, thus protecting the
connected battery against over discharge.
- 23 -
8. TABLES & DIAGRAMS
Table 1. HF-90 micro port allocations
Port Number Micro Pin Input Function Output Function
P0.0 43 D0 / DTMF Q0 A/D0
P0.1 42 D1 / DTMF Q1 A/D1
P0.2 41 D2 / DTMF Q2 A/D2
P0.3 40 D3 / DTMF Q3 A/D3
P0.4 39 D4 A/D4
P0.5 38 D5 A/D5
P0.6 37 D6 A/D6
P0.7 36 D7 A/D7
P1.0 2 TOP ROW TONE 1 OUTPUT
P1.1 3 SIG METER INPUT RIGHT COLUMN
P1.2 4 DTMF NOT VALID MIDDLE COLUMN
P1.3 5 LEFT COLUMN
P1.4 6 BOTTOM ROW TONE 2 OUTPUT
P1.5 7 SYNTH. CLOCK
P1.6 8 SYNTH. ENABLE
P1.7 9 DISPLAY ENABLE
P2.0 24 A8
P2.1 25 A9
P2.2 26 A10
P2.3 27 A11
P2.4 28 A12
P2.5 29 DTMF ENABLE
P2.6 30 (A14)
P2.7 31 (A15)
P3.0 11 RXD SE RIAL DATA/
SELCALL IN
P3.1 13 TXD ALL SERIAL DATA
P3.2 14 INT0/PTT IN PTT OUT
OUT
P3.3 15 INT1/ENCODER
P3.4 16 T0 QUAD IN
P3.5 17 T1 QUAD IN
P3.6 18 WR EXT DATA
P3.7 19 RD EXT DATA
Note:- ALE latches Port 0 address
- 24 -
Diagram 1./Table 2. Serial link chain
Diagram 1. Physical hardware
LED
100Hz
(TOC)
SDIN
LED
1kHz
LED
10kHz
SCK
DIS
Front Panel PCB RXMP
The serial link chain comprises 10, 8-bit serial shift registers with common serial clock
(SCK), select display (DIS) lines and cascade data (TOC).
Serial data is clocked through the shift registers by SCK and when 80 bits of data have gone
through, the enable DIS is pulsed high and the data is parallel loaded to internal latches.
Table 2. Software byte allocation
Byte 0
LED
100kHz
LED
1MHz
LED
10MHz
Miscellaneous
DAC
100 Hz display
Volume
DAC
PA Filter
Switch
Power
Setting etc.
Loop
Back
PASRO
PASW
(last byte)
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
1 kHz display
10 kHz display
100 kHz display
1 MHz display
10 MHz display
BIT 6 BIT 1
1 = MIC INHIBIT 1 = AGC SLOW
BIT 0
1 = USB, 0 = LSB
Bits 0 to 7 volume in range 00H - FFH (LOW = LOW VOL)
BIT7
NIL
BIT6
BAND1
BIT5
BAND6
BIT4
BAND2
BIT3
BAND5
BIT2
BAND3
BIT1
BAND4
BIT0
RESET
PA Filter
Band
Select
Disable
Byte 9
loopback
Disable
Selcall
NIL NIL +50V
OFF
Low
power
ATU
ON
NIL
(1st byte)
- 25 -
Diagram 2. Superhet. mixing scheme
3740 USB 453.6 CIO
86900 kHz
LO1
83613.6
LO2
Diagram 3. HF-90 Rx gain distribution
-0.5dB -5dB -4dB +20dB +20dB -8dB -6dB +16dB +80dB
LPF 4 x GaAS SAW
83.160 MHz
LO1
85.113 MHz
ATF
13736
ERA3
LO2
83.615 MHz
+/-10 kHz
TDA
1572
STAGE 1
CERAMIC
455 kHz
USB 453.6 kHz
LSB 456.4 kHz
TDA
1572
STAGE 2
CIO
Sensitivity = 0.25uV @ 10dB S+N/N
3I/P = +20dBm
3dB AGC knee = 1uV
- 26 -
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