Pqi COMPACTFLASH CARD User Manual

Datasheet

Product ： CompactFlash Card

Part Number： 6ACJ-XXXXRXXXX

Description ： CompactFlash Card

Release Date ： 2010.07.19

Customer ：

Customer approve：

Approved

Prepared by

LEVEL Person

DSC10007 Rev. A.1 July. 2010

Datasheet

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Note：

1. Please sign-off or stamp with company-seal on the Delivery Specification and return
the original copy back to PQI.

2. To change Delivery Specification contents or descriptions must be negotiated with PQI in
advance. Any changes made will be result in the issuing of a revised version to be signed-off
or stamp with company-seal.

3. Products that are not in agreement of prior conditions or purposes, please notify your PQI
contact window in advance.

4. PQI strives to provide quality products and excellent reliability but nevertheless, malfunction
is a nature of semi-conductor. Therefore, in addition to product quality, all designs are aimed to
provide protection from causing personal harm, fire, endangering the public, etc.

5. This is a general semi-conductor / electronic product (personal computer, general purpose
stationary goods, quantitative machine, general household electronics, etc.). Therefore, its
intended purposes is not for use when it is damaged or incorrectly operated (human error)
which may result in bodily harm (eg. intended use not for medical equipments, nuclear, aviation
and transportation controllers). PQI shall not be held liable if the product is used coincide with
machineries described not for intended use.

6. The “Delivery Notice” states product specifications, instruction manual, etc. PQI does not
guarantee the violation of third party intellectual property rights.

7. This product is not to be use or sold in overseas countries where legislations states such
products may be banned or restricted.

PQI shall not be held liable for any damages, expenses, loss of profit as a result from the purchase,

use or incorrect operation, whether it may be accidental or consequential. PQI’s guarantee only

extends to the repair, exchange or refund of the purchased product.

DSC10007 Rev. A.1 July. 2010

Datasheet

CompactFlash Card

6ACJ-XXXXRXXXX

DSC10007 Rev. A.1 July. 2010

Datasheet

Table of Contents

1. Description ................................................................................................................................ 1

2. Features ..................................................................................................................................... 1

3. Interface Description ................................................................................................................ 2

4. Access specification................................................................................................................. 9

5. ATA Command Set .................................................................................................................. 28

6. Electrical specification ........................................................................................................... 32

7. AC characteristic..................................................................................................................... 34

9. Physical outline....................................................................................................................... 50

DSC10007 Rev. A.1 July. 2010

CompactFlash Card

1. Description

6ACJ-XXXX newly redesigned CompactFlash™ offers a sustained speed of 600x. This card complies with

CompactFlash™ specification; it is suitable for the usage of data storage memory for PC or other electric equipment

and digital still camera. This card is equipped with NAND flash memory. By using this card it is possible to operate
stability for the system that have CompactFlash™ slots.
PQI CompactFlash cards offer the perfect combination of speed, capacity, and reliability.
The CFC setting to Fixed or Removable mode will no any function different or issue.

2. Features

 Flash memory card capacity support list below:

¾ 8GB
¾ 16GB
¾ 32GB

¾ 64GB

 CompactFlash™ specification: CF4.1,PCMCIA ver.2.1 and PC Card ATA ver.2.01 compatible 50pin SMT connector

and type I (3.3mm).

 3.3V/5V single power supply operation.
 Internal self-diagnostic program operates at VCC power on.
 3 variations of access mode:

¾ Memory Card Mode.
¾ I/O Card Mode.
¾ True-IDE Mode.

 True IDE Mode supports:

¾ Ultra DMA Modes: 0, 1, 2, 3, 4, 5 and 6.
¾ PIO Modes: 0, 1, 2, 3, 4, 5, and 6.

¾ Multi-Word DMA Modes 0, 1, 2, 3 and 4.
 Improve high-end UDMA DSLR & PC Host Performance
 High reliability based on internal ECC (Error Correcting Code) Function.
 Wear-leveling support

¾ Adjustable delta value

¾ Stable delta value by erase count increase
 MTBF: 3,000,000 hours
 Operation Temperature range: 0 to 70 ℃. Storage Temperature range: -40 to 85 ℃.
 Speed Type:

¾ 600X.

Notes: The performance will depend on different platform with different test result.

Rev. A.1 1/50 July. 2010

CompactFlash Card

3. Interface Description

3.1 Card pin Assignment

Pin No.

Signal name I/O Signal name I/O Signal name I/O Signal name I/O

1
2
3
4
5
6
7
8

9
10
11
12
13
14

15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

GND

D3 I/O D3 I/O D3 I/O D3 I/O
D4 I/O D4 I/O D4 I/O D4 I/O
D5 I/O D5 I/O D5 I/O D5 I/O
D6 I/O D6 I/O D6 I/O D6 I/O
D7 I/O D7 I/O D7 I/O D7 I/O

-CE1 I
A10 I

-OE I

A9
A8 I
A7

VCC

A6 I
A5 I
A4 I
A3 I
A2 I
A1 I
A0 I
D0 I/O D0 I/O D0 I/O D0 I/O
D1 I/O D1 I/O D1 I/O D1 I/O
D2 I/O D2 I/O D2 I/O D2 I/O

WP O -IOIS16 O -IOIS16 O -IOIS16 O

-CD2 O -CD2 O -CD2 O -CD2 O

-CD1 O -CD1 O -CD1 O -CD1 O
D11 I/O D11 I/O D11 I/O D11 I/O
D12 I/O D12 I/O D12 I/O D12 I/O
D13 I/O D13 I/O D13 I/O D13 I/O
D14 I/O D14 I/O D14 I/O D14 I/O
D15 I/O D15 I/O D15 I/O D15 I/O

-CE2 I -CE2 I -CS1 I -CS1 I

-VS1 O -VS1 O -VS1 O -VS1 O

-IORD I

-IOWR I

-WE I

RDY/-BSY O -IREQ O INTRQ O INTRQ O

VCC

-CSEL I -CSEL I -CSEL I -CSEL I

-VS2 O -VS2 O -VS2 O -VS2 O

RESET I RESET I -RESET I -RESET I

-WAIT O -WAIT O IORDY O IORDY O

-INPACK O -INPACK O RFU O DMARQ O

-REG I -REG I RFU I -DMACK I
BVD2 I/O -SPKR I/O -DASP I/O -DASP I/O
BVD1 I/O -STSCHG I/O -PDIAG I/O -PDIAG I/O

D8 I/O D8 I/O D8 I/O D8 I/O
D9 I/O D9 I/O D9 I/O D9 I/O

D10 I/O D10 I/O D10 I/O D10 I/O

GND

True IDE mode Memory card mode I/O card mode

PIO mode Multi-word DMA mode

－

GND

－

GND

－

GND

-CE1 I -CS0 I -CS0 I
A10 I A10 I A10 I

-OE I -ATASEL I -ATASEL I

I

A9

I

A9

I

A9

A8 I A8 I A8 I

I

－

A7

VCC

I

－

A7

VCC

I

－

A7

VCC

A6 I A6 I A6 I
A5 I A5 I A5 I
A4 I A4 I A4 I
A3 I A3 I A3 I
A2 I A2 I A2 I
A1 I A1 I A1 I
A0 I A0 I A0 I

-IORD I -IORD I -IORD I

-IOWR I -IOWR I -IOWR I

-WE I -WE I -WE I

－

－

VCC

GND

－

－

VCC

GND

－

－

VCC

GND

－

I

I

－

－

－

Rev. A.1 2/50 July. 2010

CompactFlash Card

3.2 Card pin Description

Signal Name Dir Pin No. Description

A10 to A0
(PC Card Memory Mode)

A10 to A0
(PC Card I/O Mode)

A2 to A0
(True IDE Mode)

BVD1
(PC Card Memory Mode)

-STSCHG
(PC Card Memory Mode)

-PDIAG
(True IDE Mode)

BVD2
(PC Card Memory Mode)

-SPKR
(PC Card / I/O Mode)

-DASP
(True IDE Mode)

-CD1,-CD2
(PC Card Memory Mode)

-CE1,-CE2
(PC Card I/O Mode)

-CE1,-CE2
(PC Card I/O Mode)

-CS0,-CS1
(True IDE Mode)

-CSEL
(PC Card Memory Mode

-CSEL
(PC Card I/O Mode)

-CSEL
(True IDE Mode)

8,10,11,12,14,15,16,17,18,19,20

I

18,19,20

I/O 46

I/O 45

O 26,25

I 7,32

I 39

These address lines along with the-REG signal are
used to select the following: The I/O port address
registers within the CompactFlash Storage Card or
CF + Card, the memory mapped port add address
registers within the CompactFlash Storage Card or
CF+ Card , a byte in the card’s information structure
and its configuration control and status registers.
In True IDE Mode only A {2:0} are used to select the
one of eight registers in the Task File. The
remaining address lines should be grounded by the
host.
This signal is asserted high as BVD1 is not
supported
This signal is asserted low to alert the host to
changes in the RDY/-BSY and Write Protect states;
while the I/O interface is configured. Its use is
controlled by the Card Configured and Status
Register.
In the True IDE Mode, this input/output is the Pass
Diagnostic signal in the Master/Slave handshake
protocol.
This signal is asserted high, as BVD2 is not
supported.
This line is the Binary AUDIO OUTPUT FROM THE
CARD .if the Card does not support the Binary
Audio function, this line should be held negated.
In the True IDE Mode, this input/output is the Disk
Active/Slave Present signal in the Master/Slave
These Card Detect pins are connected to ground on
the CompcatFlash Storage Card or CF + Card.
They are used by the host to determine that the
CompactFlash Storage Card or CF +Card is fully
inserted into its socket.
These input signals are used both to select the card
and to indicate to the card whether a byte or a word
operation is being performed. –CE2 always
accesses the odd byte of the word depending on A0
and –CE2. A multiplexing scheme based on
A1.-CE1,-CE2 allows 8 bit hosts to access all data
on D0 to D7.
See Access specification below.
In the True IDE Mode CS0 is the chip select for the
task file registers while CS1 is used to select the
Alternate Status Register and the Device Control
Register.
This signal is not used for this mode.

This internally pulled up signal is used to configure
this device as a Master or a Slave when configured
in the True IDE Mode. When this pin is grounded,
this device is configured as a Master. When the
pins is open, this device is configured as a Slave.

Rev. A.1 3/50 July. 2010

CompactFlash Card

Signal Name Dir Pin No. Description

D15 to D00
(PC Card Memory Mode)

D15 to D00
(PC Card I/O Mode)

D15 to D00
(True IDE Mode)

GND
(PC Card Memory Mode)

GND
(PC Card I/O Mode)

GND
(True IDE Mode)

-INPCAK
(PC Card Memory Mode)

-INPACK
(PC Card I/O Mode)

Reserved
(True IDE Mode

for PIO)

DMARQ
(True IDE Mode for
Multi-word DMA)

31,30,29,28,27,49,48,47,6,5,4,3,2,23,

I/O

22,21

─ 1,50

O 43

These lines carry the Data, Commands and Status
information between the host and the controller.D00
is the LSB of the Even Byte of the Word.D08 is the
LSB of the Even Byte of the Word.D08 is the LSB of
the Odd Byte of the Word.
True IDE Mode, all Task File operations occur in
byte mode on the low order bus D00 to D07 while
all data transfers are 16 bit using D00 to D15.
Ground

This signal is not used in this mode.

The Input Acknowledge signal is asserted by the
CompactFlash Storage Card or CF +Card when the
card is selected and responding to an I/O read
cycle at the address that is on the address bus. This
signal is used by the host to control the enable of
any input data buffers between the CompactFlash
Storage Card or CF +Card and the CPU.
In True IDE Mode this output signal is not used and
should not be connected at the host.

This signal is a DMA Request that is used for DMA
data transfers between host and device. It shall be
asserted by the device when it is ready to transfer
data to or from the host. For Multiword DMA
transfers, the direction of data transfer is controlled
by –IORD and –IOWR. This signal is used in a
handshake manner with –DMACK, i.e., the device
shall wait until the host asserts –DMACK before
negating DMARQ, and reasserting DMARQ if there
is more data to transfer.
DMARQ shall not be driven when the device is not
selected.
While a DMA operation is in progress, -CS0 and
–CS1 shall be held negated and the width of the
transfers shall not be 16 bits.
If there is no hardware support for DMA mode in the
host, this output signal is not used and should not
be connected at the host. In this case, the BIOS
must report that DMA mode is not supported by the
host so that device drivers will not attempt DMA
mode.
A host that does not support DMA mode and
implements both PCMCIA mode and True-IDE
modes of operation need not alter the PCMCIA
mode connections while in True-IDE mode as long
as this does not prevent proper operation in any
mode.

Rev. A.1 4/50 July. 2010

CompactFlash Card

Signal Name Dir Pin No. Description

-IORD
(PC Card Memory Mode)

-IORD
(PC Card I/O Mode)

-IORD
(True IDE Mode)

-IOWR
(PC Card Memory Mode)

-IOWR
(PC Card I/O Mode)

-IOWR
(True IDE Mode)

-OE
(PC Card Memory Mode)

-OE
(PC Card I/O Mode)

-ATA SEL
(True IDE Mode)

RDY/BSY
(PC Card Memory Mode)

-IREQ
(PC Card I/O Mode)

INTRQ
(True IDE Mode)

I 34

I 35

I 9

O 37

This signal is not used in this mode.

This is an I/O Read strobe generated by the host.
This signal gates I/O data onto the bus from the
CompactFlash Storage Card or CF +Card when the
card is configured to use the I/O interface.

In True IDE Mode, this signal has same function as
in PC Card I/O Mode.

This signal is not used in this mode.

The I/O Write strobe pulse is used to clock I/O data
on the Card Data bus into the CompcatFlash
Storage Card or CF +Card controller registers when
the CompactFlash Storage Card or CF +Card is
configured to use the I/O interface. The clocking will
occur on the negative to positive edge of the signal
(Trailing edge)
In True IDE Mode, this signal has the same function
as in PC Card I/O Mode.

This is an Output Enable strobe generated by the
host interface. It is used to read data from the
CompactFlash Storage Card or CF +Card in
Memory Mode and to read the CIS and
configuration registers.
In PC Card I/O Mode. This signal is used to read
the CIS and configuration registers.

To enable True IDE Mode this input should be
grounded by the host.

In Memory Mode this signal is set high when the
CompactFlash Storage Card or CF +Card is ready
to accept a new data transfer operation and held
low when the card is busy . The Host memory card
socket must provide a pull-up resistor. At power up
and at Reset the RDY/-BSY signal is held low
(busy) until the CompactFlash Storage Card or CF
+Card has completed its power up or reset function.
No access of any type should be made to the
CompactFlash Storage Card or CF +Card during
this time. The RDY/-BSY signal is held high
(disabled from being busy) whenever the following
condition is true. The CompactFlash Storage Card
or CF +Card has been powered up with + RESET
continuously disconnected or asserted.
Operation-After the CompactFlash Storage Card or
CF + Card has been configured for I/O operation;
this signal is used as interrupt Request. This line is
strobe low to generate a pulse mode interrupt or
held low for a level mode interrupt.
In True IDE Mode signal is the active high interrupt
Request to the host.

Rev. A.1 5/50 July. 2010

CompactFlash Card

Signal Name Dir Pin No. Description

This signal is used during Memory Cycles to

-REG
(PC Card Memory Mode)

-REG
(PC Card I/O Mode)

Reserved
(True IDE Mode
for PIO)

-DMACK
(True IDE Mode for
Multi-word DMA)

RESET
(PC Card Memory Mode)

RESET
(PC Card I/O Mode)

-RESET
(True IDE Mode)

VCC
(PC Card Memory Mode)
(PC Card I/O Mode)
(True IDE Mode)

-VS1 /-VS2
(PC Card Memory Mode)
(PC Card I/O Mode)
(True IDE Mode)

-WAIT
(PC Card Memory Mode)

-WAIT
(PC Card I/O Mode)

IORDY
(True IDE Mode)

I 44

I 41

─ 13,38

O 33,40

O 42

distinguish between Common Memory and
Register(Attribute) Memory accesses. High for
Common Memory. Low for Attribute Memory.
The signal must also be active (low) during I/O
Cycles when the I/O address is on the Bus.

In the True IDE Mode, this input signal is not used
and should be driven high or connected to VCC by
the host.

This is a DMA acknowledge signal that is asserted
by the host in response to DMARQ to initiate DMA
transfers.
While DMA operations are not active, the card shall
ignore the –DMACK signal, including a floating
condition.
If DMA operation is not supported by a True-IDE
mode only host, this signal should be driven high or
connected to VCC by the host.
A host that does not support DMA mode and
implements both PCMCIA and True-IDE modes of
operation need not alter the PCMCIA mode
connections while in True-IDE mode as long as this
does not prevent proper operation all modes.
The CompactFlash Storage Card or CF+ Card is
Reset when the RESET pin is high with the following
important exception:

The host may leave the RESET pin open or keep it
continually high from the application of power
without causing a continuous Reset of the card.
Under either of these conditions, the card shall
emerge from power-up having completed an initial
Reset.
The CompactFlash Storage Card or CF +Card is
also Reset when the Soft Reset bit in the Card
Configuration Option Register is set.

This signal is the same as the PC Card Memory

Mode signal.

In the True IDE Mode this input pin is the active low
hardware reset form the host.

+5V +3.3V power.

Voltage Sense Signals. –VS1 is grounded so that the
CompactFlash Storage Card or CF + Card CIS can
be read at 3.3 volts and –VS2 is reserved by
PCMCIA for a secondary voltage.
The –WAIT signal is driven low by the CompactFlash
Storage Card or CF +Card to signal the host to delay
completion of a memory or I/O cycle that is in
progress.

In True IDE Mode this output signal may be used as
IORDY.

Rev. A.1 6/50 July. 2010

CompactFlash Card

Signal Name Dir Pin No. Description

This is a signal driven by the host and used for

-WE
(PC Card Memory Mode)

-WE
(PC Card I/O Mode)

-WE
(True IDE Mode)

WP
(PC Card Memory Mode)

-IOIS16
(PC Card I/O Mode)

-IOIS16
(True IDE Mode)

I 36

O 24

starting memory write data to the registers of the
CompactFlash Storage Card or CF + Card when the
card is configured I the memory interface mode. It is
also used for writing the configuration registers.
In PC Card I/O Mode, this signal is used for writing
the configuration registers.

In True IDE Mode this input signal is not used and
should be connected to VCC by the host.

Memory Mode-The CompactFlash Storage Card or
CF + Card does not have a write protect switch. This
signal is held low after the completion of the reset
initialization sequence.

I/O Operation-When the CompactFlash Storage
Card or CF + Card is configured for I/O Operation
Pin 24 is used for the –I/O Selected is 16 Bit Port
(-IOIS16) function. A Low signal indicates that a 16
bit or odd byte only operation can be performed at
the addressed port.
In True IDE Mode this output signal is asserted low
when this device is expecting a word data transfer
cycle.

Rev. A.1 7/50 July. 2010

CompactFlash Card

3.3 Card Block Diagram

VCC

GND

Internal VCC

A0 to A10

-CE1,-CE2

-OE,-ATASEL

-WE

-IORD

-IOWR

-REG

RESET/-RESET

-CSEL

D0 to D15

RDY/-BSY/-IREQ/INTRQ

WP/-IOIS16

-INPACK

BVD1/-STSCHG/-PDIA

-WAIT/IORDY

VS1

VS1

Controller

Flash memory
bus

Reset IC

Clock

NAND FLASH

Control signal

VS2

OPEN

BVD2/-SPKR/-DAS

-CD1

-CD2

●

Rev. A.1 8/50 July. 2010

CompactFlash Card

4. Access specification

4.1 Attribute access specifications

When CIS-ROM region or Configuration register region is accessed, read and write operations are executed under the
condition of –REG = “L” as follows. That region can be accessed by Byte/Word/Odd-byte modes, which are defined by PC
card standard specifications.

Attribute Read Access Mode

Mode -REG -CE2 -CE1 A0 -OE -WE D8 to D15 D0 to D7

Standby mode X H H X X X High-Z High-Z

Byte access (8-it)

Word access (16-it) L L L X L H invalid even byte

Odd byte access (8bit) L L H X L H invalid High-Z

Note: X → L or H

L H L L L H High-Z even byte

L H L H L H High-Z invalid

Attribute Write Access Mode

Mode -REG -CE2 -CE1 A0 -OE -WE D8 to D15 D0 to D7

Standby mode × H H × × × Don’t care Don’t care

Byte access (8bit)

Word access (16bit) L L L × H L Don’t care even byte

Odd byte access (8bit) L L H × H L Don’t care Don’t care

Note: X → L or H

L H L L H L Don’t care even byte

L H L H H L Don’t care Don’t care

Attribute Access Timing Example

Rev. A.1 9/50 July. 2010

CompactFlash Card

4.2 Task file Register access specifications

There are two cases of Task File register mapping, one is mapped I/O address area, the other is mapped Memory
address area. Each case of Task File registers read and write operations is executed under the condition as follows.
That area can be accessed by Byte/World/Odd Byte modes, which are defined by PC card standard specifications.

4.2.1 I/O address map
Task File Register Read Access Mode (1)

Mode -REG -CE2 -CE1 A0 -IORD -IOWR -OE -WE D8 to D15 D0 to D7

Standby mode X H H X X X X X High-Z High-Z

Byte access (8bit)

Word access (16bit) L L L X L H H H odd byte even byte

Odd byte access (8bit) L L H X L H H H odd byte High-Z

Note: X→ L or H

L H L L L H H H High-Z even byte

L H L H L H H H High-Z odd byte

Task File Register Write Access Mode (1)

Mode -REG -CE2 -CE1 A0 -IORD -IOWR -OE -WE D8 to D15 D0 to D7

Standby mode × H H × × × × × Don’t care Don’t care

Byte access(8-bit)

Word access(16-bit) L L L × H L H H odd byte even byte

Odd byte access(8-bit) L L H × H L H H odd byte don’t care

Note: X→ L or H

L H L L H L H H Don’t care even byte

L H L H H L H H Don’t care odd byte

Task File Register Access Timing Example (1)

Rev. A.1 10/50 July. 2010

CompactFlash Card

4.2.2 Memory address map
Task File Register Read Access Mode (2)

Mode -REG -CE2 -CE1 A0 -OE -WE -IORD -IOWR D8 to D15 D0 to D7

Standby mode X H H X X X X X High-Z High-Z

Byte access (8bit)

Word access (16bit) H L L X L H H H odd byte even byte

Odd byte access (8bit) H L H X L H H H odd byte High-Z

Note: X→ L or H

Task File Register Write Access Mode (2)

Mode -REG -CE2 -CE1 A0 -OE -WE -IORD -IOWR D8 to D15 D0 to D7

Standby mode X H H X X X X X Don’t care Don’t care

H H L L L H H H High-Z even byte

H H L H L H H H High-Z odd byte

Byte access (8bit)

Word access (16bit) H L L X H L H H odd byte even byte

Odd byte access (8bit) H L H X H L H H odd byte don’t care

Note: X→ L or H

H H L L H L H H Don’t care even byte

H H L H H L H H Don’t care odd byte

Task File Register Access Timing Example (2)

Rev. A.1 11/50 July. 2010

CompactFlash Card

4.2.3 True IDE Mode

The card can be configured in a True IDE This card is configured in this mode only when the –OE input signal is
asserted GND by the host. In this True IDE mode Attribute Registers are not accessible from the host. Only I/O
operation to the task file and data register is allowed. If this card is configured during power on sequence, data register
is accessed in word (16-bit). The card permits 8-bit accessed if the user issues a Set Feature Command to put the
device in 8-bit mode.

True IDE Mode Read I/O Function

Mode -CE2 -CE1 A0~A2 -IORD -IOWR D8 to D15 D0 to D7

Invalid mode L L X X X High-Z High-Z

Standby mode H H X X X High-Z High-Z

Data register access H L 0 L H Odd byte even byte

Alternate status access L H 6H L H High-Z Status out

Other task file access H L 1~7H L H High-Z Data

Note: X→ L or H

True IDE Mode Write I/O Function

Mode -CE2 -CE1 A0~A2 -IORD -IOWR D8 to D15 D0 to D7

Invalid mode L L X X X Don’t card Don’t card

Standby mode H H X X X Don’t card even byte

Data register access H L 0 H L Odd byte Don’t card

Alternate status access L H 6H H L Don’t card Control in

Other task file access H L 1~7H H L Odd byte Data

Note: X→ L or H

True IDE Mode I/O Access Timing Example

A0~A2

-CE

-IORD

-IORW

-IOS16

D0~D15

Din

Dout

Rev. A.1 12/50 July. 2010

CompactFlash Card

4.3 Configuration register specification

This card supports four Configuration registers for the purpose of the configuration and observation of this card.

4.3.1 Configuration Option register (Address 200H)

This register is used for the configuration of the card configuration status and for the issuing soft reset to the card.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

SRESET LevIREQ INDEX

Note: initial value: 00H

Name R/W Function

Setting this bit to “1”, places the card in the reset state (Card Hard Reset). This operation is equal

SRESET
(HOST->)

R/W

to Hard Reset, except this bit is not cleared. Then this bit set to “0”,places the card in the reset
state of Hard Reset (This bit is set to “0” by Hard Reset). Card configuration status is reset and the
card internal initialized operation starts when Card Hard Reset is executed, so next access to the
card should be the same sequence as the power on sequence.

LevIREQ
(HOST->)

INDEX
(HOST->)

Note: initial value → 00H

R/W

R/W

This bit sets to “0” when pulse mode interrupt is selected and “1 when level mode interrupt is
selected.

This bits is used for select operation mode of the card as follows.
When Power on, Card Hard Reset and Soft Reset, this data is “000000” for the purpose of Memory
card interface recognition.

INDEX bit assignment

INDEX bit

5 4 3 2 1 0 Card mode Task File register address Mapping mode

0 0 0 0 0 0 Memory card 0H to FH, 400H to 7FFH memory mapped

0 0 0 0 0 1 I/O card ××0H to ××FH Contiguous I/O mapped

0 0 0 0 1 0 I/O card 1F0H to 1F7H, 3F6H to 3F7H Primary I/O mapped

0 0 0 0 1 1 I/O card 170H to 177H, 376H to 377H Secondary I/O mapped

4.3.2 Configuration and Status register (Address 202H)

This register is used for observing the card state.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

CHGED SIGCHG IOIS8 0 0 PWD INTR 0

Note: initial value: 00H

Rev. A.1 13/50 July. 2010