Power integrations LinkSwitch-LP Series Application Note

®

D

S

FB

BP

RTN

6 V,

0.33

A

L

N

D1

1N4937

C1
10 µF
400 V

C3

0.1

µF

50 V

L1

3.3 mH

D6

UF4002

D5

1N4005

C5

220 µF

25 V

C4

0.33 µF
50 V

R4

2 kΩ

R1

37.4 kΩ

R2

3 kΩ

T1

EE16

2

1

7

6

4

5

D4

1N4007

90-265

VAC

LinkSwitch

PI-4063-101005

U1

LNK564P

LinkSwitch-LP

Flyback Design Guide

Application Note AN-39

Introduction

The LinkSwitch-LP family is designed to replace inefficient
line frequency linear transformer based power supplies with
output powers < 2.5 W in applications such as cell/cordless
phones, PDAs, digital cameras, and portable audio players.
LinkSwitch-LP may also be used as auxiliary supplies employed
in applications such as white goods.

LinkSwitch-LP combines a high voltage power MOSFET switch
with an ON/OFF controller in one device. It is completely
self-powered from the DRAIN pin, has a jittered switching
frequency for low EMI and is fully fault protected. Auto-restart
limits device and circuit dissipation during overload and output
short circuit conditions while hysteretic over-temperature
protection disables the internal MOSFET during thermal
faults. EcoSmart® technology enables designs to easily attain
< 150 mW no-load consumption, meeting worldwide energy
efficiency requirements.

LinkSwitch-LP is designed to operate without the need for a
primary-side clamp circuit for output powers below 2.5 W and

thus, dramatically reduces component count and total system
cost. Figure 1 shows a

LinkSwitch-LP based 2 W power supply
without a primary-side clamp. The LinkSwitch-LP family
has been optimized to give an approximate CV/CC output
characteristic when feedback is provided from an auxillary or
bias winding on the transformer. This is ideal for applications
replacing a line frequency transformer, providing a compatible
output characteristic but with reduced overload, short circuit
current and variation with input line voltage.

Scope

This application note is for engineers designing an isolated
AC-DC flyback power supply using the LinkSwitch-LP family of
devices. It provides guidelines to enable an engineer to quickly
select key components and complete a transformer design for an
application requiring either a constant voltage (CV) or constant
voltage and constant current (CV/CC) output. To simplify the
task of transformer design, this application note refers directly
to the PI Xls design spreadsheet that is part of the PI Expert™
design software suite.

Figure 1. Basic Circuit Schematic Using LinkSwitch-LP in a Clampless™ Design.

July 2006

AN-39

Enter power supply specifications:

Input voltage range and frequency, output voltage,

output current and VI characteristic, feedback type,

loss allocation factor, diode conduction time and

input capacitance

Select LinkSwitch-LP based on Table 4

(see data sheet) and reflected

output voltage (VOR) to 80 V

Select a standard transformer design

(Table 8). See appendices for

Transformer and bobbin drawings

Select transformer core and bobbin

based on Table 5 and 6

Select input stage filter and rectifier

based on Table 7

Select BYPASS pin capacitor. Use

0.1 µF / 50 V capacitor. See Step 6

Ensure that flux density BM < 1500

Gauss (150 mT). Adjust by

increasing number of secondary turns NS

Select output diode based on
Table 8 and calculate preload

resistor

Select output capacitor based on

secondary ripple current and

output voltage (see Step 8)

PI-4137-101005

Start design

Finish design

4 V ≤ VO ≤ 12 V

PO ≤ 2 W

Yes

No

Quick Start

Figure 2. LinkSwitch-LP Flyback Design Flowchart.

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7/06

2

Step-by-Step Design procedure

I

OUT

I

OUTIOUT

V

OUT

V

OUT(TYP)

Maximum Peak

Power Point

Nominal Peak

Power Point

PI-4152-100705

I

O

I

OUT(TYP)

V

OUT(TYP)

V

O

Maximum Peak

Power Point

Nominal Peak

Power Point

PI-4172-101005

AN-39

Step 1 – Enter Application Variables: VAC

MIN

, VAC

MAX

fL, VO, IO, CV/CC spec, PO, Clamp and Feedback type,
η, Z, tC and CIN.

Determine the input voltage range (VAC

and VAC

MIN

MAX

) from

Table 1.

Nominal Input Voltage VAC

MIN

VAC

MAX

100/115 85 132

230 195 265

Universal 85 265

Table 1. Standard Worldwide, Input Line Voltage Ranges.

Line Frequency, f

L

Enter the worst-case line frequency under which the supply
should operate normally.

Output Voltage, V

O

Enter the output voltage. For loose CV/CC designs, this should
be the typical output voltage at the nominal peak power point in
the output characteristic. For CV only outputs this should be the
specified output voltage. For designs with an output cable enter
the voltages at the load. For multiple output designs enter the
voltage for the main output from which feedback is taken.

,

(a)

(b)

Figure 3. Diagram Showing Correct Values of IO and VO to enter
in the spreadsheet for (a) Optocoupler Feedback and (b)
Bias Winding Feedback

Output Current, I

O

For loose CV/CC designs, this should be the typical output current
at the nominal peak power point in the output characteristic.
For CV only outputs, this should be the maximum specified
output current. In multiple output designs, the output current
of the main output (typically the output from which feedback
is taken) should be increased such that PO matches the sum
of the output powers from all the outputs in the design. The
individual output voltages and currents should then be entered
at the bottom of the spreadsheet.

CC portions of the spec. This arrangement uses bias winding
feedback to regulate the output. During normal operation
switching cycles are enabled or disabled to maintain the voltage
at the FEEDBACK pin. This, via the turns ratio between the
bias and secondary windings regulates the output. However
as the secondary output voltage is not directly sensed, errors
caused by leakage inductance and resistive drops result is
only moderate load regulation (however still better than an
unregulated line frequency linear transformer based supply).
Once the maximum power point is reached (determined by the
primary inductance, current limit and switching frequency) the

Figure 3 shows a diagram with correct values of I

and VO to

O

enter in the spreadsheet for both Optocoupler based feedback
and Bias Winding Feedback.

voltage on the bias winding begins to fall and the switching
frequency of LinkSwitch-LP is reduced to limit the maximum
output current as an output overload increases toward a short
circuit.

CV/CC Output Specification

If the output specification is loose constant voltage and constant
current (charger) CV/CC type enter ʻYESʼ in cell B8, otherwise
enter ʻNOʼ for Constant voltage (adapter) CV only. For CV/CC
designs, the typical value of I

2

f is used in the computation of
primary inductance, while for CV only designs, the minimum
value of I2f is used to guarantee power delivery.

A CV/CC characteristic can be achieved by using either one
of the arrangements shown in Figures 1 or 4. Figure 1 shows
a low cost primary side control scheme for both the CV and

For improved performance, Figure 4 shows an arrangement
using an optocoupler and high gain voltage reference IC (U2)
to regulate the output voltage. Once the maximum power
point is reached and the output voltage falls, the output current
is controlled via the bias winding, sensed via R

and RY

X

(Figure 4). As shown in Table 3 the high gain of the system
gives an output voltage with minimal variation during CV
operation and good linearity, maintaining an almost vertical CC
characteristic. As the output is being sensed indirectly via the
bias winding during CC operation, the CC characteristic is still

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7/06

3

AN-39

Z

Total Losse

s

Secondary Side Losses

=

T1

+

+

D

S

FB

BP

DC BUS

or

HV DC

V

O

R

X

D

B

D

S

C

B

C

O

R

Y

R

3

R

1

R

2

U1

LNK564P

0.1 µF
50 V

0.33

µF

50 V

U2

LinkSwitch-LP

PI-4138-070706

Figure 4. Circuit Schematic for High Performance CV/CC Output Characteristic.

subject to unit-to-unit variation caused by the difference in the
transformer (bias to secondary coupling and leakage inductance.
Also see Enter Feedback, Bias Type and Clamp Information
section). Note that the reference IC U2 may be replaced by a
lower cost zener diode in applications where increased tolerance
is acceptable during CV operation.

Finally for improved CC performance a secondary CC sense
circuit can be used. This removes variation in the CC due to
the transformer and FEEDBACK pin.

Power Supply Efficiency,

Enter the estimated power supply efficiency measured at the
point of load. For both CV/CC and CV only designs use 0.65 if
no better data is available or until measurements can be made
on a prototype.

Power Supply Loss Allocation Factor, Z

This factor represents the proportion of losses between the
primary and the secondary of the power supply.

If no better data is available then the following values are
recommended:

• Bias winding feedback designs (CV or CV/CC): 0.5 (0.35)

• Optocoupler CV feedback and/or bias winding CC
feedback: 0.5 (0.35)

• Optocoupler CV and CC feedback: 0.75 (0.6)

4

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7/06

For designs using Filterfuse™ use the values in parenthesis,
these take into account the additional primary side losses due
to a typical value of ~50 Ω for the resistance of the Filterfuse
inductor

Bridge Diode Conduction Time, t

(ms)

C

Enter the bridge diode conduction time. Use 3 ms if no other
data is available.

Total Input Capacitance C

(µF)

IN

Enter total input capacitance using Table 2 for guidance.

η

Total Input Capacitance per Watt

of Output Power (µF/W)

AC Input

Voltage (VAC)

Half Wave

Rectification

Full Wave

Rectification

100/115 5-8 3-4

Table 2. Suggested Total Input Capacitance for Different Input
Voltage Ranges.

The capacitance should be selected to keep the minimum DC
input voltage, V

Note: For designs that have a DC rather than an AC input, the
value of the minimum and maximum DC input voltages, V
and V
on the design spreadsheet (see Figure 5).

230 1-2 1

85-265 5-8 3-4

> 50 V and ideally > 70 V.

MIN

, may be entered directly into the gray override cells

MAX

MIN

AN-39

PI-4140-101305

8

7

6

5

4

3

2

1

0

0 150 450300 600 750

Load (mA)

Output Voltage (V)

9

8

7

6

5

4

3

2

1

0

0 150 450300 600 750

Load (mA)

PI-4139-092205

Output Voltage (V)

9

8

7

6

5

4

3

2

1

0

0 150 450300 600 750

Load (mA)

PI-4173-101305

Output Voltage (V)

9

ENTER APPLICATION VARIABLES

Customer

VACMIN 85 Volts

Minimum AC Input Vo

ltage

VACMAX 265 Volts

Maximum AC Input Vo

ltage

fL 50 Hertz

AC Mains Frequency

VO 6.00 Volts

Output Voltage (main) measured at the end of output cable (For CV/CC designs enter typical CV
tolerance limit

)

IO 0.33 Amps

Power Supply Output Current (For CV/CC designs enter typical CC tolerance limit)

Constant Voltage / Constant Current Output YES CVCC Volts

Enter "YES" for approximate CV/CC output. Enter "NO" for CV only output

Output Cable Resistance

0.16 0.16 Ohms

Enter the resistance of the output cable (if used)

PO 2.00 Watts

Output Power (VO x IO + dissipation in output cable)

Feedback Ty

pe BIAS

Bias

Winding Enter 'BIAS' for Bias winding feedback and 'OPTO' for Optocoupler feedback

Add Bias Winding

YES Yes

Enter 'YES' to add a Bias winding. Enter 'NO' to continue design without a Bias winding. Addition of
Bias winding can lower no load consumptio

n

Clampless design YES

Clampless

Enter 'YES' for a clampless design. Enter 'NO' if an external clamp circuit is used

.

n 0.64

Efficiency Estimate at output terminals. For CV only designs enter 0.7 if no better data available

Z 0

.35 0.35

Loss Allocation Factor (Secondary side losses / To

tal losses)

tC 2.90 mSeconds

Bridge Rectifier Conduction Time Estimat

e

CIN 9

.40 uFarads

Input Capacitance

Input Rectification Ty

pe F

F

Choose H for Half Wave Rectifier and F for Full Wave Rectification

DC INPUT VOLTAGE PARAMETERS

VMIN 99 Volts

Minimum DC Input Voltag

e

VMAX 375 Vo

lts

Maximum DC Input Voltag

e

Bias Winding Feedback

(Figure 1)

Optocoupler with Zener

as Reference (Figure 4, U2

Replaced with Zener

Optocoupler with TL-431 as

Reference (Figure 4)

Typical Output
Characteristics

Cost Low Higher Highest

Component count

Lowest component count Higher component count Highest component count

Ease of Design High Medium Medium

CV/CC Tolerance

Table 3. Summary of Comparison Between Bias Winding Feedback and Optocoupler Feedback.

Good Better Best

Enter Feedback, Bias Type and Clamp Information

Select either bias winding feedback (primary-side feedback)
as shown in Figure 1or optocoupler feedback (secondary-side
feedback) as shown in Figure 4. Bias winding feedback makes
use of a primary-side auxiliary winding to set the output voltage.
Optocoupler feedback directly senses the output voltage and
can provide any level of accuracy depending on the voltage
reference selected. Both primary-side feedback and secondary­side feedback allow for a CV/CC output characteristic. See
Table 3 for a summary of feedback types.

Figure 5. Application Variable Section of LinkSwitch-LP Design Spreadsheet.

If optocoupler feedback is selected, the user still has the option
to reduce overall power consumption by using a bias winding
to power the optocoupler transistor. That bias winding can also
be configured as a shield, for improved EMI performance.

Clampless™ designs typically exhibit a resonance between the
leakage inductance and primary capacitance, that is normally
damped by the primary clamp. As there is less damping in a
Clampless design this creates a peak in the conducted EMI
measurements in 1-4 MHz range. It is generally the EMI

7/06

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5

AN-39

ENTER LinkSwitch-LP VARIABLES

LinkSwitch-LP

LNK564

LinkSwitch-LP device

Chosen Device

LNK564

ILIMITMIN 0.124 Amps

Minimum Current Limit

ILIMITMAX 0.146 Amps

Maximum Current Limi

t

fSmi

n 93000 Hertz

Minimum Device Switching Frequenc

y

I^2fMIN 1665 A^2Hz

I^2f Minimum value (product of current limit squared and frequency is trimmed for tighter tolerance)

I^2fTYP 1850 A^2Hz

I^2f typical value (product of current limit squared and frequency is trimmed for tighter tolerance)

VOR

80 Volts

Reflected Output Voltag

e

VD

S 10 Volts

LinkSwitch-LP on-state Drain to Source Voltage

VD 0.5 Vo

lts

Output Winding Diode Forward Voltage Drop

KP 1.53

Ripple to Peak Current Ratio (0.9<KRP<1.0 : 1.0<KDP<6.0)

performance and not the peak drain voltage that limits the use
of Clampless designs to < 2 W. However if a bias winding is
added which uses a slow diode (1N400x series) that peak in
EMI is reduced as the bias acts as a clamp, damping out the
leakage inductance ringing. This extends the power range for
Clampless designs to ≤2.5 W. In addition, the use of a small
Y-Capacitor (100 pF) can be beneficial in containing this problem
and making the EMI performance less variable.

For designs greater than 2.5 W, a

Clampless solution is not

recommended.

The guidance above applies to universal input or 230 VAC only
designs. For 100/110 VAC only input designs it may be possible
to use Clampless designs above 2 - 2.5 W but only after verifying
acceptable peak drain voltage and EMI performance.

All the variables described above can be entered in the Enter
Application Variables section of the

LinkSwitch-LP design

spreadsheet in the PI Xls design software (see Figure5).

Step 2 – Enter LinkSwitch-LP, VOR, VDS, V

D

Select the appropriate LinkSwitch-LP based on the input
voltage range and the corresponding maximum output power
(see Table 4 & 5).

Maximum Power (W)

Device Universal Input 230 VAC

LNK562 1.9 1.9

LNK563 2.5 2.5

LNK564 3 3

Table 4. Maximum Output Power Capability of LinkSwitch-LP
Devices.

Power delivery from a given device also depends on the
transformer core size selected. Table 5 provides examples of
the output power possible from each device and 3 common
core sizes. These power numbers assume a flux density of
1500 Gauss, and can be increased for higher flux densities,
based on acceptable audible noise.

Reflected Output Voltage, V

OR

(V)

This parameter is the secondary winding voltage reflected
back to the primary through the turns ratio of the transformer
(during the off time of the LinkSwitch-LP). The default
value is 80 V, however this can be increased up to 120 V to
achieve the maximum power capability from the selected
LinkSwitch-LP device. In general, start with the default value of
80 V, increasing the value when necessary to maintain KP above
its lower limit of 0.9 at the minimum input voltage of 85 VAC.
For Clampless designs, there is less flexibility in selecting the
value of VOR. Increasing VOR directly increases the peak drain
voltage. Therefore for Clampless designs, a value of 80 V should
be used and only increased once the peak drain voltage has been
measured and adequate margin to BV

determined.

DSS

LinkSwitch-LP On-State DRAIN-to-SOURCE Voltage,
VDS (V)

This parameter is the average on-state voltage developed across
the DRAIN and SOURCE pins of LinkSwitch-LP. By default, if
the gray override cell is left empty, a value of 10 V is assumed.
Use the default value if no better data is available.

Output Diode Forward Voltage Drop, V

(V)

D

Enter the average forward voltage drop of the (main) output
diode. Use 0.5 V for a Schottky diode or 1 V for a PN diode
if no better data is available. By default, a value of 0.5 V is
assumed.

Calculated Ripple to Peak Current Ratio, K

P

KP is a measure of the operating mode and primary current
waveshape of the design. KP < 1 indicates a continuous design
(the lower the KP, the more continuous the design) and a
KP > 1 indicates a discontinuous design (the higher the KP, the
more discontinuous the design).

Below a value of 1, indicating continuous conduction mode,
KP is the ratio of ripple to peak primary current (KRP). Above
a value of 1, indicating discontinuous conduction mode, KP is
the ratio of primary MOSFET off time to the secondary diode
conduction time (KDP). The value of KP should be in the range
of 0.9 < KP < 6 and guidance is given in the comments cell if
the value is outside this range.

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7/06

6

Figure 6. LinkSwitch-LP Variables Section of LinkSwitch-LP Design Spreadsheet.