Power integrations InnoSwitch3-EP, INN3672C, INN3676C, INN3677C, INN3673C Series Manual

InnoSwitch3-EP Family

Off-Line CV/CC QR Flyback Switcher IC with Integrated

725 V MOSFET, Synchronous Rectication and FluxLink Feedback.

For Applications up to 45 W

Product Highlights

Highly Integrated, Compact Footprint

• Up to 94% efciency across full load range

• Incorporates a multi-mode Quasi-Resonant (QR) / CCM yback

controller, 725 V MOSFET, secondary-side sensing and synchronous
rectication driver

• Excellent multi-output cross regulation with weighted secondary-side

regulation (SSR) feedback and synch FETs

• Integrated FluxLink™, HIPOT-isolated, feedback link

• Exceptional CV/CC accuracy, independent of external components

• Adjustable accurate output current sense using external output sense

resistor

EcoSmart™ – Energy Efcient

• Less than 15 mW no-load including line sense

• Easily meets all global energy efciency regulations

• Low heat dissipation

Advanced Protection / Safety Features

• Secondary MOSFET or diode short-circuit protection

• Open SR FET-gate detection

• Fast input line UV/OV protection

• Auto-restart fault response for output OVP

Optional Features

• Auto-restart output UV protection with option for peak power delivery

Full Safety and Regulatory Compliance

• Reinforced isolation

• Isolation voltage >4000 VAC

• 100% production HIPOT testing

• UL1577 and TUV (EN60950) safety approved

• Excellent noise immunity enables designs that achieve class “A”

performance criteria for EN61000-4 suite; EN61000-4-2, 4-3
(30 V/m), 4-4, 4-5, 4-6, 4-8 (100 A/m) and 4-9 (1000 A/m)

Green Package

• Halogen free and RoHS compliant

Applications

• Auxiliary, standby and bias power supplies for appliances, computers

and consumer products

• Utility meter, smart grid and industrial power supplies

Description

The InnoSwitch™3-EP family of ICs dramatically simplies the design
and manufacture of yback power converters, particularly those
requiring high efciency and/or compact size. The InnoSwitch3-EP
family combines primary and secondary controllers and safety-rated
feedback into a single IC.

InnoSwitch3-EP family devices incorporate multiple protection features
including line over and undervoltage protection, output overvoltage
and over-current limiting, and over-temperature shutdown. Devices are
available with standard and peak power delivery options, and
commonly used auto-restart protection behaviors.

InnoSwitch3-EP

Primary FET

and Controller

Figure 1. Typical Application Schematic.

Figure 2. High Creepage, Safety-Compliant InSOP-24D Package.

Output Power Table

Product

INN3672C 12 W 10 W

INN3673C 15 W 12 W

INN3 674C 25 W 20 W

INN3675C 30 W 25 W

INN3676C 40 W 36 W

INN3677C 45 W 40 W

Table 1. Output Power Table.

Notes:

1. Minimum continuous power in a typical non-ventilated enclosed typical size
adapter measured at 40 °C ambient. Max output power is dependent on the
design. With condition that package temperature must be < 125 °C.

2. Minimum peak power capability.

3. Package: InSOP-24D.

D V

S IS

3

SR FET

GND

BPS

FB

VOUT

Secondary
Control IC

PI-8184-050217

BPP

FWD

SR

230 VAC ± 15% 85-265 VAC

Peak or

Open Frame

1,2

Peak or

Open Frame

Optional
Current
Sense

1,2

www.power.com August 2018

This Product is Covered by Patents and/or Pending Patent Applications.

InnoSwitch3-EP

PI-8045d-091217

DETECTOR

ENABLE

SR

FORWARD

(FWD)

FEEDBACK

(FB)

SECONDARY

BYPASS

(BPS)

SECONDARY

GROUND

(GND)

ISENSE

(IS)

To

Primary

Receiver

SYNCRONOUS RECTIFIER DRIVE

(SR)

FEEDBACK

COMPENSATION

FEEDBACK

DRIVER

INH

QR

Ts

MAX

INH

QR

t

OFF(MIN)

t

SECINH(MAX)

t

SS(RAMP)

4.4 V

3.9 V

SR CONTROL

INH
DCM

VREF

IS THRESHOLD

V

PK

FORWARD

BPS

UV

OUTPUT VOLTAGE

(VOUT)

OSCILLATOR/

TIMER

REGULATOR

4.4 V

SECONDARY

LATCH

CONSTANT

POWER

HANDSHAKE/

LATCH-OFF

SR

THRESHOLD

CONTROL

SQQ

R

+

+

-

+

-

+

-

VOUT

DRAIN

(D)

GATE

SOURCE

(S)

SenseFET

I

S

V

ILIM

Power

MOSFET

Figure 3. Primary Controller Block Diagram.

UNDER/OVER

INPUT VOLTAGE (V)

INTERFACE

THERMAL

SHUTDOWN

BPP

DRIVER

LEB

+

-

LINE

UV/OV

GATE

GATE

ILIM

t

ON(MAX)

PRIMARY BYPASS

REGULATOR

ENABLE

BPP/UV

OSCILLATOR/

TIMERS

t

ON(MAX)tOFF(BLOCK)

OV/UV

AUTO-RESTART

COUNTER

RESET

PRIM-CLK

JITTER

FAULT

FAULT

SecREQ

ENABLE

PRIMARY
BYPASS PIN
CAPACITOR
SELECT AND

CURRENT

LIMIT

GATE

LATCH-OFF

QRS

BPP/UV

Q

t

OFF(BLOCK)

PRIM-CLK

SEC-

LATCH

LATCH-OFF

BPP/UV

V

ILIM

PRIM/SEC

SecPulse

PRIM/SEC

PRIMARY OVP

PRIMARY BYPASS

PRIMARY

BYPASS PIN

UNDERVOLTAGE

+

-

V

RECEIVER

CONTROLLER

LATCH

PI-8044-083017

SHUNT

V

(BPP)

BP+

From
Secondary
Controller

Figure 4. Secondary Controller Block Diagram.

2

Rev. D 08/18

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Pin Functional Description

ISENSE (IS) Pin (Pin 1)

Connection to the power supply output terminals. An external
current sense resistor should be connected between this and the
GND pin. If current regulation is not required, this pin should be tied
to the GND pin.

SECONDARY GROUND (GND) (Pin 2)

GND for the secondary IC. Note this is not the power supply output
GND due to the presence of the sense resistor between this and the
ISENSE pin.

FEEDBACK (FB) Pin (Pin 3)

Connection to an external resistor divider to set the power supply
output voltage.

SECONDARY BYPASS (BPS) Pin (Pin 4)

Connection point for an external bypass capacitor for the secondary
IC supply.

SYNCHRONOUS RECTIFIER DRIVE (SR) Pin (Pin 5)

Gate driver for external SR FET. If no SR FET is used connect this pin
to GND.

OUTPUT VOLTAGE (VOUT) Pin (Pin 6)

Connected directly to the output voltage, to provide current for the
controller on the secondary-side and provide secondary protection.

FORWARD (FWD) Pin (Pin 7)

The connection point to the switching node of the transformer output
winding providing information on primary switch timing. Provides power
for the secondary-side controller when V

NC Pin (Pin 8-12)

Leave open. Should not be connected to any other pins.

UNDER/OVER INPUT VOLTAGE (V) Pin (Pin 13)

A high-voltage pin connected to the AC or DC side of the input bridge
for detecting undervoltage and overvoltage conditions at the power
supply input. This pin should be tied to SOURCE pin to disable UV/OV
protection.

PRIMARY BYPASS (BPP) Pin (Pin 14)

The connection point for an external bypass capacitor for the
primary-side supply. This is also the ILIM selection pin for choosing
standard ILIM or ILIM+1.

NC Pin (Pin 15)

Leave open. Should not be connected to any other pins.

SOURCE (S) Pin (Pin 16-19)

These pins are the power MOSFET source connection. Also ground
reference for primary BYPASS pin.

DRAIN (D) Pin (Pin 24)

Power MOSFET drain connection.

is below threshold.

OUT

InnoSwitch3-EP

V 13 12 NC

BPP 14 11 NC

NC 15 10 NC

S 16-19

D 24

Figure 5. Pin Conguration.

InnoSwitch3-EP Functional Description

The InnoSwitch3-EP combines a high-voltage power MOSFET switch,
along with both primary-side and secondary-side controllers in one
device.

The architecture incorporates a novel inductive coupling feedback
scheme (FluxLink) using the package lead frame and bond wires to
provide a safe, reliable, and cost-effective means to transmit
accurate, output voltage and current information from the secondary
controller to the primary controller.

The primary controller on InnoSwitch3-EP is a Quasi-Resonant (QR)
yback controller that has the ability to operate in continuous
conduction mode (CCM), boundary mode (CrM) and discontinuous
conduction mode (DCM). The controller uses both variable frequency
and variable current control schemes. The primary controller consists
of a frequency jitter oscillator, a receiver circuit magnetically coupled to
the secondary controller, a current limit controller, 5 V regulator on
the PRIMARY BYPASS pin, audible noise reduction engine for light
load operation, bypass overvoltage detection circuit, a lossless input
line sensing circuit, current limit selection circuitry, over-temperature
protection, leading edge blanking, secondary output diode / SR FET
short protection circuit and a 725 V power MOSFET.

The InnoSwitch3-EP secondary controller consists of a transmitter
circuit that is magnetically coupled to the primary receiver, a constant
voltage (CV) and a constant current (CC) control circuit, a 4.4 V
regulator on the SECONDARY BYPASS pin, synchronous rectier FET
driver, QR mode circuit, oscillator and timing circuit, and numerous
integrated protection features.

Figure 3 and Figure 4 show the functional block diagrams of the
primary and secondary controller, highlighting the most important
features.

9 NC
8 NC
7 FWD
6 VOUT
5 SR
4 BPS
3 FB
2 GND
1 IS

PI-7877-022216

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3

Rev. D 08/18

InnoSwitch3-EP

Primary Controller

InnoSwitch3-EP has variable frequency QR controller plus CCM/CrM/
DCM operation for enhanced efciency and extended output power
capability.

PRIMARY BYPASS Pin Regulator

The PRIMARY BYPASS pin has an internal regulator that charges the
PRIMARY BYPASS pin capacitor to V
DRAIN pin whenever the power MOSFET is off. The PRIMARY
BYPA SS pin is the internal supply voltage node. When the power
MOSFET is on, the device operates from the energy stored in the
PRIMARY BYPASS pin capacitor.

In addition, a shunt regulator clamps the PRIMARY BYPASS pin
voltage to V
pin through an external resistor. This allows the InnoSwitch3-EP to

when current is provided to the PRIMARY BYPASS

SHUNT

be powered externally through a bias winding, decreasing the no-load
consumption to less than 15 mW in a 5 V output design.

Primary Bypass ILIM Programming

InnoSwitch3-EP ICs allows the user to adjust current limit (ILIM)
settings through the selection of the PRIMARY BYPASS pin capacitor
value. A ceramic capacitor can be used.

There are 2 selectable capacitor sizes - 0.47 mF and 4.7 mF for setting
standard and increased ILIM settings respectively.

Primary Bypass Undervoltage Threshold

The PRIMARY BYPASS pin undervoltage circuitry disables the power
MOSFET when the PRIMARY BYPASS pin voltage drops below ~4.5 V
(V

- V

BPP

pin voltage falls below this threshold, it must rise to V

) in steady-state operation. Once the PRIMARY BYPASS

BP(H)

re-enable turn-on of the power MOSFET.

Primary Bypass Output Overvoltage Function

The PRIMARY BYPASS pin has a latching OV protection feature. A
Zener diode in parallel with the resistor in series with the PRIMARY
BYPASS pin capacitor is typically used to detect an overvoltage on the
primary bias winding and activate the protection mechanism. In the
event that the current into the PRIMARY BYPASS pin exceeds ISD, the
device will latch-off or disable the power MOSFET switching for a time

t

, after which time the controller will restart and attempt to

AR(O FF)

return to regulation (see Secondary Fault Response in the Feature
Code Addenda).

VOUT OV protection is also included as an integrated feature on the
secondary controller (see Output Voltage Protection).

Over-Temperature Protection

The thermal shutdown circuitry senses the primary MOSFET die
temperature. The threshold is set to T
latch-off response.

Hysteretic response: If the die temperature rises above the threshold,
the power MOSFET is disabled and remains disabled until the die
temperature falls by T
large amount of hysteresis is provided to prevent over-heating of the

at which point switching is re-enabled. A

SD(H)

PCB due to a continuous fault condition.

Latch-off response: If the die temperature rises above the threshold
the power MOSFET is disabled. The latching condition is reset by
bringing the PRIMARY BYPASS pin below V
the UNDER/OVER INPUT VOLTAGE pin UV (I

by drawing current from the

BPP

to

SHUNT

with either a hysteretic or

SD

or by going below

BPP(RESET)

) threshold.

UV-

1.05

1.0

(A)

0.95

LIM

0.9

0.85

Normalized I

0.8

0.75

30 40 50 60 70 90 10080

Steady-State Switching Frequency (kHz)

Figure 6. Normalized Primary Current vs. Frequency.

Current Limit Operation

The primary-side controller has a current limit threshold ramp that is
linearly decreasing to the time from the end of the previous primary
switching cycle (i.e. from the time the primary MOSFET turns off at
the end of a switching cycle).

This characteristic produces a primary current limit that increases as
the switching frequency (load) increases (Figure 6).

This algorithm enables the most efcient use of the primary switch
with the benet that this algorithm responds to digital feedback
information immediately when a feedback switching cycle request is
received.

At high load, switching cycles have a maximum current approaching

100% I

load decreases. Once 30% current limit is reached, there is no

. This gradually reduces to 30% of the full current limit as

LIM

further reduction in current limit (since this is low enough to avoid
audible noise). The time between switching cycles will continue to
increase as load reduces.

Jitter

The normalized current limit is modulated between 100% and 95%
at a modulation frequency of f
~7 kHz with average frequency of ~100 kHz.

. This results in a frequency jitter of

M

Auto-Restart

In the event a fault condition occurs (such as an output overload,
output short-circuit, or external component/pin fault), the
InnoSwitch3-EP enters auto-restart (AR) or latches off. The latching
condition is reset by bringing the PRIMARY BYPASS pin below ~3 V or
by going below the UNDER/OVER INPUT VOLTAGE pin UV (I
threshold.

In auto-restart, switching of the power MOSFET is disabled for t
There are 2 ways to enter auto-restart:

)

UV-

AR(O FF)

1. Continuous secondary requests at above the overload detection

frequency f

2. No requests for switching cycles from the secondary for >t

The second is included to ensure that if communication is lost, the
primary tries to restart. Although this should never be the case in
normal operation, it can be useful when system ESD events (for
example) causes a loss of communication due to noise disturbing the
secondary controller. The issue is resolved when the primary restarts
after an auto-restart off-time.

(~110 kHz) for longer than 82 ms (tAR).

OVL

AR(SK)

.

PI-8205-120516

.

4

Rev. D 08/18

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InnoSwitch3-EP

The rst auto-restart off-time is short (t
restart time is to provide quick recovery under fast reset conditions.

). This short auto-

AR(OFF)SH

The short auto-restart off-time allows the controller to quickly check to
determine whether the auto-restart condition is maintained beyond

t

. If so, it will resort to a full auto-restart off-time.

AR(OFF)SH

The auto-restart is reset as soon as an AC reset occurs.

SOA Protection

In the event that there are two consecutive cycles where the I
reached within ~500 ns (the blanking time + current limit delay time),

is

LIM

the controller will skip 2.5 cycles or ~25 ms (based on full frequency
of 100 kHz). This provides sufcient time for the transformer to reset
with large capacitive loads without extending the start-up time.

Secondary Rectier/SR MOSFET Short Protection (SRS)

In the event that the output diode or SR FET is short-circuited before
or during the primary conduction cycle, the drain current (prior to the
end of the leading edge blanking time) can be much higher than the
maximum current limit threshold. If the controller turns the high­voltage power MOSFET off, the resulting peak drain voltage could
exceed the rated BV
even with minimum on-time.

of the device, resulting in catastrophic failure

DSS

To address this issue, the controller features a circuit that reacts
when the drain current exceeds the maximum current limit threshold
prior to the end of leading-edge blanking time. If the leading-edge
current exceeds current limit within a cycle (200 ns), the primary
controller will trigger a 30 ms off-time event. SOA mode is triggered if
there are two consecutive cycles above current limit within t
(~500 ns). SRS mode also triggers ~200 ms off-time, if the current

LES

limit is reached within 200 ns after a 30 ms off-time.

Input Line Voltage Monitoring

The UNDER/OVER INPUT VOLTAGE pin is used for input undervoltage
and overvoltage sensing and protection.

A 4 MΩ resistor is tied between the high-voltage DC bulk capacitor
after the bridge (or to the AC side of the bridge rectier for fast AC
reset) and the UNDER/OVER INPUT VOLTAGE pin to enable this
functionality. This function can be disabled by shorting the UNDER/
OVER INPUT VOLTAGE pin to SOURCE pin.

At power-up, after the primary bypass capacitor is charged and the
ILIM state is latched, and prior to switching, the state of the UNDER/
OVER INPUT VOLTAGE pin is checked to conrm that it is above the
brown-in and below the overvoltage shutdown thresholds.

In normal operation, if the UNDER/OVER INPUT VOLTAGE pin current
falls below the brown-out threshold and remains below brown-in for
longer than t
resume once the UNDER/OVER INPUT VOLTAGE pin current is above

, the controller enters auto-restart. Switching will only

UV-

the brown-in threshold.

In the event that the UNDER/OVER INPUT VOLTAGE pin current is
above the overvoltage threshold, the controller will also enter
auto-restart. Again, switching will only resume once the UNDER/
OVER INPUT VOLTAGE pin current has returned to within its normal
operating range.

The input line UV/OV function makes use of an internal high-voltage
MOSFET on the UNDER/OVER INPUT VOLTAGE pin to reduce power
consumption. If the cycle off-time t
internal high-voltage MOSFET will disconnect the external 4 MΩ

is greater than 50 ms, the

OFF

resistor from the internal IC to eliminate current drawn through the
4 MΩ resistor. The line sensing function will activate again at the
beginning of the next switching cycle.

P: Primary Chip

Start

P: Powered Up, Switching

S: Powering Up

S: Has powered

up within 64 ms?

Yes

P: Switching

S: Sends Handshaking Pulses

P: Has Received

Handshaking

Pulses

Yes

P: Stops Switching, Hands
Over Control to Secondary

S: Has Taken

Control?

Yes

End of Handshaking,

Secondary Control Mode

Figure 7. Primary-Secondary Handshake Flowchart.

No

No

No

S: Secondary Chip

P: Auto-Restart
S: Powering Up

2s

P: Goes to Auto-Restart Off

S: Bypass Discharging

64 ms

P: Continuous Switching

S: Doesn’t Take Control

P: Not Switching

S: Doesn’t Take Control

PI-7416-102814

Primary-Secondary Handshake

At start-up, the primary-side initially switches without any feedback
information (this is very similar to the operation of a standard
TOPSwitch™, TinySwitch™ or LinkSwitch™ controllers).

If no feedback signals are received during the auto-restart on-time
(t

), the primary goes into auto-restart mode. Under normal

AR

conditions, the secondary controller will power-up via the FORWARD
pin or from the OUTPUT VOLTAGE pin and take over control. From
this point onwards the secondary controls switching.

If the primary controller stops switching or does not respond to cycle
requests from the secondary during normal operation (when the
secondary has control), the handshake protocol is initiated to ensure
that the secondary is ready to assume control once the primary
begins to switch again. An additional handshake is also triggered if
the secondary detects that the primary is providing more cycles than
were requested.

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5

Rev. D 08/18

InnoSwitch3-EP

The most likely event that could require an additional handshake is
when the primary stops switching as the result of a momentary line
brown-out event. When the primary resumes operation, it will default
to a start-up condition and attempt to detect handshake pulses from
the secondary.

If the secondary does not detect that the primary responds to
switching requests for 8 consecutive cycles, or if the secondary
detects that the primary is switching without cycle requests for 4 or
more consecutive cycles, the secondary controller will initiate a
second handshake sequence. This provides additional protection
against cross-conduction of the SR FET while the primary is
switching. This protection mode also prevents an output overvoltage
condition in the event that the primary is reset while the secondary is
still in control.

Wait and Listen

When the primary resumes switching after initial power-up recovery
from an input line voltage fault (UV or OV) or an auto-restart event, it
will assume control and require a successful handshake to relinquish
control to the secondary controller.

As an additional safety measure the primary will pause for an
auto-restart on-time period, t
this “wait” time, the primary will “listen” for secondary requests. If it

(~82 ms), before switching. During

AR

sees two consecutive secondary requests, separated by ~30 ms, the
primary will infer secondary control and begin switching in slave
mode. If no pulses occurs during the tAR “wait” period, the primary
will begin switching under primary control until handshake pulses are
received.

Audible Noise Reduction Engine

The InnoSwitch3-EP features an active audible noise reduction mode
whereby the controller (via a “frequency skipping” mode of operation)
avoids the resonant band (where the mechanical structure of the
power supply is most likely to resonate − increasing noise amplitude)
between 7 kHz and 12 kHz - 143 ms and 83 ms. If a secondary
controller switch request occurs within this time window from the last
conduction cycle, the gate drive to the power MOSFET is inhibited.

Secondary Controller

As shown in the block diagram in Figure 4, the IC is powered by a

4.4 V (V
SECONDARY BYPASS pin is connected to an external decoupling
capacitor and fed internally from the regulator block.

The FORWARD pin also connects to the negative edge detection
block used for both handshaking and timing to turn on the SR FET
connected to the SYNCHRONOUS RECTIFIER DRIVE pin. The
FORWARD pin voltage is used to determine when to turn off the
SR FET in discontinuous conduction mode operation. This is when
the voltage across the R

In continuous conduction mode (CCM) the SR FET is turned off when
the feedback pulse is sent to the primary to demand the next
switching cycle, providing excellent synchronous operation, free of
any overlap for the FET turn-off.

The mid-point of an external resistor divider network between the
OUTPUT VOLTAGE and SECONDARY GROUND pins is tied to the
FEEDBACK pin to regulate the output voltage. The internal voltage
comparator reference voltage is VFB (1.265 V).

The external current sense resistor connected between ISENSE and
SECONDARY GROUND pins is used to regulate the output current in
constant current regulation mode.

) regulator which is supplied by either VOUT or FWD. The

BPS

of the SR FET drops below zero volts.

DS(O N)

Minimum Off-Time

The secondary controller initiates a cycle request using the inductive­connection to the primary. The maximum frequency of secondary­cycle requests is limited by a minimum cycle off-time of t
is in order to ensure that there is sufcient reset time after primary

OFF(MIN)

. This

conduction to deliver energy to the load.

Maximum Switching Frequency

The maximum switch-request frequency of the secondary controller
is f

.

SREQ

Frequency Soft-Start

At start-up the primary controller is limited to a maximum switching
frequency of f
at the switch-request frequency of 100 kHz.

and 75% of the maximum programmed current limit

SW

The secondary controller temporarily inhibits the FEEDBACK short
protection threshold (V
time. After hand-shake is completed the secondary controller linearly
ramps up the switching frequency from fSW to f
time period.

) until the end of the soft-start (t

FB(OFF)

SREQ

over the t

SS(R AMP)

SS(R AMP)

)

In the event of a short-circuit or overload at start-up, the device will
move directly into CC (constant-current) mode. The device will go
into auto-restart (AR), if the output voltage does not rise above the
V

threshold before the expiration of the soft-start timer (t

FB(AR)

after handshake has occurred.

SS(R AMP)

)

The secondary controller enables the FEEDBACK pin-short protection
mode (V
short maintains the FEEDBACK pin below the short-circuit threshold,

) at the end of the t

FB(OFF)

time period. If the output

SS(R AMP)

the secondary will stop requesting pulses triggering an auto-restart
cycle.

If the output voltage reaches regulation within the t
period, the frequency ramp is immediately aborted and the secondary

SS(R AMP)

time

controller is permitted to go full frequency. This will allow the
controller to maintain regulation in the event of a sudden transient
loading soon after regulation is achieved. The frequency ramp will
only be aborted if quasi-resonant-detection programming has already
occurred.

Maximum Secondary Inhibit Period

Secondary requests to initiate primary switching are inhibited to
maintain operation below maximum frequency and ensure minimum
off-time. Besides these constraints, secondary-cycle requests are
also inhibited during the “ON” time cycle of the primary switch (time
between the cycle request and detection of FORWARD pin falling
edge). The maximum time-out in the event that a FORWARD pin
falling edge is not detected after a cycle requested is ~30 ms.

Output Voltage Protection

In the event that the sensed voltage on the FEEDBACK pin is 2%
higher than the regulation threshold, a bleed current of ~2.5 mA (3
mA max) is applied on the OUTPUT VOLTAGE pin (weak bleed). This
bleed current increases to ~200 mA (strong bleed) in the event that
the FEEDBACK pin voltage is raised beyond ~10% of the internal
FEEDBACK pin reference voltage. The current sink on the OUTPUT
VOLTAGE pin is intended to discharge the output voltage after
momentary overshoot events. The secondary does not relinquish
control to the primary during this mode of operation.

If the voltage on the FEEDBACK pin is sensed to be 20% higher than
the regulation threshold, a command is sent to the primary to either
latch-off or begin an auto-restart sequence (see Secondary Fault
Response in Feature Code Addendum). This integrated V
be used independently from the primary sensed OVP or in conjunction.

OVP can

OUT

6

Rev. D 08/18

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InnoSwitch3-EP

Output Voltage

Request Window

Primary VDS

FEEDBACK Pin Short Detection

If the sensed FEEDBACK pin voltage is below V
secondary controller will complete the handshake to take control of
the primary complete t
auto-restart (no cycle requests made to primary for longer than t

and will stop requesting cycles to initiate

SS(R AMP)

second triggers auto-restart).

at start-up, the

FB(OFF)

AR(S K)

During normal operation, the secondary will stop requesting pulses
from the primary to initiate an auto-restart cycle when the FEEDBACK
pin voltage falls below the V
protection mode is on for less than ~10 ms. By this mechanism, the

threshold. The deglitch lter on the

FB(OFF)

secondary will relinquish control after detecting that the FEEDBACK
pin is shorted to ground.

Auto-Restart Thresholds

The OUTPUT VOLTAGE pin includes a comparator to detect when the
output voltage falls below V

t

or t

FB(AR)

control when this fault condition is detected. This threshold is meant

respectively. The secondary controller will relinquish

VO(AR)

FB(AR)

or V

, for a duration exceeding

VO(AR)

to limit the range of constant current (CC) operation and is included
to support high power charger applications.

SECONDARY BYPASS Pin Overvoltage Protection

The InnoSwitch3-EP secondary controller features a SECONDARY
BYPASS pin OV feature similar to the PRIMARY BYPASS pin OV
feature. When the secondary is in control, in the event that the
SECONDARY BYPASS pin current exceeds I
secondary will send a command to the primary to initiate an
auto-restart off-time (t

AR(O FF)

).

(~7 mA) the

BPS (SD)

Output Constant Current and Constant Power Regulation

The InnoSwitch3-EP regulates the output current through an external
current sense resistor between the ISENSE and SECONDARY
GROUND pins and also controls output power in conjunction with the
output voltage sensed on the OUTPUT VOLTAGE pin. If constant
current regulation is not required, the ISENSE pin must be tied to the
SECONDARY GROUND pin. The InnoSwitch3-EP has constant current
regulation below the V
prole above the VPK threshold. The transition between CP and CC is

threshold, and a constant output power

PK

set by the VPK threshold and the set constant current is programmed
by the resistor between the ISENSE and SECONDARY GROUND pins.

PI-8147-102816

FORWARD Pin Voltage

Figure 8. Intelligent Quasi-Resonant Mode Switching.

Time

Time

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7

Rev. D 08/18

InnoSwitch3-EP

SR Disable Protection

In each cycle SR is only engaged if a set cycle was requested by the
secondary controller and the negative edge is detected on the
FORWARD pin. In the event that the voltage on the ISENSE pin
exceeds approximately 3 times the CC threshold, the SR FET drive is
disabled until the surge current has diminished to nominal levels.

SR Static Pull-Down

To ensure that the SR gate is held low when the secondary is not in
control, the SYNCHRONOUS RECTIFIER DRIVE pin has a nominally
“ON” device to pull the pin low and reduce any voltage on the SR gate
due to capacitive coupling from the FORWARD pin.

Open SR Protection

In order to protect against an open SYNCHRONOUS RECTIFIER
DRIVE pin system fault the secondary controller has a protection
mode to ensure the SYNCHRONOUS RECTIFIER DRIVE pin is
connected to an external FET. If the external capacitance on the
SYNCHRONOUS RECTIFIER DRIVE pin is below 100 pF, the device
will assume the SYNCHRONOUS RECTIFIER DRIVE pin is “open” and
there is no FET to drive. If the pin capacitance detected is above
100 pF, the controller will assume an SR FET is connected.

In the event the SYNCHRONOUS RECTIFIER DRIVE pin is detected to
be open, the secondary controller will stop requesting pulses from
the primary to initiate auto-restart.

If the SYNCHRONOUS RECTIFIER DRIVE pin is tied to ground at
start-up, the SR drive function is disabled and the open

SYNCHRONOUS RECTIFIER DRIVE pin protection mode is also
disabled.

Intelligent Quasi-Resonant Mode Switching

In order to improve conversion efciency and reduce switching
losses, the InnoSwitch3-EP features a means to force switching when
the voltage across the primary switch is near its minimum voltage
when the converter operates in discontinuous conduction mode (DCM).
This mode of operation is automatically engaged in DCM and disabled
once the converter moves to continuous-conduction mode (CCM).

Rather than detecting the magnetizing ring valley on the primary­side, the peak voltage of the FORWARD pin voltage as it rises above
the output voltage level is used to gate secondary requests to initiate
the switch “ON” cycle in the primary controller.

The secondary controller detects when the controller enters in
discontinuous-mode and opens secondary cycle request windows
corresponding to minimum switching voltage across the primary
power MOSFET.

Quasi-Resonant (QR) mode is enabled for 20 ms after DCM is detected
or when ring amplitude (pk-pk) >2 V. Afterwards, QR switching is
disabled, at which point switching may occur at any time a secondary
request is initiated.

The secondary controller includes blanking of ~1 ms to prevent false
detection of primary “ON” cycle when the FORWARD pin rings below
ground. See Figure 8.

8

Rev. D 08/18

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Applications Example

PI-8374-051818

C10

R3

2 MΩ

10 µF
400 V

L1

330 µH

1%

R4

1.8 MΩ
1%

C3

DFLR1200-7

BR1
DF08S
800 V

F1

1 A

RT1
10 Ω

90 - 265

VAC

L N

C2
10 µF
400 V

O

t

InnoSwitch3-EP

470 pF

250 VAC

21FL1

CONTROL

BPP

4.7 µF

4

3

C6

16 V

FL2

6

5

NC

T1

EE1621

InnoSwitch3-EP

INN3672C-H602

R9

47 Ω

1/10 W

FWD

R24

62 Ω

1/8 W

U1

C4

R8

1000 pF

200 kΩ

630 V

D1

R22

DFLR1600-7

68 Ω

600 V

D7

C5

22 µF

50 V

MMSZ5231B-7-F

D3

BAV21WS-7-F

6.2 kΩ
1/10 W

VR1

D V

R26
36 Ω

R6

1/10 W

S IS

AO4486

C22
1 nF

200 V

Q1

AO6420

SR

C21

1 nF

200 V

Q2

30 Ω

1/8 W

VO

R25

2.2 µF

C19

680 µF

16 V

C18

560 µF

6.3 V

C7

25 V

BPS

C8

330 pF

50 V

GND

FB

R29

100 Ω

1/10 W

C23

2.2 nF
50 V

R30

100 Ω

1/10 W

C24

2.2 nF
50 V

R16

133 kΩ

1%

1/16 W

R13

33.2 kΩ
1%

1/16 W

R12

0.2 Ω
1%

R27

1.2 MΩ
1%

1/16 W

10 µH

10 µH

L2

L3

VR2

SMAZ8V2-13-F

8.2 V

C12

2.2 µF
25 V

C14

2.2 µF
25 V

12 V, 0.7 A

12 V

RTN

5 V, 0.3 A

RTN

Figure 9. Schematic DER-611, 5 V, 0.3 A and 12 V, 0.7 A for HVAC (Heating, Ventilation and Air-Conditioning) Application.

The circuit shown in Figure 9 is a low cost 5 V, 0.3 A and 12 V, 0.7 A
dual output power supply using INN3672C. This dual output design
features high efcient design satisfying cross regulation requirement
without a post-regulator.

Bridge rectier BR1 recties the AC input supply. Capacitors C2 and
C3 provide ltering of the rectied AC input and together with
inductor L1 form a pi-lter to attenuate differential mode EMI.
Y capacitor C10 connected between the power supply output and
input help reduce common mode EMI.

Thermistor RT1 limits the inrush current when the power supply is
connected to the input AC supply.

Input fuse F1 provides protection against excess input current
resulting from catastrophic failure of any of the components in the
power supply. One end of the transformer primary is connected to
the rectied DC bus; the other is connected to the drain terminal of
the MOSFET inside the InnoSwitch3-EP IC (U1).

A low-cost RCD clamp formed by diode D1, resistors R22, R8, and
capacitor C4 limits the peak drain voltage of U1 at the instant of
turn-off of the MOSFET inside U1. The clamp helps to dissipate the
energy stored in the leakage reactance of transformer T1.

The InnoSwitch3-EP IC is self-starting, using an internal high-voltage
current source to charge the PRIMARY BYPASS pin capacitor (C6)
when AC is rst applied. During normal operation the primary-side
block is powered from an auxiliary winding on the transformer T1.
Output of the auxiliary (or bias) winding is rectied using diode D7
and ltered using capacitor C5. Resistor R6 limits the current being
supplied to the PRIMARY BYPASS pin of InnoSwitch3-EP IC (U1). The
latch off primary-side overvoltage protection is obtained using Zener
diode VR1 with current limiting resistor R26.

The secondary-side controller of the InnoSwitch3-EP IC provides
output voltage sensing, output current sensing and drive to a
MOSFET providing synchronous rectication. The 5 V secondary of

the transformer is rectied by SR FET Q1 and ltered by capacitor
C18. High frequency ringing during switching transients that would
otherwise create radiated EMI is reduced via a snubber (resistor R24
and capacitor C22). The 12 V secondary of the transformer is rectied
by SR FET Q2 and ltered by capacitor C19. High frequency ringing
during switching transients that would otherwise create radiated EMI
is reduced via a snubber (resistor R25 and capacitor C21).

Synchronous rectications (SR) are provided by MOSFETs Q1 and Q2.
Q1 and Q2 are turned on by the secondary-side controller inside IC
U1, based on the winding voltage sensed via resistor R9 and fed into
the FORWARD pin of the IC.

In continuous conduction mode of operation, the MOSFET is turned
off just prior to the secondary-side’s commanding a new switching
cycle from the primary. In discontinuous conduction mode of
operation, the power MOSFET is turned off when the voltage drop
across the MOSFET falls below 0 V. Secondary-side control of the
primary-side power MOSFET avoids any possibility of cross
conduction of the two MOSFETs and provides extremely reliable
synchronous rectication.

The secondary-side of the IC is self-powered from either the
secondary winding forward voltage or the output voltage. Capacitor
C7 connected to the SECONDARY BYPASS pin of InnoSwitch3-EP IC
U1, provides decoupling for the internal circuitry.

Total output current is sensed by R12 between the IS and GROUND
pins with a threshold of approximately 35 mV to reduce losses. Once
the current sense threshold is exceeded the device adjusts the
number of switch pulses to maintain a xed output current.

The output voltages are sensed via resistor divider R13, R16, and
R27, and output voltages are regulated so as to achieve a voltage of

1.265 V on the FEEDBACK pin. The 12 V phase boost circuit, R30 and
C24, in parallel with 12 V feedback resistor, R27, and 5 V phase boost
circuit, R29 and C23, in parallel with 5 V feedback resistor, R16,
reduce the output voltage ripples. Capacitor C8 provides noise

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9

Rev. D 08/18