POWER INT200PFI2, INT200PFI1, INT200TFI2, INT200TFI1 Datasheet

INT200

HSD2

HS IN

PI–284C–072291

COM

N/C

LS IN

LS OUT

HSD1

Low-side Driver IC

Low-side Drive and High-side Control with Simultaneous Conduction Lockout

Product Highlights

®

5 V CMOS Compatible Control Inputs

• Combines logic inputs for low and high-side drives

• Schmidt-triggered inputs for noise immunity

Built-in High-voltage Level Shifters

• Integrated level shifters simplify high-side interface

• Can withstand up to 800 V for direct interface to the INT201 high-side driver

• Pulsed high-voltage level shifters reduce power consumption

Gate Drive Output for an External MOSFET

• Provides 300 mA sink/150 mA source current

• Can drive MOSFET gate at up to 15 V

• External MOSFET allows flexibility in design for various motor sizes

Built-in Protection Features

• Simultaneous conduction lockout protection

• UV lockout

Description

The INT200 Low-side driver IC provides gate drive for an external low-side MOSFET switch and high-side level shifting. When used in conjunction with the INT201 high-side driver, the INT200 provides a simple, cost-effective interface between low-voltage control logic and high-voltage loads. The INT200 is designed to be used with rectified 110 V or 220 V supplies. Both high-side and low-side switches can be controlled independently from ground-referenced 5 V logic inputs on the low side driver.

INT201

HS IN

LS IN

Figure 1. Typical Application

Figure 2. Pin Configuration.

INT200

3-PHASE

BRUSHLESS

DC MOTOR

PI-11762-012396

Built-in protection logic prevents both switches from turning on at the same time and shorting the high voltage supply. Pulsed level shifting saves power and provides enhanced noise immunity. The circuit is powered from a nominal 15 V supply to provide adequate gate drive for external N-channel MOSFETs.

Applications include motor drives, electronic ballasts, and uninterruptible power supplies. The INT200 can also be used to implement full- bridge and multi-phase configurations.

The INT200 is available in 8-pin plastic DIP and SOIC packages.

ORDERING INFORMATION

PART PACKAGE ISOLATION

NUMBER OUTLINE VOLTAGE

INT200PFI1 P08A 600 V INT200TFI1 T08A 600 V INT200PFI2 P08A 800 V INT200TFI2 T08A 800 V

January 1996

INT200

Pin Functional Description

Pin 1:

Active-low logic-level input HS IN controls the pulse circuit which signals the INT201 high-side driver.

Pin 2:

Active-high logic level input LS IN controls the low side driver output.

Pin 3: LS OUT is the driver output which

controls the low-side MOSFET.

Pin 4: COM connection; analog reference point

for the circuit.

Pin 5:

Level shift output HSD 2 signals the high-side driver to turn off. One short, precise pulse is sent on each positive transition of

HS IN

Pin 6:

Level shift output HSD 1 signals the high-side driver to turn on. Two short, precise pulses are sent on each negative transition of

HS IN

Pin 7:

N/C for creepage distance.

Pin 8: V

supplies power to the logic, high-

side interface, and low-side driver.

LINEAR

REGULATOR

UV

LOCKOUT

HS IN

LS IN

COM

Figure 3. Functional Block Diagram of the INT200

PULSE

CIRCUIT

DELAY

HSD1 HSD2

LS OUT

PI-286F-043093

1/96

INT200 Functional Description

INT200

5 V Regulator

The 5 V linear regulator circuit provides the supply voltage for the control logic and high-voltage level shift circuit. This allows the logic section to be directly compatible with 5 V CMOS logic without the need of an external 5 V supply.

Undervoltage Lockout

The undervoltage lockout circuit disables the LS OUT pin and both HSD pins whenever the VDD power supply falls below typically 9.0 V, and maintains this condition until the VDD power supply rises above typically 9.35 V. This guarantees that both MOSFETs will remain off during power-up or fault conditions.

HSD1/HSD2

The HSD1 and HSD2 outputs are connected to integrated high-voltage Nchannel MOSFET transistors which perform the level-shifting function for communication to the high-side driver. Controlled current capability allows the drain voltage to float with the high-side driver. Two individual channels produce a true differential communication channel for accurately controlling the high-side driver in the presence of fast moving high-voltage waveforms.

Pulse Circuit

The pulse circuit provides the two highvoltage level shifters with precise timing signals. Two pulses are sent over HSD1 to signal the high-side driver to turn on. One pulse is sent over HSD2 to signal the high-side driver to turn off. The combination of differential communication with the precise timing provides maximum immunity to noise.

Conduction Latch

An RS latch prevents the low-side driver and high-side driver from being on at the same time, regardless of the input signals. .

Delay Circuit

The delay circuit matches the low-side propagation delay with the combination of the pulse circuit, high voltage level shift, and high-side driver propagation delays. This ensures that the low-side driver and high-side driver will never be on at the same time during switching transitions in either direction.

Driver

The CMOS drive circuit provides drive power to the gate of the MOSFET used on the low side of the half bridge circuit. The driver consists of a CMOS buffer capable of driving an external transistor gate at up to 15 V.

HV+

8765

INT201

1234

8765

INT200

1234

HS IN

LS IN

HV-

Figure 4. Using the INT200 and INT201 in a 3-phase Configuration.

PHASE 1

PHASE 2

PHASE 3

3-PHASE

BRUSHLESS

DC MOTOR

PI-1461-042695

1/96

INT200

General Circuit Operation

One phase of a three-phase brushless DC motor drive circuit is shown in Figure 4 to illustrate an application of the INT200/201. The LS IN signal directly controls MOSFET Q1. The

HS IN

signal causes the INT200 to command the INT201 to turn MOSFET Q2 on or off as required. The INT200 will ignore input signals that would command both Q1 and Q2 to conduct simultaneously, protecting against shorting the HV+ bus to HV-.

Local bypassing for the low-side driver is provided by C1. Bootstrap bias for the high-side driver is provided by D1 and C2. Slew rate and effects of parasitic oscillations in the load waveforms are controlled by resistors R1 and R2.

The inputs are designed to be compatible with 5 V CMOS logic levels and should not be connected to VDD. Normal CMOS power supply sequencing should be observed. The order of signal application

should be VDD, logic signals, and then HV+. V

should be supplied from a

low impedance voltage source.

Maximum frequency of operation is limited by power dissipation due to highvoltage switching, gate charge, and bias

power. Figure 5 indicates the maximum The length of time that the high-side can remain on is limited by the size of the bootstrap capacitor. Applications with extremely long high-side on times

switching frequency as a function of

input voltage and gate charge. For higher

ambient temperatures, the switching

frequency should be derated linearly. require special techniques discussed in AN-10.

400

PDIP

VIN = 200 V

300

200

100

Switching Frequncy (kHz)

0 100 200

VIN = 300 V VIN = 400 V

Gate Charge (nC)

PI-1782-020696

Figure 5. Switching Frequency versus Gate Charge for a) PDIP and b) SOIC.

400

VIN = 200 V

300

200

100

Switching Frequncy (kHz)

0 100 200

VIN = 300 V VIN = 400 V

Gate Charge (nC)

SOIC

PI-1785-020696

HV+

8765

INT201

1234

8765

INT200

HV-

OSCILLATOR

Figure 6. Using the INT200 and INT201 to Drive a Fluorescent Lamp.

1234

FLUORESCENT

LAMP

PI-1462-042695

1/96

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