POSEICO AT607S08 Datasheet

Tj

From 75% VDRM up to 2600 A, gate 10V 5ohm

-30 /

standard specification

ANSALDO

Ansaldo Trasporti s.p.a.

Unita' Semiconduttori

PHASE CONTROL THYRISTOR AT607

Repetitive voltage up to 800 V
Mean on-state current 2585 A
Surge current 36 kA

FINAL SPECIFICATION

feb 97 - ISSUE : 03

Via N. Lorenzi 8 - I 16152 GENOVA - ITALY
Tel. int. +39/(0)10 6556549 - (0)10 6556488
Fax Int. +39/(0)10 6442510
Tx 270318 ANSUSE I -

Symbol Characteristic Conditions

[°C]

Value Unit

BLOCKING

V RRM Repetitive peak reverse voltage 140 800 V
V RSM Non-repetitive peak reverse voltage 140 900 V
V DRM Repetitive peak off-state voltage 140 800 V

I RRM Repetitive peak reverse current V=VRRM 140 100 mA
I DRM Repetitive peak off-state current V=VDRM 140 100 mA

CONDUCTING

I T (AV) Mean on-state current 180° sin, 50 Hz, Th=55°C, double side cooled 2585 A
I T (AV) Mean on-state current 180° sin, 50 Hz, Tc=85°C, double side cooled 2420 A

I TSM Surge on-state current sine wave, 10 ms 140 36 kA
I² t I² t without reverse voltage 6480 x1E3 A²s
V T On-state voltage On-state current = 6000 A 25 1.55 V
V T(TO) Threshold voltage 140 0.8 V

r T On-state slope resistance 140 0.120 mohm

SWITCHING

di/dt Critical rate of rise of on-state current, min.
dv/dt Critical rate of rise of off-state voltage, min. Linear ramp up to 70% of VDRM 140 500 V/µs
td Gate controlled delay time, typical VD=100V, gate source 25V, 10 ohm , tr=.5 µs 25 3 µs
tq Circuit commutated turn-off time, typical dV/dt = 20 V/µs linear up to 75% VDRM 250 µs
Q rr Reverse recovery charge di/dt=-20 A/µs, I= 1730 A 140 µC

I rr Peak reverse recovery current VR= 50 V A

I H Holding current, typical VD=5V, gate open circuit 25 300 mA

I L Latching current, typical VD=5V, tp=30µs 25 700 mA

140 200 A/µs

GATE

V GT Gate trigger voltage VD=5V 25 3.5 V

I GT Gate trigger current VD=5V 25 200 mA
V GD Non-trigger gate voltage, min. VD=VDRM 140 0.25 V
V FGM Peak gate voltage (forward) 30 V
I FGM Peak gate current 10 A
V RGM Peak gate voltage (reverse) 5 V
P GM Peak gate power dissipation Pulse width 100 µs 150 W
P G Average gate power dissipation 2 W

MOUNTING

R th(j-h) Thermal impedance, DC Junction to heatsink, double side cooled 21 °C/kW
R th(c-h) Thermal impedance Case to heatsink, double side cooled 6 °C/kW

T j Operating junction temperature
F Mounting force 22.0 / 24.5 kN

Mass 520 g

ORDERING INFORMATION : AT607 S 08

VDRM&VRRM/100

140 °C

AT607 PHASE CONTROL THYRISTOR

ANSALDO

FINAL SPECIFICATION feb 97 - ISSUE : 03

DISSIPATION CHARACTERISTICS

SQUARE WAVE

Th [°C]

140
130
120
110
100

30°

90

60°

80

90°

70
60

120°

180°

DC

50

PF(AV) [W]

4500
4000
3500
3000
2500
2000
1500
1000

500

0 500 1000 1500 2000 2500 3000 3500

IF(AV) [A]

180°

120°

90°

60°

30°

DC

0

0 500 1000 1500 2000 2500 3000 3500

IF(AV) [A]