POSEICO AT403S12 Datasheet
POSEICO SPA
P
P
P
OSEICO
OSEICO SPA
Ower SEmiconductors Italian COrporation
Via N. Lorenzi 8, 16152 Genova - ITALY
Tel. ++ 39 010 6556234 - Fax ++ 39 010 6557519
Sales Office:
Tel. ++ 39 010 6556775 - Fax ++ 39 010 6442510
PHASE CONTROL THYRISTOR AT403
Repetitive voltage up to 1200 V
Mean on-state current 400 A
Surge current 5 kA
FINAL SPECIFICATION
gen 03 - ISSUE : 05
Symbol Characteristic Conditions
Tj
[°C]
Value Unit
BLOCKING
V RRM Repetitive peak reverse voltage 125 1200 V
V
RSM Non-repetitive peak reverse voltage 125 1300 V
V
DRM Repetitive peak off-state voltage 125 1200 V
I
RRM Repetitive peak reverse current V=VRRM 125 30 mA
I
DRM Repetitive peak off-state current V=VDRM 125 30 mA
CONDUCTING
I T (AV) Mean on-state current 180° sin, 50 Hz, Th=55°C, double side cooled 400 A
I
T (AV) Mean on-state current 180° sin, 50 Hz, Tc=85°C, double side cooled 320 A
I
TSM Surge on-state current sine wave, 10 ms 125 5 kA
I² t I² t without reverse voltage 125 x1E3 A²s
V
T On-state voltage On-state current = 600 A 25 1.35 V
V
T(TO) Threshold voltage 125 1.0 V
r
T On-state slope resistance 125 0.850 mohm
SWITCHING
di/dt Critical rate of rise of on-state current, min. From 75% VDRM up to 410 A, gate 10V 5ohm 125 200 A/µs
dv/dt Critical rate of rise of off-state voltage, min. Linear ramp up to 70% of VDRM 125 500 V/µs
td Gate controlled delay time, typical VD=100V, gate source 10V, 10 ohm , tr=.5 µs 25 0.6 µs
tq Circuit commutated turn-off time, typical dV/dt = 20 V/µs linear up to 75% VDRM 200 µs
Q rr Reverse recovery charge di/dt=-20 A/µs, I= 270 A 125 µC
I rr Peak reverse recovery current VR= 50 V A
I
H Holding current, typical VD=5V, gate open circuit 25 300 mA
I
L Latching current, typical VD=5V, tp=30µs 25 700 mA
GATE
V GT Gate trigger voltage VD=5V 25 3.5 V
I
GT Gate trigger current VD=5V 25 200 mA
V
GD Non-trigger gate voltage, min. VD=VDRM 125 0.25 V
V
FGM Peak gate voltage (forward) 20 V
I
FGM Peak gate current 8A
V
RGM Peak gate voltage (reverse) 5V
P
GM Peak gate power dissipation Pulse width 100 µs 75 W
P
G Average gate power dissipation 1 W
MOUNTING
R th(j-h) Thermal impedance, DC Junction to heatsink, double side cooled 95 °C/kW
R
th(c-h) Thermal impedance Case to heatsink, double side cooled 20 °C/kW
j Operating junction temperature -30 / 125 °C
T
F Mounting force 4.9 / 5.9 kN
Mass 55 g
ORDERING INFORMATION : AT403 S 12
standard specification
VDRM&VRRM/100
AT403 PHASE CONTROL THYRISTOR
P
P
P
FINAL SPECIFICATION gen 03 - ISSUE : 05
DISSIPATION CHARACTERISTICS
SQUARE WAVE
Th [°C]
130
120
110
100
90
30°
80
70
60
50
0 100 200 300 400 500 600
60°
90°
120°
180°
OSEICO
DC
OSEICO SPA
Ower SEmiconductors Italian COrporation
F(AV) [W]
P
800
700
600
500
400
300
200
100
F(AV) [A]
I
DC
180°
30°
60°
90°
120°
0
0 100 200 300 400 500 600
F(AV) [A]
I
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