POLYTRON ST6242 Schematic

8-BIT OTP/EPROM MCU WITH LCD DRIVER,

■ 3.0 to 6.0V Supply Operating Range

■ 8 MHz Maximum Clock Frequency

■ -40 to +85°C Operating Temperature Range

■ Run, Wait and Stop Modes

■ 5 Interrupt Vectors

■ Look-up Table capability in Program Memory

■ Data Storage in Program Memory:

User selectable size

■ Data RAM: 192 bytes

■ Data EEPROM: 128 bytes

■ User Programmable Options

■ 18 I/O pins, fully programmable as:

– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
– LCD segments (8 combiport lines)

■ 4 I/Olinescan sink up to 20mA todrive LEDs or

TRIACs directly

■ Two 8-bit Timer/Counter with 7-bit

programmable prescaler

■ Digital Watchdog

■ 8-bit A/D Converter with 6 analog inputs

■ 8-bit Synchronous Peripheral Interface (SPI)

■ LCD driver with 40 segment outputs, 4

backplane outputs and selectable multiplexing
ratio.

■ On-chip Clockoscillator canbe driven by Quartz

Crystal or Ceramic resonator

■ One external Non-Maskable Interrupt

■ ST6242-EMU2 Emulation and Development

System (connects to an MS-DOS PC via a
parallel port).

ST62T42B/E42B

EEPROM AND A/D CONVERTER

PQFP64

CQFP64W

(See end of Datasheet for Ordering Information)

DEVICE SUMMARY

DEVICE

ST62T42B 7948 - 10to 18
ST62E42B 7948 10 to 18

OTP

(Bytes)

EPROM

(Bytes)

I/O Pins

Rev. 2.6

August 1999 1/68

1

Table of Contents

Document

Page

ST62T42B/E42B . ....................................1

1 GENERAL DESCRIPTION . . . . . . ................................................ 5

1.1 INTRODUCTION . . . . . . . . . . . . . ............................................5

1.2 PIN DESCRIPTIONS . . . . . . ................................................7

1.3 MEMORY MAP . . . . . . . . . . ................................................8

1.3.1 Introduction . . . ..................................................... 8

1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . ................................. 8

1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . .............................. 10

1.3.4 Stack Space . . . . . . . . . . . . ...........................................10

1.3.5 Data Window Register (DWR) . ........................................11

1.3.6 Data RAM/EEPROM Bank Register (DRBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.3.7 EEPROM Description . . . . . . . . . . . . . . . . . . . . ........................... 13

1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.4.1 Option Byte . . . .................................................... 15

1.4.2 Program Memory . . . ................................................ 15

1.4.3 EEPROM Data Memory . . . . . . . . . . . . . . . . . . . ........................... 15

1.4.4 EPROM Erasing .................................................... 15

2 CENTRAL PROCESSING UNIT . . ............................................... 16

2.1 INTRODUCTION . . . . . . . . . . . . . ........................................... 16

2.2 CPU REGISTERS . . . .................................................... 16

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . ................... 18

3.1 CLOCK SYSTEM . . . . . . . . . . . . . ...........................................18

3.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . ................................. 18

3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.1 RESET Input . . .................................................... 19

3.2.2 Power-on Reset .................................................... 19

3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . ................................. 20

3.2.4 Application Notes . . . ................................................ 20

3.2.5 MCU Initialization Sequence . . . . . . . . .................................. 20

3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . .................................. 22

3.3.1 Digital Watchdog Register (DWDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.3.2 Application Notes . . . ................................................ 24

3.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 26

3.4.1 Interrupt request . ...................................................26

3.4.2 Interrupt Procedure . . . . . . . . . . . . . . . . ................................. 27

3.4.3 Interrupt Option Register (IOR) . . . .. . . . . . . . . . . . . . . . . . . . . ............... 28

3.4.4 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 30

3.5.1 WAIT Mode ....................................................... 30

3.5.2 STOP Mode . . . . . . . . ...............................................30

3.5.3 Exit from WAIT and STOP Modes . . . . ..................................31

2/68

2

68

Table of Contents

4 ON-CHIP PERIPHERALS . . . . . . . . . . . ...........................................32

4.1 I/O PORTS . . . . . . . . . . . . . . . . . . ...........................................32

4.1.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . ........................... 33

4.1.2 Safe I/O State Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5 I/O PORTS (Cont’d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 34

5.0.1 LCD alternate functions (combiports) . ..................................36

5.0.2 SPI alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 36

5.0.3 I/O Port Option Registers . . . . . . . . . . . .................................. 37

5.0.4 I/O Port Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.0.5 I/O Port Data Registers . . . . . . ........................................ 37

5.1 TIMER 1 & 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . ................................. 38

5.1.1 TIMER 1 & 2 Operating Mode ......................................... 40

5.1.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . ................................40

5.1.3 Application Notes . . . ................................................ 40

5.1.4 TIMER 1 Registers . . . . . . . . . . ........................................41

5.1.5 TIMER 2 Registers . . . . . . . . . . ........................................42

5.2 A/D CONVERTER (ADC) . . ............................................... 43

5.2.1 Application Notes . . . ................................................ 43

5.3 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . ........... 45

5.4 LCD CONTROLLER-DRIVER . . . . . . ........................................47

5.4.1 Multiplexing ratio and frame frequency setting . . . . . . . . . ...................48

5.4.2 Segment and common plates driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.4.3 LCD RAM . . . . . .................................................... 49

5.4.4 Stand by or STOP operation mode . . . . . . . . . . . . . . . . . . . . . . ............... 50

5.4.5 LCD Mode Control Register (LCDCR) . . .................................50

6 SOFTWARE . . . . . . . . . . . . . . . . . ............................................... 51

6.1 ST6 ARCHITECTURE . ...................................................51

6.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . .................................. 51

6.3 INSTRUCTION SET . . . . . . . ............................................... 52

7 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . .............................. 57

7.1 ABSOLUTE MAXIMUM RATINGS . . . ........................................57

7.2 RECOMMENDED OPERATING CONDITIONS . . . .............................. 58

7.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........59

7.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

7.5 A/D CONVERTERCHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

7.6 TIMER CHARACTERISTICS . . . . ...........................................61

7.7 SPI CHARACTERISTICS . . ...............................................61

7.8 LCD ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . ............... 61

7.9 PSS ELECTRICAL CHARACTERISTICS (WHEN AVAILABLE) . ................... 61

8 GENERAL INFORMATION . . . . . . . . . . ........................................... 62

8.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . ........................... 62

8.2 PACKAGE THERMAL CHARACTERISTIC . . . . . . . . ........................... 63

8.3 ORDERING INFORMATION . . . . . . . . . . . . . .................................. 63

Document

Page

3/68

3

Table of Contents

Document

Page

ST6242B ...........................................65

1 GENERAL DESCRIPTION . . . . . . ............................................... 66

1.1 INTRODUCTION . . . . . . . . . . . . . ........................................... 66

1.2 ROM READOUT PROTECTION . . . . . . . . . . . . ................................66

1.3 ORDERING INFORMATION . . . . . . . . . . . . . .................................. 68

1.3.1 Transfer of Customer Code . . . . . . . . . . ................................. 68

1.3.2 Listing Generation and Verification . . . . ................................. 68

4/68

4

68

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

ST62T42B/E42B

The ST62T42B and ST62E42B devices are low
cost members of the ST62xx 8-bit HCMOS family
of microcontrollers, which are targeted at low to
medium complexity applications. All ST62xx de­vices are based on a building block approach: a

Figure 1. Block Diagram

8-BIT

TEST/V

NMI

PP

TEST

INTERRUPT

PROGRAM

Memory

7948 bytes

A/D CONVERTER

DATA ROM

USER

SELECTABLE

DATA RAM

192 Bytes

DATA EEPROM

128 Bytes

common core is surrounded by a number of on­chip peripherals.

The ST62E42B is the erasable EPROM version of
the ST62T42B device, which may be used to em­ulate the ST62T42B device, as well as the respec­tive ST6242B ROM devices.

PORT A

PORT B

PORT C

LCD DRIVER

TIMER 2

PA4..PA7/Ain

PB2..PB3/Ain
PB4/20mA Sink
PB5/Scl/20mA Sink
PB6/Sin/20mA Sink
PB7/Sout/20mA Sink

PC0..PC7/S33..S40

S9..S32, S41..S48

COM1..COM4

VLCD
VLCD1/3
VLCD2/3

STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6

POWER

SUPPLY

V

DDVSS

(V

on EPROM/OTP versions only)

PP

PC

8 BIT CORE

OSCILLATOR

OSCin OSCout RESET

TIMER 1

DIGITAL

WATCHDOG

SPI (SERIAL

PERIPHERAL

INTERFACE)

RESET

VA0479M

5/68

5

ST62T42B/E42B

INTRODUCTION (Cont’d)

OTP and EPROM devices are functionally identi-

Figure 2. 64 Pin QFP Package

cal. The ROM based versions offer the same func­tionality selecting as ROM options the options de­fined in the programmable option byte of the

3348

OTP/EPROM versions.OTP devices offer all the
advantages of user programmability at low cost,

49

32

which make them the ideal choice in a wide range
of applications where frequent code changes, mul­tiple code versions or last minute programmability
are required.

These compact low-cost devices feature two Tim­ers comprising an 8-bit counter and a 7-bit pro­grammable prescaler, EEPROM data capability, a
serial synchronous port interface (SPI), an 8-bit
A/D Converter with 6 analog inputs, a Digital
Watchdog timer, and a complete LCD controller
driver, making them well suitedfor a wide range of

64

12

3

16

automotive, appliance and industrial applications.

Table 1. ST6242 Pin Description

Pin

number

1 S45 17 VDD 33 S13 49 S29
2 S46 18 VSS 34 S14 50 S30
3 S47 19 RESET 35 S15 51 S31
4 S48 20 OSCout 36 S16 52 S32
5 COM4 21 OSCin 37 S17 53 PC0/S33
6 COM3 22 NMI 38 S18 54 PC1/S34
7 COM2 23 PB7/ Sout * 39 S19 55 PC2/S35
8 COM1 24 PB6/ Sin* 40 S20 56 PC3/S36

9 VLCD1/ 3 25 PB5/ SCL * 41 S21 57 PC4/S37
10 VLCD2/ 3 26 PB4 * 42 S22 58 PC5/S38
11 VLCD 27 PB3/ Ain 43 S23 59 PC6/S39
12 PA7/Ain 28 PB2/ Ain 44 S24 60 PC7/S40
13 PA6/Ain 29 S9 45 S25 61 S41
14 PA5/Ain 30 S10 46 S26 62 S42
15 PA4/Ain 31 S11 47 S27 63 S43
16 TEST 32 S12 48 S28 64 S44

Pin

name

Pin

number

Pin

name

Pin

number

Pin

name

Pin

number

17

VR01649B

Pin

name

*Note: 20mA Sink

6/68

6

1.2 PIN DESCRIPTIONS

ST62T42B/E42B

VDDand VSS. Power is supplied to the MCU via

these two pins. VDDis the power connection and
VSSis the ground connection.

OSCin and OSCout. These pins are internally
connected tothe on-chip oscillator circuit. A quartz
crystal, a ceramic resonator or an external clock
signal can be connected between these two pins.
The OSCin pin is the input pin, the OSCout pin is
the output pin.

RESET. The active-low RESET pin is used to re­start the microcontroller.

TEST/VPP. The TEST must be held at VSSfor nor-
mal operation (an internal pull-down resistor se­lects normal operating mode if TEST pin is not
connected). If TEST pin is connected to a +12.5V
level during the reset phase, the EPROM/OTP
programming Mode is entered.

NMI. TheNMI pin provides the capability for asyn­chronous interruption, byapplying an external non
maskable interrupt to the MCU. The NMI input is
falling edge sensitive with Schmitt trigger charac­teristics. The user can select as option the availa­bility of an on-chip pull-up at this pin.

PA4-PA7. These 4 lines are organised as one I/O
port (A). Each line may be configured under soft­ware control as input with or without internal pull­up resistors, input with interrupt generation and
pull-up resistor, open-drain or push-pull outputs, or
as analog inputs for the A/D converter.

PB2...PB7. These 6 lines are organised asone I/O
port (B). Each line may be configured under soft-

ware control as input with or without internal pull­up resistors, input with interrupt generation and
pull-up resistor, open-drain or push-pull output or
as analog input for the A/D converter. PB0..PB3
can be used as analog inputs for the A/D con­verter, while PB7/Sout, PB6/Sin and PB5/Scl can
be used respectively as data out, data in and
Clock pins for the on-chip SPI. In addition,
PB4..PB7 can sink 20mA for direct LED or TRIAC
drive.

PC0-PC7. These 8 lines are organised as one I/O
port (C). Each line may be configured under soft­ware control as input with or without internal pull­up resistor, input with interrupt generation and
pull-up resistor, open-drain or push-pull output, or
as LCD segment output S33..S40.

COM1-COM4. These four pins are the LCD pe­ripheral common outputs. They are the outputs of
the on-chip backplane voltage generator which is
used for multiplexing the 45 LCD lines allowingup
to 180 segments to be driven.

S9-S48. These pins are the 40 LCD peripheral
segment outputs. S33..S40 are alternate functions
of the Port C I/O pins. (Combiports feature)

VLCD. Display voltage supply. It determines the
high voltage level on COM1-COM4 and S4-S48
pins.

VLCD1/3, VLCD2/3. Display supplyvoltage inputs
for determining the display voltage levels on
COM1-COM4 and S4-S48 pins during multiplex
operation.

7/68

7

ST62T42B/E42B

1.3 MEMORY MAP

1.3.1 Introduction

The MCU operates in three separate memory
spaces: Program space, Data space, and Stack
space. Operationin these three memory spaces is
described in the following paragraphs.

Briefly, Program space contains user program
code in Program memory and user vectors; Data
space contains user data in RAM and in Program
memory, and Stack space accommodates six lev­els of stack for subroutine and interrupt service
routine nesting.

1.3.2 Program Space

Program Space comprises the instructions to be
executed, the data required for immediate ad­dressing mode instructions, the reserved factory
test area and the user vectors. Program Space is
addressed via the 12-bit Program Counter register
(PC register).

Program Space is organised in four 2K pages.
Three of them are addressedin the 000h-7FFh lo­cations of the Program Space by the Program
Counter and by writing the appropriate code in the
Program ROM Page Register (PRPR register). A

Figure 4. Memory Addressing Diagram

common (STATIC) 2K page is available all the
time for interrupt vectors and common subrou­tines, independently of the PRPR register content.
This “STATIC” page is directly addressed in the
0800h-0FFFh by the MSB of the ProgramCounter
register PC 11. Note this page can also be ad­dressed in the 000-7FFh range. It is two different
ways of addressing the same physical memory.

Jump from a dynamic page to another dynamic
page is achieved by jumping back to the static
page, changing contents of PRPR and then jump­ing to the new dynamic page.

Figure 3. 8Kbytes Program Space Addressing

PC
SPACE

000h

7FFh
800h

FFFh

0000h

Page 0

Page 1

Static
Page

ROM SPACE

Page 1

Static
Page

1FFFh

Page 2 Page 3

0000h

0FF0h

0FFFh

PROGRAM SPACE

PROGRAM

MEMORY

INTERRUPT &

RESET VECTORS

0-63

000h

03Fh
040h

07Fh
080h
081h
082h
083h
084h

0C0h

0FFh

DATA SPACE

RAM / EEPROM
BANKING AREA

DATA READ-ONLY

MEMORY

X REGISTER
Y REGISTER
V REGISTER

W REGISTER

DATA READ-ONLY

WINDOW SELECT

BANK SELECT

ACCUMULATOR

WINDOW

RAM

MEMORY

DATA RAM

VR01568

8/68

8

MEMORY MAP (Cont’d)

ST62T42B/E42B

Table 2. ST62E42B/T42B Program MemoryMap

ROM Page Device Address Description

Page 0

Page 1
“STATIC”

Page 2

Page 3

0000h-007Fh
0080h-07FFh

0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFFh

0000h-000Fh

0010h-07FFh

0000h-000Fh

0010h-07FFh

Reserved

User ROM
User ROM

Reserved

Interrupt Vectors

Reserved

NMI Vector

Reset Vector

Reserved

User ROM

Reserved

User ROM

Note: OTP/EPROM devices can be programmed
with thedevelopment toolsavailable fromSTMicro­electronics (ST62E4X-EPB or ST6240-KIT).

1.3.2.1 Program ROM Page Register (PRPR)

The PRPR register can be addressed like a RAM
location in the Data Space at the address CAh ;
nevertheless it is a write only register that cannot
be accessed with single-bit operations. This regis­ter is used to select the 2-Kbyte ROM bank of the
Program Space that will be addressed. The
number of the page has to be loaded in the PRPR
register. Refer to the Program Space description
for additional information concerning the use of
this register. The PRPR register is not modified
when an interrupt or a subroutine occurs.

Care is required when handling the PRPR register
as it is write only. For this reason, it is not allowed
to change the PRPR contents while executing in­terrupt service routine, as the service routine
cannot save and then restore its previous content.
This operation may be necessary if common rou­tines and interrupt service routines take more than
2K bytes; in this case it could be necessary to di­vide the interruptservice routineinto a (minor) part
in the static page (start and end) and to a second
(major) part in one ofthe dynamic pages. If it is im­possible to avoid the writing ofthis register in inter­rupt service routines, an image of this register
must be saved in a RAM location, and each time
the program writes to the PRPR it must write also
to the image register. The image register must be
written before PRPR, so if an interrupt occurs be­tween the two instructions the PRPR is not af­fected.

Program ROM Page Register (PRPR)

Address: CAh — Write Only

70

- - - - - - PRPR1 PRPR0

Bits 7-2= Not used.
Bit 1-0 = PRPR1-PRPR0:

Program ROM Select.

These two bits select the corresponding page to
be addressed in the lower part of the 4K program
address space as specified in Table 3.

Caution

: this register is undefined on Reset. Nei­ther read nor single bit instructions may be used to
address this register.

Table 3. 8Kbytes Program ROM Page Register

Coding

PRPR1 PRPR0 PC bit 11 Memory Page

X X 1 Static Page (Page 1)

0 0 0 Page 0
0 1 0 Page 1 (Static Page)
1 0 0 Page 2
1 1 0 Page 3

1.3.2.2 Program Memory Protection

The Program Memory in OTP or EPROM devices
can be protected againstexternal readoutof mem­ory by selecting the READOUT PROTECTION op­tion in the option byte.

In the EPROM parts, READOUT PROTECTION
option can be disactivated only by U.V. erasure
that also results into the whole EPROM context
erasure.

Note: Once the Readout Protection is activated, it
is no longer possible, even for STMicroelectronics,
to gain access to the Program memory contents.
Returned parts with a protection set can therefore
not be accepted.

9/68

9

ST62T42B/E42B

MEMORY MAP (Cont’d)

1.3.3 Data Space

Data Space accommodates all the data necessary
for processing the user program. This space com­prises the RAM resource, the processor core and
peripheral registers, as well as read-only data
such as constants and look-up tables in Program
memory.

1.3.3.1 Data ROM

All read-only data is physically stored in program
memory, which also accommodates the Program
Space. The program memory consequently con­tains the program code to be executed, as well as
the constants and look-up tables required by the
application.

The Data Space locations in which the different
constants and look-up tables are addressedby the
processor core may be thought of as a 64-byte
window through which it is possible to access the
read-only data stored in Program memory.

1.3.3.2 Data RAM/EEPROM

In ST62T42B and ST62E42B devices, the data
space includes 60 bytes of RAM, the accumulator
(A), the indirect registers (X), (Y), the short direct
registers (V), (W), the I/O port registers, the pe­ripheral data and control registers, the interrupt
option register and the Data ROM Window Regis­ter (DRW register).

Additional RAM and EEPROM pages can also be
addressed using banks of 64 bytes located be­tween addresses 00h and 3Fh.

1.3.4 Stack Space

Stack space consists of six 12-bit registers which
are used to stack subroutine and interrupt return
addresses, as well as the current program counter
contents.

Table 4. Additional RAM/EEPROM Banks.

Device RAM EEPROM

ST62T42B/E42B 2 x 64 bytes 2 x 64 bytes

Table 5. ST62T42B/E42B Data Memory Space

DATA and EEPROM

DATAROM WINDOW AREA

X REGISTER 080h
Y REGISTER 081h
V REGISTER 082h

W REGISTER 083h

DATA RAM

PORT A DATAREGISTER 0C0h
PORT B DATAREGISTER 0C1h

SPI INTERRUPT DISABLE REGISTER 0C2h

PORT C DATAREGISTER 0C3h
PORT A DIRECTION REGISTER 0C4h
PORT B DIRECTION REGISTER 0C5h
PORT C DIRECTION REGISTER 0C6h

RESERVED 0C7h
INTERRUPT OPTION REGISTER 0C8h*
DATAROM WINDOWREGISTE R 0C9h*

ROM BANK SELECT REGISTER 0CAh*

RAM/EEPROM BANKSELECT REGISTER 0CBh*

PORT A OPTION REGISTER 0CCh

RESERVED 0CDh

PORT B OPTION REGISTER 0CEh
PORT C OPTION REGISTER 0CFh

A/D DATAREGISTER 0D0h

A/D CONTROL REGISTER 0D1h

TIMER 1 PRESCALER REGISTER 0D2h

TIMER 1 COUNTER REGISTER 0D3h

TIMER 1 STATUS/CONTROL REGISTER 0D4h

TIMER 2 PRESCALER REGISTER 0D5h

TIMER 2 COUNTER REGISTER 0D6h

TIMER 2 STATUS/CONTROL REGISTER 0D7h

WATCHDOGREGISTER 0D8h

RESERVED 0D9h

RESERVED 0DAh

RESERVED 0DBh

LCD MODE CONTROL REGISTER 0DCh

SPI DATAREGISTER 0DDh

RESERVED 0DEh

EEPROM CONTROL REGISTER 0DFh

LCD RAM

DATA RAM

ACCUMULATOR OFFh

* WRITE ONLYREGISTER

000h
03Fh

040h
07Fh

084h

0BFh

0E0h
0F7h

0F8h
0FEh

10/68

10

MEMORY MAP (Cont’d)

1.3.5 Data Window Register (DWR)

ST62T42B/E42B

Data Window Register (DWR)

The Data Read-Only Memory window is located
from address 0040h to address 007Fh in Data
space. It allows direct reading of 64 consecutive
bytes located anywhere in program memory, be­tween address0000h and 1FFFh (top memory ad­dress depends on the specific device). All the pro­gram memory can therefore beused tostore either
instructions or read-only data. Indeed, the window
can be moved in steps of 64 bytes along the pro­gram memoryby writingtheappropriate code inthe
Data Window Register (DWR).

The DWR can beaddressed like anyRAM location
in the Data Space, it is however a write-only regis­ter and therefore cannotbe accessed using single­bit operations. This register is used to position the
64-byte read-only data window (from address 40h
to address 7Fh of the Data space) in program
memory in 64-byte steps. The effective address of
the byte to be read as data in program memory is
obtained by concatenating the 6 least significant
bits of the register address given in the instruction
(as least significant bits) and the content of the
DWR register(as most significant bits), as illustrat­ed in Figure 5 below. For instance, when address­ing location 0040h of the Data Space, with 0 load­ed in the DWR register, the physical location ad­dressed inprogram memory is 00h. The DWRreg­ister is not cleared on reset, therefore it must be
written to prior tothe first access to the Data read­only memory window area.

Address: 0C9h — Write Only

70

- - DWR5 DWR4 DWR3 DWR2 DWR1 DWR0

Bits 6, 7 = Not used.
Bit 5-0 = DWR5-DWR0:

Window Register Bits.

Data read-only memory

These are the Data read­only memory Window bits that correspond to the
upper bits of the data read-only memory space.

Caution:

This register is undefined on reset. Nei­ther read nor single bit instructions may be used to
address this register.

Note: Care is required when handling the DWR
register as it is write only. For this reason, the
DWR contents should not be changed while exe­cuting an interrupt service routine, as the service
routine cannot saveand then restore the register’s
previous contents. If it is impossible to avoid writ­ing to the DWR during the interrupt service routine,
an image of the register must be saved in a RAM
location, and each time the program writes to the
DWR, it must also write to the image register. The
image register must be written first so that, if an in­terrupt occurs between the two instructions, the
DWR is not affected.

Figure 5. Data read-only memory Window Memory Addressing

543210

DATA ROM

WINDOW REGISTER

CONTENTS

(DWR)

12

13

765432 0

67891011

1

543210

01

Example:

DWR=28h

ROM

ADDRESS:A19h

11

00000000

11

0

0000

0

1

1

01001

1

11

PROGRAM SPACE ADDRESS

READ

DATA SPACE ADDRESS

40h-7Fh

IN INSTRUCTION

DATA SPACE ADDRESS

59h

VR01573A

11/68

11

ST62T42B/E42B

MEMORY MAP (Cont’d)

1.3.6 Data RAM/EEPROM Bank Register
(DRBR)

Address: CBh — Write only

70

- - - DRBR4 DRBR3 - DRBR1 DRBR0

Bit 7-5 = These bits are not used
Bit 4 - DRBR4. This bit, when set, selects RAM

Page 2.
Bit 3 - DRBR3. This bit, when set, selects RAM

Page 1.
Bit2. This bit is not used.
Bit 1 - DRBR1. This bit, when set, selects

EEPROM Page 1.
Bit 0 - DRBR0. This bit, when set, selects

EEPROM Page 0.
The selection of the bank is made by programming

the Data RAM Bank Switch register (DRBR regis­ter) located at address CBh of the Data Space ac­cording to Table 1. No more than one bank should
be set at a time.

The DRBR register can be addressed like a RAM
Data Space at the address CBh; nevertheless it is
a write only register that cannot be accessed with
single-bit operations. This register isused to select
the desired 64-byte RAM/EEPROM bank of the
Data Space. Thenumber of banks has to be load­ed in the DRBR register and the instruction has to
point to the selected location as if it was in bank 0
(from 00h address to 3Fhaddress).

This register is not cleared during the MCU initiali­zation, therefore it must be written before the first
access to the Data Space bank region. Refer to
the Data Space description for additional informa­tion. The DRBR register is not modified when an
interrupt or a subroutine occurs.

Notes :
Care is required when handling the DRBR register

as it is write only. For this reason, it is not allowed
to change the DRBR contents while executing in­terrupt service routine, as the service routine can­not save and thenrestore its previous content. If it
is impossible to avoid the writing of this register in
interrupt service routine, an image of this register
must be saved in a RAM location, and each time
the program writes to DRBR it must write also to
the image register. The image register must be
written first, so if an interrupt occurs between the
two instructions the DRBR is not affected.

In DRBR Register, only 1 bit must be set. Other­wise two or more pages are enabled in parallel,
producing errors.

Table 6. Data RAM Bank Register Set-up

DRBR ST62T42B/E42B

00h None
01h EEPROM Page 0
02h EEPROM Page 1

08h RAM Page 1
10h1 RAM Page 2
other Reserved

12/68

12

MEMORY MAP (Cont’d)

1.3.7 EEPROM Description

EEPROM memory is located in 64-byte pages in
data space. This memory maybe used by theuser
program for non-volatile data storage.

Data spacefrom 00h to3Fh is paged as described
in Table 7. EEPROM locations are accessed di­rectly by addressing these paged sections of data
space.

The EEPROM does not require dedicated instruc­tions forreadorwrite access.Onceselectedvia the
Data RAM Bank Register, the active EEPROM
page is controlled by the EEPROM Control Regis­ter (EECTL), which is described below.

Bit E20FFof the EECTL registermust bereset prior
to any write or read access to the EEPROM. If no
bank hasbeen selected, or if E2OFF is set, any ac­cess is meaningless.

Programming must be enabled by setting the
E2ENA bit of the EECTL register.

The E2BUSY bitof the EECTL register is setwhen
the EEPROM is performing a programming cycle.
Any access to the EEPROM when E2BUSY is set
is meaningless.

Provided E2OFF and E2BUSY are reset, an EEP­ROM location is read just like any other data loca­tion, also in terms of access time.

Writing to the EEPROM may be carried out in two
modes: Byte Mode (BMODE) and Parallel Mode

ST62T42B/E42B

(PMODE). In BMODE, one byte is accessed at a
time, while in PMODE up to 8 bytes in the same
row are programmed simultaneously (with conse­quent speed and power consumption advantages,
the latter being particularly important in battery
powered circuits).

General Notes:
Data should be written directly to the intended ad-

dress in EEPROM space. There is nobuffer mem­ory between data RAM and the EEPROM space.

When the EEPROM is busy (E2BUSY = “1”)
EECTL cannot be accessed in write mode, it is
only possible to read the status of E2BUSY. This
implies that as long as the EEPROM is busy, it is
not possible to change the status of the EEPROM
Control Register. EECTL bits 4 and 5 are reserved
and must never be set.

Care is required whendealing withthe EECTL reg­ister, as some bits are write only. For this reason,
the EECTL contents must not be altered while ex­ecuting an interrupt service routine.

If it is impossible to avoid writing to this register
within an interrupt service routine, an image of the
register must be saved in a RAM location, and
each time the program writes to EECTL it must
also write to the image register.The image register
must be written to first so that, if an interrupt oc­curs between the two instructions, the EECTL will
not be affected.

Table 7. Row Arrangement for Parallel Writing of EEPROM Locations

Dataspace
addresses.
Banks 0and 1.

Byte 0 1234567
ROW7 38h-3Fh
ROW6 30h-37h
ROW5 28h-2Fh
ROW4 20h-27h
ROW3 18h-1Fh
ROW2 10h-17h
ROW1 08h-0Fh
ROW0 00h-07h

Up to 8 bytes in each row may be programmed simultaneously in Parallel Write mode.

The number of available 64-byte banks (1 or 2) is device dependent.

13/68

13

ST62T42B/E42B

MEMORY MAP (Cont’d)
Additional Notes on Parallel Mode:

If the user wishes to perform parallel program­ming, the first step should be to set the E2PAR2
bit. From this time on, the EEPROM will be ad­dressed in write mode, the ROW address will be
latched and it will be possible to change it only at
the end of the programming cycle, or by resetting
E2PAR2 without programming the EEPROM. Af­ter the ROW addressis latched,the MCU can only
“see” the selected EEPROM row and any attempt
to write or read other rows will produce errors.

The EEPROM should not be read while E2PAR2
is set.

As soon as the E2PAR2 bit is set, the 8 volatile
ROW latches are cleared. From this moment on,
the user can load data in allor in part ofthe ROW.
Setting E2PAR1 will modify the EEPROM regis­ters corresponding to the ROW latches accessed
after E2PAR2. For example, if the software sets
E2PAR2 and accesses the EEPROM by writing to
addresses 18h, 1Ah and 1Bh, and then sets
E2PAR1, these three registers will be modified si­multaneously; the remaining bytes in the row will
be unaffected.

Note that E2PAR2 is internally reset at the end of
the programming cycle. This implies that the user
must setthe E2PAR2 bit between two parallel pro­gramming cycles. Note that if the user tries to set
E2PAR1 while E2PAR2 is not set, there will be no
programming cycleand the E2PAR1 bit will be un­affected. Consequently, the E2PAR1bit cannot be
set if E2ENA is low. The E2PAR1 bit can be setby
the user, only if the E2ENA and E2PAR2 bits are
also set.

EEPROM Control Register (EECTL)

Address: DFh — Read/Write
Reset status: 00h

70

D7 E2OFF D5 D4 E2PAR1 E2PAR2 E2BUSY E2ENA

Bit 7 = D7:

Unused.

Bit6= E2OFF:

Stand-byEnable Bit.

IfthisbitissettheEEPROMisdisabled(anyaccess
will bemeaningless) and the power consumption of
the EEPROM is reduced to its lowest value.

Bit 5-4 = D5-D4:
Bit 3 = E2PAR1:

Reserved.

MUST be kept reset.

Parallel Start Bit.

OnceinParallelMode,as soonastheuser software
sets the E2PAR1 bit, parallel writing of the 8 adja­cent registers will start. This bit is internally reset at
the end of the programming procedure. Note that
less than 8 bytescan bewritten if required, the un­defined bytes being unaffected by the parallel pro­grammingcycle;thisis explained ingreater detailin
the Additional Notes on Parallel Mode overleaf.

Bit 2 = E2PAR2:

Parallel Mode En. Bit.

ONLY. This bit must be set by the user program in
order to perform parallel programming. If E2PAR2
is set and the parallel start bit (E2PAR1) is reset,
up to 8 adjacent bytes can be written simultane­ously. These 8 adjacent bytes are considered as a
row, whose address lines A7, A6, A5, A4, A3 are
fixed while A2, A1 and A0 are the changingbits, as
illustrated in Table 7. E2PAR2 is automatically re­set at the end of any parallel programming proce­dure. It can be reset by the user software before
starting the programming procedure, thus leaving
the EEPROM registers unchanged.

Bit 1 = E2BUSY:

EEPROM Busy Bit.

LY. This bit is automatically set by the EEPROM
control logic when the EEPROM is in program­ming mode. The userprogram should test it before
any EEPROM read or write operation; any attempt
to access the EEPROM while the busy bit is set
will be aborted and the writing procedure in
progress will be completed.

Bit 0 = E2ENA:

EEPROM Enable Bit.

LY. This bit enables programming of the EEPROM
cells. It must be set before any write to the EEP­ROM register. Any attempt to write to the EEP­ROM when E2ENA is low is meaningless and will
not trigger a write cycle.

Caution:

This register is undefined on reset. Nei­ther read nor single bit instructions may be used to
address this register.

WRITE ONLY.

WRITE ONLY.

WRITE

READ ON-

WRITE ON-

14/68

14

1.4 PROGRAMMING MODES

ST62T42B/E42B

1.4.1 Option Byte

The Option Byte allows configuration capability to
the MCUs. Option byte’s content is automatically
read, and the selected options enabled, when the
chip reset is activated.

It can only be accessed during the programming
mode. This access is made either automatically
(copy from a master device) or by selecting the
OPTION BYTE PROGRAMMING modeof the pro­grammer.

The option byte is located in a non-user map. No
address has to be specified.

EPROM Code Option Byte

70

NMI

PULL

PRO­TECT

- WDACT - - -

-

Bit 7. Reserved.
Bit 6 = NMI PULL. . This bit mustbe set high to re-

move the NMI pin pull up resistor when it is low, a
pull up is provided.

Bit 5 = PROTECT. This bit allows the protection of
the software contents against piracy. When the bit
PROTECT is set high, readout of the OTP con­tents is prevented by hardware. No programming
equipment is able to gain access to the user pro­gram. When this bit is low, the user program can
be read.

Bit 4. Reserved.
Bit 3 = WDACT. This bit controls the watchdog ac-

tivation. When it is high, hardware activation is se­lected. The software activation is selected when
WDACT is low.

Bit 2 = Reserved. Must be set to 1.
Bit 1-0 = Reserved.
The Option byte is written during programming ei-

ther by using the PC menu (PC driven Mode) or

1.4.2 Program Memory

EPROM/OTP programming mode is set by a
+12.5V voltage applied to the TEST/VPPpin. The
programming flow of the ST62T42B/E42B is de­scribed in the User Manual of the EPROM Pro­gramming Board.

The MCUs can be programmed with the
ST62E4xB EPROM programming tools available
from STMicroelectronics.

1.4.3 EEPROM Data Memory

EEPROM data pages are supplied in the virgin
state FFh. Partial or total programming of EEP­ROM data memory can be performed either
through the application software, or through anex­ternal programmer. Any STMicroelectronics tool
used for the program memory (OTP/EPROM) can
also be used to program the EEPROM data mem­ory.

1.4.4 EPROM Erasing

The EPROM of the windowed package of the
MCUs may be erased by exposure to Ultra Violet
light. The erasure characteristic of the MCUs is
such that erasure begins when the memory is ex­posed to light with a wave lengths shorter than ap­proximately 4000Å. It should be noted that sun­lights and some types of fluorescent lamps have
wavelengths in the range 3000-4000Å.

It is thus recommended that the window of the
MCUs packages be covered by an opaque label to
prevent unintentional erasure problems when test­ing the application in such an environment.

The recommended erasure procedure of the
MCUs EPROM is the exposure to short wave ul­traviolet light which have a wave-length 2537A.
The integrated dose (i.e. U.V. intensity x exposure
time) for erasure should be a minimum of 15W­sec/cm2. The erasure time with this dosage is ap­proximately 15 to 20 minutes using an ultraviolet
lamp with 12000µW/cm2power rating. The
ST62E42B should be placed within 2.5cm (1Inch)
of the lamp tubes during erasure.

automatically (stand-alone mode)

15/68

15

ST62T42B/E42B

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

The CPU Coreof ST6devicesisindependent ofthe
I/O or Memory configuration. As such, it may be
thought of as an independent central processor
communicating with on-chip I/O, Memory and Pe­ripherals via internal address, data, and control
buses. In-core communication is arranged as
shown in Figure 6; the controller being externally
linked to both the Reset and Oscillator circuits,
while thecore is linked to thededicated on-chip pe­ripherals via the serial data bus and indirectly, for
interrupt purposes, through the control registers.

2.2 CPU REGISTERS

TheST6FamilyCPUcorefeaturessixregisters and
three pairs of flags available to the programmer.
These are described in the following paragraphs.

Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic cal­culations, logical operations, and data manipula­tions. The accumulator can be addressed in Data
space as a RAM location at address FFh. Thus the
ST6 can manipulate the accumulator just like any
other register in Data space.

Figure 6. ST6 Core Block Diagram

Indirect Registers (X, Y). These two indirect reg-

isters are used as pointers to memory locations in
Data space. They are used in the register-indirect
addressing mode. These registers can be ad­dressed in the dataspace as RAM locations at ad­dresses 80h (X) and 81h (Y). They can also beac­cessed with the direct, short direct, or bit direct ad­dressing modes. Accordingly, the ST6 instruction
set can usethe indirect registers as any other reg­ister of the data space.

Short Direct Registers (V, W). These two regis­ters are used to save a byte in short direct ad­dressing mode. They can be addressed in Data
space as RAM locations at addresses 82h (V)and
83h (W). They can also be accessed using the di­rect and bit direct addressing modes. Thus, the
ST6 instruction set can use the short direct regis­ters as any other register of the data space.

Program Counter (PC). The program counter is a
12-bit register which contains the address of the
next ROM location to be processed by the core.
This ROM location may be an opcode, an oper­and, or the address of an operand. The 12-bit
length allows the direct addressing of 4096 bytes
in Program space.

PROGRAM

ROM/EPROM

12

RESET

CONTROLLER

OPCODE

Program Counter

and

6 LAYER STACK

FLAG

VALUES

0,01 TO 8MHz

OSCin

CONTROL

SIGNALS

2

A-DATA

FLAGS

OSCout

ADDRESS/READ LINE

ADDRESS

DECODER

B-DATA

ALU

RESULTS TO DATA SPACE (WRITE LINE)

INTERRUPTS

256

DATA SPACE

DATA

RAM/EEPROM

DATA

ROM/EPROM

DEDICATIONS

ACCUMULATOR

VR01811

16/68

16

CPU REGISTERS (Cont’d)
However, ifthe program space contains more than

4096 bytes, the additional memory in program
space can be addressed by using the Program
Bank Switch register.

The PC value is incremented after reading the ad­dress of the current instruction. Toexecute relative
jumps, the PC and the offset are shifted through
the ALU, where they are added; the result is then
shifted backinto the PC.The programcounter can
be changedin the following ways:

- JP (Jump) instructionPC=Jump address

- CALL instructionPC= Call address

- Relative Branch Instruction.PC= PC +/- offset

- Interrupt PC=Interrupt vector

- Reset PC= Reset vector

- RET & RETI instructionsPC= Pop (stack)

- Normal instructionPC=PC + 1

Flags (C, Z). The ST6 CPU includes three pairs of
flags (Carry and Zero), each pair being associated
with one of the three normal modes of operation:
Normal mode, Interrupt mode and Non Maskable
Interrupt mode. Each pair consists of a CARRY
flag and a ZERO flag. One pair (CN, ZN) is used
during Normal operation, another pair is used dur­ing Interrupt mode (CI, ZI), and a third pair is used
in the Non Maskable Interrupt mode (CNMI, ZN­MI).

The ST6 CPU uses the pair of flags associated
with the current mode: as soon as an interrupt (or
a Non Maskable Interrupt) is generated, the ST6
CPU uses the Interrupt flags (resp. the NMI flags)
instead of the Normal flags. When the RETI in­struction is executed, the previously used set of
flags is restored. It should be noted that each flag
set can only be addressed in its own context (Non
Maskable Interrupt, Normal Interrupt or Main rou­tine). The flags are not cleared during context
switching and thus retain their status.

The Carry flag is set when a carry or a borrow oc­curs during arithmetic operations; otherwise it is
cleared. The Carry flag is also set to the value of
the bit tested in a bit test instruction; it also partici­pates in the rotate left instruction.

The Zero flag is set if the result of the last arithme­tic or logical operation was equal to zero; other­wise it is cleared.

Switching between the three sets of flags is per­formed automatically when an NMI, an interrupt or
a RETI instructions occurs. As the NMI mode is

ST62T42B/E42B

automatically selected after the reset of the MCU,
the ST6 core uses at first the NMI flags.

Stack. The ST6 CPU includes a true LIFO hard­ware stack which eliminates the need for a stack
pointer. The stack consists of six separate 12-bit
RAM locations that do not belong to the data
space RAM area. When a subroutine call (or inter­rupt request) occurs, the contents of each level are
shifted intothe next higher level, while the content
of the PC is shifted into the first level (the original
contents of the sixth stack level are lost). When a
subroutine or interruptreturn occurs (RET or RETI
instructions), the first level register is shifted back
into the PC and the value of each level is popped
back into the previous level. Since the accumula­tor, in common with all other data space registers,
is not stored in this stack, management of these
registers should be performed within the subrou­tine. The stack will remain in its “deepest” position
if morethan 6 nested calls orinterrupts are execut­ed, and consequently the last return address will
be lost. It will also remain in its highest position if
the stack is emptyand aRET or RETI is executed.
In this case the next instruction will be executed.

Figure 7. ST6 CPU Programming Mode

l

INDEX

REGISTER

INTERRUPTFLAGS

NMI FLAGS

b7
b7

b7
b7

b7

PROGRAMCOUNTER

SIX LEVELS

STACKREGISTER

X REG. POINTER

Y REG. POINTER

VREGISTER

W REGISTER

ACCUM ULATOR

b0
b0

b0
b0

b0

b0b11

CZNORMAL FLAGS

CZ

CZ

SHORT

DIRECT

ADDRESSING

MODE

VA000 4 23

17/68

17

ST62T42B/E42B

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES

3.1 CLOCK SYSTEM

3.1.1 Main Oscillator

The MCU featuresa Main Oscillator which can be
driven by an external clock, or used in conjunction
with an AT-cut parallel resonant crystal or a suita­ble ceramic resonator.

Figure 8 illustrates various possible oscillator con­figurations using anexternal crystal or ceramic res­onator, an external clock input. CL1an CL2should
have acapacitance in the range 12 to 22 pF for an
oscillator frequency in the 4-8 MHz range.

The internal MCU clock Frequency (F

) is divid-

INT

ed by 13 to drive the CPU core and by 12 to drive
the A/D converter and the watchdog timer, while
clock used to drive on-chip peripherals depends
on the peripheral as shown in the clock circuit
block diagram.

With an 8MHz oscillator frequency, the fastest ma­chine cycle is therefore 1.625µs.

A machine cycle is the smallest unit of time needed
to executeany operation (for instance, toincrement
the Program Counter). An instruction may require
two, four, or five machine cycles for execution.

Figure 8. Oscillator Configurations

CRYSTAL/RESONATOR CLOCK

ST6xxx

OSC

C

L1n

EXTERNAL CLOCK

OSC

in

ST6xxx

in

OSC

OSC

NC

out

out

C

L2

VA0016

VA0015A

Figure 9. Clock Circuit Block Diagram

f

OSC

OSCin

MAIN

OSCILLATOR

OSCout

f

INT

POR

:13

f

INT

:12

Core

Timer 1 & 2

Watchdog

ADC

LCD
CONTROLLER
DRIVER

18/68

18

3.2 RESETS

ST62T42B/E42B

The MCU can be reset in three ways:
– by the external Reset input being pulled low;
– by Power-on Reset;
– by the digital Watchdog peripheral timing out.

3.2.1 RESET Input

The RESET pin may be connected to a device of
the application board in order to reset the MCU if
required. The RESET pin may be pulled low in
RUN, WAIT or STOP mode. This input can be
used to reset the MCU internal state and ensure a
correct start-up procedure. The pin is active low
and features a Schmitt trigger input. The internal
Reset signal is generated by adding a delay to the
external signal. Therefore even short pulses on
the RESET pin are acceptable, provided VDDhas
completed its risingphase andthat the oscillator is
running correctly (normal RUN or WAIT modes).
The MCU is kept in the Reset state as long as the
RESET pin is held low.

If RESET activation occurs in the RUN or WAIT
modes, processing of the user program is stopped
(RUN modeonly), the Inputs and Outputs are con­figured as inputs with pull-up resistors and the
main Oscillator is restarted. When the level on the
RESET pin then goes high, the initialization se­quence is executed following expiry of the internal
delay period.

If RESET pin activation occurs in the STOP mode,
the oscillator starts up and all Inputs and Outputs
are configured as inputs with pull-up resistors.
When the level of the RESET pin then goes high,
the initialization sequence is executed following
expiry of the internal delay period.

3.2.2 Power-on Reset

The function of the POR circuit consists in waking
up the MCU at an appropriate stage during the
power-on sequence. At the beginning of this se­quence, the MCU is configured in the Reset state:
all I/O ports are configured as inputs with pull-up
resistors and no instruction is executed. When the
power supplyvoltage rises to a sufficient level, the
oscillator starts to operate, whereupon an internal
delay is initiated, in order to allow the oscillator to
fully stabilize before executing the first instruction.
The initialization sequence isexecuted immediate­ly following the internal delay.

The internaldelay isgenerated byan on-chipcoun­ter. Theinternal reset lineis released 2048 internal
clock cycles after release of the external reset.

Notes:

To ensure correct start-up, the user should take
care that the reset signal is not released before the
VDDlevel is sufficient to allow MCU operation at
the chosen frequency (see Recommended Oper­ating Conditions).

A proper reset signal for a slow rising VDDsupply
can generally be provided by an external RC net­work connected to the RESET pin.

Figure 10. Reset and Interrupt Processing

RESET

NMI MASK SET

INT LATCH CLEARED

( IF PRESENT )

SELECT

NMI MODE FLAGS

PUT FFEH

ON ADDRESS BUS

YES

IS RESET STILL

PRESENT?

NO

LOAD PC

FROM RESET LOCATIONS

FFE/FFF

FETCH INSTRUCTION

VA000427

19/68

19

ST62T42B/E42B

RESETS (Cont’d)

3.2.3 Watchdog Reset

The MCU provides a Watchdog timer function in
order to ensure graceful recovery from software
upsets. If the Watchdog register is not refreshed
before an end-of-count condition is reached, the
internal reset will be activated. This, amongst oth­er things, resets the watchdog counter.

The MCU restarts just as though the Reset had
been generated by the RESET pin, including the
built-in stabilisation delay period.

3.2.4 Application Notes

No external resistor is required between VDDand
the Reset pin, thanks to the built-in pull-up device.

The POR circuit operates dynamically, in that it
triggers MCU initialization on detecting the rising
edge of VDD. The typical threshold is in the region
of 2 volts, but the actual value of the detected
threshold depends on the way in which VDDrises.

The POR circuit is
static, or slowly rising or falling VDD.

3.2.5 MCU Initialization Sequence

When a reset occurs the stack is reset, the PC is
loaded with the address of the Reset Vector (locat­ed in program ROM starting at address 0FFEh). A
jump tothe beginning of theuser program must be
coded at this address. Following a Reset, the In­terrupt flag is automatically set, so that the CPU is
in Non Maskable Interrupt mode; this prevents the

NOT

designed to supervise

initialisation routine from being interrupted. The in­itialisation routine should therefore be terminated
by a RETI instruction, in order to revert to normal
mode and enable interrupts. Ifno pending interrupt
is presentat theend of the initialisation routine, the
MCU will continue by processing the instruction
immediately following the RETI instruction. If, how­ever, a pending interrupt is present, it will be serv­iced.

Figure 11. Reset and Interrupt Processing

RESET

RESET

VECTOR

INITIALIZATION

ROUTINE

JP

RETI

JP:2 BYTES/4 CYCLES

RETI: 1 BYTE/2 CYCLES

VA00181

Figure 12. Reset Block Diagram

V

DD

300kΩ

RESET

2.8kΩ

POWER

WATCHDOG RESET

20/68

ON RESET

20

f

OSC

RESET

CK

COUNTER

RESET

ST6
INTERNAL
RESET

VA0200B

RESETS (Cont’d)
Table 8. Register Reset Status

Register Address(es) Status Comment

EEPROM Control Register
Port Data Registers
Port A,B Direction Register
Port A,B Option Register
Interrupt Option Register

0DFh
0C0h, 0C2h, 0C3h
0C4h to 0C5h
0CCh, 0CEh
0C8h

00h

ST62T42B/E42B

EEPROM enabled

I/O are Input with pull-up

Interrupt disabled

SPI Registers
LCD Mode Control Register
32kHz Oscillator Register

Port C Direction Register
Port C Option Register

X, Y,V, W, Register
Accumulator
Data RAM
Data RAM Page REgister
Data ROM Window Register
EEPROM
A/D Result Register

TIMER 1 Status/Control
TIMER 1 Counter Register
TIMER 1 Prescaler Register

TIMER 2 Status/Control
TIMER 2 Counter Register
TIMER 2 Prescaler Register

Watchdog Counter Register
A/D Control Register

0C2h to 0DDh
0DCh
0DBh

0C6h
0CFh

080H TO083H
0FFh
084h to 0BFh
0CBh
0C9h
00h to 03Fh
0D0h

0D4h
0D3h
0D2h

0D7h
0D5h
0D6h

0D8h
0D1h

SPI disabled
LCD display off
Interrupt disabled

FFh LCD Output

Undefined As written if programmed

00h
FFh
7Fh

00h
FFh
7Fh

FEh

40h

TIMER 1disabled/Max count loaded

TIMER 2disabled/Max count loaded

A/D in Standby

21/68

21