POLAROID LS21W, TLA-01901C Schematic
TLA-01901C Service Manual
1
Content
Chapter 1 - Specifications and Composition………………………………2
Chapter 2 - Brief introduction of the main
integrated circuit function……………………………………5
Chapter 3 - Analysis of the Signal process
Flowchart and Key Point Measure Data
Chapter 4 - Spare part list …………………………………………………38
Chapter 5 - The factory mode setting
and noticeable proceeding ……………………………………39
Chapter 6 - The flow of software update
and noticeable proceedin g……………………………………41
Annex ： 1、 TLA-01901C Circuit diagram
2、 TLA-01901C exploded mechanical diagram
*Annex parts hasn’t been attached in this file. They will be provided
in separated files.
*The chassises of this LCD TV are called LS16 or L16W in this file.
LS16 and LS16W use the same TV resolution. The difference is the
connectors arrangement between these two chasises.
………………………25
2
Chapter 1 - Specifications and Composition
1、Models of the chassis
LS16：TBD
LS16W： TLA-01901C
2、Main Feature
RF Input ， including CATV Function(capable of compatible receiving
NTSC/ATSC/CLEAR-QAM ).
Capable of receiving the program of ATSC/NTSC within 54MHZ – 803MHz.
● AV Input
● HDMI Digital Signal Input
● VGA Input
● YPbPr Input
● Headphone Output
● SPDIF Digital Audio Output (Optional)
● 191 sets of programs presetting
In ATV mode, the TV can save 191 sets of program which fully prepared for the
richness programs in the future .
● Timer Function
Automatically on/off in certain preset time.
● Blue Background with Noise Silence (Optional)
The soft blue background will be displayed if there is no signal input in TV、
AV modes
● Automatic off if no signal input
LCD TV will go to the standby mode 15 or 5 minutes after there is no signal
input in TV mode.
● English / French/Spanish OSD menu
Simple graphic OSD menu makes the operation more convenient and more direct
viewing
● Power Energy Saving Function(power management mode)(only for LS16)
In PC mode, the LCD TV will automatically power off within 30 seconds and
enter into the Power Energy Saving Mode if there is no VGA signal input. It will
automatically exit from the Power Energy Saving Mode and work again when it
received a valid VGA signal or press any button on the panel/remote control.
● Plug and Play
It is no need to equip any installation software when the product is used as
computer terminal display equipment.
(In order to obtain a good image quality, perhaps,some minor adjustment should
be done with the PC display setting or TV pc set up. )
● Legerity , Convenience and Low power consumption
3、Unit circuit modules：
LS16 and LS16W chassis LCD TV is mainly composed of regulator IC,RF IC, video
processor IC ,power amplify IC, analog video IC, system control IC and key control
3
IC. See the IC frame as below:
r
[
]
[
]
Power Board
+5V
+5V
+12V
+12V
Main Board
+5V
+12V
Speake
TDA1517
TL062
MSD116
TS
0…7
LCD Panel
AUDIO
K Panel
IR Panel
L V D S
S-FLASH
HD
0…7
CVBS
SIF
TUNER
4、PCB assembly introduction：
LS16 and LS16W LCD TV is mainly composed of AV Board , Remote Receiver Board,
Local Key Board and Main Board. The under sheet is the function introduction of every
MSD809
IF-D
AV
MST3383
HDMI PCYPbPr
4
PCD Assembly:
NO. Parts Function Description
1
Main Board
module
3
4
5
6
Remote
Control
Receiver
Assembly
Built-in
Power Board
Assembly
Key Board
Assembly
Panel
Assembly
Main Board module is the core of LCD TV signal processing.
Under the control of the System Control Circuit, It undertakes the
task of converting the external input signal into the unified digital
signal that the LCD screen could identify 。 After RF signal
processed by tuner, It was sent to the main chip (analog signal was
sent to MSD116 for processing ,and digital signal was sent to
MSD809 for decoding first and then to MSD116 for processing ),
then the main chip(MSD116 ) produce LVDS signal displayed on
the screen .In addition, signals input from VGA、AV、SVIDEO and
YPbPr would directly enter into MSD116 for processing, format
transformation and on screen display. HDMI signal was sent to
MST3383 for processing first and then transmitted to MSD116 for
processing, format transformation and on screen display. And there
is a headphone output interface near the tuner. For LS16 only, it
has a digital audio output interface(SPDIF).
It is composite of one light indicator and one remote control
receiver, which enable users operate the TV conveniently and
know its current working status simply with a remote control.
It can transform AC power into DC for ICs including+12V，+5V and
ADJ for switching the backlight of LCD on or off and adjusting the
brightness.
It consists of 7 function buttons by which users can operate the TV
freely.
The LCD screen is used to display the image after the image signal
has been processed by the main board.
5
Chapter 2 - Brief introduction of the main integrated circuit
function
1、LS16 and LS16W Chassis Main ICs and function：
Main Board
Number Position Part Number Main function
1 U12,U6 24LC02 EEPROM
2 U23 24LC512 EEPROM
3 U7 MSD809 Demodulator
4 U9 MST3383AMCK-LF-170 HDMI Decoder
5 U8 DTVS205CH201A Tuner
6 U22 MSD116L Video and audio processor.
7 U24 M25P16-VMN6P/
S25FL016A0LMFI013
8 U28,U29,U30 IS42S16400D-6TL/
W9864G6GH-6/
K4S641632K-UC60
9 U31 TDA1517P Audio amplifier
10 U32 TL062CD Integration amplifier
Flash for code storage
SDRAM
2、LS16 and LS16W Chassis IC function.
2.1 TUNER(DTVS205CH201A)
GENERAL DESCRIPTION:
Receiving System: ATSC/NTSC system
Intermediate Frequency: Digital(center): 44MHz
Analog(P-carrier):45.75MHz
Input Impedance: 75Ω,Unbalanced
IF Output Impedance: 10Ω,Balanced
Band Change-Over System: PLL system
Tuning System: PLL system
Internal RF AGC function:
Built in wideband AGC detector with 6 programmable take-over points
Narrow band output to be filtering by a 5.6MHz SAW filter
Built in the additional IF amplifier with AGC circuit
Reference Frequency The X-tal the RF block’s PLL:4MHz
Control Data Bus: I²C (BUS VOLT AGE:3.3V)
Control Data Format: Refer to 6 Section
DTVS205CH201A BLOCK DIAGRAM：
6
PIN FUNCTION DESCRIPTION：
PIN PIN NAME DESCRIPTION
1 NC not connected
2 NC not connected
3 NC not connected
4 NC not connected
5 NC not connected
6 NC not connected
7 RF AGC TP
8 NC not connected
9 VT 30V
10 IF OUT (+) digital IF
11 IF OUT (-) digital IF
12 IF AGC
13 TP(IF)
14 CLOCK
15 DATA
16 GND
17 5V
18 NC
19 AFT analog demod
20 SIF analog demod
21 CVBS analog demod
EXTERNAL
7
2.2 MSD116L
GENERAL DESCRIPTION:
The MSD116L is a highly integrated SOC for LCD/PDP DTV applications with
resolutions up to SXGA/WXGA+.It is configured with an integrated triple-ADC/PLL,
a multi-standard TV video and audio decoder, a DTV video and audio decoder, a
video de-interlacer, a scaling engine, the MStarACE-3 color engine, a graphics engine,
an 8-bit MCU and a built-in output panel interface. The built-in DTV decoder
including transport stream de-multiplexer and MPEG-2 AV decoder are designed to
support ATSC HD/SDTV program while handling ATSC CC and EPG. For analog TV,
the MSD116L receives NTSC/PAL/SECAM CVBS/S-Video and component video
signals from various analog graphic & video sources. To further reduce system costs,
the MSD116L also integrates intelligent power management control capability for
green-mode requirements and spread-spectrum support for EMI management.
FEATURES
●Twin-turbo 8051 Micro-controller
●Transport Stream De-multiplexer
●MPEG-2 A/V Decoder
●NTSC/PAL/SECAM Video Decoder
●
Multi-Standard TV Sound Processor
●Digital Audio Interface
I2S digital audio input & output
S/PDIF digital audio input & output
●Analog RGB Compliant Input Ports
●Auto-Configuration/Auto-Detection
Two analog ports support up to 135MHz
Supports PC RGB input up to SXGA@75Hz
Supports HDTV RGB/YPbPr/YCbCr
Supports Composite Sync and SOG (Sync-on-Green) separator
Automatic color calibration
●High-Performance Scaling Engine
●
Video Processing & Conversion
●
Output Interface
Supports up to 8-bit dual LVDS SXGA/WXGA+ panel interface
Supports 2 data output formats: Thine & TI data mappings
Compatible with TIA/EIA
With 6/8 bits options
Spread spectrum output frequency for EMI suppression
Supports flexible spread spectrum frequency
●2D Graphics Engine
●Digital PWM Controller
●Miscellaneous
8
SDRAM controller to support up to 48-bit data bus
Supports serial flash with up to 2M address
Two I2C interfaces in master/slave mode
One IR receiver input with power-down wakeup
256-LQFP package
Operating at 1.8V (core) and 3.3V (I/O and analog)
PIN FUNCTION DESCRIPTION：
Analog Interface
Pin Name Pin Type Function Pin
VCLAMP CVBS/YC Mode Clamp Voltage Bypass 20
REFM Internal ADC Bottom De-coupling Pin 18
REFP Internal ADC Top De-coupling Pin 19
SOGIN1 Analog Input Sync-on-Green slicer input from
channel 1
BINP Analog Input Analog B Input of VGA 1
GINP Analog Input Analog G Input of VGA 3
RINP Analog Input Analog R Input of VGA 4
PBINP Analog Input Analog Pb Input 11
VCOMB Analog Input Common Negative Input for
12
B-component ADC
SOGIN0 Analog Input Sync-on-Green slicer input from
13
channel 0
VCOMG Analog Input Common Negative Input for
15
G-component ADC
YINP Analog Input Analog Y Input 14
VCOMR Analog Input Common Negative Input for
17
R-component ADC
PRINP Analog Input Analog Pr Input 16
C0INP Analog Input Analog Chroma Input for TV S-Video0 23
YS0INP Analog Input Analog Luma Input of TV S-Video0 24
C1INP Analog Input Analog Chroma Input for TV S-Video1
25
/ Analog Composite Input of TV CVBS4
YS1INP Analog Input Analog Luma Input of TV S-Video0 /
26
Analog Composite Input of TV CVBS3
VCOMY Analog Input Common Negative Input for
27
Y-component ADC
CVBSOUT Analog
CVBS Output buffered from CVBS input 32
Output
CVBS0 Analog Input Analog Composite Input for TV CVBS0 31
CVBS1 Analog Input Analog Composite Input for TV CVBS1 30
CVBS2 Analog Input Analog Composite Input for TV CVBS2 29
CVBS3 Analog Input Analog Composite Input for TV CVBS3 28
DREXT Analog Input Reference Current Generator, 820 170
2
9
ohm to Ground
HSYNC0 Schmitt
Trigger
HSYNC / Composite Sync for VGA Input
from channel 0
Input w/
5V-tolerant
VSYNC0 Schmitt
VSYNC for VGA Input from channel 1 10
Trigger
Input w/
5V-tolerant
HSYNC1 Schmitt
Trigger
HSYNC / Composite Sync for VGA Input
from channel 1
Input w/
5V-tolerant
VSYNC1
Schmitt Trigger
Input
w/ 5V-tolerant
VSYNC for VGA Input from channel 1
Digital Panel Output Interface
LVA0M Output
LVA0P Output
LVA1M Output
LVA1P Output
LVA2M Output
LVA2P Output
LVDS A-Link Channel 0 Negative Data
Output
LVDS A-Link Channel 0 Positive Data
Output
LVDS A-Link Channel 1 Negative Data
Output
LVDS A-Link Channel 1 Positive Data
Output
LVDS A-Link Channel 2 Negative Data
Output
LVDS A-Link Channel 2 Positive Data
Output
186
185
184
183
182
181
LVACKM Output LVDS A-Link Negative Clock Output 180
LVACKP Output LVDS A-Link Positive Clock Output 179
LVA3M Output
LVA3P Output
LVB0M Output
LVB0P Output
LVB1M Output
LVB1P Output
LVDS A-Link Channel 3 Negative Data
Output
LVDS A-Link Channel 3 Positive Data
Output
LVDS B-Link Channel 0 Negative Data
Output
LVDS B-Link Channel 0 Positive Data
Output
LVDS B-Link Channel 1 Negative Data
Output
LVDS B-Link Channel 1 Positive Data
Output
178
177
199
198
197
196
9
8
7
10
LVB2M Output
LVB2P Output
LVDS B-Link Channel 2 Negative Data
Output
LVDS B-Link Channel 2 Positive Data
Output
195
194
LVBCKM Output LVDS B-Link Negative Clock Output 190
LVBCKP Output LVDS B-Link Positive Clock Output 189
LVB3M Output
LVB3P Output
LVDS B-Link Channel 3 Negative Data
Output
LVDS B-Link Channel 3 Positive Data
Output
188
187
Internal MCU Interface with Serial Flash Memory
SAR3 Analog Input SAR Low Speed ADC Input 3 204
SAR2 Analog Input SAR Low Speed ADC Input 2 203
SAR1 Analog Input SAR Low Speed ADC Input 1 202
SAR0 Analog Input SAR Low Speed ADC Input 0 201
SCK Output SPI Interface Sampling Clock 171
SDI Output SPI Interface Data-In 172
SDO
Input w/
5V-tolerant
SPI Interface Data-Out 173
CSZ Output SPI Interface Chip Select 174
GPIO_P10-GPI
O_P17
UART_TX
UART_RX
I/O w/
5V-tolerant
I/O w/
5V-tolerant
I/O w/
5V-tolerant
General Purpose Input/Output; 4mA
driving strength
41-4
8
Universal Asynchronous Transmitter 55
Universal Asynchronous Receiver 56
Input
IRIN
w/5V-toleran
IR Receiver Input 57
t
INT Input
MCU Bus Interrupt; 4mA driving
strength
58
SCLM Output I2C Master Clock 59
SDAM
I/O w/
5V-tolerant
I2C Master Data 60
DDC_SCL I/O DDC Clock for D-SUB Input 33
DDC_SDA I/O DDC Data for D-SUB Input 34
DDC_ROMSCL I/O DDC ROM Clock for D-SUB Input 35
DDC_ROMSDA I/O DDC ROM Data for D-SUB Input 36
SDRAM Interface
SDR_CSZ Output SDRAM Chip Select; active low 134
SDR_CKE Output SDRAM Clock Enable 126
SDR_AD[11:0] Output SDRAM Address Bus
148137
11
SDR_BA[1:0] Output SDRAM Bank Select
129,
130
168161,
157-
SDR_DQ[31:0] I/O SDRAM Data Bus
150,
124117,
114107
SDR_RASZ Output SDRAM Row Address Strobe; active low 131
SDR_CASZ Output
SDRAM Column Address Strobe; active
low
132
SDR_WEZ Output SDRAM Write Enable 133
169,
SDR_DQM[3:0] Output
SDRAM Data Mask for Low Byte; active
high
149,
125,
106
SDR_MCLKO Output Master Clock Output to SDRAM 128
SDR1_CKE Output SDRAM1 Clock Enable 225
SDR1_AD[11:0
]
Output SDRAM1 Address Bus
SDR1_BA[1:0] Output SDRAM1 Bank Select
224-
213
233,
232
251-
245,
SDR1_DQ[15:0
]
I/O SDRAM1 Data Bus
243,
242,
240-
234
SDR1_RASZ Output
SDR1_CASZ Output
SDRAM1 Row Address Strobe; active
low
SDRAM1 Column Address Strobe;
active low
231
230
SDR1_WEZ Output SDRAM1 Write Enable 227
SDR1_DQM[1:0
]
Output
SDRAM1 Data Mask for Low Byte;
active high
229,
228
SDR1_MCLKO Output Master Clock Output to SDRAM1 226
TS Input Interface
TSCLK Input TS Clock 95
TSDATA[7:0] Input
TS Data in Parallel; LSB (bit 0) is
for serial TS data
96-1
03
TSVALID Input TS Data Valid 104
TSSYNC Input TS Sync-Byte Indicator 105
12
Audio Input/Output Interface
SIF0M Analog Input
Reference Ground for SIF Audio Input
Channel 0
50
SIF0P Analog Input SIF Audio Input Channel 0 51
SIF1P Analog Input SIF Audio Input Channel 1 53
SIF1M Analog Input
Reference Ground for SIF Audio Input
Channel 1
54
I2S_OUT_MCK Output Audio Master Clock Output 85
I2S_OUT_BCK Output Audio Bit Clock Output 86
I2S_OUT_WS Output
I2S_OUT_SD Output
SPDIFO Output
Word Select Output; 4mA driving
strength
Audio Serial Data Output; 4mA
driving strength
S/PDIF Audio Output; 4mA driving
strength
87
88
90
I2S_OUT_MUTE Output Audio Output Mute Control 89
I2S_IN_BCK Input Audio Bit Clock Input 81
I2S_IN_WS Input Word Select Input 82
I2S_IN_SD Input Audio Serial Data Input 83
SPDIFI Input S/PDIF Audio Input 84
AUVRM
AUVRP
AUVAG
Analog
Output
Analog
Output
Analog
Output
Negative Reference Voltage for
Audio ADC
Positive Reference Voltage for
Audio ADC
Reference Voltage for Audio Common
Mode
64
65
66
AUL0 Analog Input Audio Line Input Left Channel 0 68
AUR0 Analog Input Audio Line Input Right Channel 0 69
AUL1 Analog Input Audio Line Input Left Channel 1 70
AUR1 Analog Input Audio Line Input Right Channel 1 71
AUCOM Analog Input
Reference Ground for Audio Line
Input
72
AUL2 Analog Input Audio Line Input Left Channel 2 73
AUR2 Analog Input Audio Line Input Right Channel 2 74
AUL3 Analog Input Audio Line Input Left Channel 3 75
AUR3 Analog Input Audio Line Input Right Channel 3 76
AUOUTL1
AUOUTR1
AUOUTL0
Analog
Output
Analog
Output
Analog
Output
Main Audio Output Left Channel 0 77
Main Audio Output Right Channel 0 78
Main Audio Output Left Channel 0 79
AUOUTR0 Analog Main Audio Output Right Channel 0 80
13
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