PMD MC3510 Datasheet

Pilot™ Motion Processor
MC3510 Single Chip
Technical Specifications
Performance Motion Devices, Inc.
55 Old Bedford Road
Lincoln, MA 01773
Revision 1.1, July 2003
NOTICE
This document contains proprietary and confidential information of Performance Motion Devices, Inc., and is protected by federal copyright law. The contents of this document may not be disclosed to third parties, translated, copied, or duplicated in any form, in whole or in part, without the express written permission of PMD.
The information contained in this document is subject to change without notice. No part of this document may be reproduced or transmitted in any form, by any means, electronic or mechanical, for any purpose, without the express written permission of PMD.
Copyright 2000 by Performance Motion Devices, Inc. Navigator, Pilot and C-Motion are trademarks of Performance Motion Devices, Inc
Warranty
PMD warrants performance of its products to the specifications applicable at the time of sale in accordance with PMD's standard warranty. Testing and other quality control techniques are utilized to the extent PMD deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
Performance Motion Devices, Inc. (PMD) reserves the right to make changes to its products or to discontinue any product or service without notice, and advises customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
Safety Notice
Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage. Products are not designed, authorized, or warranted to be suitable for use in life support devices or systems or other critical applications. Inclusion of PMD products in such applications is understood to be fully at the customer's risk.
In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent procedural hazards.
Disclaimer
PMD assumes no liability for applications assistance or customer product design. PMD does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of PMD covering or relating to any combination, machine, or process in which such products or services might be or are used. PMD's publication of information regarding any third party's products or services does not constitute PMD's approval, warranty or endorsement thereof.
MC3510 Technical Specifications
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MC3510 Technical Specifications
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Related Documents
Pilot Motion Processor User’s Guide (MC3000UG)
How to set up and use all members of the Pilot Motion Processor family.
Pilot Motion Processor Programmer’s Reference (MC3000PR)
Descriptions of all Pilot Motion Processor commands, with coding syntax and examples, listed alphabetically for quick reference.
Pilot Motion Processor Technical Specifications
These booklets contain physical and electrical characteristics, timing diagrams, pinouts and pin descriptions of each:
MC3110, for brushed servo motion control (MC3110TS)
MC3310, for brushless servo motion control (MC3310TS)
MC3410, for microstepping motion control (MC3410TS)
MC3510, for stepper motion control (MC3510TS)
Pilot Motion Processor Developer’s Kit Manual (DK3000M)
How to install and configure the DK3510 developer’s kit PC board.
MC3510 Technical Specifications
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MC3510 Technical Specifications
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Table of Contents
Warranty...................................................................................................................................................... iii
Safety Notice ................................................................................................................................................iii
Disclaimer.....................................................................................................................................................iii
Related Documents....................................................................................................................................... v
Table of Contents........................................................................................................................................ vii
1 The Pilot Family ........................................................................................................................................ 9
2 Functional Characteristics...................................................................................................................... 11
2.1 Configurations, parameters, and performance.............................................................................. 11
2.2 Physical characteristics and mounting dimensions....................................................................... 13
2.3 Environmental and electrical ratings............................................................................................14
2.4 System configuration.................................................................................................................... 14
2.5 Peripheral device address mapping...............................................................................................15
3 Electrical Characteristics........................................................................................................................ 16
3.1 DC characteristics......................................................................................................................... 16
3.2 AC characteristics......................................................................................................................... 16
4 I/O Timing Diagrams..............................................................................................................................18
4.1 Clock ............................................................................................................................................ 18
4.2 Quadrature encoder input............................................................................................................. 18
4.3 Reset............................................................................................................................................. 18
4.4 Host interface, 8/16 mode (requires external logic device).......................................................... 19
4.4.1 Instruction write, 8/16 mode................................................................................................. 19
4.4.2 Data write, 8/16 mode...........................................................................................................19
4.4.3 Data read, 8/16 mode............................................................................................................20
4.4.4 Status read, 8/16 mode..........................................................................................................20
4.5 Host interface, 16/16 mode (requires external logic device) ........................................................ 21
4.5.1 Instruction write, 16/16 mode............................................................................................... 21
4.5.2 Data write, 16/16 mode......................................................................................................... 21
4.5.3 Data read, 16/16 mode.......................................................................................................... 22
4.5.4 Status read, 16/16 mode........................................................................................................ 22
4.6 External memory timing............................................................................................................... 23
4.6.1 External memory read........................................................................................................... 23
4.6.2 External memory write......................................................................................................... 23
4.7 Peripheral device timing............................................................................................................... 24
4.7.1 Peripheral device read........................................................................................................... 24
4.7.2 Peripheral device write.........................................................................................................24
5 Pinouts and Pin Descriptions.................................................................................................................. 25
5.1 Pinouts for MC3510..................................................................................................................... 25
5.2 CP chip pin description table........................................................................................................ 26
6 Parallel Communication......................................................................................................................... 29
6.1 Host interface pin description table.............................................................................................. 29
6.2 16-bit Host Interface (IOPIL16)................................................................................................... 31
MC3510 Technical Specifications
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8-bit Host Interface (IOPIL8)....................................................................................................... 45
6.3
7 Application Notes..................................................................................................................................... 60
7.1 Design Tips................................................................................................................................... 60
7.2 RS-232 Serial Interface ................................................................................................................ 62
7.3 RS 422/485 Serial Interface.......................................................................................................... 64
7.4 RAM Interface.............................................................................................................................. 66
7.5 User-defined I/O........................................................................................................................... 68
7.6 12-bit A/D Interface...................................................................................................................... 70
7.7 16-bit A/D Input........................................................................................................................... 72
7.8 External Gating Logic Index ........................................................................................................ 74
MC3510 Technical Specifications
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1 The Pilot Family
Number of axes Motor type supported
Output format
Incremental encoder input
MC3110 MC3310 MC3410 MC3510
1 1 1 1
Brushed servo Brushed servo
(single phase)
Brushless servo Stepping Stepping
Commutated (6-
step or sinusoidal)
Parallel word device input
Parallel communication Serial communication S-curve profiling On-the-fly changes
1
1 1 1 √ √ √ √
Directional limit switches
Programmable bit output Software-invertable
signals PID servo control
√ √
Feedforward (accel & vel)
Derivative sampling time Data trace/diagnostics PWM output Pulse & direction output Index & Home signals Motion error detection Axis settled indicator DAC-compatible output Position capture Analog input User-defined I/O External RAM support
√ √ √ √ √ √ -
- - - √ √ √ √ √ √ √ √ ­√ √ √ √ √ √ √
Multi-chip synchronization
Chip part numbers Developer's Kit p/n's:
1
Parallel communication is available via an additional logic device
(MC3113) (MC3313) (MC3413)
MC3110 MC3310 MC3410 MC3510
DK3110 DK3310 DK3410 DK3510
Microstepping Pulse and Direction
- -
- -
- -
(with encoder) (with encoder)
(with encoder) (with encoder)
-
Introduction
This manual describes the operational characteristics of the MC3510 Motion Processor from PMD. This device is a member of the MC3000 family of single-chip, single-axis motion processors.
MC3510 Technical Specifications
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Each device of the MC3000 family is a complete chip-based motion processor providing trajectory generation and related motion control functions for one axis including pulse and direction output or servo loop closure or on-board commutation where appropriate. This family of products provides a software-compatible selection of dedicated motion processors that can handle a large variety of system configurations.
The chip architecture not only makes it ideal for the task of motion control, it allows for similarities in software commands, so software written for one motor type can be re-used if the motor type is changed.
Pilot Family Summary
MC3110 – This single-chip, single-axis motion processor outputs motor commands in either Sign/Magnitude PWM or DAC-compatible format for use with brushed servo motors, or with brushless servo motors having external commutation.
MC3310 – This single-chip, single-axis motion processor outputs sinusoidally commutated motor signals appropriate for driving brushless motors. Depending on the motor type, the output is a two­phase or three-phase signal in either PWM or DAC-compatible format.
MC3410 – This single-chip, single-axis motion processor outputs microstepping signals for stepping motors. Two phased signals per axis are generated in either PWM or DAC-compatible format.
MC3510 – This single-chip, single-axis motion processor outputs pulse and direction signals for stepping motor systems.
MC3510 Technical Specifications
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2 Functional Characteristics

2.1 Configurations, parameters, and performance

Configuration
Operating modes
Communication modes
Serial port baud rate range
Position range
Velocity range
Acceleration/ deceleration ranges
Jerk range
Profile modes
Position error tracking
Maximum pulse rate
Maximum encoder rate
Parallel encoder word size
Parallel encoder read rate
Cycle loop timing range
Minimum cycle loop time
Limit switches
Position-capture triggers
Other digital signals
Software-invertable signals
Analog input
User defined discrete I/O
RAM/external memory support
Single axis, single chip. Open loop (pulse generator is driven by trajectory generator output)
Stall detection (pulse generator is driven by trajectory generator output and encoder feedback is used for stall detection)
8/16 parallel (8 bit external parallel bus with 16 bit internal command word size) 16/16 parallel (16 bit external parallel bus with 16 bit internal command word
size) Point to point asynchronous serial Multi-drop asynchronous serial 1,200 baud to 416,667 baud
-2,147,483,648 to +2,147,483,647 counts
-32,768 to +32,767 counts/sample with a resolution of 1/65,536 counts/sample
-32,768 to +32,767 counts/sample 0 to ½ counts/sample S-curve point-to-point (Velocity, acceleration, jerk, and position parameters) Trapezoidal point-to-point (Velocity, acceleration, deceleration, and position
parameters) Velocity-contouring (Velocity, acceleration, and deceleration parameters) Motion error window (allows axis to be stopped upon exceeding programmable
window) Tracking window (allows flag to be set if axis exceeds a programmable position
window) Axis settled (allows flag to be set if axis exceeds a programmable position
window for a programmable amount of time after trajectory motion is compete) 50,000 pulses/sec Incremental (up to 5 million counts/sec) Parallel-word (up to 160 million counts/sec) 16 bits 20 kHz (reads all axes every 50 µsec)
102.4 µsec to 32.767 milliseconds
102.4 µsec 2 per axis: one for each direction of travel 2 per axis: index and home signals 1xAxisIn, 1xAxisOut, 1xAtRest Index, Home, AxisIn, AxisOut, PositiveLimit, NegativeLimit (all individually
programmable) 8 10-bit analog inputs 256 16-bit wide user defined I/O 65,536 blocks of 32,768 16-bit words per block. Total accessible memory is
2,147,483,648 16 bit words
3
, with a resolution of 1/4,294,967,296 counts/sample3
2
with a resolution of 1/65,536 counts/sample2
MC3510 Technical Specifications
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Trace modes
Max. number of trace variables
Number of traceable variables
Number of host instructions
one-time continuous 4 20 112
MC3510 Technical Specifications
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2.2 Physical characteristics and mounting dimensions
All dimensions are in inches (with millimeters in brackets).
Dimension Minimum
(inches)
D 1.070 1.090 D1 0.934 0.966 D2 1.088 1.112 D3 0.800 nominal
Maximum (inches)
MC3510 Technical Specifications
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2.3 Environmental and electrical ratings
Storage Temperature (Ts)
Operating Temperature (T
Power Dissipation (P
Nominal Clock Frequency (F
Supply Voltage limits (V
a)
d)
clk)
cc)
Supply Voltage operating range (V
* An industrial version with an operating range of -40°C to 85°C is also available. Please contact PMD for more information.
2.4 System configuration
The following figure shows the principal control and data paths in an MC3510 system.
Host
Parallel port
System clock (40 MHz)
HostData0-15
Parallel Communication
HostRdy
~HostSlct
PLD/FPGA
~HostWrite
-55 °C to 150 °C
0 °C to 70 °C*
400 mW
20.0 MHz
-0.3V to +7.0V
HostCmd
4.75V to 5.25V
Pilot Motion Processor
M
2
H
0
z
c
l
o
c
k
Serial Port
CP
HostIntrpt
Home
Index
B
A
Encoder
cc)
~HostRead
16 bit data/address bus
External memory
User I/O
Parallel-word input
Serial port configuration
AxisIn
AxisOut
Positive
Limit
switches
Negative
AtRest
Pulse
Motor
Amplifier
Direction
The shaded area shows the CPLD/FPGA that must be provided by the designer if parallel communication is required. A description and the necessary logic (in the form of schematics) of this device are detailed in section 6 of this manual. The CP chip contains the profile generator, which calculates velocity, acceleration, and position values for a trajectory. The output of the trajectory generator is used to produce pulse and direction signals that control motor position.
MC3510 Technical Specifications
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Optional axis position information returns to the motion in the form of incremental encoder feedback or in the form of parallel-word feedback. This position feedback may be used to detect motor stalling errors.

2.5 Peripheral device address mapping

Device addresses on the CP chip’s data bus are memory-mapped to the following locations:
Address Device Description
0200h Serial port data Contains the configuration data (transmission rate,
0800h Parallel-word encoder Base address for parallel-word feedback devices
1000h User-defined Base address for user-defined I/O devices
2000h RAM page pointer Page pointer to external memory
4000h Motor-output DACs Base address for motor-output D/A converters
8000h Parallel interface Base address for parallel interface communication
parity, stop bits, etc) for the asynchronous serial port
MC3510 Technical Specifications
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3 Electrical Characteristics
3.1 DC characteristics
(Vcc and Ta per operating ratings, F
= 20.0 MHz)
clk
Symbol Parameter Minimum Maximum Conditions
Vcc Supply Voltage 4.75 V 5.25 V Idd Supply Current 80 mA open outputs
Input Voltages
Vih Logic 1 input voltage 2.0 V Vcc + 0.3 V Vil Logic 0 input voltage -0.3 V 0.8 V V
Logic 1 voltage for clock pin
ihclk
3.0 V Vcc + 0.3 V
(ClockIn)
V
Logic 0 voltage for clock pin
oclk
-0.3 V 0.7 V
(ClockIn)
V
Logic 1 voltage for reset pin (reset) 2.2 V Vcc + 0.3 V
ihreset
Output Voltages
Voh Logic 1 Output Voltage 2.4 V @CP Io = -23 mA Vol Logic 0 Output Voltage 0.33 V @CP Io = 6 mA
Other
I
Tri-State output leakage current
out
Iin Input current
-5 µA 5 µA
-10 µA
10 µA
@CP 0 < V @CP 0 < V
< Vcc
out
< Vcc
i
Cio Input/Output capacitance 15 pF @CP typical
Zai Analog input source impedance E
Differential nonlinearity error.
dnl
Difference between the step width and the ideal value.
E
Integral nonlinearity error.
inl
Maximum deviation from the best straight line through the ADC transfer characteristics, excluding the quantization error.
3.2 AC characteristics
See timing diagrams, Section 4, for Tn numbers. The symbol “~” indicates active low signal.
Timing Interval Tn Minimum Maximum
Clock Frequency (F Clock Pulse Width T1 25 nsec Clock Period (note 2) T2 50 nsec Encoder Pulse Width T3 150 nsec Dwell Time Per State T4 75 nsec ~HostSlct Hold Time T6 0 nsec
) > 0 MHz 20 MHz (note 1)
clk
Analog Input
9k
-1 1.5 LSB
+/-1.5 LSB
MC3510 Technical Specifications
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Timing Interval Tn Minimum Maximum
~HostSlct Setup Time T7 0 nsec HostCmd Setup Time T8 0 nsec HostCmd Hold Time T9 0 nsec Read Data Access Time T10 25 nsec Read Data Hold Time T11 10 nsec ~HostRead High to HI-Z Time T12 20 nsec HostRdy Delay Time T13 100 nsec 150 nsec ~HostWrite Pulse Width T14 70 nsec Write Data Delay Time T15 35 nsec Write Data Hold Time T16 0 nsec Read Recovery Time (note 2) T17 60 nsec Write Recovery Time (note 2) T18 60 nsec Read Pulse Width T19 70 nsec Address Setup Delay Time T20 7 nsec Data Access Time T21 19 nsec Data Hold Time T22 2 nsec Address Setup Delay Time T23 7 nsec Address Setup to WriteEnable High T24 72 nsec RAMSlct Low to WriteEnable High T25 79 nsec Address Hold Time T26 17 nsec WriteEnable Pulse Width T27 39 nsec Data Setup Time T28 3 nsec Data Setup before Write High Time T29 42 nsec Address Setup Delay Time T30 7 nsec Data Access Time T31 71 nsec Data Hold Time T32 2 nsec Address Setup Delay Time T33 7 nsec Address Setup to WriteEnable High T34 122 nsec PeriphSlct Low to WriteEnable High T35 129 nsec Address Hold Time T36 17 nsec WriteEnable Pulse Width T37 89 nsec Data Setup Time T38 3 nsec Data Setup before Write High Time T39 92 nsec Read to Write Delay Time T40 50 nsec Reset Low Pulse Width T50 RAMSlct Low to Strobe Low T51 1 nsec Strobe High to RAMSlct High T52 4 nsec WriteEnable Low to Strobe Low T53 1 nsec Strobe High to WriteEnable High T54 3 nsec PeriphSlct Low to Strobe Low T55 1 nsec Strobe High to PeriphSlct High T56 4 nsec
5.0 µsec
Note 1 Performance figures and timing information valid at F
information and performance parameters at F
< 20.0 MHz, refer to section 7.1.
clk
= 20.0 MHz only. For timing
clk
Note 2 The clock low/high split has an allowable range of 45-55%.
MC3510 Technical Specifications
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4 I/O Timing Diagrams
For the values of Tn, please refer to the table in Section 3.2.
The host interface timing shown in diagrams 4.4 and 4.5 is only valid when an external logic device is used to provide a parallel communication interface. Refer to section 6 for more information.
4.1 Clock
ClockIn

4.2 Quadrature encoder input

Quad A
Quad B
~Index
4.3 Reset
T1 T2
T3
T4
T1
T3
T4
ClockIn
~RESET
V
cc
T50
MC3510 Technical Specifications
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4.4 Host interface, 8/16 mode (requires external logic device)

4.4.1 Instruction write, 8/16 mode

T7
see note
~HostSlct
T6
HostCmd
~HostWrite
HostData0-7
HostRdy
Note: If setup and hold times are met, ~HostSlct and HostCmd may be de-asserted at this point.

4.4.2 Data write, 8/16 mode

~HostSlct
T7
T8
T15
T14
T16
T18
T9
see note
T14
T16
Low byteHigh byte
T15
T13
T6
see note
HostCmd
~HostWrite
HostData0-7
HostRdy
T8
see note
T16
T18
T14
T15
T14
High byte
T15
Note: If setup and hold times are met, ~HostSlct and HostCmd may be de-asserted at this point.
T9
T16
Low byte
T13
MC3510 Technical Specifications
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4.4.3 Data read, 8/16 mode

~HostSlct
T7
T6
see note
HostCmd
~HostRead
HostData0-7
High-Z
HostRdy
Note: If setup and hold times are met, ~HostSlct and HostCmd may be de-asserted at this point.

4.4.4 Status read, 8/16 mode

~HostSlct
T8
T7
T10
T19
High
byte
T11
T12
see note
High-Z
Low byte
T13
T9
High-Z
T6
HostCmd
~HostRead
HostData0-7
T8
T17
T19
T12
High-Z High-Z
T10
High byte
T11
MC3510 Technical Specifications
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Low byte
T9
High-Z

4.5 Host interface, 16/16 mode (requires external logic device)

4.5.1 Instruction write, 16/16 mode

~HostSlct
HostCmd
T7 T6
~HostWrite
HostData0-15
HostRdy

4.5.2 Data write, 16/16 mode

~HostSlct
HostCmd
T8
T14
T15
T13
T7 T6
T8
T9
T16
T9
~HostWrite
HostData0-15
HostRdy
T14
T15
T13
MC3510 Technical Specifications
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T16

4.5.3 Data read, 16/16 mode

~HostSlct
HostCmd
~HostRead
HostData0-15
HostRdy
T7
T8
High-Z
T10
T19
T13
T6
T9
T12
High-Z
T11

4.5.4 Status read, 16/16 mode

~HostSlct
HostCmd
~HostRead
HostData0-15
T7
T8
High-Z
T10
T19
T6
T9
T11
T12
High-Z
MC3510 Technical Specifications
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4.6 External memory timing

4.6.1 External memory read

Note: PMD recommends using memory with an access time no greater than 15 nsec.
~RAMSlct
Addr0-Addr15
W/~R
~WriteEnbl
Data0-Data15
~Strobe

4.6.2 External memory write

~RAMSlct
T20
T23
T40
T21
T52T51
T24
Addr0-Addr15
T25
R/~W
W/~R
T29
~WriteEnbl
T28
Data0-Data15
~Strobe
T26
T27
T53 T54
T27
MC3510 Technical Specifications
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4.7 Peripheral device timing

4.7.1 Peripheral device read

~PeriphSlct
Addr0-Addr15
T30
T40
W/~R
~WriteEnbl
Data0-Data15
~Strobe

4.7.2 Peripheral device write

~PeriphSlct
Addr0-Addr15
R/~W
W/~R
T33
T31
T35
T34
T39
T36
T32
T31
T56T55
~WriteEnbl
Data0-Data15
~Strobe
T38
T37
T53 T54
T37
MC3510 Technical Specifications
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5 Pinouts and Pin Descriptions
5.1 Pinouts for MC3510
2, 7, 13, 21, 35, 36, 40, 47, 50,
52, 60, 62, 66, 93, 103, 121
~WriteEnbl
1 4
R/~W
6
~Strobe
~PeriphSlct
130 129
~RAMSlct
41
~Reset
W/~R132
43
SrlRcv
44
SrlXmt
99
SrlEnable
98
~HostIntrpt
58
ClockIn
110 Addr0
111
Addr1
112
Addr2
114
Addr3
115
Addr4
116
Addr5
117
Addr6
118
Addr7
119
Addr8
122
Addr9
123
Addr10
124
Addr11
125
Addr12
126
Addr13
127
Addr14
128
Addr15
9
Data0
10
Data1
11
Data2
12
Data3
15
Data4
16
Data5
17
Data6
18
Data7
19
Data8
22
Data9
23
Data10
24
Data11
25
Data12
26
Data13
27
Data14
28
Data15
VCC
CP
GND
AnalogVcc
AnalogRefHigh
AnalogRefLow
AnalogGnd
Analog1 Analog2 Analog3 Analog4 Analog5 Analog6 Analog7 Analog8
PosLim1 NegLim1 AxisOut1
AxisIn1
Direction1
Pulse1
QuadA1 QuadB1 ~Index1
~Home1
I/OIntrpt
PrlEnable
84
85 86 87 74 89 75 88 76 83 77 82 63 64 94 72
105 106
107AtRest1
67 68 69 70
53
65
3, 8, 14, 20, 29, 37, 46, 56, 59,
61, 71, 92, 104, 113, 120
Unassigned
5, 30-34, 38, 39, 42, 45, 48, 49,
51, 54, 55, 57, 73, 90, 91, 95-
97, 100-102, 108, 109, 131
AGND
78-81
MC3510 Technical Specifications
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5.2 CP chip pin description table

Pin Name and number Direction Description
~WriteEnbl 1 R/~W 4
~Strobe 6
~PeriphSlct 130 ~RAMSlct 129 ~Reset 41
W/~R 132
SrlRcv 43
SrlXmt 44 SrlEnable 99
~HostIntrpt 98 I/OIntrpt 53
PrlEnable
65
output When low, this signal enables data to be written to the bus. output This signal is high when the CP chip is performing a read, and low when it is
output This signal is low when the data and address are valid during CP
output This signal is low when peripheral devices on the data bus are being addressed. output This signal is low when external memory is being accessed. input This is the master reset signal. When brought low, this pin resets the processor to
output This signal is the inverse of R/~W; it is high when R/~W is low, and vice versa. For
input This pin receives serial data from the asynchronous serial port. If serial
output This pin transmits serial data to the asynchronous serial port. output This pin sets the serial port enable line. SrlEnable is always high for the point-to-
output When low, this signal causes an interrupt to be sent to the host processor. input This signal interrupts the CP chip when a host I/O transfer is complete. It
input This signal enables/disables the parallel communication with the host. If this
performing a write.
communications.
its initial conditions.
some decode circuits, this is more convenient than
communication is not used, this pin should be tied to V
R/~W.
.
cc
point protocol and is high during transmission for the multi-drop protocol.
should be connected to
CPIntrpt of the parallel interface chip.
If the parallel interface is disabled (see below) this signal can be left unconnected or tied to V
.
cc
signal is tied high, the parallel interface is enabled. If this signal is tied low the parallel interface is disabled. See section 6 of this manual for more information on parallel communication.
Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7 Data8 Data9 Data10 Data11 Data12 Data13 Data14 Data15
9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28
WARNING! This signal should only be tied high if an external logic device that implements the parallel communication logic included in the design. This signal is an output during device reset and as such any connection to GND or V
must be via a series
cc
resistor.
bi-directional Multi-purpose data lines. These pins comprise the CP chip’s external data bus,
used for all communications with peripheral devices such as external memory or DACs. They may also be used for parallel-word input and for user-defined I/O operations.
MC3510 Technical Specifications
26
Pin Name and number Direction Description
Addr0 Addr1 Addr2 Addr3 Addr4 Addr5 Addr6 Addr7 Addr8 Addr9 Addr10 Addr11 Addr12 Addr13 Addr14 Addr15 ClockIn 58
AnalogVcc 84
AnalogRefHigh 85
AnalogRefLow 86
AnalogGND 87
Analog1 Analog2 Analog3 Analog4 Analog5 Analog6 Analog7 Analog8 Pulse1 106
Direction1 105
AtRest1 107
QuadA1 QuadB1
110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128
74 89 75 88 76 83 77 82
67 68
output Multi-purpose Address lines. These pins comprise the CP chip’s external address
bus, used to select devices for communication over the data bus. They may be used for DAC output, parallel word input, or user-defined I/O operations. See the Pilot Motion Processor User’s Guide for a complete memory map.
input This is the clock signal for the Motion Processor. It is driven at a nominal
20MHz.
input CP chip analog power supply voltage. This pin must be connected to the analog
input supply voltage, which must be in the range 4.5-5.5 V If the analog input circuitry is not used, this pin must be connected to V
input CP chip analog high voltage reference for A/D input. The allowed range is
AnalogRefLow to AnalogVcc.
If the analog input circuitry is not used, this pin must be connected to V
input CP chip analog low voltage reference for A/D input. The allowed range is
AnalogGND to AnalogRefHigh.
If the analog input circuitry is not used, this pin must be connected to GND.
CP chip analog input ground. This pin must be connected to the analog input
power supply return. If the analog input circuitry is not used, this pin must be connected to GND.
input These signals provide general-purpose analog voltage levels, which are sampled
by an internal A/D converter. The A/D resolution is 10 bits. The allowed range is
Any unused pins should be tied to AnalogGND. If the analog input circuitry is not used, these pins should be tied to GND.
output This pins provides the pulse (also called step) signal to the motor amplifier. A
“step” occurs when the signal transitions from a high state to a low state. This
default operation can be changed using the SetSignalSense command. Refer
to the Pilot Programmer’s Reference for more information.
output This pin indicates the direction of motion and works in conjunction with the
pulse signal. A high level on this signal indicates a positive direction move and a low level indicates a negative direction move.
output The AtRest signal indicates that the axis is at rest and the step motor can be
switched to low power or standby. A high level on this signal indicates the axis is at rest. A low signal indicates the axis is in motion.
input These pins provide the A and B quadrature signals for the incremental encoder.
When the axis is moving in the positive (forward) direction, signal A leads signal B by 90°. The theoretical maximum encoder pulse rate is 5.1 MHz. Actual maximum rate will vary, depending on signal noise. NOTE: Many encoders require a pull-up resistor on each signal to establish a proper high signal. Check your encoder’s electrical specification.
AnalogRefLow to AnalogRefHigh.
.
cc
.
cc
MC3510 Technical Specifications
27
Pin Name and number Direction Description
~Index1 69
input This pin provides the Index signal for the incremental encoder. A valid index
pulse is recognized by the chip when
There is no internal gating of the index signal with the encoder A and B inputs. This must be performed externally if desired. Refer to the Application Notes section at the end of this manual for an example.
this signal transitions from high to low.
~Home1 70
PosLim1
NegLim1
AxisOut1 94
AxisIn1 72
Vcc
63
64
2, 7, 13, 21, 35, 36, 40,
input This pin provides the Home signal, general-purpose inputs to the position-
input This signal provides input from the positive-side (forward) travel limit switch.
input This signal provides input from the negative-side (reverse) travel limit switch. On
output This pin can be programmed to track the state of any bit in the status registers.
input This is a general-purpose or programmable input. It can be used as a breakpoint
47, 50, 52, 60, 62, 66, 93, 103, 121
capture mechanism. A valid Home signal is recognized by the chip when
~Home
goes low.
WARNING! If this pin is not used, its signal should be tied high.
On power-up or interpretation can be set explicitly using the
Reset this signal defaults to active low interpretation, but the
SetSignalSense instruction.
WARNING! If this pin is not used, its signal should be tied high.
power-up or interpretation can be set explicitly using the
Reset this signal defaults to active low interpretation, but the
SetSignalSense instruction.
WARNING! If this pin is not used, its signal should be tied high. This signal is an output during device reset and as such any connection to GND or V
If this pin is not used it may be left unconnected.
input, to stop a motion axis, or to cause an Update to occur.
If this pin is not used it may be left unconnected. CP digital supply voltage. All of these pins must be connected to the supply
voltage. V
must be in the range 4.75 - 5.25 V
cc
must be via a series resistor.
cc
WARNING! Pin 35 must be tied HIGH with a pull-up resistor. A nominal value of 22K Ohms is suggested.
GND
AGND
unassigned
unassigned
3, 8, 14, 20, 29, 37, 46,
CP ground. All of these pins must be connected to the power supply return. 56, 59, 61, 71, 92, 104, 113, 120
78-81 These signals must be tied to AnalogGND.
If the analog input circuitry is not used, these pins must be tied to GND. 45, 48, 49, 51, 54, 55,
73, 90, 91, 108, 109 5, 30-34, 38, 39, 42,
These signals may be connected to GND for better noise immunity and reduced
power consumption or they can be left unconnected (floating).
These signals must be left unconnected (floating). 57, 95, 96, 97, 100, 101, 102, 131
MC3510 Technical Specifications
28
6 Parallel Communication
With the addition of an external logic device, the Pilot motion processor can communicate with a host processor using a parallel data stream. This offers a higher communication rate than a serial interface and may be used in configurations where a serial connection is not available or not convenient. This section details the required logic that must be implemented in the external device as well as the necessary connections to the CP chip.
The reference design files for the parallel interface chip, in Actel/ViewLogic format, are available from PMD. There are two versions of the design, one for interfacing with host processors that have an 8-bit data bus and one for host processors that have a 16-bit data bus. The designs are called IOPIL8 and IOPIL16 respectively. The interface to the CP chip is essentially identical in both.
The function of the I/O chip is to provide a shared-memory style interface between the host and CP chip, comprised of four 16-bit wide locations. These are used for transferring commands and data between the host and Pilot motion processor. The CP chip accesses the command/data registers using its 16-bit external data bus while the host accesses the registers via a parallel interface with chip select, read, write and command/data signals. If necessary, the host side interface can be modified by the designer to match specific requirements of the host processor.

6.1 Host interface pin description table

Pin Name Direction Description
HostCmd
HostRdy
~HostRead ~HostWrite ~HostSlct CPIntrpt
CPR/~W
CPStrobe
input This signal is asserted high to write a host instruction to the motion processor, or to
read the status of the a data word.
output This signal is used to synchronize communication between the motion processor
and the host. write operation according to the interface mode in use, as follows:
Interface Mode
8/16 after the second byte of the instruction word after the second byte of each data word is transferred 16/16 after the 16-bit instruction word after each 16-bit data word serial n/a
HostRdy will go high, indicating that the host port is ready to transmit, when the last
transmission has been processed. All host port communications must be made with
HostRdy high (ready).
A typical busy-to-ready cycle is 12.5 microseconds, but can be substantially longer,
up to 100 microseconds. input When ~HostRead is low, a data word is read from the motion processor. input When ~HostWrite is low, a data word is written to the motion processor. input When ~HostSlct is low, the host port is selected for reading or writing operations. output I/O chip to CP chip interrupt. This signal sends an interrupt to the CP chip
whenever a host–chipset transmission occurs. It should be connected to CP chip
pin 53,
I/OIntrpt.
input This signal is high when the I/O chip is reading data from the I/O chip, and low
when it is writing data. It should be connected to CP chip pin 4, input This signal goes low when the data and address become valid during Motion
processor communication with peripheral devices on the data bus, such as external
memory or a DAC. It should be connected to CP chip pin 6,
HostRdy and HostIntrpt signals. It is asserted low to read or write
HostRdy will go low (indicating host port busy) at the end of a read or
HostRdy goes low
R/W.
Strobe.
MC3510 Technical Specifications
29
Pin Name Direction Description
CPPeriphSlct
CPAddr0 CPAddr1 CPAddr15
MasterClkIn
CPClk
HostData0 HostData1 HostData2 HostData3 HostData4 HostData5 HostData6 HostData7 HostData8 HostData9 HostData10 HostData11 HostData12 HostData13 HostData14 HostData15 CPData0 CPData1 CPData2 CPData3 CPData4 CPData5 CPData6 CPData7 CPData8 CPData9 CPData10 CPData11 CPData12 CPData13 CPData14 CPData15
input This signal goes low when a peripheral device on the data bus is being addressed. It
should be connected to CP chip pin 130, input These signals are high when the CP chip is communicating with the I/O chip (as
distinguished from any other device on the data bus). They should be connected to
CP chip pins 110 ( input This is the master clock signal for the motion processor. It is driven at a nominal
40 MHz output This signal provides the clock pulse for the CP chip. Its frequency is half that of
MasterClkIn (pin 89), or 20 MHz nominal. It is connected directly to the CP chip
I/Oclk signal (pin 58).
bi-directional, tri-state
These signals transmit data between the host and the Motion processor through
the parallel port. Transmission is mediated by the control signals
~HostWrite, ~HostRead and HostCmd
In 16-bit mode, all 16 bits are used (
order 8 bits of data are used (
bi-directional These signals transmit data between the I/O chip and pins Data0-15 of the CP chip,
via the motion processor data bus.
PeriphSlct.
Addr0), 111 (Addr1), and 128 (Addr15).
~HostSlct,
.
HostData0-15). In 8-bit mode, only the low-
HostData0-7).
MC3510 Technical Specifications
30
6.2 16-bit Host Interface (IOPIL16)
This design implements a parallel interface with a host processor utilizing a 16-bit data bus. An understanding of the underlying operation of the design is only necessary if the designer intends to make modifications. In most cases this design can be implemented without changes. The following notes should be read while referencing the schematics. IOPIL16 1 is the top level schematic. The timing for the host to I/O chip communication can be found in section 4.5 and the timing for the CP to I/O chip communication can be found in section 4.7.
The description below identifies the key elements of each schematic starting with the host side signals. The paragraph title identifies the key schematic(s) being described in the text.
IOPIL16 3
The host interface is shown in sheet IOPIL16 3. The incoming data HD[15:0] is latched in the transparent latches when ~HG1 and ~HG2 go high. This would be the result of a write from the host to the CP. The latched data HI[15:8] and HI[7:0] go to schematic IOPIL16 1 and IOPIL16 5. Data from the interface to the host, HO[15:8] and HO[7:0] is enabled onto the host bus, HD[15:0], by HOES2 and HOES1 respectively. The output latches, which present the data during a host read, are always transparent because GOUT is connected to VDD. The latched I/O is an I/O option on the Actel part used and could be omitted in the host interface if a different CPLD or FPGA does not have this feature.
IOPIL16 1
The control for the host interface starts on IOPIL16 1. HOES1 and HOES2 are the AND of ~HSEL and ~HRD and enable read data onto the host bus, as previously described. HRDY is a handshaking signal to the host to allow asynchronous communication between the host and the CP. The host must wait until HRDY is true before attempting to communicate with the CP. This signal is copied as a bit in the host status register. The host status register may be read at any time to determine the state of HRDY, or the HRDY output may be used as an interrupt to the host. ~HSEL, ~HRD, ~HWR, and HA0 are the buffered inputs of the host control signals.
HOST INTERFACE/IOPIL16 5
Data from the host HI[15:8] and HI[7:0] is written into REG1 and REG2 on the schematic HOST INTERFACE by ~EN1 and ~EN2. These registers have a 2 to 1 multiplexed input with both the host data and the CP data being written to these registers. This is convenient for diagnostic purposes and is very efficient in the Actel A42MX FPGA's, which are multiplexer based but if the configuration of the logic device used demands it, separate registers could be used for the host and CP data. The schematic for this register is shown as DFME8. Only commands and checksums are written to registers REG1 and REG2 while data is written and read from the set of data registers, DATREG shown on IOPIL16 5. These 3 data registers buffer data sent to and from the CP, reducing the number of interrupts the CP must handle. The output from REG1 and REG2, CIQ[15:8] and CIQ[7:0] go to IOPIL16 5, where they are multiplexed with the other data registers. The multiplexed result, IQ[15:8] and IQ[7:0], is multiplexed with HST[15:8] and HST[7:0] - the output of the host status registers REG3 and REG4. As previously mentioned, HRDY becomes HST15 so it can be read by the host. The rest of the status register is written by the CP to provide information to the host. HA0 acts as an address bit, and usually is an address bit on the bus. When the host is writing, HA0 low indicates data and HA0 high indicates a command. When the host is reading, HAO low indicates data and HA0 high indicates status. Read status is the only transaction
MC3510 Technical Specifications
31
allowed while HRDY is low. During a host write the AND gate (G1:HOST INTERFACE) and two flops latch the incoming data in the interface latches by driving ~HG1, and ~HG2 low from the start of the write transaction until the first negative clock transition after the first positive transition following the start of the write cycle. This tail-biting circuit removes the requirement for hold time on the data bus.
HICTLA
Most of the control logic for the host interface is shown on schematic HICTLA. The sequencer at the top generates HCYC one clock interval after the interface has been accessed and the host has finished the transaction. The nature of the transaction, rd/wr, command/data, and read status is preserved in the three flops F13, F8, and F9. A host write or a CP write, DSIW, enable REG1 and REG2 on the HOST INTERFACE schematic discussed previously. A host data write generates ~ENHD1 and ~ENHD2 for the data registers on the DATREG schematic. The logic at the bottom of the page generates the CP interrupt, the HRDY and the HCMDFL. The HCMDFL is used in the CP status to indicate a command. DSIW, the CP writing to REG1 and REG2 on the HOST INTERFACE schematic clears the interrupt and reasserts HRDY. HRDY is de-asserted during all host transactions except read status, and stays de-asserted until the CP has completed the DSIW cycle that clears the interrupt and reasserts HRDY. As mentioned previously data transfers to and from the host use the data registers and do not interrupt the CP. The CP knows the number of data transfers that must take place after decoding the command. It places this number, 0-3, in the 2 least significant bits of the host status register, HST[1:0]. These become DPNT[1:0] on this page of the schematic and enable an interrupt at 0 for a read and 1 or 0 for a write. The CP always leaves theses bit set to 0 unless setting up a multiple word data transfer. If INTEN is true and LRDST, latched read status, is false, HCYC will generate an interrupt to the CP. This will also hold HRDY false until after the CP writes to the interface register, DSIW, thereby generating ~CLRFLGS.
IOPIL16 4
The CP interface is shown in sheet IOPIL16 4. The incoming data DSD[15:0] is latched in the transparent latches when ~DG1 and ~DG2 go high. This occurs at the completion of a write from the CP to the I/O chip. The latched data DSI[15:8] and DSI[7:0] go to schematic IOPIL16 1 and IOPIL16 5. DSI[7:0] also goes to IOPIL16 2. Data from the interface to the CP, DO[15:8] and DO[7:0] is enabled onto the CP bus, DSD[15:0], by DOE2 and DOE1 respectively. The output latches, which present the data during a CP read, are always transparent because GOUT is connected to VDD. The latched I/O in the Actel part contains both input and output latches. The output latches could be omitted in the CP interface if a different CPLD or FPGA does not have this feature. The two incoming CP address bits CPA0 and CPA1 are also latched using ~DG3. The 20CK signal is the clock for the CP. This is a 20 MHz clock derived from a 40 MHz clock input.
IOPIL16 2
The CP control starts on IOPIL16 2. The I/O control is generated from ~CPSTRB, ~CPIS, CPSEL and R/W. ~DG1, ~DG2, and ~DG3 latch the incoming data and DOE1 and DOE2 out­enable the data from this chip to the CP. F2 and F4 tail-bite the write to avoid having to specify hold times on the data. Flop F1 divides the 40MHz clock down to 20 MHz. A 20 MHz clock could be used for this interface and the CP.
MC3510 Technical Specifications
32
DSPWA
The CP write control is contained on schematic DSPWA. The CP interface uses page addressing to save I/O pins. F0, F1 and F2 make up the page register. In addition there are the 2 address bits, LA0 and LA1. A write to address 0 selects the page register with DSI[2:0] going to the page register and selecting the page for the successive transfers. A read from address 0 reads the status register on all pages. Pages 4 and 6 are the only ones implemented in this device. L1 latches the r/w level. The write decoding generates DSIW which enables writes to the DFME8 registers reg1 and reg2 shown on the HOST INTERFACE schematic. DSIW also clears the CP interrupt and restores HRDY. DSWST writes to the host status register also shown on the HOST INTERFACE schematic. DSWDREG implements writing to the data registers shown on IOPIL16 5 and DATREG. Finally the logic at the bottom of the page generates CPCYC, a 1-clock interval after the CP cycle is over that implements the actual writes to the registers. The use of the data bus latches and the post bus cycle transfers keeps as much of the logic synchronous as possible given two asynchronous devices, without requiring clocking at several times the bus speed.
DSPRA
The CP read control is contained on schematic DSPRA. The 2 by 16 bit mux selects CP status if the CP latched address is 0 and IQ[15:0] if the address is not 0. The only significant status bits are bits 15 (indicating the CP is interrupting the host), bits 13 and 14 (both 0 indicating a 16 bit host interface) and bit 0 (set to 1 during a host command transfer and 0 during data transfer).
HOST INTERFACE
Both the CP and the host use a special mode to transfer data to avoid unnecessary CP interrupts. This special mode is under the control of the CP and is transparent to the host. When the CP receives a command from the host it initializes the transfer by setting the number of transfers expected (0,1,2 or 3) in the 2 LSB's of the host status register, REG3 and REG4 on HOST INTERFACE. This write (DSWST) also loads these bits into the 2 bit down counter DCNT2 on IOPIL16 5. Note that a Q8 low, which indicates a host command, asynchronously clears this register enabling interrupts on schematic HICTLA. If DPNT[1:0] is not 0 and Q8 is high, indicating a host data transfer, and SINT goes high indicating the end of a host cycle the counter is decremented. MXAD2 selects address RA from the CP latched address bits if the page register contains 6, or the counter contents DPNT[1:0] if not. This allows the CP to have direct access to registers 1, 2, and 3, using addresses 1,2,and 3 on page 6. The host on the other hand can only read or write to the data register, HA0 low and the counter will auto decrement from 3 down to 0 allowing the host to access the registers on DATREG where REG1=R1 and R2, REG2=R3 and R4, and REG3=R5 and R6. The writes are enabled by the two decoders DECE2X4, while the reads are selected by the two 4x8 muxes, MUX1 and MUX2 controlled by the two 2x1 muxes MDS1 and MDS0. The output data IQ[15:0] goes to HOST INTERFACE schematic below IOPIL16 1 and to DSPRA below IOPIL16 2. The write data is HI[15:8], HI[7:0] from the host and DSI[15:8] and DSI[7:0] from the CP.
MC3510 Technical Specifications
33
DCBA
INBUF
HSTSEL
1
2
HSTRD
HSTWR HWR
HADR0
PAD Y
PAD Y
PAD Y
PAD Y
HRD
HSEL
IN17
HSEL
INBUF
IN18
HRD
INBUF
IN19
INBUF
IN20
HA0
A
Y
AND2B
B
HOES1
HI[7:0]
HI[15:8]
DSI[15:8]
DSI[7:0]
DPNT[1:0]
DSWST
DSIW
IQ[7:0]
IQ[15:8]
CLK
HINTF
HSEL
HRD
HWR
HA0
HI[7:0]
HI[15:8]
DSI[15:8]
DSI[7:0]
HST[1:0]
DSWST
DSIW
IQ[7:0]
IQ[15:8]
CLK
HOST INTERFACE
(HINTRFA)
HO[7:0]
HO[15:8]
CIQ[7:0]
CIQ[15:8]
HST14
HCMDFL
DSPINTR
HST15
ENHD1
ENHD2
SINT
HG1
HG2
HO[7:0]
HO[15:8]
CIQ[7:0]
CIQ[15:8]
Q8
Q8
SINT
HG1
HG2
ST15
ST0
DSPINTR
RDY HRDY
ENHD1
ENHD2
OUTBUF
D PAD
1
2
3
4
HRD
HSEL
A
Y
AND2B
B
HOES2
DSPINTR
OUTBUF
D PAD
OUT5
DSPINT
3
4
IOPIL16 1
22 OCT 2002 DBS
A B C D
DRAWN BY:
DCBA
PNT0
PNT1
DSPWA
DSPWA
DSWDREG
DSIW
DSWST
CPCYC
1
DSI[7:0]
IN27
INBUF
PAD Y
CS
INBUF
PAD Y
CPR-W
INBUF
PAD Y
CPSTRB
CPIS
CPSEL
R/W
STRB
IS
20CK
INBUF
PAD Y
CKBUF
2
3
CLKINT
CPSEL
IN28
IN26
IN30
R/W
CPSTRB
YA
A
G1
Y
B
C
A
B
C
NAND3B
AND4B
CSACC
G2
Y
DOE1
CPIS
CLK
D
A
G3
B
Y
DOE2
AND4B
C
DG3
DSI[7:0]
DG3
LA0
LA0
LA1
LA1
CPSEL
R/W
CPSTRB
CPIS
CLK
CSEL0
CSEL1
DSWDREG
DSIW
DSWST
PP6
PP6
PP4
PP4
CPCYC
CLKIN
PAD Y
IQ[15:0]
IB1
ST0
ST15
INBUF
DSPRA
ST0
ST15
IQ[15:0]
DO[15:0]
LA0
LA1
40CK
LA0
LA1
DSPRA
F1
QN
D
DF1A
CLK
DO[15:0]
20CK
1
2
3
D
G4
A
Y
B
C
A
B
C
A
4
CSACC
CQ3
B
C
D
DG1
NAND3B
G5
Y
DG2
NAND3B
F2
G6
Y
DG3
NAND4B
CSACC CQ3
CLK
D
Q
DF1
CLK
CQ1
F4
D
Q
DF1
CLK
4
IOPIL16 2
24 OCT 2002 DBS
A B C D
DRAWN BY:
DCBA
HIGH SLEW
D
HO0
GOUT
HO1
GOUT
G
D
BBDLHS
GIN
G
D
G
1
VDD
D
BBDLHS
GIN
HO2
GOUT
G
D
G
2
D
BBDLHS
GIN
G
D
HO3
GOUT
G
3
HG1
GIN
HO[7:0]
D
BBDLHS
G
E
PAD
PAD
PAD
PAD
HD0
Q
HI0
HD1
Q
HI1
HD2
Q
HI2
HD3
Q
HI3
HO4
HO5
HO6
HO7
GOUT
GOUT
GOUT
GOUT
HG1
D
G
D
BBDLHS
GIN
G
D
G
D
BBDLHS
GIN
G
D
G
D
BBDLHS
GIN
G
D
G
D
BBDLHS
GIN
G
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
PAD
HI[7:0]
PAD
PAD
PAD
HD4
VDDVDD
Q
HI4
HD5
Q
HI5
HD6
Q
HI6
HD7
Q
HI7
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
QD
Q
HO8
HO9
HO10
HO11
GOUT
GOUT
GOUT
GOUT
D
G
D
BBDLHS
GIN
G
D
G
D
BBDLHS
GIN
G
D
G
D
BBDLHS
GIN
G
D
G
D
BBDLHS
GIN
G
HO[15:8]
HIGH SLEW
E
PAD
PAD
PAD
PAD
HD8
VDD
Q
HI8
HD9
Q
HI9
HD10
Q
HI10
HD11
Q
HI11
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
QD
Q
HO12
HO13
HO14
HO15
GOUT
GOUT
GOUT
GOUT
HG2
D
G
D
BBDLHS
GIN
G
D
G
D
BBDLHS
GIN
G
D
G
D
BBDLHS
GIN
G
D
G
D
BBDLHS
GIN
G
HIGH SLEW
E
PAD
PAD
PAD
PAD
HD12
1
Q
HI12
HD13
Q
HI13
2
HD14
Q
HI14
HD15
Q
HI15
3
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
QD
Q
HI[15:0]
HOES1 HOES2
4
A B C D
VCC
Y
VDD
HG2
IOPIL16 3
21 OCT 2002 DBS
DRAWN BY:
4
DCBA
DOE1
D
DO0
DOE1
DO1
GOUT
GOUT
G
D
BBDLHS
GIN
G
D
G
VDD
1
D
BBDLHS
GIN
G
DOE1
2
DO2
GOUT
D
G
D
BBDLHS
GIN
G
DOE1
D
DO3
GOUT
G
3
DG3
GOUT
GIN
4
D
BBDLHS
GIN
G
DO[7:0]
GND
D
QD
G
Q
D
BBDLHS
G
A B C D
QD
Q
QD
Q
QD
Q
QD
Q
E
HIGH SLEW
HIGH SLEW
E
HIGH SLEW
E
HIGH SLEW
E
HIGH SLEW
E
PAD
PAD
DSD0
VDD VDD VDD
Q
DSI0
PAD
DSD1
Q
DSI1
PAD
DSD2
Q
DSI2
PAD
DSD3
Q
DSI3
CPA0
GOUT
Q
LA0
DG3
DOE1
D
DO4
GOUT
G
D
BBDLHS
GIN
G
DOE1
D
DO5
GOUT
G
D
BBDLHS
GIN
GOUT
G
D
G
DOE1
DO6
D
BBDLHS
GIN
GOUT
G
D
G
DOE1
DO7
D
BBDLHS
GIN
G
DG1
DOE1
GND
D
HIGH SLEW
E
QD
PAD
HIGH SLEW
E
PAD
PAD
PAD
PAD
DSI[7:0]
DSD4
Q
DSI4
DSD5
Q
DSI5
DSD6
Q
DSI6
DSD7
Q
DSI7
DOE2
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
QD
Q
CPA1
G
Q
Q
D
BBDLHS
GIN
G
LA1
OUTBUF
D PAD
VCC
DOE2
D
DO8
GOUT
G
D
BBDLHS
GIN
G
DOE2
D
DO9
GOUT
G
D
BBDLHS
GIN
G
DOE2
D
DO10
GOUT
G
D
BBDLHS
GIN
G
DOE2
D
DO11
GOUT
G
D
BBDLHS
GIN
G
DO[15:8]
DG2
Y
VDD
CLKOUT20CK
HIGH SLEW
E
PAD
PAD
PAD
PAD
DSD8
Q
DSI8
DSD9
Q
DSI9
DSD10
Q
DSI10
DSD11
Q
DSI11
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
QD
Q
21 OCT 2002
DOE2
D
DO12
GOUT
G
D
GIN
G
DOE2
D
DO13
GOUT
G
D
GIN
GOUT
G
D
G
DOE2
DO14
D
GIN
GOUT
G
D
G
DOE2
DO15
D
GIN
G
DG2
DOE2
IOPIL16 4
BBDLHS
BBDLHS
BBDLHS
BBDLHS
DRAWN BY:
HIGH SLEW
E
PAD
PAD
PAD
PAD
DSD12
Q
DSI12
DSD13
Q
DSI13
DSD14
Q
DSI14
DSD15
Q
DSI15
1
2
3
4
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
QD
Q
DSI[15:8]
DBS
DCBA
Q8
SINT
NAND2B
A
B
A
B
Y
END1
OR2A
1
Y
END2DOE1
OR2A
A
B
Y
DPINC
AND3
C
Y
2
3
ENHD1
DSWDREG
1
PP4
CIQ[7:0]
CIQ[15:8]
HI[7:0]
HI[15:8]
DSI[7:0]
DSI[15:8]
2
3
RA[1:0]
LA[1:0]
PP6
END1
END2
CLK
DSWST
DPINC
Q8
CLK
DSI[1:0]
DREG
DOE1
PP4
CIQ[7:0]
CIQ[15:8]
HI[7:0]
HIH[15:8]
DSI[7:0]
DSI[15:8]
RA[1:0]
LA[1:0]
PP6
END1
END2
CLK
DCNT2
SLOAD
ENABLE
ACLR
CLOCK
DATA[1:0]
DATREG
Q[1:0]
IQ[7:0]
IQ[15:8]
DPNT[1:0]
IQ[7:0]
IQ[15:8]
MXAD2
DPNT0
DPNT1
ENHD2
A
B
DATA0_[1:0]
RESULT[1:0]
DATA1_[1:0]
LA0
LA1
4
LA[1:0]
SEL0
RA[1:0]
4
IOPIL16 5
PP6
22 OCT 2002
A B C D
DRAWN BY:
DBS
DCBA
REG1
EN1
1
DSIW
BUF2
CLK
2
BUF
BUF1
YA
HI[7:0]
DSI[7:0]
YA
DSL
BUF
EN2
DSLA
HI[15:8]
DSI[15:8]
REG2
EN1
S
A[7:0]
B[7:0]
EN1
S
A[7:0]
B[7:0]
DFME8
CK
Q[7:0]
DFME8
CK
Q[7:0]
CIQ[7:0]
CIQ[15:8]
DSWST
CLK
DSI[7:2]
DSWST
VDD
CLK
DSI[14:8]
REG3
REG4
REG6
ENABLE
CLOCK
DATA[5:0]
REG7
ENABLE
ACLR
CLOCK
DATA[6:0]
Q[5:0]
Q[6:0]
HST[1:0]
HST[7:2]
HST[14:8]
IQ[7:0]
HST[7:0]
HST14
IQ[15:8]
MUX1
HA0
MUX2
DATA0_[7:0]
DATA1_[7:0]
MUX2X8
RESULT[7:0]
MUX2X8
HO[7:0]
SEL0
1
2
HICTLA
HST[1:0]
HSEL
3
G1
A
4
HWR
HSEL
CLK
Y
AND2B
B
D
Q
DF1
CLK
D
DF1C
CLK
HWR
HRD
HA0
DSIW
CLK
QN
DPNT[1:0]
HSEL
HWR
HRD
HA0
DSIW
CK
G2
A
B
G3
A
B
DSPINTR
HCMDFL
HICTLA
Y
HG1
NAND2
Y
HG2
NAND2
ENHD1
ENHD2
SINT
EN1
EN2
HRDY
ENHD1
ENHD2
SINT
Q8
Q8
EN1
EN2
HST15
DSPINTR
HCMDFL
HST[15:8]
HOST INTERFACE
(HINTRFA)
24 OCT 2002
A B C D
DATA0_[7:0]
RESULT[7:0]
DATA1_[7:0]
SEL0
HA0
DRAWN BY:
HO[15:8]
3
4
DBS
CLR
CLR
CS
JKF2C
JKF2C
Q
CS
Q
CS
Q
G21
A
B
C
D
DCBA
LWR
INV3
AY
Q8 HCMD
INV
INV4
AY
INV
2
2
Y
HRDY
NOR4
CC
1
LRDSTQ9
2
3
INV1
AY
HRD
HWR
HRD
HSEL
G2
1
2
3
DPNT[1:0]
HWR
HSEL
CK
DPNT0
DPNT1
LWR
A
B
AND2B
HRD
INV
A
B
C
G1
Y
OA1C
Y
HWR
HWR
DSIW
A
Y
B
NAND3B
C
A
NAND2B
B
LRDST
HCYC
RDEN
WREN
Q8
Y
A
AND2A
B
F1
D
Q
DF1
CLK
A
B
A
B
Y
NOR2
NOR2
EN2
Y
EN1
A
B
Y
OR3C
C
INTEN
SINT
CLRFLGS
Y
F2 F3
D
DF1
Q2Q1
Q
CLK
Q1
HCYC
HWR
Q8
A
B
Y
SINTR
AND3
C
A
Y
NAND2
B
A
Y
NAND2
B
F6
J
Q
JKF
CLK
K
GND
ENHD2
ENHD1
DSPINTR
D0 D1 D2 D3
DFM6A
S0 S1
CLK
CLR
HCYC
Q
VCC
Y
INV2
AY
INV
F5
D
CLK
CK
HSEL
HWR
HSEL
HWR
HA0
HSEL
HRD
HA0
F10
D
Q
DF1
Q
DF1
CLK
A
Q1
B
Q2
C
HCYC
D
Q9
A
B
G7
A
B
C
G10
A
B
C
DSPINTR
AND3B
AND2B
AND3B
HCYC
CK
VDD
Y
HCYC
CK
VDD
Y
HCYC
CK
VDD
Y
OA4
SHWR
SHCMD
SLRDST
Y
EBSY
F13
J
CLK
K
F8
J
CLK
K
F9
J
JKF2C
CLK
K
CLR
G19
CLRFLGS
A
Y
AND2
B
HCCYC
CK
F7
J
JKF
CLK
K
HCMDFL
Q
HICTLA
DRAWN BY:
DBS21 OCT 2002
4
HCYC
HCMD
4
DSIW
A B C D
AY
INV
DSI[7:0]
DCBA
DSI0
1
F0 PNT0
D
Q
DFE1B
E
CLK
A
B
Y
AND3B
C
PP4
1
A
B
Y
DSI1
F1
D
DFE1B
E
PNT1
Q
AND3A
C
PP6
CLK
DSI2
DSWPNT
CLK
F2
D
DFE1B
E
CLK
2
3
4
L1
R/W LR/W
DG3
CPIS
CPSTRB
CPSEL
CLK
Q
D
DL1B
G
G6
A
B
Y
AND3B
C
A B C D
PNT2
Q
G2
A
CPS
DEC2
LA0
LR/W
LA1
VCC
Y
Q3
AY
CPCYC
ADW0
Y0
DECE2X4D
A
Y1
E
B
F4
D
DFE3A
E
CLK
CLR
INV
ADW2
Y2
ADW3
Y3
G11
CPCYC1
PP4
ADW2
G12
CPCYC1
PP4
ADW3
ADW0
LR/W
CPCYC1
PP6
Q2
Q
Y
NAND2
B
A
B
Y
AND3
C
A
B
Y
AND3
C
A
B
Y
AND4B
C
D
AY
INV
DSWPNT
DSIW
DSWST
DSWDREG
Q3
2
3
Q2
GND
CPS
F5
D0 D1 D2 D3
DFM6A
S0 S1
CLK
CLR
Q3
Q
VCC
Y
BUF2
BUF3
YA
CPCYC
BUF
YA
CPCYC1
BUF
4
24 OCT 2002
DSPWA
DRAWN BY:
DBS
DCBA
ST0
1
2
3
ST15
Y
GND
BUF
BUF
BUF
$ARRAY=12
YA
CH0
YA
CH15
MUX2X16
CH15,GND,GND,GND[12:1],CH0
IQ[15:0]
GND[12:1]
YA
A
LA0
B
LA1
DATA0_[15:0]
RESULT[15:0]
DATA1_[15:0]
SEL0
Y
IQSEL
OR2
DO[15:0]
1
2
3
4
A B C D
DSPRA
DRAWN BY:
DBS24 OCT 2002
4
A[7:0]
DCBA
1
2
3
B[7:0]
B4B0 B1 B2 B3 B5 B6 B7
A4A0 A1 A2 A3 A5 A7
S
EN1
CK
ABS
CLK
ABS
CLK
E
DFME1A
Q
ABS
CLK
E
DFME1A
Q
ABS
CLK
E
DFME1A
Q
ABS
CLK
E
DFME1A
Q
ABS
E
DFME1A
Q
E
CLK
DFME1A
Q
Q4 Q7Q6Q5Q3Q2Q1Q0
CLK
A6
F7F6F5F4F3F2F1F0
ABS
CLK
E
DFME1A
Q
Q[7:0]
ABS
E
DFME1A
Q
1
2
3
4
A B C D
DFME8
DRAWN BY:
DBS19 NOV. 2002
4
RESULT[7:0]
RESULT[7:0]
DCBA
IQ[7:0]
SEL0
1
2
IQ[15:8]
SEL0
3
4
R1
EN1R1
DSPSEL
1
HI[7:0]
DSI[7:0]
EN2R1
EN1
S
DFME8
CK
A[7:0]
Q[7:0]
B[7:0]
R2
R1[7:0]
EN1R3
DSPSEL2
HI[7:0]
DSI[7:0]
EN1
EN2R3
S
A[7:0]
B[7:0]
DFME8
CK
Q[7:0]
R1[15:8]
CLK
HIH[15:8]
DSI[15:8]
CLK
HIH[15:8]
DSI[15:8]
R3
A
RA[1:0]
LA0
LA1
PP4
DOE1
B
Y
AND4A
C
D
S
A
RA0
MX2
B
GND
Y
GND
END1
RA0
RA1
2
EN1R2
DSPSEL1
EN1
S
DFME8
CK
HI[7:0]
DSI[7:0]
A[7:0]
B[7:0]
Q[7:0]
R2[7:0]
R4
EN2R2
CLK
3
HIH[15:8]
DSI[15:8]
EN1
S
A[7:0]
B[7:0]
DFME8
CK
Q[7:0]
R2[15:8]
LA[1:0]
B1
YA
DSPSELPP6
BUF
B2
YA
DSPSEL1
BUF
B3
YA
DSPSEL2
BUF
4
R5 MUX1
EN1
S
DFME8
CK
A[7:0]
Q[7:0]
R3[7:0]
B[7:0]
R6
EN1
S
DFME8
CK
A[7:0]
Q[7:0]
R3[15:8]
B[7:0]
DSIR
S
A
DECE2X4
DECE2X4
RA1
GND
Y
MDS1
MX2
B
EQ0
EN1R1
EQ1
EN1R2
EQ2
EN1R3
EQ3
EQ0
EN2R1
EQ1
EN2R2
EQ2
EN2R3
EQ3
Y
MDS0
DEC1
DATA0
DATA1
ENABLE
DEC2
DATA0
DATA1
CIQ[7:0]
R1[7:0]
R2[7:0]
R3[7:0]
CIQ[15:8]
R1[15:8]
R2[15:8]
R3[15:8]
MUX4X8
DATA0_[7:0]
DATA1_[7:0]
DATA2_[7:0]
DATA3_[7:0]
SEL1
MDS1 MDS0
MUX2
MUX4X8
DATA0_[7:0]
DATA1_[7:0]
DATA2_[7:0]
DATA3_[7:0]
SEL1
MDS1 MDS0
DATREG
END2
ENABLE
DRAWN BY:
A B C D
DBS24 OCT 2002

6.3 8-bit Host Interface (IOPIL8)

This design implements a parallel interface with a host processor utilizing an 8-bit data bus. An understanding of the underlying operation of the design is only necessary if the designer intends to make modifications. In most cases this design can be implemented without changes. The following notes should be read while referencing the schematics. IOPIL16 1 is the top level schematic. The timing for the host to I/O chip communication can be found in section 4.4 and the timing for the CP to I/O chip communication can be found in section 4.7.
The description below identifies the key elements of each schematic starting with the host side signals. The paragraph title identifies the key schematic(s) being described in the text.
IOPIL8 3
The host interface for IOPIL8 is shown in sheet IOPIL8 3. The incoming data HD[7:0] is latched in the transparent latches when ~HG1 goes high. This would be a write from the host to the CP. The latched data HI[7:0] goes to IOPIL8 1 and IOPIL8 5. Data from the interface to the host, HO[7:0] is enabled onto the host bus, HD[7:0], by HOES1. The output latches, which present the data during a host read, are always transparent because GOUT is connected to VDD. The latched I/O is an I/O option on the Actel part used and could be omitted in the host interface if a different CPLD or FPGA does not have this feature. HD[15:8] are tri-stated outputs because Actel grounds unused I/O pins and this would interfere with using existing PMD test equipment. These reserved I/O's can be ommitted in a different implementation with an 8 bit bus.
IOPIL8 1
The control for the host interface starts on IOPIL8 1. HOES1 is the AND of ~HSEL and ~HRD, and enable read data onto the host bus, as previously described. HRDY is a handshaking signal to the host to allow asynchronous communication between the host and the CP. The host must wait until HRDY is true before attempting to communicate with the CP. This signal is copied as a bit in the host status register. The host status register may be read at any time to determine the state of HRDY, or the HRDY output may be used as an interrupt to the host. ~HSEL, ~HRD, ~HWR, and HA0 are the buffered inputs of the host control signals.
HOST INTERFACE/IOPIL8 5
Data from the host HI[7:0] is written into REG1 and REG2 on the schematic HOST INTERFACE by ~EN1 and ~EN2. All transfers are 16 bits and take two writes or reads on the 8-bit bus. These registers have a 2 to 1 multiplexed input with both the host data and the CP data being written to this register.
This is convenient for diagnostic purposes and is very efficient in the Actel A42MX FPGA's, which are multiplexer based but if the configuration of the logic device used demands it, separate registers could be used for the host and CP data. The schematic for this register is shown as DFME8. Only commands and checksums are written to registers REG1 and REG2 while data is written and read from the set of data registers, DATREG shown on IOPIL8 5. These 3 data registers buffer data sent to and from the CP, reducing the number of interrupts the CP must handle. The output from REG1 and REG2, CIQ[15:8] and CIQ[7:0] go to IOPIL8 5, where they are multiplexed with the other data registers. The multiplexed result, IQ[15:8] and IQ[7:0], is multiplexed with HST[15:8] and HST[7:0] ­the output of the host status registers REG3 and REG4. This four input mux, MUX4X8, also muxes the 16 bit data onto the 8-bit bus. As previously mentioned HRDY becomes HST15 so it can be read by the host. The rest of the status register is written by the CP to provide information to the
MC3510 Technical Specifications
45
host. HA0 acts as an address bit, and usually is an address bit on the bus. When the host is writing, HA0 low indicates data and HA0 high indicates a command. When the host is reading, HAO low indicates data and HA0 high indicates status. Read status is the only transaction allowed while HRDY is low. During a host write the AND gate (G1:HOST INTERFACE) and two flops latch the incoming data in the interface latches by driving ~HG1 low from the start of the write transaction until the first negative clock transition after the first positive transition following the start of the write cycle. This tail-biting circuit removes the requirement for hold time on the data bus.
HICTLA
Most of the control logic for the host interface is shown on schematic HICTLA. The sequencer at the top generates HCYC one clock interval after the interface has been accessed and the host has finished the transaction. The nature of the transaction, rd/wr, command/data, and read status is preserved in the three flops F13, F8, and F9. Since 16 bit transfers must take place over an 8 bit bus two transfers are required. The toggle flop is used to determine whether a cycle is the first or second of the 2 required. The toggle flop may be initialized to the 0 state, which indicates that this is the first transfer (high byte), by the CP writing a one to host status bit 15. This status bit is read by the host as the HRDY bit and is not writable by the CP. In addition flop F12 and the associated gating determine if the present command transaction is the first or second byte of a command. If the toggle flop gets into the wrong state due to a missed or aborted transfer the next command will set it back to the correct state. A host write or a CP write, DSIW, enable REG1 and REG2 on the HOST INTERFACE schematic discussed previously. A host data write generates ~ENHD1 and ~ENHD2 for the data registers on the DATAREG schematic. For host writes ~EN2, ~EN1, ~ENHD2, and ~ENHD1 are also determined by the state of the toggle flop using HIEN and LOEN. 1CMD is used in this logic to ensure correct behavior when the command is correcting the state of the toggle. The logic at the bottom of the page generates the CP interrupt, the HRDY and the HCMDFL. The HCMDFL is used in the CP status to indicate a command. DSIW, the CP writing to REG1 and REG2 on the HOST INTERFACE schematic clears the interrupt and reasserts HRDY. HRDY is de-asserted during all host transactions except read status, and stays de-asserted until the CP has completed the DSIW cycle that clears the interrupt and reasserts HRDY. As mentioned previously data transfers to and from the host use the data registers and do not interrupt the CP. The CP knows the number of data transfers that must take place after decoding the command. It places this number, 0-3, in the 2 least significant bits of the host status register, HST[1:0]. These become DPNT[1:0] on this page of the schematic and enable an interrupt at 0 for a read and 1 or 0 for a write. The CP always leaves these bits at 0 unless setting up a multiple word data transfer. If INTEN is true and LRDST, latched read status, is false, HCYC will generate an interrupt to the CP. This will also hold HRDY false until after the CP writes to the interface register, DSIW, thereby generating ~CLRFLGS.
IOPIL8 4
The CP interface is shown in sheet IOPIL8 4. The incoming data DSD[15:0] is latched in the transparent latches when ~DG1 and ~DG2 go high. This occurs at the completion of a write from the CP to the I/O chip. The latched data DSI[15:8] and DSI[7:0] go to schematic IOPIL8 1 and IOPIL16 5. DSI[7:0] also goes to IOPIL16 2. Data from the interface to the CP, DO[15:8] and DO[7:0] is enabled onto the CP bus, DSD[15:0], by DOE2 and DOE1 respectively. The output latches, which present the data during a CP read, are always transparent because GOUT is connected to VDD. The latched I/O in the Actel part contains both input and output latches. The output latches could be omitted in the CP interface if a different CPLD or FPGA does not have this feature. The two incoming CP address bits CPA0 and CPA1 are also latched using ~DG3. The 20CK signal is the clock for the CP. This is a 20 MHz clock derived from a 40 MHz clock input.
MC3510 Technical Specifications
46
IOPIL8 2
The CP control starts on IOPIL8 2. The I/O control is generated from ~CPSTRB, ~CPIS, CPSEL and R/W. ~DG1, ~DG2, and ~DG3 latch the incoming data and DOE1 and DOE2 out-enable the data from this chip to the CP. F2 and F4 tail-bite the write to avoid having to specify hold times on the data. Flop F1 divides the 40MHz clock down to 20 MHz. A 20 MHz clock could be used for this interface and the CP.
DSPWA
The CP write control is contained on schematic DSPWA. The CP interface uses page addressing to save I/O pins. F0, F1 and F2 make up the page register. In addition there are the 2 address bits, LA0 and LA1. A write to address 0 selects the page register with DSI[2:0] going to the page register and selecting the page for the successive transfers. A read from address 0 reads the status register on all pages. Pages 4 and 6 are the only ones implemented in this device. L1 latches the r/w level. The write decoding generates DSIW which enables writes to the DFME8 registers reg1 and reg2 shown on the HOST INTERFACE schematic. DSIW also clears the CP interrupt and restores HRDY. DSWST writes to the host status register also shown on the HOST INTERFACE schematic. DSWDREG implements writing to the data registers shown on IOPIL8 5 and DATREG. Finally the logic at the bottom of the page generates CPCYC, a 1-clock interval after the CP cycle is over that implements the actual writes to the registers. The use of the data bus latches and the post bus cycle transfers keeps as much of the logic synchronous as possible given two asynchronous devices, without requiring clocking at several times the bus speed.
DSPRA
The CP read control is contained on schematic DSPRA. The 2 by 16 bit mux selects CP status if the CP latched address is 0 and IQ[15:0] if the address is not 0. The only significant status bits are bits 15 (indicating the CP is interrupting the host), bit 14 (1 indicating an 8-bit host interface) and bit 0 (set to 1 during a host command transfer and 0 during data transfer).
HOST INTERFACE
Both the CP and the host use a special mode to transfer data to avoid unnecessary CP interrupts. This special mode is under the control of the CP and is transparent to the host. When the CP receives a command from the host it initializes the transfer by setting the number of transfers expected (0,1,2 or 3) in the 2 LSB's of the host status register, REG3 and REG4 on HOST INTERFACE. This write (DSWST) also loads these bits into the 2 bit down counter DCNT2 on IOPIL8 5. Note that a Q8 low, which indicates a host command, asynchronously clears this register enabling interrupts on schematic HICTLA. If DPNT[1:0] is not 0 and Q8 is high, indicating a host data transfer, and SINT goes high indicating the end of a host cycle the counter is decremented. MXAD2 selects address RA from the CP latched address bits if the page register contains 6, or the counter contents DPNT[1:0] if not. This allows the CP to have direct access to registers 1, 2, and 3, using address 1,2,and 3 on page 6. The host on the other hand can only read or write to the data register, HA0 low and the counter will auto decrement from 3 down to 0 allowing the host to access the registers on DATAREG where REG1=R1 and R2, REG2=R3 and R4, and REG3=R5 and R6. The writes are enabled by the two decoders DECE2X4 while the reads are selected by the two 4x8 muxes, MUX1 and MUX2 controlled by the two 2x1 muxes MDS1 and MDS0. The output data IQ[15:0] goes to HOST INTERFACE schematic below IOPIL8 1 and to DSPRA below IOPIL8 2. The write data is HI[7:0] from the host and DSI[15:8] and DSI[7:0] from the CP. Note that END1
MC3510 Technical Specifications
47
and END2, the write enables, are both high for DSWDREG, while they are high one at a time for host writes controlled by the toggle flop. SINT enables DPINC only when the toggle is high after the second transfer.
MC3510 Technical Specifications
48
DCBA
INBUF
HSTSEL
1
2
HSTRD
HSTWR HWR
HADR0
PAD Y
PAD Y
PAD Y
PAD Y
HRD
HSEL
IN17
HSEL
INBUF
IN18
HRD
INBUF
IN19
INBUF
IN20
HA0
A
Y
AND2B
B
HOES1
HI[7:0]
DSI[15:8]
DSI[7:0]
DPNT[1:0]
DSWST
DSIW
IQ[7:0]
IQ[15:8]
CLK
HINTF
HSEL
HRD
HWR
HA0
HI[7:0]
DSI[15:8]
DSI[7:0]
HST[1:0]
DSWST
DSIW
IQ[7:0]
IQ[15:8]
CLK
HOST INTERFACE
(HINTRFA)
HO[7:0]
CIQ[7:0]
CIQ[15:8]
HST14
HCMDFL
DSPINTR
HST15
ENHD1
ENHD2
SINT
HG1
HO[7:0]
CIQ[7:0]
CIQ[15:8]
Q8
Q8
SINT
HG1
ST15
ST0
DSPINTR
RDY HRDY
ENHD1
ENHD2
D PAD
1
2
OUTBUF
3
OUTBUF
DSPINTR
4
D PAD
OUT5
DSPINT
3
4
IOPIL8 1
22 OCT 2002
A B C D
DRAWN BY:
DBS
DCBA
CSEL0
PNT0
CSEL1
PNT1
ST0
ST15
IB1
INBUF
DSIW
DSWDREG
DSIW
DSWST
PP4
PP4
PP6
PP6
CPCYC
CLKIN
IQ[15:0]
PAD Y
DSPWA
DSPWA
DSWDREG
DSWST
CPCYC
1
DSI[7:0]
IN27
INBUF
PAD Y
CS
IN28
INBUF
PAD Y
CPR-W
IN26
INBUF
PAD Y
CPSTRB
CPIS
CPSEL
R/W
STRB
IS
20CK
INBUF
PAD Y
CKBUF
CLKINT
A
B
C
D
A
B
C
IN30
YA
A
G1
Y
B
NAND3B
C
G2
AND4B
G3
AND4B
CSACC
Y
DOE1
Y
DOE2
CPSEL
R/W
CPSTRB
CPIS
CLK
2
3
DG3
LA0
LA1
DSI[7:0]
DG3
LA0
LA1
CPSEL
R/W
CPSTRB
CPIS
CLK
DSPRA
ST0
ST15
IQ[15:0]
DO[15:0]
LA0
LA1
40CK
LA0
LA1
DSPRA
F1
QN
D
DF1A
CLK
DO[15:0]
20CK
1
2
3
D
G4
A
Y
B
NAND3B
C
G5
A
B
NAND3B
4
CSACC
CQ3
C
A
G6
B
NAND4B
C
D
A B C D
DG1
F2
Y
DG2
CSACC CQ3
D
Q
DF1
CLK
Y
DG3
CLK
CQ1
F4
D
Q
CLK
DF1
IOPIL8 2
DRAWN BY:
DBS30 OCT 2002
4
DCBA
HIGH SLEW
D
HO0
GOUT
HO1
GOUT
G
D
BBDLHS
GIN
G
D
G
1
VDD
D
BBDLHS
GIN
HO2
GOUT
G
D
G
2
D
BBDLHS
GIN
G
D
HO3
GOUT
G
3
D
BBDLHS
GIN
G
E
PAD
PAD
PAD
PAD
HD0
VDD
Q
HI0
HD1
Q
HI1
HD2
Q
HI2
HD3
Q
HI3
HO4
HO5
HO6
HO7
GOUT
GOUT
GOUT
GOUT
D
G
D
BBDLHS
GIN
G
D
G
D
BBDLHS
GIN
G
D
G
D
BBDLHS
GIN
G
D
G
D
BBDLHS
GIN
G
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
PAD
HI[7:0]
PAD
PAD
PAD
HD4
Q
HI4
HD5
Q
HI5
HD6
Q
HI6
HD7
Y
Q
HI7
GND
HI BYTE TRISTATE TO
AVOID LOADING 16 BIT BUSSES
E
D
D
D
D
D
D
D
D
TRIBUFF
TRIBUFF
TRIBUFF
TRIBUFF
TRIBUFF
TRIBUFF
TRIBUFF
TRIBUFF
PAD
HD8
E
PAD
HD9
E
PAD
HD10
E
PAD
HD11
E
PAD
HD12
E
PAD
HD13
E
PAD
HD14
E
PAD
HD15
1
2
3
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
QD
Q
HG1
HO[7:0]
HOES1
4
HG1
VCC
Y
VDD
4
IOPIL8 3
24 OCT 2002 DBS
A B C D
DRAWN BY:
DCBA
DOE1
D
DO0
DOE1
DO1
GOUT
GOUT
G
D
BBDLHS
GIN
G
D
G
VDD
1
D
BBDLHS
GIN
G
DOE1
2
DO2
GOUT
D
G
D
BBDLHS
GIN
G
DOE1
D
DO3
GOUT
G
3
DG3
GOUT
GIN
4
D
BBDLHS
GIN
G
DO[7:0]
GND
D
QD
G
Q
D
BBDLHS
G
A B C D
QD
Q
QD
Q
QD
Q
QD
Q
E
HIGH SLEW
HIGH SLEW
E
HIGH SLEW
E
HIGH SLEW
E
HIGH SLEW
E
PAD
PAD
DSD0
VDD VDD VDD
Q
DSI0
PAD
DSD1
Q
DSI1
PAD
DSD2
Q
DSI2
PAD
DSD3
Q
DSI3
CPA0
GOUT
Q
LA0
DG3
DOE1
D
DO4
GOUT
G
D
BBDLHS
GIN
G
DOE1
D
DO5
GOUT
G
D
BBDLHS
GIN
GOUT
G
D
G
DOE1
DO6
D
BBDLHS
GIN
GOUT
G
D
G
DOE1
DO7
D
BBDLHS
GIN
G
DG1
DOE1
GND
D
HIGH SLEW
E
QD
PAD
HIGH SLEW
E
PAD
PAD
PAD
PAD
DSI[7:0]
DSD4
Q
DSI4
DSD5
Q
DSI5
DSD6
Q
DSI6
DSD7
Q
DSI7
DOE2
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
QD
Q
CPA1
G
Q
Q
D
BBDLHS
GIN
G
LA1
OUTBUF
D PAD
VCC
DOE2
D
DO8
GOUT
G
D
BBDLHS
GIN
G
DOE2
D
DO9
GOUT
G
D
BBDLHS
GIN
G
DOE2
D
DO10
GOUT
G
D
BBDLHS
GIN
G
DOE2
D
DO11
GOUT
G
D
BBDLHS
GIN
G
DO[15:8]
DG2
Y
VDD
CLKOUT20CK
HIGH SLEW
E
PAD
PAD
PAD
PAD
DSD8
Q
DSI8
DSD9
Q
DSI9
DSD10
Q
DSI10
DSD11
Q
DSI11
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
QD
Q
HIGH SLEW
E
QD
Q
DOE2
DO12
GOUT
DOE2
DO13
GOUT
DOE2
DO14
GOUT
DOE2
DO15
GOUT
DG2
DOE2
IOPIL8 4
HIGH SLEW
D
G
D
BBDLHS
GIN
G
D
E
PAD
PAD
DSD12
Q
DSI12
DSD13
1
QD
Q
HIGH SLEW
E
QD
G
Q
PAD
DSI13
DSD14
2
Q
D
BBDLHS
GIN
G
HIGH SLEW
D
E
QD
G
Q
PAD
DSI14
DSD15
Q
D
BBDLHS
GIN
G
HIGH SLEW
D
E
QD
G
Q
Q
D
BBDLHS
GIN
G
DSI[15:8]
DRAWN BY:
DSI15
3
4
DBS22 OCT 2002
DCBA
Q8
SINT
NAND2B
A
B
A
B
Y
OR2A
OR2A
END1
1
Y
END2
A
B
Y
DPINC
AND3
C
Y
2
3
ENHD1
DSWDREG
1
DOE1
PP4
CIQ[7:0]
CIQ[15:8]
HI[7:0]
DSI[7:0]
DSI[15:8]
RA[1:0]
2
LA[1:0]
PP6
END1
END2
CLK
DSWST
DPINC
3
Q8
CLK
DSI[1:0]
DREG
DOE1
PP4
CIQ[7:0]
CIQ[15:8]
HI[7:0]
DSI[7:0]
DSI[15:8]
RA[1:0]
LA[1:0]
PP6
END1
END2
CLK
DCNT2
SLOAD
ENABLE
ACLR
CLOCK
DATA[1:0]
DATREG
Q[1:0]
IQ[7:0]
IQ[15:8]
DPNT[1:0]
IQ[7:0]
IQ[15:8]
MXAD2
DPNT0
DPNT1
ENHD2
A
B
DATA0_[1:0]
RESULT[1:0]
DATA1_[1:0]
LA0
LA1
4
LA[1:0]
SEL0
RA[1:0]
4
IOPIL8 5
PP6
DRAWN BY:
A B C D
DBS22 OCT 2002
DCBA
REG1
EN1
1
DSIW
CLK
2
BUF2
HI[7:0]
DSI[7:0]
BUF1
YA
DSL
BUF
EN2
YA
BUF
DSLA
HI[7:0]
DSI[15:8]
REG2
EN1
S
A[7:0]
B[7:0]
EN1
S
A[7:0]
B[7:0]
DFME8
CK
Q[7:0]
DFME8
CK
Q[7:0]
CIQ[7:0]
CIQ[15:8]
DSWST
CLK
DSI[7:2]
DSWST
VDD
CLK
DSI[14:8]
REG3
REG4
ENABLE
CLOCK
DATA[5:0]
ENABLE
ACLR
CLOCK
DATA[6:0]
REG6
Q[5:0]
REG7
Q[6:0]
HST[1:0]
HST[7:2]
HST[14:8]
HST14
IQ[7:0]
HST[7:0]
IQ[15:8]
HST[15:8]
AY
TOGGLE
INV
HA0
TOGGLE LO
SELECTS [15:8], HI BYTE FIRST
DATA0_[7:0]
DATA1_[7:0]
DATA2_[7:0]
DATA3_[7:0]
SEL1
MUX4X8
RESULT[7:0]
1
HO[7:0]
SEL0
2
HICTLA
A
Y
ENHD1
ENHD2
SINT
Q8
TOGGLE
EN1
EN2
HRDY
DSPINTR
HCMDFL
RSTOG
ENHD1
ENHD2
SINT
Q8
TOGGLE
EN1
EN2
HST15
DSPINTR
HCMDFL
HST[15:8]
HOST INTERFACE
3
4
NAND2
B
(HINTRFA)
24 AUG 2001
DRAWN BY:
DBS
DSWST
DSI15
HICTLA
HST[1:0]
RSTOG
3
G1
A
4
HWR
HSEL
CLK
Y
AND2B
B
D
Q
DF1
CLK
A B C D
D
QN
DF1C
CLK
HSEL
HWR
HRD
HA0
DSIW
CLK
G2
A
NAND2
B
Y
DPNT[1:0]
RSTOG
HSEL
HWR
HRD
HA0
DSIW
CK
HG1
CLR
CLR
CLR
JKF2C
JKF2C
JKF2C
Q
CS
Q
CS
Q
CS
DCBA
LWR
INV3
AY
Q8 HCMD
INV
INV4
AY
INV
1
LRDSTQ9
2
SHWR
SHCMD
SLRDST
F13
J
CLK
K
F8
J
CLK
K
F9
J
CLK
K
INV1
CK
AY
INV
A
B
C
G2
A
B
AND2B
OA1C
Y
G1
Y
HWR
TOGGLE LO (1ST BYTE) LD HI, RD HI
F1
D
Q
DF1
CLK
F4
RSTOG
D
DFE3A
E
CLK
CLR
HCYC
CK
F2 F3
D
DF1
Q2Q1
Q
CLK
A
1CMD
TOGGLE
NAND2A
B
Q
Q8
HCYC
CK
HCYC
D0
GND
D1 D2 D3
DFM6A
S0 S1
Q1
CLK
CLR
Y
LCMD
F12
D
Q
DFE
E
CLK
HCYC
Q
VCC
Y
A
Y
AND2A
B
1CMD
HSEL
HWR
HSEL
HWR
HA0
HSEL
HRD
HA0
HCYC
CK
VDD
A
Y
AND2B
B
HCYC
CK
VDD
G7
A
B
Y
AND3B
C
HCYC
CK
VDD
G10
A
B
Y
AND3B
C
HRD HRD
HWR
HRD
HSEL
1
2
HWR
HSEL
G12
A
B
C
Y
HCYC
HCMD
C
G14
C
OR3C
CLRFLGS
A
B
Y
EN2
AOI1
A
B
Y
AOI1
INTEN
Y
EN1
A
SINT
CLRFLGS
G19
A
Y
AND2
B
B
C
HCCYC
CK
AND3
HWR
HIEN
DSIW
HWR
LOEN
DSIW
RDEN
WREN
Q8
A
B
AND3A
C
AY
INV
AND2A
A
B
Y
OR2A
A
Y
AND2A
B
A
Y
B
NAND3B
C
A
Y
NAND2B
B
LRDST
Y
HCYC
ENINTR
DSIW
TOGGLE
1CMD
1CMD
3
DPNT[1:0]
1CMD
TOGGLE
4
TOGGLE
DPNT0
DPNT1
LWR
A
B
A B C D
HIEN
HWR
Q8
LOEN
Y
SINTR
A
Y
B
NAND3
C
ENHD2
A
Y
B
NAND3
C
F6
J
CLK
ENHD1
DSPINTR
Q
JKF
K
F7
J
JKF
CLK
HCMDFL
Q
K
INV2
AY
INV
F5
D
Q
DF1
CLK
CK
DSPINTR
G21
A
2
B
2
NOR4
F10
D
Q
DF1
C
D
CLK
A
Q1
B
Q2
C
HCYC
Q9
D
Y
EBSY
OA4
HICTLA
22 OCT 2002 DBS
DRAWN BY:
Y
HRDY
CC
3
4
DSI[7:0]
DCBA
DSI0
1
DSI1
F0
D
DFE1B
E
PNT0
Q
CLK
F1
D
DFE1B
E
PNT1
Q
CLK
DSI2
DSWPNT
CLK
L1
2
3
4
R/W LR/W
DG3
CPIS
CPSTRB
CPSEL
CLK
F2
D
DFE1B
E
CLK
Q
D
DL1B
PNT2
Q
DEC2
Y0
LA0
LR/W
LA1
DECE2X4D
A
Y1
E
B
G
VCC
Y
F4
D
Q3
G6
A
B
Y
AND3B
C
A B C D
CPS
DFE3A
E
CLK
CLR
AY
INV
A
B
Y
AND3B
C
PP4
1
A
B
Y
AND3A
C
CPCYC
ADW0
ADW2
Y2
ADW3
Y3
CPCYC1
PP4
ADW2
CPCYC1
PP4
ADW3
ADW0
LR/W
CPCYC1
PP6
Q2
Q
PP6
G2
A
NAND2
B
G11
A
B
AND3
C
G12
A
B
AND3
C
A
B
AND4B
C
D
AY
INV
Y
DSWPNT
2
Y
DSIW
Y
DSWST
Y
DSWDREG
3
Q2
F5
CPS
D0 D1 D2 D3
DFM6A
S0 S1
CLK
CLR
GND
Q3
Q3
Q
VCC
Y
BUF2
BUF3
YA
CPCYC
BUF
YA
CPCYC1
BUF
4
24 OCT 2002
DSPWA
DRAWN BY:
DBS
DCBA
VCC
ST0
1
ST15
YA
CH0
BUF
YA
CH15
BUF
Y
VDD
1
DATA0_[15:0]
DATA1_[15:0]
MUX2X16
RESULT[15:0]
DO[15:0]
SEL0
2
3
CH15,VDD,GND,GND[12:1],CH0
GND[12:1]
YA
BUF
$ARRAY=12
GND
2
3
GND
Y
LA0
LA1
A
Y
OR2
B
IQSEL
IQ[15:0]
4
A B C D
DSPRA
DRAWN BY:
DBS30 OCT 2002
4
A[7:0]
DCBA
1
2
3
B[7:0]
B4B0 B1 B2 B3 B5 B6 B7
A4A0 A1 A2 A3 A5 A7
S
EN1
CK
ABS
CLK
ABS
CLK
E
DFME1A
Q
ABS
CLK
E
DFME1A
Q
ABS
CLK
E
DFME1A
Q
ABS
CLK
E
DFME1A
Q
ABS
E
DFME1A
Q
E
CLK
DFME1A
Q
Q4 Q7Q6Q5Q3Q2Q1Q0
CLK
A6
F7F6F5F4F3F2F1F0
ABS
CLK
E
DFME1A
Q
Q[7:0]
ABS
E
DFME1A
Q
1
2
3
4
A B C D
DFME8
DRAWN BY:
DBS19 NOV. 2002
4
R1
EN1R1
DSPSEL
1
HI[7:0]
DSI[7:0]
EN2R1
EN1
S
DFME8
CK
A[7:0]
Q[7:0]
B[7:0]
R2
R1[7:0]
EN1R3
DSPSEL2
HI[7:0]
DSI[7:0]
EN1
EN2R3
S
A[7:0]
B[7:0]
DFME8
CK
Q[7:0]
R1[15:8]
CLK
HI[7:0]
DSI[15:8]
CLK
HI[7:0]
DSI[15:8]
R3
2
EN1R2
DSPSEL1
EN1
S
DFME8
CK
HI[7:0]
DSI[7:0]
A[7:0]
B[7:0]
Q[7:0]
R2[7:0]
LA0
LA1
PP4
DOE1
A B
Y
AND4A
C
D
RA0
GND
R5 MUX1
EN1
S
DFME8
CK
A[7:0]
Q[7:0]
R3[7:0]
B[7:0]
R6
EN1
S
DFME8
CK
A[7:0]
Q[7:0]
R3[15:8]
B[7:0]
DSIR
S
A
Y
MDS0
MX2
B
CIQ[7:0]
R1[7:0]
R2[7:0]
R3[7:0]
CIQ[15:8]
R1[15:8]
R2[15:8]
R3[15:8]
MUX4X8
DATA0_[7:0]
DATA1_[7:0]
RESULT[7:0]
DATA2_[7:0]
DATA3_[7:0]
SEL1
MDS1 MDS0
MUX2
DATA0_[7:0]
DATA1_[7:0]
DATA2_[7:0]
DATA3_[7:0]
MUX4X8
RESULT[7:0]
DCBA
IQ[7:0]
SEL0
1
2
IQ[15:8]
R4
EN2R2
CLK
3
HI[7:0]
DSI[15:8]
EN1
S
A[7:0]
B[7:0]
DSIR
DFME8
CK
Q[7:0]
R2[15:8]
RA1
GND
S
A
Y
MDS1
MX2
B
MDS1
SEL1
SEL0
MDS0
3
Y
GND
B1
YA
BUF
B2
YA
DSPSEL1
BUF
B3
YA
DSPSEL2
BUF
LA[1:0]DSPSELPP6
RA[1:0]
END1
DECE2X4
DATA0
ENABLE
DATA1
EQ0
EQ1
EQ2
EQ3
EN1R1
EN1R2
EN1R3
DECE2X4
4
RA0
END2
RA1
DATA0
ENABLE
DATA1
EQ0
EQ1
EQ2
EQ3
EN2R1
EN2R2
EN2R3
DATREG
DRAWN BY:
4
DBS30 OCT 2002
A B C D
7 Application Notes
7.1 Design Tips
The following are recommendations for the design of circuits that utilize a PMD Motion Processor.
Serial Interface
If the serial configuration decode logic is not implemented (see section 7.2) the CP data bus should be tied high. This places the serial interface in a default configuration of 9600,n,8,1 after power on or reset.
Controlling pulse output during reset
When the motion processor is in a reset state (when the reset line is held low) or immediately after a power on, the pulse outputs can be in an unknown state, causing undesirable motor movement. It is recommended that the enable line of any motor amplifier be held in a disabled state by the host processor or some logic circuitry until communication to the motion processor is established. This can be in the form of a delay circuit on the amplifier enable line after power up, or the enable line can be ANDed with the CP reset line.
Parallel word encoder input
When using parallel word input for motor position, it is useful to also decode this information into the User I/O space. This allows the current input value to be read using the chip instruction ReadIO for diagnostic purposes.
Using a non standard system clock frequency
It is often desirable to share a common clock among several components in a design. In the case of the PMD Motion Processors it is possible to use a clock below the standard value of 20MHz. In this case all system frequencies will be reduced as a fraction of the input clock verses the standard 20MHz clock. The list below shows the affected system parameters:-
Serial baud rate
Maximum pulse rate
Timing characteristics as shown in section 3.2
Cycle time
For example, if an input clock of 17MHz is used with a serial baud rate of 9600 the following timing changes will result:-
Serial baud rate decreases to 9600 bps *17/20 = 8160 bps
Maximum step rate decreases to 50K pulses *17/20 = 42.5K pulses
Cycle time per axis increases to 102.4 µsec *20/17 = 120.48 µsec
MC3510 Technical Specifications
60
MC3510 Technical Specifications
61

7.2 RS-232 Serial Interface

The interface between the MC3510 chip and an RS-232 serial port is shown in the following figure.
Comments on Schematic
S1 and S2 encode the characteristics of the serial port such as baud rate, number of stop bits, parity, etc. The CP will read these switches during initialization, but these parameters may also be set or changed using the connected directly to the serial port of a PC without requiring a null modem cable.
SetSerialPort chipset command. The DB9 connector wired as shown can be
MC3510 Technical Specifications
62
8
7
6
5
4
3
2
1
R?
DS[0..15]
D D
C C
B B
22K
DS0 A2 DS1 A3 DS2 A4 DS3 A5 DS4 A6 DS5 A7 DS6 A8 DS7 A9 DS8 A10 DS9 A11 DS10 A12 DS11 A13 DS12 A14 DS13 A15 DS14 DS15
9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28
63 64
72 98 94
67 68 69 70
RS­CLK
58
13
47
21
40
7
24136
35
~RS
VCC
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15
POSLIM1 NEGLIM1
AXISIN1 ~HOSTINTRPT AXISOUT1
QUADA1 QUADB1 ~INDEX1 ~HOME1
50
52
VCC
VCC
VCC
VCC
VCC
VCC
VCC
~RESET CLOCKIN
3
GND
8
GND
GND
GND
14
20
GND
GND
294659617192104
37
VCC
60
6293103
121
VCC
VCC
VCC
VCC
VCC
ADDR0
VCC
ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8
ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15
~RAMSLCT
~PERIPHSLCT
~STROBE
~WRITEENBL
DIRECTION1
PULSE1
ATREST1
SRLRCV SRLXMT
SRLENABLE
I/OINTRPT
PRLENABLE
ANALOG1 ANALOG2 ANALOG3 ANALOG4 ANALOG5 ANALOG6 ANALOG7 ANALOG8
ANALOGVCC ANALOGREFHIGH ANALOGREFLOW
ANALOGGND
GND
GND
GND
GND
GND
GND
56
N/C
R/~W
W/~R
GND
113
GND
IS­R/W STRB-
A[0..15]
IS-
STRB-
U2
NOT U2
NOT
12
A9 R/W
12
U1
A0
110
A1
111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 131 129 130 4 6 1 132
105 106 107
43 44 99
53 65
74 89 75 88 76 83 77 82
84 85 86 87
GND
CP2N11
120
RS1
RSIP9
S1 1 2 3 4 5 6 7 8
SW DIP-8
U2
2 3
4 5
NAND4
VCC
1
COM
SW1 SW9
2
R1
SW2
3
R2
SW3
4
R3
SW4
5
R4
SW5
6
R5
SW6
7
R6
SW7
8
R7
SW8
9
R8
SW1
16
SW2
15
SW3
14
SW4
13
SW5
12
SW6
11
SW7
10
SW8
9
2 4 6
8 11 13 15 17
1 19
U2 1A1
1A2 1A3 1A4 2A1 2A2 2A3 2A4
1G 2G
74LS244
DS[0..15]
1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4
DS0
18
DS1
16
DS2
14
DS3
12
DS4
9
DS5
7 5
DS7
3
U2 AND U3 COULD BE IMPLEMENTED IN A PLD
1
C1 .1UF 50V
C2
SERXMIT TXD .1UF 50V
SERRCV RXD
U3
C1+
1
C1+
C1- V+
3
C1-
C2+ V-
4
C2
C2-
5
C2-
11
T1IN
10
T2IN
12
R1OUT
9
R2OUT
T1OUT T2OUT
R1IN R2IN
V+
AD232
GND
1 2 3 4 5 6 7 8
RS2
RSIP9
S2
SW DIP-8
COM
VCC
1 2
R1
SW10
3
R2
SW11
4
R3
SW12
5
R4
SW13
6
R5
SW14
7
R6
SW15
8
R7
SW16
9
R8
SW9
16
SW10
15
SW11
14
SW12
13
SW13
12
SW14
11
SW15DS6
10
SW16
9
2 4 6
8 11 13 15 17
1 19
U3 1A1
1A2 1A3 1A4 2A1 2A2 2A3 2A4
1G 2G
74LS244
DS[0..15]
1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4
DS8
18
DS9
16
DS10
14
DS11
12
DS12
9
DS13
7
DS14
5
DS15
3
VCC
C3 .1UF 50V
C5 .1UF 50V
2 6
V-
GND
C4 .1UF 50V
J1 5 9 4 8 3 7 2 6 1
CONNECTOR DB9
FEMALE DB9 WIRED
AS SHOWN WILL CONNECT TO A PC WITHOUT A DUMMY MODEM.
14 7
13 8
A A
8
7
6
5
4
3
PERFORMANCE MOTION DEVICES 55 OLD BEDFORD RD LINCOLN, MA 01773
Title
RS232 SERIAL INTERFACE
Size Document Number Rev
B
of
Date: Sheet
2
10Monday, July 07, 2003
1
B

7.3 RS 422/485 Serial Interface

The interface between the MC3510 chip and an RS-422/485 serial port is shown in the following figure.
Comments on Schematic
Use the included table to determine the jumper setup that matches the chosen configuration. If using RS485, the last CP must have its jumpers set to RS485 LAST. The DB9 connector wiring is for example only. The DB9 should be wired according to the specification that accompanies the connector to which it is attached.
For correct operation, logic should be provided that contains the start up serial configuration for the motion processor. Refer to the RS232 Serial Interface schematic for an example of the required logic.
Note that the RS485 interface cannot be used in point to point mode. It can only be used in a multi­drop configuration where the chip SrlEnable line is used to control transmit/receive operation of the serial transceiver.
Chips in a multi-drop environment should not be operated at different baud rates. This will result in communication problems.
MC3510 Technical Specifications
64
8
D D
7
6
5
JP3
1
3 2
JMP3
4
TERMINATE TRANSMITTX-RX +
TXT
JP1
1
3 2
3
2
1
JMP3
VCC
R3
4.7K
GND
5
DI
4
DE
3
RE
2
RO
SRLXMT SRLRCV SRLENABLE
C C
GND
VCC
C1
+
4.7UF 10V TANT
C2
.1UF 50V CER
U1
14
9
Y
VCC
10
Z
12
A
11
B
GND
GND
MAX491
7
6
TX+
TX-
RX+
RX-
R2 120
JP4
1
3 2
RXT
JMP3
B B
TX-RX -
R1 120
JP2
1
JMP3
TERMINATE RECEIVE
P1 5 9 4 8 3 7 2 6 1
CONNECTOR DB9
RT ANGLE MALE
3 2
TO HOST
COM TYPE JP1 JP2 JP3 JP4
RS422
RS485
RS485 LAST
1-2 1-2 2-3 2-3
2-3 2-3 1-2 1-2
1-2 2-3 1-2 1-2
NOTE:RS422 IS CAPABLE OF FULL DUPLEX AND USES 2 PAIRS.
RS485 IS HALF-DUPLEX ON 1 PAIR AND MAY BE DAISY CHAINED
A A
THE CP USES RS485. A SINGLE CP MAY COMMUNICATE WITH AN
RS422 HOST AS SHOWN IN THE TABLE.
A SINGLE PAIR MAY BE WIRED TO EITHER P1-1,9 OR P1-2,3
FOR RS485.
8
7
PERFORMANCE MOTION DEVICES 55 OLD BEDFORD RD LINCOLN, MA 01773
Title
RS422/485 Interface
Size Document Number Rev
B
6
5
4
3
Date: Sheet
2
11Thursday, April 11, 2002
1
A
of
7.4 RAM Interface
The following schematic shows an interface circuit between the MC3510 and external ram.
Comments on Schematic
The CP is capable of directly addressing 32K words of 16-bit memory. It will also use a 16 bit paging register to address up to 32K word pages. The schematic shows the paging and addressing for 128KB RAM chips, i.e. 4 pages per RAM chip. The page address decoding is shown for only 6 of the 16 possible paging bits. The decoding time from W/R and DS- to the memory output must not exceed 18 ns. for a read with no wait states. The writes provide 25 extra ns access time for W/R and DS- to reverse the CP data bus.
MC3510 Technical Specifications
66
8
7
6
5
4
3
2
1
D[0..15]
D D
C C
B B
A A
R?
VCC
121
VCC
VCC
VCC
VCC
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8
ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15
N/C
~RAMSLCT
~PERIPHSLCT
R/~W
~STROBE
~WRITEENBL
W/~R
DIRECTION1
PULSE1
ATREST1
SRLRCV SRLXMT
SRLENABLE
I/OINTRPT
PRLENABLE
ANALOG1 ANALOG2 ANALOG3 ANALOG4 ANALOG5 ANALOG6 ANALOG7 ANALOG8
ANALOGVCC
ANALOGGND
GND
GND
GND
GND
GND
113
7
VCC
U?
A0 D1 MPG1 A6 D5 A6 D13
110
A1 D2 CS1 A7 D6 A7 D14
111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 131 129 130 4 6 1 132
105 106 107
D0 MPG0 A5 D4 A5 D12
IS-
D9
R/W
D10
D11 WE- D12 W/R D13
D14
D15
WE-
PGR-
U2
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18
D8
11
CLK
1
G 74LS377
U2
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18
D8
11
CLK
1
G 74LS377
2
Q1
5
Q2
6
Q3
9
Q4
12
Q5
15
Q6
16
Q7
19
Q8
2
Q1
5
Q2
6
Q3
9
Q4
12
Q5
15
Q6
16
Q7
19
Q8
NOTE: POS139 IS A STANDARD 139 WITH INVERTED OUTPUTS
U2A 2 3
1
14 13
15
NOTE:THE CRITICAL DECODE AND MEMORY
ACCESS TIME IS DURING READ, THE REQUIRED ACCESS TIME IS 18 NS. FROM DS- LOW. AS ILLUSTRATED THERE IS ~ 100NS. TO ACCOMPLISH THE DECODING FROM PAGE REG WRITE TO MEMORY READ OR WRITE. DECODING WILL HAVE TO BE CAREFULLY DONE ON MEMORIES WITH A SINGLE CHIP SELECT.
A
B
G
POS139
U2B
A
B
G
POS139
4
Y0
5
Y1
6
Y2
7
Y3
12
Y0
11
Y1
10
Y2
9
Y3
PAGE REGISTER UP TO 16 BITS
GND
120
GND
43 44 99
53 65
74 89 75 88 76 83 77 82
84 85 86 87
CP2N11
GND
U2
A13 A4 D3 A4 D11
IS- PGR- A5 D4 A5 D12 R/W A6 D5 A6 D13
NOT
6
U2
12
2 3 4
1
OR3
5
4
22K
13
7
24136
35
~RS
VCC
VCC
D0 A2 D3 CS2 A8 D7 A8 D15 D1 A3 D4 CS3 A9 A9 D2 A4 D5 CS4 A10 A10 D3 A5 D6 A11 A11 D4 A6 D7 A12 A12 D5 A7 A13 A13 D6 A8 WE- A14 A14 D7 A9 PGR- MPG0 MPG0 D8 A10 CS5 MPG1 MPG1 D9 A11 CS6 D10 A12 CS7 DS- DS­D11 A13 GND CS8 CS1 CS1 D12 A14 D13 WE- WE­D14 W/R W/R D15 DS- D8
RS­CLK
VCC
9
DATA0
10
DATA1
11
DATA2
12
DATA3
15
DATA4
16
DATA5
17
DATA6
18
DATA7
19
DATA8
22
DATA9
23
DATA10
24
DATA11
25
DATA12
26
DATA13
27
DATA14
28
DATA15
63
POSLIM1
64
NEGLIM1
72 98
AXISIN1 ~HOSTINTRPT
94
AXISOUT1
67
QUADA1
68
QUADB1
69
~INDEX1
70
~HOME1
~RESET
58
CLOCKIN
GND
3
8
47
21
40
50
VCC
VCC
VCC
VCC
GND
GND
GND
GND
14
20
294659617192104
8
37
60
6293103
52
VCC
VCC
VCC
ANALOGREFHIGH ANALOGREFLOW
GND
GND
GND
56
A0 A0 A1 D0 A1 D8 A2 D1 A2 D9 A3 D2 A3 D10 A4 D3 A4 D11
A0 A0 A1 D0 A1 D8 A2 D1 A2 D9 A3 D2 A3 D10
A7 D6 A7 D14 A8 D7 A8 D15 A9 A9 A10 A10 A11 A11 A12 A12 A13 A13 A14 A14 MPG0 MPG0 MPG1 MPG1
DS- DS­CS2 CS2
WE- WE­W/R W/R
12 11 10
27 26 23 25
28 31
22 30
29 24
A[0..14]
12 11 10
27 26 23 25
28 31
22 30
29 24
9 8 7 6 5
4 3 2
9 8 7 6 5
4 3 2
U? A0
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
CE1 CE2
WE OE
MCM6226
U? A0
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
CE1 CE2
WE OE
MCM6226
U?
12
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
13 14 15 17 18 19 20 21
11 10
27 26 23 25
28 31
22 30
29 24
9 8 7 6 5
4 3 2
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
CE1 CE2
WE OE
MCM6226
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
13 14 15 17 18 19 20 21
D[0..15]
U?
12
13
DQ0
14
DQ1
15
DQ2
17
DQ3
18
DQ4
19
DQ5
20
DQ6
21
DQ7
PERFORMANCE MOTION DEVICES 55 OLD BEDFORD RD LINCOLN, MA 01773
Title
RAM INTERFACE
Size Document Number Rev
B
3
Date: Sheet of
2
11 10
27 26 23 25
28 31
22 30
29 24
9 8 7 6 5
4 3 2
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
CE1 CE2
WE OE
MCM6226
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
13 14 15 17 18 19 20 21
1 0Saturday, December 07, 2002
B
1
A[0..14]
7.5 User-defined I/O
The interface between the MC3510 chip and 16 bits of user output and 16 bits of user input is shown in the following figure.
Comments on Schematic
The schematic implements 1 word of user output registered in the 74LS377’s and 1 word of user inputs read via the 244’s. The schematic decodes the low 3 bits of the address to 8 possible UIO addresses UIO0 through UIO7. Registers and buffers are shown for only UIO0, but the implementation shown may be easily extended. The lower 8 address bits may be decoded to provide up to 256 user output words and 256 user input words of 16 bits.
MC3510 Technical Specifications
68
8
7
6
5
4
3
2
1
D[0..15]
A[0..14]
D D
C C
B B
A A
R?
22K
D0 A2 D3 UO0-3 UIO UIO5
9
D1 A3 D4 UO0-4 A3 UIO6
10
D2 A4 D5 UO0-5 A4 UIO7
11
D3 A5 D6 UO0-6
12
D4 A6 D7 UO0-7
15
D5 A7
16
D6 A8 WE-
17
D7 A9 UIO0
18
D8 A10
19
D9 A11
22
D10 A12
23
D11 A13
24
D12 A14
25
D13
26
D14
27
D15 D8 UO0-8 A12 A12n
28
63 64
72 98 94
67 68 69 70
RS- D13 UI0-13 CLK D15 UI0-15
58
13
47
21
40
7
24136
35
~RS
VCC
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15
POSLIM1 NEGLIM1
AXISIN1 ~HOSTINTRPT AXISOUT1
QUADA1 QUADB1 ~INDEX1 ~HOME1
VCC
VCC
VCC
VCC
VCC
VCC
50
VCC
~RESET CLOCKIN
GND
GND
GND
GND
14
20
294659617192104
3
8
GND
GND
37
60
6293103
121
52
VCC
VCC
VCC
VCC
VCC
VCC
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8
ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15
~RAMSLCT
~PERIPHSLCT
~STROBE
~WRITEENBL
DIRECTION1
PULSE1
ATREST1
SRLRCV SRLXMT
SRLENABLE
I/OINTRPT
PRLENABLE
ANALOG1 ANALOG2 ANALOG3 ANALOG4 ANALOG5 ANALOG6 ANALOG7 ANALOG8
ANALOGVCC
ANALOGREFHIGH
ANALOGREFLOW
ANALOGGND
GND
GND
GND
GND
GND
GND
56
VCC
U?
A0 D1 UO0-1 UIO3
110
A1 D2 UO0-2 UIO4
111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 131
N/C
129 130 4
R/~W
6 1 132
W/~R
105 106 107
43 44 99
53 65
74 89 75 88 76 83 77 82
84 85 86 87
D0 UO0-0 A2 UIO2
IS-
D9 UO0-9 UIO D10 UO0-10 IS-
D11 UO0-11 WE- D12 UO0-12 W/R D13 UO0-13
D14 UO0-14
D15 UO0-15
WE-
UIO0 A12n
D0 UI0-0
D1 UI0-1
D2 UI0-2
D3 UI0-3
D4 UI0-4
D5 UI0-5
D6 UI0-6
D7 UI0-7
D8 UI0-8
D9 UI0-9
D10 UI0-10
D11 UI0-11
D12 UI0-12
D14 UI0-14
GND
GND
GND
CP2N11
113
120
GND
U2
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18
D8
11
CLK
1
G 74LS377
U2
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18
D8
11
CLK
1
G 74LS377
U2
18
1Y1
16
1Y2
14
1Y3
12
1Y4
9
2Y1
7
2Y2
5
2Y3
3
2Y4
244 U2
18
1Y1
16
1Y2
14
1Y3
12
1Y4
9
2Y1
7
2Y2
5
2Y3
3
2Y4
2
Q1
5
Q2
6
Q3
9
Q4
12
Q5
15
Q6
16
Q7
19
Q8
USER OUTPUTS
2
Q1
5
Q2
6
Q3
9
Q4
12
Q5
15
Q6
16
Q7
19
Q8
2
1A1
4
1A2
6
1A3
8
1A4
11
2A1
13
2A2
15
2A3
17
2A4
UI0n
1
1G
UI0n
19
1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4
2G
2 4 6 8 11 13 15 17
UI0n
1
1G
UI0n
19
2G
USER INPUTS
A0 UIO0 A1 UIO1
1 2 3
6 4 5
U2
NOT
2
IS- W/R UI0n
3
THE LOGIC LABELED U2 MAY BE IMPLEMENTED IN
A CPLD. THE LOWER 8 ADDRESS BITS, A0-A8, MAY BE
DECODED TO PROVIDE 256 16 BIT USER INPUTS
AND 256 USER OUTPUTS.
U2
OR2
U2 A
B C
G1 G2A G2B
138
15
Y0
14
Y1
13
Y2
12
Y3
11
Y4
10
Y5
9
Y6
7
Y7
12
2 3
UIOn
1
UIO0
244
8
7
6
5
4
3
U2
NOR2
1
U2 2 3 4
1
OR3
PERFORMANCE MOTION DEVICES 55 OLD BEDFORD RD LINCOLN, MA 01773
Title
USER I/O
Size Document Number Rev
B
Date: Sheet of
2
1 0Saturday, December 07, 2002
D
1

7.6 12-bit A/D Interface

The following schematic shows a typical interface circuit between the MC3510 and a quad 12 bit 2’s complement A/D converter used as a position input device. Any single channel A/D can also be used provided it meets the interface timing requirements.
Comments on Schematic
The A/D converter samples the 2’s complement digital words. DACRD- is used to perform the read and is also used to load the counter to FFh. The counter will be reloaded for each read and will not count significantly between reads. The counter will therefore start counting down after the last
read and will generate the cvt- pulse after 12.75 µsec. The conversions will take approximately 35 µsec, and the data will be available for the next set of reads after 50 µsec. The 12 bit words from the
A/D are extended to 16 bits with the 74LS244.
MC3510 Technical Specifications
70
8
R?
DS0 DS1 DS2 DS3 DS4 DS5 DS6 DS7 DS8 DS9 DS10 DS11 DS12 DS13 DS14 DS15
RS­CLK
22K
9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28
63 64
72 98 94
67 68 69 70
58
13
47
21
40
7
24136
35
~RS
VCC
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15
POSLIM1 NEGLIM1
AXISIN1 ~HOSTINTRPT AXISOUT1
QUADA1 QUADB1 ~INDEX1 ~HOME1
VCC
VCC
VCC
VCC
VCC
50
VCC
~RESET CLOCKIN
GND
GND
GND
GND
14
20
3
8
GND
294659617192104
37
DS[0..15]
D D
C C
B B
60
6293103
52
VCC
VCC
VCC
VCC
VCC
VCC
~RAMSLCT
~PERIPHSLCT
~STROBE
~WRITEENBL
DIRECTION1
ATREST1
SRLRCV SRLXMT
SRLENABLE
I/OINTRPT
PRLENABLE
ANALOG1 ANALOG2 ANALOG3 ANALOG4 ANALOG5 ANALOG6 ANALOG7 ANALOG8
ANALOGVCC ANALOGREFHIGH ANALOGREFLOW
ANALOGGND
GND
GND
GND
GND
GND
GND
56
7
VCC
121
VCC
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8
ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15
N/C
R/~W
W/~R
PULSE1
GND
GND
113
GND
120
GND
U1
110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 131 129 130 4 6 1 132
105 106 107
43 44 99
53 65
74 89 75 88 76 83 77 82
84 85 86 87
CP2N11
6
A[0..15]
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
NOTE:FS INPUTS ARE +- 10V
IS­STRB­W/R
A11
U2
12
NOT
VCC
U2
3
A
QA
4
B
QB
5
C
QC
6
D
QD
CLK CLK DACRD- DACRD­GND
ENCNT-
RCO
2
CLK
9
LOAD
1
U/D
10
ENT
7
ENP 74ALS169
DACRD- WILL LOAD THE COUNTER TO 255.
12.8 USEC. AFTER THE LAST DACRD­THE COUNTER WILL REACH 0 AND START THE NEXT CONVERSION. THE INPUT WILL BE CONVERTED IN 35 USEC. READY FOR THE NEXT READ 50 USEC LATER.
NOTE:THE LOGIC LABELED U2 MAY BE IMPLEMENTEDIN A PLD.
5
4
3
2
1
VCC
DS11
DS[0..15]
2 4 6
8 11 13 15 17
1 19
U2 1A1
1A2 1A3 1A4 2A1 2A2 2A3 2A4
1G 2G
74LS244
DS15
18
1Y1
DS14
16
1Y2
DS13
14
1Y3
DS12
12
1Y4
9
2Y1
7
2Y2
5
2Y3
3
2Y4
GND
DB11 DB10
U2 DFF2
CLK
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
U?
DS11
10
DS10
11
DS9
12
DS8
13
DS7
15
DS6
16
DS5
17
DS4
18
DS3
19
DS2
20
DS1
21
DS0
22 4
INT
NOTE:SIGN EXTENTION FOR 2'S COMPLEMENT
AD7874
12
QD
CL
4
3
9
POS1
POS2
POS3
POS4
CVT- DACRD-
DACRD-
U2
2 3
4 5
OR4
1
27
28
24 25
1
2
5 6 7
8
VIN1
VIN2
VIN3
VIN4
CONVST RD CS
REFIN REFOUT CLK
VSS
VDD
AGND
VDD
DGND
262314
-5VA
VCC AGND
10
3 4 5 6
2 9 1
7
U2 A
B C D
CLK LOAD U/D ENT ENP
74ALS169
RCO
14
QA
13
QB
12
QC
11
QD
CVT- ENCNT-
15
U2
NOT
12
3
CLK
14 13 12 11 15
GND
DACRD-
GND
A A
8
7
6
5
4
3
PERFORMANCE MOTION DEVICES 55 OLD BEDFORD RD LINCOLN, MA 01773
Title
12 BIT A/D IN
Size Document Number Rev
B
Date: Sheet of
2
1 0Saturday, December 07, 2002
1
A

7.7 16-bit A/D Input

The interface between the MC3510 chip and a 16-bit A/D converter as a parallel input position device is shown in the following figure.
Comments on Schematic
The schematic shows a 16 bit A/D used to provide parallel position input to axis 1. The 374 registers are required on the output of the A/D converters to make the 68-nanosecond access time of the CP. The worst-case timing of the A/D’s specify 83 nanoseconds for data on the bus and 83 nanoseconds from data to tri-state on the bus. Each time the data is read the 169 counter is set to 703 decimal. This provides a 35.2-microsecond delay before the next conversion. With a 10­microsecond conversion time the data will be available for the next set of reads after 50 microseconds. The delay is used to provide a position sample close to the actual position.
MC3510 Technical Specifications
72
8
R?
DS[0..15]
D D
C C
B B
22K
DS0 A2 DS1 A3 DS2 A4 DS3 A5 AIN1 DS4 A6 DS5 A7 DS6 A8 DS7 A9 DS8 A10 DS9 A11 DS10 A12 DS11 A13 DS12 A14 DS13 A15 CVT­DS14 DS15 GND
9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28
63 64
72 98 94
67 68 69 70
RS­CLK
58
13
47
21
40
7
24136
35
~RS
VCC
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15
POSLIM1 NEGLIM1
AXISIN1 ~HOSTINTRPT AXISOUT1
QUADA1 QUADB1 ~INDEX1 ~HOME1
VCC
VCC
VCC
VCC
VCC
50
VCC
~RESET CLOCKIN
GND
GND
GND
GND
14
20
3
8
GND
294659617192104
37
60
6293103
52
VCC
VCC
VCC
VCC
VCC
VCC
ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15
~RAMSLCT
~PERIPHSLCT
~STROBE
~WRITEENBL
DIRECTION1
ATREST1
SRLRCV SRLXMT
SRLENABLE
I/OINTRPT
PRLENABLE
ANALOG1 ANALOG2 ANALOG3 ANALOG4 ANALOG5 ANALOG6 ANALOG7 ANALOG8
ANALOGVCC ANALOGREFHIGH ANALOGREFLOW
ANALOGGND
GND
GND
GND
GND
GND
GND
56
7
VCC
121
VCC
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9
N/C
R/~W
W/~R
PULSE1
GND
GND
113
GND
6
U1
110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 131 129 130 4 6 1 132
105 106 107
A[0..15]
A0 A1
IS­STRB- DACRD­W/R A11n
2 3
4 5
U2
A11 A11n AGND
NOT
43 44 99
53 65
74 89 75 88 76 83 77 82
84 85 86 87
GND
CP2N11
120
U2
1
OR4
12
NOTE:THE LOGIC LABELED U2 MAY
BE IMPLEMENTEDIN A PLD.
5
NOTE:FS INPUTS ARE +- 10V
4
R1
200
R2
33.2
C1
2.2UF
C1
2.2UF
1
3
4 25 24 23
3
+5A VCC
27
VANA
VIN
REF CAP CS R/C BYTE
AGND1
2514 28
AGND2
DGND VCC
D15 D14 D13 D12 D11 D10
BUSY
2
U2
3
D0
4
D1
7
U3
6 7 8 9 10 11 12
D9
13
D8
15
D7
16
D6
17
D5
18
D4
19
D3
20
D2
21
D1
22
D0
26
AD976
DACRD-
D2
8
D3
13
D4
14
D5
17
D6
18
D7
1
OC
11
CLK 374
U2
3
D0
4
D1
7
D2
8
D3
13
D4
14
D5
17
D6
18
D7
1
OC
11
CLK 374
DS[0..15]
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
1
2 5 6 9 12 15 16 19
2 5 6 9 12 15 16 19
GND
SEE ANALOG DEVICES SPECIFICATIONS FOR ADITIONAL INFORMATION AND POWER BYPASSING.
GND
VCC VCC VCC
U2
3
A
4
B
5
10
8
6 2
9 1
7
C D
CLK LOAD U/D ENT ENP
74ALS169
A A
CLK CLK CLK DACRD- DACRD- DACRD- CLK GND GND GND
ENCNT- DACRD-
RCO
14
QA
13
QB
12
QC
11
QD
15
10
7
3 4 5 6
2 9 1
7
U2 A
B C D
CLK LOAD U/D ENT ENP
74ALS169
RCO
14
QA
13
QB
12
QC
GND
11
QD
15
U2
3
A
4
B
5
C
6
D
RCO
2
CLK
9
LOAD
1
U/D
10
ENT
7
ENP 74ALS169
6
CVT-
14
QA
13
QB
12
QC
11
QD
15
U2
NOT
5
U2 DFF2
12
3
CLK
4
ENCNT-
12
QD
CL
DACRD- WILL LOAD THE COUNTER TO 700.
38.4 USEC. AFTER THE DACRD­THE COUNTER WILL REACH 0 AND START THE NEXT CONVERSION. THE INPUT WILL BE CONVERTED IN 10 USEC. READY FOR THE NEXT READ AFTER 50 USEC.
4
PERFORMANCE MOTION DEVICES 55 OLD BEDFORD RD LINCOLN, MA 01773
Title
16 BIT A/D INPUT
Size Document Number Rev
B
3
Date: Sheet of
2
1 1Saturday, December 07, 2002
A
1

7.8 External Gating Logic Index

A typical circuit for gating the Index signal with the encoder A & B channels is shown in the following schematic.
Comments on Schematic
In order for proper operation of the Index signal when used for position capture or phase correction, the signal must be gated with the A & B encoder channels to ensure that this signal is only active when all three signals are LOW. The motion processor does not perform this gating internally.
MC3510 Technical Specifications
74
5
4
3
2
1
D D
C C
B B
QUADA1 QUADB1 INDEX1
U3 2 3 4
1
OR3
A A
5
4
QUADA1 QUADB1
HOME1
INDX1
R?
22K
9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28
63 64
72 98 94
67 68 69 70
58
13
47
21
40
7
24136
35
~RS
VCC
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15
POSLIM1 NEGLIM1
AXISIN1 ~HOSTINTRPT AXISOUT1
QUADA1 QUADB1 ~INDEX1 ~HOME1
VCC
VCC
VCC
VCC
VCC
VCC
50
VCC
~RESET CLOCKIN
GND
GND
GND
GND
14
20
294659617192104
3
8
GND
GND
37
60
6293103
121
52
VCC
VCC
VCC
VCC
VCC
VCC
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8
ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15
~RAMSLCT
~PERIPHSLCT
~STROBE
~WRITEENBL
DIRECTION1
PULSE1
ATREST1
SRLRCV SRLXMT
SRLENABLE
I/OINTRPT
PRLENABLE
ANALOG1 ANALOG2 ANALOG3 ANALOG4 ANALOG5 ANALOG6 ANALOG7 ANALOG8
ANALOGVCC
ANALOGREFHIGH
ANALOGREFLOW
ANALOGGND
GND
GND
GND
GND
GND
GND
56
3
VCC
R/~W
W/~R
GND
N/C
GND
113
GND
120
U1
110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128 131 129 130 4 6 1 132
105 106 107
43 44 99
53 65
74 89 75 88 76 83 77 82
84 85 86 87
CP24N11
GND
PERFORMANCE MOTION DEVICES 55 OLD BEDFORD RD LINCOLN, MA 01773
Title
EXTERNAL GATING LOGIC INDEX
Size Document Number Rev
B
2
Date: Sheet of
1 1Saturday, December 07, 2002
1
A
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