PMD MC3410 Datasheet

Performance Motion Devices, Inc.
55 Old Bedford Road
Lincoln, MA 01773
Pilot™ Motion Processor
MC3410 Single Chip
Technical Specifications
Revision 1.5, July 2003
NOTICE
This document contains proprietary and confidential information of Performance Motion Devices, Inc., and is protected by federal copyright law. The contents of this document may not be disclosed to third parties, translated, copied, or duplicated in any form, in whole or in part, without the express written permission of PMD.
The information contained in this document is subject to change without notice. No part of this document may be reproduced or transmitted in any form, by any means, electronic or mechanical, for any purpose, without the express written permission of PMD.
Copyright 2000 by Performance Motion Devices, Inc. Navigator, Pilot and C-Motion are trademarks of Performance Motion Devices, Inc
MC3410 Technical Specifications
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Warranty
PMD warrants performance of its products to the specifications applicable at the time of sale in accordance with PMD's standard warranty. Testing and other quality control techniques are utilized to the extent PMD deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
Performance Motion Devices, Inc. (PMD) reserves the right to make changes to its products or to discontinue any product or service without notice, and advises customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
Safety Notice
Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage. Products are not designed, authorized, or warranted to be suitable for use in life support devices or systems or other critical applications. Inclusion of PMD products in such applications is understood to be fully at the customer's risk.
In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent procedural hazards.
Disclaimer
PMD assumes no liability for applications assistance or customer product design. PMD does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of PMD covering or relating to any combination, machine, or process in which such products or services might be or are used. PMD's publication of information regarding any third party's products or services does not constitute PMD's approval, warranty or endorsement thereof.
MC3410 Technical Specifications
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MC3410 Technical Specifications
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Related Documents
Pilot Motion Processor User’s Guide (MC3000UG)
How to set up and use all members of the Pilot Motion Processor family.
Pilot Motion Processor Programmer’s Reference (MC3000PR)
Descriptions of all Pilot Motion Processor commands, with coding syntax and examples, listed alphabetically for quick reference.
Pilot Motion Processor Technical Specifications
These booklets contain physical and electrical characteristics, timing diagrams, pinouts and pin descriptions of each:
MC3110, for brushed servo motion control (MC3110TS)
MC3310, for brushless servo motion control (MC3310TS)
MC3410, for microstepping motion control (MC3410TS)
MC3510, for stepper motion control (MC3510TS)
Pilot Motion Processor Developer’s Kit Manual (DK3000M)
How to install and configure the DK3410 developer’s kit PC board.
MC3410 Technical Specifications
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MC3410 Technical Specifications
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Table of Contents
Warranty...................................................................................................................................................... iii
Safety Notice ................................................................................................................................................iii
Disclaimer.....................................................................................................................................................iii
Related Documents....................................................................................................................................... v
Table of Contents........................................................................................................................................ vii
1 The Pilot Family ........................................................................................................................................ 9
2 Functional Characteristics...................................................................................................................... 11
2.1 Configurations, parameters, and performance.............................................................................. 11
2.2 Physical characteristics and mounting dimensions....................................................................... 13
2.3 Environmental and electrical ratings............................................................................................14
2.4 System configuration.................................................................................................................... 14
2.5 Peripheral device address mapping...............................................................................................15
3 Electrical Characteristics........................................................................................................................ 16
3.1 DC characteristics......................................................................................................................... 16
3.2 AC characteristics......................................................................................................................... 16
4 I/O Timing Diagrams..............................................................................................................................18
4.1 Clock ............................................................................................................................................ 18
4.2 Quadrature encoder input.............................................................................................................18
4.3 Reset............................................................................................................................................. 18
4.4 Host interface, 8/16 mode (requires external logic device).......................................................... 19
4.4.1 Instruction write, 8/16 mode................................................................................................. 19
4.4.2 Data write, 8/16 mode...........................................................................................................19
4.4.3 Data read, 8/16 mode............................................................................................................20
4.4.4 Status read, 8/16 mode..........................................................................................................20
4.5 Host interface, 16/16 mode (requires external logic device) ........................................................ 21
4.5.1 Instruction write, 16/16 mode............................................................................................... 21
4.5.2 Data write, 16/16 mode......................................................................................................... 21
4.5.3 Data read, 16/16 mode.......................................................................................................... 22
4.5.4 Status read, 16/16 mode........................................................................................................ 22
4.6 External memory timing............................................................................................................... 23
4.6.1 External memory read........................................................................................................... 23
4.6.2 External memory write......................................................................................................... 23
4.7 Peripheral device timing............................................................................................................... 24
4.7.1 Peripheral device read........................................................................................................... 24
4.7.2 Peripheral device write.........................................................................................................24
5 Pinouts and Pin Descriptions.................................................................................................................. 25
5.1 Pinouts for MC3410..................................................................................................................... 25
5.2 CP chip pin description table........................................................................................................ 26
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6 Parallel Communication......................................................................................................................... 30
6.1 Host interface pin description table.............................................................................................. 30
6.2 16-bit Host Interface (IOPIL16)................................................................................................... 32
6.3 8-bit Host Interface (IOPIL8)....................................................................................................... 46
7 Application Notes..................................................................................................................................... 62
7.1 Design Tips................................................................................................................................... 62
7.2 RS-232 Serial Interface ................................................................................................................ 64
7.3 RS 422/485 Serial Interface.......................................................................................................... 66
7.4 PWM Motor Interface .................................................................................................................. 68
7.5 12-bit Parallel DAC Interface....................................................................................................... 70
7.6 16-bit Serial DAC Interface.......................................................................................................... 72
7.7 RAM Interface.............................................................................................................................. 74
7.8 User-defined I/O........................................................................................................................... 76
7.9 12-bit A/D Interface...................................................................................................................... 78
7.10 16-bit A/D Input........................................................................................................................... 80
7.11 External Gating Logic Index ........................................................................................................ 82
MC3410 Technical Specifications
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1 The Pilot Family
MC3110 MC3310 MC3410 MC3510
Number of axes
1 1 1 1
Motor type supported
Brushed servo
Brushless servo Stepping Stepping
Output format
Brushed servo
(single phase)
Commutated (6-
step or sinusoidal)
Microstepping Pulse and Direction
Incremental encoder input
Parallel word device input
Parallel communication
1
1 1 1
Serial communication
S-curve profiling
On-the-fly changes
Directional limit switches
Programmable bit output
Software-invertable signals
PID servo control
- -
Feedforward (accel & vel)
- -
Derivative sampling time
- -
Data trace/diagnostics
PWM output
-
Pulse & direction output
- - -
Index & Home signals
Motion error detection
(with encoder) (with encoder)
Axis settled indicator
(with encoder) (with encoder)
DAC-compatible output
-
Position capture
Analog input
User-defined I/O
External RAM support
Multi-chip synchronization
(MC3113) (MC3313) (MC3413)
-
Chip part numbers
MC3110 MC3310 MC3410 MC3510
Developer's Kit p/n's:
DK3110 DK3310 DK3410 DK3510
1
Parallel communication is available via an additional logic device
Introduction
This manual describes the operational characteristics of the MC3410 Motion Processor from PMD. This device is a member of the MC3000 family of single-chip, single-axis motion processors.
MC3410 Technical Specifications
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Each device of the MC3000 family is a complete chip-based motion processor providing trajectory generation and related motion control functions for one axis including servo loop closure or on­board commutation where appropriate. This family of products provides a software-compatible selection of dedicated motion processors that can handle a large variety of system configurations.
The chip architecture not only makes it ideal for the task of motion control, it allows for similarities in software commands, so software written for one motor type can be re-used if the motor type is changed.
Pilot Family Summary
MC3110 – This single-chip, single-axis motion processor outputs motor commands in either Sign/Magnitude PWM or DAC-compatible format for use with brushed servo motors, or with brushless servo motors having external commutation.
MC3310 – This single-chip, single-axis motion processor outputs sinusoidally commutated motor signals appropriate for driving brushless motors. Depending on the motor type, the output is a two­phase or three-phase signal in either PWM or DAC-compatible format.
MC3410 – This single-chip, single-axis motion processor outputs microstepping signals for stepping motors. Two phased signals per axis are generated in either PWM or DAC-compatible format.
MC3510 – This single-chip, single-axis motion processor outputs pulse and direction signals for stepping motor systems.
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2 Functional Characteristics
2.1 Configurations, parameters, and performance
Configuration
Single axis, single chip.
Operating modes
Open loop (motor command is driven from output of trajectory generator and microstep generator, encoder input used for stall detection)
Communication modes
8/16 parallel (8 bit external parallel bus with 16 bit internal command word size) 16/16 parallel (16 bit external parallel bus with 16 bit internal command word
size) Point to point asynchronous serial Multi-drop asynchronous serial
Serial port baud rate range
1,200 baud to 416,667 baud
Position range
-2,147,483,648 to +2,147,483,647 counts
Velocity range
-32,768 to +32,767 counts/sample with a resolution of 1/65,536 counts/sample
Acceleration/ deceleration ranges
-32,768 to +32,767 counts/sample
2
with a resolution of 1/65,536 counts/sample2
Jerk range
0 to ½ counts/sample
3
, with a resolution of 1/4,294,967,296 counts/sample3
Profile modes
S-curve point-to-point (Velocity, acceleration, jerk, and position parameters) Trapezoidal point-to-point (Velocity, acceleration, deceleration, and position
parameters) Velocity-contouring (Velocity, acceleration, and deceleration parameters)
Filter modes
Scalable PID + Velocity feedforward + Acceleration feedforward + Bias. Also includes integration limit, settable derivative sampling time, and output motor command limiting
Filter parameter resolution
16 bits
Position error tracking
Motion error window (allows axis to be stopped upon exceeding programmable window)
Tracking window (allows flag to be set if axis exceeds a programmable position window)
Axis settled (allows flag to be set if axis exceeds a programmable position window for a programmable amount of time after trajectory motion is compete)
Motor output modes
PWM (80 kHz, 8-bit*) DAC (16 bits)
Commutation rate
20 kHz
Microstepping waveform
Sinusoidal
Number of microsteps per full step
Programmable 1 to 256
Maximum encoder rate
Incremental (up to 5 million counts/sec) Parallel-word (up to 160 million counts/sec)
Parallel encoder word size
16 bits
Parallel encoder read rate
20 kHz (reads all axes every 50 µsec)
Cycle loop timing range
153.6 µsec to 32.767 milliseconds
Minimum cycle loop time
153.6 µsec
Limit switches
2 per axis: one for each direction of travel
Position-capture triggers
2 per axis: index and home signals
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Other digital signals
1xAxisIn, 1xAxisOut
Software-invertable signals
Index, Home, AxisIn, AxisOut, PositiveLimit, NegativeLimit (all individually programmable)
Analog input
8 10-bit analog inputs
User defined discrete I/O
256 16-bit wide user defined I/O
RAM/external memory support
65,536 blocks of 32,768 16-bit words per block. Total accessible memory is 2,147,483,648 16 bit words
Trace modes
one-time continuous
Max. number of trace variables
4
Number of traceable variables
27
Number of host instructions
116
* The MC3410 is also available with 20 kHz, 10-bit PWM output. Please contact PMD for information.
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2.2 Physical characteristics and mounting dimensions
All dimensions are in inches (with millimeters in brackets).
Dimension Minimum
(inches)
Maximum (inches)
D 1.070 1.090 D1 0.934 0.966 D2 1.088 1.112 D3 0.800 nominal
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2.3 Environmental and electrical ratings
Storage Temperature (Ts)
-55 °C to 150 °C
Operating Temperature (T
a)
0 °C to 70 °C*
Power Dissipation (P
d)
400 mW
Nominal Clock Frequency (F
clk)
20.0 MHz
Supply Voltage limits (V
cc)
-0.3V to +7.0V
Supply Voltage operating range (V
cc)
4.75V to 5.25V
* An industrial version with an operating range of -40°C to 85°C is also available. Please contact PMD for more information.
2.4 System configuration
The following figure shows the principal control and data paths in an MC3410 system.
Host
CP
HostData0-15
~HostSlct
Parallel port
Serial Port
System clock (40 MHz)
HostIntrpt
HostRdy
~HostWrite
HostCmd
~HostRead
Parallel-word input
External memory
User I/O
Serial port configuration
Parallel Communication
PLD/FPGA
2
0
M
H
z
c
l
o
c
k
16 bit data/address bus
AxisOut
Negative
Positive
AxisIn
Hall sensors
(MC3310 only)
Motor
Amplifier
PWM output
DAC output
D/A
converter
A
Home
Index
B
Encoder
Pilot Motion Processor
Limit
switches
The shaded area shows the CPLD/FPGA that must be provided by the designer if parallel communication is required. A description and the necessary logic (in the form of schematics) of this device are detailed in section 6 of this manual. The CP chip contains the profile generator, which calculates velocity, acceleration, and position values for a trajectory; and the commutation unit, which
MC3410 Technical Specifications
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calculates a motor command for each motor phase. The commutation unit produces one of two types of output:
a Pulse-Width Modulated (PWM) signal output; or
a DAC-compatible value routed via the data bus to the appropriate D/A converter.
Axis position information returns to the motion processor in the form of encoder feedback using either the incremental encoder input signals, or via the bus as parallel word input.
2.5 Peripheral device address mapping
Device addresses on the CP chip’s data bus are memory-mapped to the following locations:
Address Device Description
0200h Serial port data Contains the configuration data (transmission rate,
parity, stop bits, etc) for the asynchronous serial port
0800h Parallel-word encoder Base address for parallel-word feedback devices
1000h User-defined Base address for user-defined I/O devices
2000h RAM page pointer Page pointer to external memory
4000h Motor-output DACs Base address for motor-output D/A converters
8000h Parallel interface Base address for parallel interface communication
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3 Electrical Characteristics
3.1 DC characteristics
(Vcc and Ta per operating ratings, F
clk
= 20.0 MHz)
Symbol Parameter Minimum Maximum Conditions
Vcc Supply Voltage 4.75 V 5.25 V Idd Supply Current 80 mA open outputs
Input Voltages
Vih Logic 1 input voltage 2.0 V Vcc + 0.3 V Vil Logic 0 input voltage -0.3 V 0.8 V V
ihclk
Logic 1 voltage for clock pin
(ClockIn)
3.0 V Vcc + 0.3 V
V
oclk
Logic 0 voltage for clock pin
(ClockIn)
-0.3 V 0.7 V
V
ihreset
Logic 1 voltage for reset pin (reset) 2.2 V Vcc + 0.3 V
Output Voltages
Voh Logic 1 Output Voltage 2.4 V @CP Io = -23 mA Vol Logic 0 Output Voltage 0.33 V @CP Io = 6 mA
Other
I
out
Tri-State output leakage current
-5 µA 5 µA
@CP 0 < V
out
< Vcc
Iin Input current
-10 µA
10 µA
@CP 0 < V
i
< Vcc
Cio Input/Output capacitance 15 pF @CP typical
Analog Input
Zai Analog input source impedance
9k
E
dnl
Differential nonlinearity error.
Difference between the step width and the ideal value.
-1 1.5 LSB
E
inl
Integral nonlinearity error.
Maximum deviation from the best straight line through the ADC transfer characteristics, excluding the quantization error.
+/-1.5 LSB
3.2 AC characteristics
See timing diagrams, Section 4, for Tn numbers. The symbol “~” indicates active low signal.
Timing Interval Tn Minimum Maximum
Clock Frequency (F
clk
) > 0 MHz 20 MHz (note 1) Clock Pulse Width T1 25 nsec Clock Period (note 2) T2 50 nsec Encoder Pulse Width T3 150 nsec Dwell Time Per State T4 75 nsec ~HostSlct Hold Time T6 0 nsec
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Timing Interval Tn Minimum Maximum
~HostSlct Setup Time T7 0 nsec HostCmd Setup Time T8 0 nsec HostCmd Hold Time T9 0 nsec Read Data Access Time T10 25 nsec Read Data Hold Time T11 10 nsec ~HostRead High to HI-Z Time T12 20 nsec HostRdy Delay Time T13 100 nsec 150 nsec ~HostWrite Pulse Width T14 70 nsec Write Data Delay Time T15 35 nsec Write Data Hold Time T16 0 nsec Read Recovery Time (note 2) T17 60 nsec Write Recovery Time (note 2) T18 60 nsec Read Pulse Width T19 70 nsec Address Setup Delay Time T20 7 nsec Data Access Time T21 19 nsec Data Hold Time T22 2 nsec Address Setup Delay Time T23 7 nsec Address Setup to WriteEnable High T24 72 nsec RAMSlct Low to WriteEnable High T25 79 nsec Address Hold Time T26 17 nsec WriteEnable Pulse Width T27 39 nsec Data Setup Time T28 3 nsec Data Setup before Write High Time T29 42 nsec Address Setup Delay Time T30 7 nsec Data Access Time T31 71 nsec Data Hold Time T32 2 nsec Address Setup Delay Time T33 7 nsec Address Setup to WriteEnable High T34 122 nsec PeriphSlct Low to WriteEnable High T35 129 nsec Address Hold Time T36 17 nsec WriteEnable Pulse Width T37 89 nsec Data Setup Time T38 3 nsec Data Setup before Write High Time T39 92 nsec Read to Write Delay Time T40 50 nsec Reset Low Pulse Width T50
5.0 µsec RAMSlct Low to Strobe Low T51 1 nsec Strobe High to RAMSlct High T52 4 nsec WriteEnable Low to Strobe Low T53 1 nsec Strobe High to WriteEnable High T54 3 nsec PeriphSlct Low to Strobe Low T55 1 nsec Strobe High to PeriphSlct High T56 4 nsec
Note 1 Performance figures and timing information valid at F
clk
= 20.0 MHz only. For timing
information and performance parameters at F
clk
< 20.0 MHz, refer to section 7.1.
Note 2 The clock low/high split has an allowable range of 45-55%.
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4 I/O Timing Diagrams
For the values of Tn, please refer to the table in Section 3.2.
The host interface timing shown in diagrams 4.4 and 4.5 is only valid when an external logic device is used to provide a parallel communication interface. Refer to section 6 for more information.
4.1 Clock
4.2 Quadrature encoder input
4.3 Reset
T1 T2
ClockIn
T1
V
cc
ClockIn
~RESET
T50
T3
T3
T4
T4
Quad A
Quad B
~Index
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4.4 Host interface, 8/16 mode (requires external logic device)
4.4.1 Instruction write, 8/16 mode
HostData0-7
~HostSlct
HostCmd
HostRdy
~HostWrite
Note: If setup and hold times are met, ~HostSlct and HostCmd may be de-asserted at this point.
T7
T6
see note
T8
T18
T9
T14
T14
see note
T16
T16
T15
T13
T15
Low byteHigh byte
4.4.2 Data write, 8/16 mode
HostData0-7
~HostSlct
HostCmd
HostRdy
~HostWrite
Note: If setup and hold times are met, ~HostSlct and HostCmd may be de-asserted at this point.
T7
T8
T6
T9
T15
see note
see note
Low byte
T16
T13
T16
T15
High byte
T18
T14
T14
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4.4.3 Data read, 8/16 mode
HostData0-7
~HostSlct
T7
T8
T19
T6
T9
T13
T11
HostCmd
HostRdy
~HostRead
T12
T10
High-Z
High-Z
High-Z
High
byte
Low byte
Note: If setup and hold times are met, ~HostSlct and HostCmd may be de-asserted at this point.
see note
see note
4.4.4 Status read, 8/16 mode
~HostSlct
T7
T8
T17
T6
T9
T11
HostCmd
HostData0-7
~HostRead
T12
T10
High-Z High-Z
High-Z
High byte
Low byte
T19
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4.5 Host interface, 16/16 mode (requires external logic device)
4.5.1 Instruction write, 16/16 mode
T7 T6
T9
T14
T16
T8
T13
T15
~HostSlct
HostCmd
~HostWrite
HostData0-15
HostRdy
4.5.2 Data write, 16/16 mode
T7 T6
T9
T14
T16
T8
T13
T15
~HostSlct
HostCmd
~HostWrite
HostData0-15
HostRdy
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4.5.3 Data read, 16/16 mode
~HostSlct
T7
T8
T13
T11
HostCmd
HostData0-15
HostRdy
~HostRead
T12
T10
High-Z
High-Z
T6
T9
T19
4.5.4 Status read, 16/16 mode
~HostSlct
T7
T8
T11
HostCmd
HostData0-15
~HostRead
T12
T10
High-Z
High-Z
T6
T9
T19
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4.6 External memory timing
4.6.1 External memory read
Note: PMD recommends using memory with an access time no greater than 15 nsec.
4.6.2 External memory write
Addr0-Addr15
R/~W
W/~R
~WriteEnbl
Data0-Data15
~RAMSlct
T26
T27
T27
T23
T28
T24
T25
T29
~Strobe
T53 T54
~RAMSlct
Addr0-Addr15
W/~R
~WriteEnbl
Data0-Data15
T21
T20
T40
~Strobe
T52T51
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4.7 Peripheral device timing
4.7.1 Peripheral device read
4.7.2 Peripheral device write
Addr0-Addr15
R/~W
W/~R
~WriteEnbl
Data0-Data15
~PeriphSlct
T36
T37
T37
T33
T38
T34
T35
T39
~Strobe
T53 T54
~PeriphSlct
Addr0-Addr15
W/~R
~WriteEnbl
Data0-Data15
T31
T32
T30
T31
T40
~Strobe
T56T55
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5 Pinouts and Pin Descriptions
5.1 Pinouts for MC3410
CP
~WriteEnbl
~PeriphSlct
GND
3, 8, 14, 20, 29, 37, 46, 56, 59,
61, 71, 92, 104, 113, 120
Unassigned
5, 30-34, 38, 39, 42, 45, 48, 49,
51, 55, 57, 73, 90, 91, 95, 105,
106, 107-109, 131
VCC
2, 7, 13, 21, 35, 36, 40, 47, 50,
52, 60, 62, 66, 93, 103, 121
9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28
111 112 114 115 116 117 118 119 122 123 124 125 126 127 128
43 44 99 98 58
SrlRcv SrlXmt SrlEnable ~HostIntrpt ClockIn
Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7 Data8 Data9 Data10 Data11 Data12 Data13 Data14 Data15
Addr1 Addr2 Addr3 Addr4 Addr5 Addr6 Addr7 Addr8 Addr9 Addr10 Addr11 Addr12 Addr13 Addr14 Addr15
4
6 130 129
41
R/~W ~Strobe
~RAMSlct ~Reset
W/~R132
1
63 64
PosLim1
NegLim1
85 86 87
94 72
74 89 75 88 76 83 77 82
AxisOut1
AxisIn1
Analog1 Analog2 Analog3 Analog4 Analog5 Analog6 Analog7 Analog8
AnalogVcc
AnalogRefHigh
AnalogRefLow
AnalogGnd
84
67 68
QuadA1 QuadB1
69 70
100 101
~Index1
~Home1
PWMMag1 PWMMag2
110 Addr0
102PWMMag3
96PWMSign1
97PWMSign2
54
NC/Synch
I/OIntrpt
53
PrlEnable
65
AGND
78-81
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