PMD MC2500 Datasheet

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Navigator™ Motion

Processor

MC2500 Series

Technical Specifications

for Stepping Motion Control

Performance Motion Devices, Inc.

55 Old Bedford Road

Lincoln, MA 01773

Revision 1.8, October 2003

NOTICE

This document contains proprietary and confidential information of Performance Motion Devices, Inc., and is protected by federal copyright law. The contents of this document may not be disclosed to third parties, translated, copied or duplicated in any form, in whole or in part, without the express written permission of PMD.

The information contained in this document is subject to change without notice. No part of this document may be reproduced or transmitted in any form, by any means, electronic or mechanical, for any purpose, without the express written permission of PMD.

MC2500 Technical Specifications

Warranty

PMD warrants performance of its products to the specifications applicable at the time of sale in accordance with PMD's standard warranty. Testing and other quality control techniques are utilized to the extent PMD deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

Performance Motion Devices, Inc. (PMD) reserves the right to make changes to its products or to discontinue any product or service without notice, and advises customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

Safety Notice

Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage. Products are not designed, authorized, or warranted to be suitable for use in life support devices or systems or other critical applications. Inclusion of PMD products in such applications is understood to be fully at the customer's risk.

In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent procedural hazards.

Disclaimer

PMD assumes no liability for applications assistance or customer product design. PMD does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of PMD covering or relating to any combination, machine, or process in which such products or services might be or are used. PMD's publication of information regarding any third party's products or services does not constitute PMD's approval, warranty or endorsement thereof.

MC2500 Technical Specifications

iii

MC2500 Technical Specifications

Related Documents

Navigator Motion Processor User’s Guide (MC2000UG)

How to set up and use all members of the Navigator Motion Processor family.

Navigator Motion Processor Programmer’s Reference (MC2000PR)

Descriptions of all Navigator Motion Processor commands, with coding syntax and examples, listed alphabetically for quick reference.

Navigator Motion Processor Technical Specifications

Four booklets containing physical and electrical characteristics, timing diagrams, pinouts, and pin descriptions of each series:

MC2100 Series, for brushed servo motion control (MC2100TS); MC2300 Series, for brushless servo motion control (MC2300TS); MC2400 Series, for microstepping motion control (MC2400TS); MC2500 Series, for stepping motion control (MC2500TS); MC2800 Series, for brushed servo and brushless servo motion control (MC2800TS).

Navigator Motion Processor Developer’s Kit Manual (DK2000M)

How to install and configure the DK2000 developer’s kit PC board.

MC2500 Technical Specifications

Table of Contents

Warranty...................................................................................................................................................... iii

Safety Notice ................................................................................................................................................ iii

Disclaimer..................................................................................................................................................... iii

Related Documents....................................................................................................................................... v

Table of Contents........................................................................................................................................ vii

1 The Navigator Family ............................................................................................................................... 9

2 Functional Characteristics...................................................................................................................... 11

2.1 Configurations, parameters, and performance .............................................................................. 11

2.2 Physical characteristics and mounting dimensions....................................................................... 13

2.2.1 CP chip ................................................................................................................................. 13

2.2.2 I/O chip................................................................................................................................. 14

2.3 Environmental and electrical ratings ............................................................................................15

2.4 System configuration.................................................................................................................... 15

2.5 Peripheral device address mapping...............................................................................................16

3 Electrical Characteristics........................................................................................................................ 17

3.1 DC characteristics......................................................................................................................... 17

3.2 AC characteristics......................................................................................................................... 17

4 I/O Timing Diagrams .............................................................................................................................. 19

4.1 Clock ............................................................................................................................................ 19

4.2 Quadrature encoder input ............................................................................................................. 19

4.3 Reset ............................................................................................................................................. 19

4.4 Host interface, 8/8 mode............................................................................................................... 20

4.4.1 Instruction write, 8/8 mode................................................................................................... 20

4.4.2 Data write, 8/8 mode ............................................................................................................20

4.4.3 Data read, 8/8 mode.............................................................................................................. 21

4.4.4 Status read, 8/8 mode............................................................................................................ 21

4.5 Host interface, 8/16 mode............................................................................................................. 22

4.5.1 Instruction write, 8/16 mode................................................................................................. 22

4.5.2 Data write, 8/16 mode...........................................................................................................22

4.5.3 Data read, 8/16 mode............................................................................................................23

4.5.4 Status read, 8/16 mode..........................................................................................................23

4.6 Host interface, 16/16 mode........................................................................................................... 24

4.6.1 Instruction write, 16/16 mode............................................................................................... 24

4.6.2 Data write, 16/16 mode......................................................................................................... 24

4.6.3 Data read, 16/16 mode.......................................................................................................... 25

4.6.4 Status read, 16/16 mode........................................................................................................ 25

4.7 External memory timing............................................................................................................... 26

4.7.1 External memory read........................................................................................................... 26

4.7.2 External memory write ......................................................................................................... 26

4.8 Peripheral device timing............................................................................................................... 27

4.8.1 Peripheral device read........................................................................................................... 27

4.8.2 Peripheral device write .........................................................................................................27

MC2500 Technical Specifications

vii

5 Pinouts and Pin Descriptions.................................................................................................................. 28

5.1 Pinouts for MC2540 ..................................................................................................................... 28

5.2 Pinouts for MC2520 ..................................................................................................................... 29

5.3 Pinouts for MC2510 ..................................................................................................................... 30

5.4 Pin description tables.................................................................................................................... 31

5.4.1 I/O chip................................................................................................................................. 31

5.4.2 CP chip ................................................................................................................................. 34

6 Application Notes..................................................................................................................................... 37

6.1 Design Tips................................................................................................................................... 37

6.2 ISA Bus Interface ......................................................................................................................... 39

6.3 RS-232 Serial Interface ................................................................................................................ 41

6.4 RS 422/485 Serial Interface.......................................................................................................... 43

6.5 12-bit A/D Interface...................................................................................................................... 45

6.6 16-bit A/D Input ........................................................................................................................... 47

6.7 RAM Interface.............................................................................................................................. 49

6.8 User-defined I/O........................................................................................................................... 51

MC2500 Technical Specifications

viii

1 The Navigator Family

MC2100

# of axes

Motor type supported

Output format

Incremental encoder input

Parallel word device input Parallel communication Serial communication Diagnostic port S-curve profiling Electronic gearing On-the-fly changes Directional limit switches Programmable bit output Software-invertable

signals PID servo control Feedforward (accel & vel) Derivative sampling time Data trace/diagnostics PWM output

Motion error detection

Axis settled indicator

DAC-compatible output

Series

4, 2, or 1 4, 2 or 1 4, 2 or 1 4, 2, or 1 4 or 2

Brushed servo

(single phase)

√√√√ √√√√ √√√√ √√√√ √√√√

√√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√

√√√√ √√√√ √√√√ √√√√ √√√√

√√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√

√√√√ √√√√

√√√√ √√√√ √√√√

MC2300

Series

Brushless

servo

Commutated

(6-step or

sinusoidal)

MC2400

Series

Stepping Stepping

Microstepping

MC2500

Series

Pulse and

direction

- -

√√√√

(with

encoder)

√√√√

(with

encoder)

√√√√

encoder)

√√√√

encoder)

Pulse & direction output - - Index & Home signals Position capture Analog input User-defined I/O External RAM support

Chipset part numbers

Developer's Kit p/n

√√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√

MC2140

(4 axes)

MC2120

(2 axes)

MC2110

(1 axis)

DK2100 DK2300 DK2400 DK2500 DK2800

MC2340

(4 axes)

MC2320

(2 axes)

MC2310

(1 axis)

MC2440

(4 axes)

MC2420

(2 axes)

MC2410

(1 axis)

MC2540

(4 axes)

MC2520

(2 axes)

MC2510

(1 axis)

(with

√√√√

MC2800

Series

Brushed servo

+ brushless servo

Brushed servo

(single phase)

+ commutated

(6-step or

sinusoidal)

MC2840

(4 axes)

MC2820

(2 axes)

√√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√ √√√√

√√√√ √√√√ √√√√ √√√√ √√√√

√√√√

√√√√ √√√√ √√√√ √√√√ √√√√

MC2500 Technical Specifications

Introduction

This manual describes the operational characteristics of the MC2540, MC2520 and MC2510 Motion Processors from PMD. These devices are members of PMD’s second-generation motion processor family, which consists of 14 separate products organized into 5 series.

Each of these devices is a complete chip-based motion processor. They provide trajectory generation and related motion control functions, and high speed pulse and direction outputs. Together these products provide a software-compatible family of dedicated motion processors that can handle a large variety of system configurations.

Each of these chips utilize a similar architecture, consisting of a high-speed computation unit, along with an ASIC (Application Specific Integrated Circuit). The computation unit contains special onboard hardware that makes it well suited for the task of motion control.

Each chipset consists of two PQFP (Plastic Quad Flat Pack) ICs: a 100-pin Input/Output (I/O) chip, and a 132-pin Command Processor (CP) chip.

Four of the series in the Navigator family are designed for a particular type of motor or control scheme. The fifth allows the user to control 2 servo motor types (brushed and brushless). Here is a summary description of each series.

Family Summary

MC2100 Series (MC2140, MC2120, MC2110) – This series outputs motor commands in either Sign/Magnitude PWM or DAC-compatible format for use with brushed servo motors, or with brushless servo motors having external commutation.

MC2300 Series (MC2340, MC2320, MC2310) – This series outputs sinusoidally or 6-step commutated motor signals appropriate for driving brushless motors. Depending on the motor type, the output is a two-phase or three-phase signal in either PWM or DAC-compatible format.

MC2400 Series (MC2440, MC2420, MC2410) – This series provides microstepping signals for stepping motors. Two phased signals per axis are generated in either PWM or DAC-compatible format.

MC2500 Series (MC2540, MC2520, MC2510) – These chipsets provide high-speed pulse and direction signals for stepping motor systems.

MC2800 Series (MC2840, MC2820) – This series outputs sinusoidally or 6-step commutated motor signals appropriate for driving brushless servo motors as well as PWM or DAC- compatible outputs for driving brushed servo motors.

MC2500 Technical Specifications

2 Functional Characteristics

2.1 Configurations, parameters, and performance

Available configurations 4 axes (MC2540), 2 axes (MC2520), or 1 axis (MC2510) Operating modes Open loop (pulse generator is driven by trajectory generator output)

Stall detection (pulse generator is driven by trajectory generator output and encoder feedback is used for stall detection)

Communication modes 8/8 parallel (8 bit external parallel bus with 8 bit internal command word size)

8/16 parallel (8 bit external parallel bus with 16 bit internal command word size) 16/16 parallel (16 bit external parallel bus with 16 bit internal command word

size) Point to point asynchronous serial Multidrop asynchronous serial

Serial port baud rate range 1,200 baud to 416,667 baud Position range -2,147,483,648 to +2,147,483,647 counts Velocity range -32,768 to +32,767 counts/sample with a resolution of 1/65,536 counts/sample Acceleration/deceleration

ranges Jerk range 0 to ½ counts/sample3, with a resolution of 1/4,294,967,296 counts/sample3

Profile modes S-curve point-to-point (Velocity, acceleration, jerk, and position parameters)

Electronic gear ratio range -32,768 to +32,767 with a resolution of 1/65,536 (negative and positive direction) Maximum pulse rate 4.98 M-pulses/sec Maximum encoder rate Incremental (up to 5 Mcounts/sec)

Parallel encoder word size 16 bits

Parallel encoder read rate

Cycle rate timing range

Minimum cycle time

Limit switches 2 per axis: one for each direction of travel Position-capture triggers 2 per axis: index and home signals Other digital signals (per axis) 1 AxisIn signal per axis, 1 AxisOut signal per axis Software-invertable signals Encoder A, Encoder B, Index, Home, AxisIn, AxisOut, PositiveLimit,

Analog input 8 10-bit analog inputs User defined discrete I/O 256 16-bit wide user defined I/O RAM/external memory support 65,536 blocks of 32,768 16 bit words per block. Total accessible memory is

Trace modes one-time

-32,768 to +32,767 counts/sample2 with a resolution of 1/65,536 counts/sample2

Trapezoidal point-to-point (Velocity, acceleration, deceleration, and position parameters)

Velocity-contouring (Velocity, acceleration, and deceleration parameters) Electronic Gear (Encoder or trajectory position of one axis used to drive a second

axis. Master and slave axes and gear ratio parameters)

Parallel-word (up to 160 Mcounts/sec)

20 kHz (reads all axes every 50 µsec)

102.4 µsec to 32.767 milliseconds

102.4 µsec per enabled axis

NegativeLimit, Pulse, Direction (all individually programmable per axis)

2,147,483,648 16 bit words

continuous

MC2500 Technical Specifications

Max. number of trace variables 4 Number of traceable variables 20 Number of host instructions 112

MC2500 Technical Specifications

2.2 Physical characteristics and mounting dimensions

2.2.1 CP chip

All dimensions are in inches (with millimeters in brackets).

Dimension Minimum

(inches)

D 1.070 1.090 D1 0.934 0.966 D2 1.088 1.112 D3 0.800 nominal

Maximum (inches)

MC2500 Technical Specifications

2.2.2 I/O chip

All dimensions are in millimeters.

Dimension Minimum

(mm)

A 3.40 A1 0.25 0.33 A2 2.55 2.80 3.05 b 0.22 0.38 c 0.13 0.23 D 22.95 23.20 23.45 D1 19.90 20.00 20.10 E 16.95 17.20 17.45 E1 13.90 14.00 14.01 e 0.65 BSC L 0.73 0.88 1.03 ccc 0.10 theta 0° 7°

Nominal (mm)

Maximum (mm)

MC2500 Technical Specifications

2.3 Environmental and electrical ratings

All ratings and ranges are for both the I/O and CP chips.

Storage Temperature (T

Operating Temperature (T

Power Dissipation (P

Nominal Clock Frequency (F

Supply Voltage Limits (V

)

) 600 mW (I/O and CP combined)

) 40.0 MHz

clk

) -0.3V to +7.0V

Supply Voltage Operating Range (V

* An industrial version with an operating range of -40°C to 85°C is also available. Please contact PMD for more information.

2.4 System configuration

The following figure shows the principal control and data paths in an MC2500 system.

Host

Parallel port

System clock (40 MHz)

HostData0-15

Navigator Motion Processor

HostRdy

~HostSlct

~HostWrite

I/O CP

-55 °C to 150 °C

0 °C to 70 °C*

) 4.75V to 5.25V

HostCmd

~HostRead

20MHz clock

Serial-port

host

Serial port

(alternatives)

Navigator Motion Processor

HostIntrpt

Index

Home

AtRest

Pulse and Direction

Encoder

Motor amplifie r

16-bit data bus

Serial port configuration

Parallel word input

Other user devices

AxisIn

AxisOut

External memory

User I/O

Positive

Limit

switches

Negative

The CP chip contains the profile generator, which calculates velocity, acceleration, and position values for a trajectory. The output of the trajectory generator is used to produce pulse and direction signals that control motor position.

Optional axis position information returns to the motion processor through the I/O chip, in the form of encoder feedback, or through the CP chip, in the form of parallel-word feedback. This position feedback may be used to detect motor stalling errors.

MC2500 Technical Specifications

Analog inputs

2.5 Peripheral device address mapping

Device addresses on the CP chip’s data bus are memory-mapped to the following locations:

Address Device Description

0200h Serial port data Contains the configuration data (transmission rate,

0800h Parallel-word encoder Base address for parallel-word feedback devices

1000h User-defined Base address for user-defined I/O devices

2000h RAM page pointer Page pointer to external memory

4000h Reserved Reserved for future use

8000h I/O chip Base address for I/O chip communications

parity, stop bits, etc) for the asynchronous serial port

MC2500 Technical Specifications

3 Electrical Characteristics

3.1 DC characteristics

(Vcc and Ta per operating ratings, F

= 40.0 MHz)

clk

Symbol Parameter Minimum Maximum Conditions

Vcc Supply Voltage 4.75 V 5.25 V Idd Supply Current 120 mA open outputs

Input Voltages

Vih Logic 1 input voltage 2.0 V Vcc + 0.3 V Vil Logic 0 input voltage -0.3 V 0.8 V V

Logic 1 voltage for reset pin (reset) 2.2 V Vcc + 0.3 V

ihreset

Output Voltages

Voh Logic 1 Output Voltage 2.4 V @CP Io = -23 mA

@I/O I

= -6 mA

Vol Logic 0 Output Voltage 0.33 V @CP Io = 6 mA

= 6 mA

@I/O I

Other

Tri-State output leakage current

out

Iin Input current

-5 µA 5 µA

-10 µA

Cio Input/Output capacitance 15 pF

10 µA

-10 µA

10 pF

@CP

< Vcc

0 < V

out

@CP @I/O 0 < V

< Vcc

@CP typical @I/O

Zai Analog input source impedance E

Differential nonlinearity error.

dnl

Difference between the step width and the ideal value.

Integral nonlinearity error.

inl

Maximum deviation from the best straight line through the ADC transfer characteristics, excluding the quantization error.

3.2 AC characteristics

See timing diagrams, section 4, for Tn numbers. The symbol “~” indicates active low signal.

Timing Interval Tn Minimum Maximum

Clock Frequency (F Clock Pulse Width T1 10 nsec Clock Period (note 3) T2 25 nsec Encoder Pulse Width T3 150 nsec Dwell Time Per State T4 75 nsec

) > 0 MHz 40 MHz (note 1)

clk

Analog Input

9kΩ

-1 1.5 LSB

+/-1.5 LSB

MC2500 Technical Specifications

Timing Interval Tn Minimum Maximum

Index Setup and Hold (relative to Quad A and Quad B low) ~HostSlct Hold Time T6 0 nsec ~HostSlct Setup Time T7 0 nsec HostCmd Setup Time T8 0 nsec HostCmd Hold Time T9 0 nsec Read Data Access Time T10 25 nsec Read Data Hold Time T11 10 nsec ~HostRead High to HI-Z Time T12 20 nsec HostRdy Delay Time T13 100 nsec 150 nsec ~HostWrite Pulse Width T14 70 nsec Write Data Delay Time T15 25 nsec Write Data Hold Time T16 0 nsec Read Recovery Time (note 2) T17 60 nsec Write Recovery Time (note 2) T18 60 nsec Read Pulse Width T19 70 nsec Address Setup Delay Time T20 7 nsec Data Access Time T21 19 nsec Data Hold Time T22 2 nsec Address Setup Delay Time T23 7 nsec Address Setup to WriteEnable High T24 72 nsec RAMSlct Low to WriteEnable High T25 79 nsec Address Hold Time T26 17 nsec WriteEnable Pulse Width T27 39 nsec Data Setup Time T28 3 nsec Data Setup before Write High Time T29 42 nsec Address Setup Delay Time T30 7 nsec Data Access Time T31 71 nsec Data Hold Time T32 2 nsec Address Setup Delay Time T33 7 nsec Address Setup to WriteEnable High T34 122 nsec PeriphSlct Low to WriteEnable High T35 129 nsec Address Hold Time T36 17 nsec WriteEnable Pulse Width T37 89 nsec Data Setup Time T38 3 nsec Data Setup before Write High Time T39 92 nsec Read to Write Delay Time T40 50 nsec Reset Low Pulse Width T50

RAMSlct Low to Strobe Low T51 1 nsec Strobe High to RAMSlct High T52 4 nsec WriteEnable Low to Strobe Low T53 1 nsec Strobe High to WriteEnable High T54 3 nsec PeriphSlct Low to Strobe Low T55 1 nsec Strobe High to PeriphSlct High T56 4 nsec Device Ready/ Outputs Initialized T57 1 msec

Note 1 Performance figures and timing information valid at F

information and performance parameters at F

T5 0 nsec

5.0 µsec

< 40.0 MHz refer to section 6.1.

clk

= 40.0 MHz only. For timing

clk

Note 2 For 8/8 and 8/16 interface modes only.

Note 3 The clock low/high split has an allowable range of 45-55%.

MC2500 Technical Specifications

4 I/O Timing Diagrams

For the values of Tn, please refer to the table in Section 0.

4.1 Clock

MasterClkIn

4.2 Quadrature encoder input

Quad A

Quad B

~Index

4.3 Reset

T1 T2

(= ~QuadA * ~QuadB * ~Index)

Index

I/OClk

~RESET

T50

MC2500 Technical Specifications

T57

4.4 Host interface, 8/8 mode

4.4.1 Instruction write, 8/8 mode

~HostSlct

HostCmd

~HostWrite

HostData0-7

HostRdy

4.4.2 Data write, 8/8 mode

~HostSlct

HostCmd

T15

T14

T13

T16

see note

~HostWrite

HostData0-7

HostRdy

T16

T18

T14

T16

Low byte

T15

T13

T14

High byte

T15

Note: If setup and hold times are met, ~HostSlct and HostCmd may be de-asserted at this point.

MC2500 Technical Specifications

4.4.3 Data read, 8/8 mode

~HostSlct

see

note

HostCmd

~HostRead

High-Z

HostData0-7

HostRdy

Note: If setup and hold times are met, ~HostSlct and HostCmd may be de-asserted at this point.

4.4.4 Status read, 8/8 mode

~HostSlct

T10

T19

High byte

T11

T12

T17

see

note

High-Z

Low byte

T13

High-Z

HostCmd

~HostRead

HostData0-7

High-Z

T14

T12

T10

T11

MC2500 Technical Specifications

High-Z

4.5 Host interface, 8/16 mode

4.5.1 Instruction write, 8/16 mode

~HostSlct

see note

HostCmd

~HostWrite

HostData0-7

HostRdy

Note: If setup and hold times are met, ~HostSlct and HostCmd may be de-asserted at this point.

4.5.2 Data write, 8/16 mode

~HostSlct

T15

T14

T16

T18

see note

T14

T16

Low byteHigh byte

T15

T13

see note

HostCmd

~HostWrite

HostData0-7

HostRdy

see note

T14

High byte

T15

Note: If setup and hold times are met, ~HostSlct and HostCmd may be de-asserted at this point.

T18

T16

T14

T15

T16

Low byte

T13

MC2500 Technical Specifications

4.5.3 Data read, 8/16 mode

~HostSlct

see note

HostCmd

~HostRead

HostData0-7

High-Z

HostRdy

Note: If setup and hold times are met, ~HostSlct and HostCmd may be de-asserted at this point.

4.5.4 Status read, 8/16 mode

~HostSlct

T10

T19

High

byte

T11

T12

see note

High-Z

Low byte

T13

High-Z

HostCmd

~HostRead

HostData0-7

T17

T19

T12

High-Z High-Z

T10

High

byte

T11

MC2500 Technical Specifications

Low byte

High-Z

4.6 Host interface, 16/16 mode

4.6.1 Instruction write, 16/16 mode

~HostSlct

HostCmd

T7 T6

~HostWrite

HostData0-15

HostRdy

4.6.2 Data write, 16/16 mode

~HostSlct

HostCmd

T14

T15

T13

T7 T6

T16

~HostWrite

HostData0-15

HostRdy

T14

T15

T13

MC2500 Technical Specifications

T16

4.6.3 Data read, 16/16 mode

~HostSlct

HostCmd

~HostRead

HostData0-15

HostRdy

High-Z

T10

T14

T13

T12

High-Z

T11

4.6.4 Status read, 16/16 mode

~HostSlct

HostCmd

~HostRead

HostData0-15

High-Z

T10

T14

T11

T12

High-Z

MC2500 Technical Specifications

4.7 External memory timing

4.7.1 External memory read

Note: PMD recommends using memory with an access time no greater than 15 nsec.

~RAMSlct

Addr0-Addr15

W/~R

T20

T40

~WriteEnbl

Data0-Data15

~Strobe

4.7.2 External memory write

~RAMSlct

Addr0-Addr15

R/~W

W/~R

~WriteEnbl

T23

T28

T21

T25

T24

T29

T27

T52T51

T26

T27

Data0-Data15

T53 T54

~Strobe

MC2500 Technical Specifications

4.8 Peripheral device timing

4.8.1 Peripheral device read

~PeriphSlct

Addr0-Addr15

W/~R

~WriteEnbl

Data0-Data15

~Strobe

4.8.2 Peripheral device write

~PeriphSlct

T30

T33

T31

T34

T32

T40

T31

T56T55

Addr0-Addr15

T35

R/~W

W/~R

T39

~WriteEnbl

T38

Data0-Data15

~Strobe

T36

T37

T53 T54

T37

MC2500 Technical Specifications

5 Pinouts and Pin Descriptions

5.1 Pinouts for MC2540

16, 17, 40, 65, 66, 67, 90

100

94 77 53 54 52 41 43 50 89 24

91 12 10 99 98

11 97 95 76 74 73 75

38 36 35 32 31

HostCmd

~HostRdy ~HostRead ~HostWrite ~HostSlct CPIntrpt CPR/~W CPStrobe CPPeriphSlct CPAddr0 CPAddr1 CPAddr15 MasterClkIn CPClk

HostMode0 HostMode1 HostData0 HostData1 HostData2 HostData3

HostData4 HostData5 HostData6 HostData7 HostData8 HostData9 HostData10 HostData11

HostData12

HostData13

HostData14

HostData15 CPData0 CPData1 CPData2 CPData3 CPData4

4, 9, 22, 34, 46, 57, 64, 72, 84, 96

VCC

I/O

GND

Unassigned

19, 27, 55,

56, 62, 78, 87

CPData5 CPData6 CPData7 CPData8

CPData9 CPData10 CPData11 CPData12 CPData13 CPData14 CPData15

Pulse1 Pulse2 Pulse3

Pulse4 Direction1 Direction2 60 Direction3 Direction4

AtRest1 AtRest2 AtRest3

AtRest4 QuadA1 QuadB1 ~Index1

~Home1

QuadA2 QuadB2 ~Index2

~Home2

QuadA3 QuadB3 ~Index3

~Home3

QuadA4 QuadB4 ~Index4

~Home4

2, 7, 13, 21, 35, 36, 40, 47, 50,

52, 60, 62, 93, 103, 121

37 42 39 18 14 71 13 70 15 69

68 21 85 20 79 61

59 26 23 86 63 80

130 129

110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128

43 44 99 98 53 58

10 11 12 15 16 17 18 19 22 23 24 25 26 27 28

1 4 6

~WriteEnbl R/~W ~Strobe ~PeriphSlct ~RAMSlct ~Reset

W/~R132 SrlRcv SrlXmt SrlEnable ~HostIntrpt I/OIntrpt I/OClk

Addr0 Addr1 Addr2 Addr3 Addr4 Addr5 Addr6 Addr7 Addr8 Addr9 Addr10 Addr11 Addr12 Addr13 Addr14 Addr15 Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7 Data8 Data9 Data10 Data11 Data12 Data13 Data14 Data15

3, 8, 14, 20, 29, 37, 46, 56, 59,

61, 71, 92, 104, 113, 120

Unassigned

5, 30-34, 38, 39, 42, 45, 48, 57,

68-70, 73, 78-81, 90, 91, 101,

102, 105, 107-109, 131

VCC

GND

AnalogVcc

AnalogRefHigh

AnalogRefLow

AnalogGnd

Analog1 Analog2 Analog3 Analog4 Analog5 Analog6 Analog7

Analog8 PosLim1 PosLim2 PosLim3 PosLim4 NegLim1 NegLim2 NegLim3 NegLim4 AxisOut1 AxisOut2 AxisOut3 AxisOut4

AxisIn1 AxisIn2 AxisIn3 AxisIn4

84 85 86 87 74 89 75 88 76 83 77 82 63 65 54 49 64 66 55 51 94 95 96 97 72 100 106 67

MC2500 Technical Specifications

5.2 Pinouts for MC2520

16, 17, 40, 65, 66, 67, 90

100

94 77 53 54 52 41 43 50 89 24

91 12 10 99 98

11 97 95 76 74 73 75

38 36 35 32 31

2 3 7 6

HostCmd ~HostRdy ~HostRead ~HostWrite ~HostSlct CPIntrpt CPR/~W CPStrobe CPPeriphSlct CPAddr0 CPAddr1 CPAddr15 MasterClkIn CPClk HostMode0 HostMode1 HostData0 HostData1 HostData2 HostData3 HostData4 HostData5 HostData6 HostData7 HostData8 HostData9 HostData10 HostData11 HostData12 HostData13 HostData14 HostData15 CPData0 CPData1 CPData2 CPData3 CPData4

4, 9, 22, 34, 46, 57, 64, 72, 84, 96

19, 20, 26, 27, 30, 33, 45, 51, 55, 56, 58, 59, 62, 63, 78, 79, 80, 83,

VCC

I/O

GND

Unassigned

87, 88

CPData5 CPData6 CPData7 CPData8

CPData9 CPData10 CPData11 CPData12 CPData13 CPData14 CPData15

Pulse1

Pulse2 Direction1 Direction2 60

AtRest1 AtRest22386

QuadA1 QuadB1 ~Index1

~Home1

QuadA2 QuadB2 ~Index2

~Home2

2, 7, 13, 21, 35, 36, 40, 47, 50,

52, 60, 62, 93, 103, 121

37 42 39 18 14 71 13 70 15 69 68 21 85 61

47 25 49 82 48 44 93 29

130 129

110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128

43 44 99 98 53 58

10 11 12 15 16 17 18 19 22 23 24 25 26 27 28

1 4 6

~WriteEnbl R/~W ~Strobe ~PeriphSlct ~RAMSlct ~Reset

W/~R132 SrlRcv SrlXmt SrlEnable ~HostIntrpt I/OIntrpt I/OClk

VCC

GND

AnalogVcc

AnalogRefHigh

AnalogRefLow

AnalogGnd

Analog1 Analog2 Analog3 Analog4 Analog5 Analog6 Analog7

Analog8 PosLim1 PosLim2 NegLim1 NegLim2 AxisOut1 AxisOut2

AxisIn1 AxisIn2

84 85 86 87 74 89 75 88 76 83 77 82 63 65 64 66 94 95 72 100

3, 8, 14, 20, 29, 37, 46, 56, 59,

61, 71, 92, 104, 113, 120

Unassigned

5, 30-34, 38, 39, 42, 45, 48, 49,

51, 54, 55, 57, 67-70, 73, 78-81,

90, 91, 96, 97, 101, 102, 105,

106-109, 131

MC2500 Technical Specifications

5.3 Pinouts for MC2510

16, 17, 40, 65, 66, 67, 90

100

94 77 53 54 52 41 43 50 89 24

91 12 10 99 98

11 97 95 76 74 73 75

38 36 35 32 31

2 3 7 6

4, 9, 22, 34, 46, 57, 64, 72, 84, 96

19, 20, 26, 27, 29, 30, 33, 44, 45,

48, 51, 55, 56, 58-60, 62, 63, 78,

VCC

I/O

GND

Unassigned

79, 80, 83, 85-87, 88, 93

CPData5 CPData6 CPData7 CPData8

CPData9 CPData10 CPData11 CPData12 CPData13 CPData14 CPData15

Pulse1

Direction1

AtRest1 23 QuadA1 QuadB1 ~Index1

~Home1

2, 7, 13, 21, 35, 36, 40, 47, 50,

52, 60, 62, 93, 103, 121

37 42 39 18 14 71 13 70 15 69 68 21 61

47 25 49 82

130 129

110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128

43 44 99 98 53 58

10 11 12 15 16 17 18 19 22 23 24 25 26 27 28

1 4 6

~WriteEnbl R/~W ~Strobe ~PeriphSlct ~RAMSlct ~Reset

W/~R132 SrlRcv SrlXmt SrlEnable ~HostIntrpt I/OIntrpt I/OClk

VCC

GND

AnalogVcc

AnalogRefHigh

AnalogRefLow

AnalogGnd

Analog1 Analog2 Analog3 Analog4 Analog5 Analog6 Analog7

Analog8 PosLim1 NegLim1 AxisOut1

AxisIn1

84 85 86 87 74 89 75 88 76 83 77 82 63 64 94 72

3, 8, 14, 20, 29, 37, 46, 56, 59,

61, 71, 92, 104, 113, 120

Unassigned

5, 30-34, 38, 39, 42, 45, 48, 49,

51, 54, 55, 57, 65-70, 73, 78-81,

90, 91, 95-97, 100-102, 105,

106-109, 131

MC2500 Technical Specifications

5.4 Pin description tables

5.4.1 I/O chip

Pin Name and Number

HostCmd 81

HostRdy 8

~HostRead 92 ~HostWrite 100 ~HostSlct 94

CPIntrpt 77

CPR/~W 53

CPStrobe 54

CPPeriphSlct 52

CPAddr0 CPAddr1 CPAddr15

MasterClkIn 89

CPClk 24

41 43 50

Input

Output

Input When ~HostRead is low, a data word is read from the Motion Processor. Input When ~HostWrite is low, a data word is written to the Motion Processor. Input

Output

Input

Output

I/O Chip

Direction Description

This signal is asserted high to write a host instruction to the Motion Processor, or to read the status of the asserted low to read or write a data word.

This signal is used to synchronize communication between the Motion Processor and the host. the end of a read or write operation according to the interface mode in use, as follows:

Interface Mode

8/8 after the instruction byte is transferred after the second byte of each data word is transferred 8/16 after the second byte of the instruction word after the second byte of each data word is transferred 16/16 after the 16-bit instruction word after each 16-bit data word serial n/a

HostRdy will go high, indicating that the host port is ready to transmit,

when the last transmission has been processed. All host port communications must be made with A typical busy-to-ready cycle is 12.5 microseconds.

~HostSlct is low, the host port is selected for reading or writing

When operations.

I/O chip to CP chip interrupt. This signal sends an interrupt to the CP chip whenever a host–chipset transmission occurs. It should be connected to CP chip pin 53,

This signal is high when the I/O chip is reading data from the I/O chip, and low when it is writing data. It should be connected to CP chip pin 4,

R/W.

This signal goes low when the data and address become valid during Motion Processor communication with peripheral devices on the data bus, such as external memory or a DAC. It should be connected to CP chip pin 6,

This signal goes low when a peripheral device on the data bus is being addressed. It should be connected to CP chip pin 130,

These signals are high when the CP chip is communicating with the I/O chip (as distinguished from any other device on the data bus). They should be connected to CP chip pins 110 (

Addr15).

( This is the master clock signal for the Motion Processor. It is driven at a

nominal 40 MHz This signal provides the clock pulse for the CP chip. Its frequency is half

that of the CP chip

Strobe.

MasterClkIn (pin 89), or 20 MHz nominal. It is connected directly to

I/Oclk signal (pin 58).

HostRdy and HostIntrpt signals. It is

HostRdy will go low (indicating host port busy) at

HostRdy goes low

HostRdy high (ready).

I/OIntrpt.

PeriphSlct.

Addr0), 111 (Addr1), and 128

MC2500 Technical Specifications

Pin Name and Number

HostMode1 HostMode0

91 5

I/O Chip

Direction Description

Input These two signals determine the host communications mode, as follows:

HostMode1 HostMode0

0 0 16/16 parallel (16-bit bus, 16-bit instruction) 0 1 8/8 parallel (8-bit bus, 8-bit instruction) 1 0 8/16 parallel (8-bit bus, 16-bit instruction) 1 1 serial

HostData0 HostData1 HostData2 HostData3 HostData4 HostData5 HostData6 HostData7 HostData8 HostData9 HostData10 HostData11 HostData12 HostData13 HostData14 HostData15 CPData0 CPData1 CPData2 CPData3 CPData4 CPData5 CPData6 CPData7 CPData8 CPData9 CPData10 CPData11 CPData12 CPData13 CPData14 CPData15 Pulse1 Pulse2 Pulse3 Pulse4

Direction1 Direction2 Direction3 Direction4

12 10 99 98 1 11 97 95 76 74 73 75 2 3 7 6 38 36 35 32 31 37 42 39 18 14 71 13 70 15 69 68 21 85 20 79

61 60 59 26

Bi-directional, tri-state

Bi-directional

Output

These signals transmit data between the host and the Motion Processor through the parallel port. Transmission is mediated by the control signals

~HostSlct, ~HostWrite, ~HostRead and HostCmd.

In 16 bit mode, all 16 bits are used ( low-order 8 bits of data are used (

HostMode1 signals select the communication mode this port operates in.

These signals transmit data between the I/O chip and pins

HostData0-15). In 8 bit mode, only the

HostData0-7). The HostMode0 and

Data0-15 of the

CP chip, via the Motion Processor data bus.

These pins provide the Pulse signal to the motor. This signal is always a square wave, regardless of the pulse rate. A “step” occurs when the signal transitions from a high state to a low state. For the MC2540 all 4 pins are valid. For MC2520 only Pulse1 and Pulse2 are valid. For MC2510 only Pulse1 is valid.

Invalid axis pins may be left unconnected. These pins indicate the direction of motion and work in conjunction with

the pulse signal. A high level on this signal indicates a positive direction move and a low level indicates a negative direction move. For MC2540 all 4 pins are valid. For MC2520 only Direction1 and Direction2 are valid. For MC2510 only Direction1 is valid. Invalid axis pins may be left unconnected.

MC2500 Technical Specifications

Pin Name and Number

AtRest1 AtRest2 AtRest3 AtRest4

QuadA1 QuadB1 QuadA2 QuadB2 QuadA3 QuadB3 QuadA4 QuadB4

~Index1 ~Index2 ~Index3 ~Index4

23 86 63 80

47 25 48 44 33 51 30 58

49 93 83 28

Direction Description

Output

Input

The AtRest signal indicates the axis is at rest and the step motor can be switched to low power or standby. A high level on this signal indicates the axis is at rest. A low signal indicates the axis is in motion. For MC2540 all 4 pins are valid. For MC2520 only AtRest1 and AtRest2 are valid. For MC2510 only AtRest1 is valid. Invalid axis pins may be left unconnected.

These pins provide the A and B quadrature signals for the incremental encoder for each axis. When the axis is moving in the positive (forward) direction, signal A leads signal B by 90°. The theoretical maximum encoder pulse rate is 5.1 MHz. Actual maximum rate will vary, depending on signal noise. NOTE: Many encoders require a pull-up resistor on each signal to establish a proper high signal. Check your encoder’s electrical specifications.

For MC2540, all 8 pins are valid. For MC2520, only the first four pins (axes 1 and 2) are valid. For MC2510, only the first two pins (axis 1) are valid.

WARNING! If a valid axis pin is not used, its signal should be tied high.

Invalid axis pins may be left unconnected.

Input

These pins provide the Index quadrature signals for the incremental encoders. A valid index pulse is recognized by the chipset when and

B are all low.

For MC2540, all 4 pins are valid. For MC2520, only are valid. For MC2510, only ~Index1 is valid.

I/O Chip

~Index, A,

~Index1 and ~Index2

~Home1 ~Home2 ~Home3 ~Home4

Vcc

GND

unassigned

82 29 88 45

Input

16, 17, 40, 65, 66, 67, 90

4, 9, 22, 34, 46, 57, 64, 72, 84, 96

19, 27, 55, 56, 62, 78, 87

WARNING! If a valid axis pin is not used, its signal should be tied high.

Invalid axis pins may be left unconnected. These pins provide the Home signals, general-purpose inputs to the

position-capture mechanism. A valid Home signal is recognized by the chipset when

~Homen goes low. These signals are similar to ~Index, but are

not gated by the A and B encoder channels. For MC2140, all 4 pins are valid. For MC2120, only

~Home1 and ~Home2

are valid. For MC2110, only ~Home1 is valid.

WARNING! If a valid axis pin is not used, its signal should be tied high.

Invalid axis pins may be left unconnected. All of these pins must be connected to the I/O chip’s digital supply

voltage, which should be in the range 4.75 to 5.25 V. I/O chip ground. All of these pins must be connected to the digital

power supply return. These pins may be left unconnected (floating).

MC2500 Technical Specifications

5.4.2 CP chip

Pin Name and Number

~WriteEnbl 1 R/~W 4

~Strobe 6

~PeriphSlct 130

~RAMSlct 129 ~Reset 41

W/~R 132

SrlRcv 43

CP chip

Direction Description

Output When low, this signal enables data to be written to the bus. Output

Output

Output This signal is low indicates that external memory is being accessed. Input

Output

Input This pin receives serial data from the serial transceiver.

This signal is high when the CP chip is performing a read, and low when it is performing a write. It should be connected to I/O chip pin 53,

CPR/~W.

This signal is low when the data and address are valid during CP communications. It should be connected to I/O chip pin 54,

CPStrobe.

This signal is low when peripheral devices on the data bus are being addressed. It should be connected to I/O chip pin 52,

CPPeriphSlct.

This is the master reset signal. When brought low, this pin resets the chipset to its initial conditions.

This signal is the inverse of some decode circuits, this is more convenient than

R/~W; it is high when R/~W is low, and vice versa. For

R/~W.

NOTE! If this signal is not used, it should be tied high.

SrlXmt 44 SrlEnable 99

~HostIntrpt 98 I/OIntrpt 53

Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7 Data8 Data9 Data10 Data11 Data12 Data13 Data14 Data15

9 10 11 12 15 16 17 18 19 22 23 24 25 26 27 28

Output This pin transmits serial data to the asynchronous serial port. Output

This pin sets the serial port enable line. SrlEnable is always high for the point-to-

point protocol and is high during transmission for the multi-drop protocol. Output When low, this signal causes an interrupt to be sent to the host processor. Input

Bidirectional

This signal interrupts the CP chip when a host I/O transfer is complete. It

should be connected to I/O chip pin 77,

CPIntrpt.

Multi-purpose data lines. These pins comprise the CP chip’s external data bus,

used for all communications with the I/O chip and peripheral devices such as

external memory or DACs. They may also be used for parallel-word input and

for user-defined I/O operations.

MC2500 Technical Specifications

Pin Name and

Direction Description

Number

Addr0 Addr1 Addr2 Addr3 Addr4 Addr5 Addr6 Addr7 Addr8 Addr9 Addr10 Addr11 Addr12 Addr13 Addr14 Addr15 I/OClk 58

AnalogVcc 84

AnalogRefHigh 85

AnalogRefLow 86

AnalogGND 87

Analog1 Analog2 Analog3 Analog4 Analog5 Analog6 Analog7 Analog8 PosLim1 PosLim2 PosLim3 PosLim4

110 111 112 114 115 116 117 118 119 122 123 124 125 126 127 128

74 89 75 88 76 83 77 82 63 65 54 49

Output

Input

CP chip

Multi-purpose Address lines. These pins comprise the CP chip’s external address

bus, used to select devices for communication over the data bus.

Addr15 are connected to the corresponding CPAddr pins on the I/O chip, and

and

are used to communicate between the CP and I/O chips.

Other address pins may be used for DAC output, parallel word input, or user-

defined I/O operations. See the Navigator Motion Processor User’s Guide for a

complete memory map.

This is the CP chip clock signal. It should be connected to I/O chip pin 24,

CPClk.

CP chip analog power supply voltage. This pin must be connected to the analog

input supply voltage, which must be in the range 4.5-5.5 V

CP chip analog high voltage reference for A/D input. The allowed range is

AnalogRefLow to AnalogVcc.

CP chip analog low voltage reference for A/D input. The allowed range is

AnalogGND to AnalogRefHigh.

CP chip analog input ground. This pin must be connected to the analog input

power supply return.

These signals provide general-purpose analog voltage levels, which are sampled

by an internal A/D converter. The A/D resolution is 10 bits.

The allowed range is

AnalogRefLow to AnalogRefHigh.

These signals provide inputs from the positive-side (forward) travel limit

switches. On power-up or

but the interpretation can be set explicitly using the

For MC2540, all 4 pins are valid. For MC2520, only

valid. For MC2510, only

Reset these signals default to active low interpretation,

SetSignalSense instruction.

PosLim1 and PosLim2 are

PosLim1 is valid.

Addr0, Addr1,

WARNING! If a valid axis pin is not used, its signal should be tied

high. PosLim2 is an output during device reset and as such any

connection to GND or V

Invalid axis pins may also be left unconnected.

MC2500 Technical Specifications

must be via a series resistor.

Pin Name and Number

NegLim1 NegLim2 NegLim3 NegLim4

AxisOut1 AxisOut2 AxisOut3 AxisOut4

AxisIn1 AxisIn2 AxisIn3 AxisIn4

Vcc

Direction Description

64 66 55 51

94 95 96 97

72 100 106 67

2, 7, 13, 21, 35, 36, 40, 47, 50, 52, 60, 62, 93, 103, 121

Input

Output

Input

CP chip

These signals provide inputs from the negative-side (reverse) travel limit

switches. On power-up or

but the interpretation can be set explicitly using the

For MC2540, all 4 pins are valid. For MC2520, only

valid. For MC2510, only

WARNING! If a valid axis pin is not used, its signal should be tied

high. NegLim1 is an output during device reset and as such any

connection to GND or V

Invalid axis pins may also be left unconnected.

Each of these pins can be conditioned to track the state of any bit in the Status

registers associated with its axis.

For MC2540, all 4 pins are valid. For MC2520, only

valid. For MC2510, only

Invalid or unused pins may be left unconnected.

These are general-purpose programmable inputs. They may be used as a

breakpoint input, to stop a motion axis, or to cause an UPDATE to occur.

For MC2540, all 4 pins are valid. For MC2520, only

For MC2510, only

Invalid or unused pins may be left unconnected.

CP digital supply voltage. All of these pins must be connected to the supply

voltage. V

must be in the range 4.75 - 5.25 V

WARNING! Pin 35 must be tied HIGH with a pull-up resistor. A

nominal value of 22K Ohms is suggested.

Reset these signals default to active low interpretation,

SetSignalSense instruction.

NegLim1 and NegLim2 are

NegLim1 is valid.

must be via a series resistor.

AxisOut1 and AxisOut2 are

AxisOut1 is valid.

AxisIn1 and AxisIn2 are valid.

AxisIn1 is valid.

GND

unassigned (MC2540)

3, 8, 14, 20, 29, 37, 46, 56, 59, 61, 71, 92, 104, 113, 120

5, 30-34, 38, 39, 42, 45, 48, 57, 68-70, 73, 78-81, 90, 91, 101, 102, 105, 107-9, 131

CP ground. All of these pins must be connected to the power supply return.

These signals may be left unconnected (floating).

MC2500 Technical Specifications

6 Application Notes

6.1 Design Tips

The following are recommendations for the design of circuits that utilize a PMD Motion Processor.

Serial Interface

The serial interface is a convenient interface that can be used before host software has been written to communicate through the parallel interface. It is recommended that even if the serial interface is not utilized as a standard communication interface, that the serial receive and transmit signals are brought to test points so that they may be connected during initial board configuration/debugging. This is especially important during the prototype phase. The serial receive line should include a pullup resistor to avoid spurious interrupts when it is not connected to a transceiver.

If the serial configuration decode logic is not implemented (see section 6.3) and the serial interface may be used for debugging as mentioned above, the CP data bus should be tied high. This places the serial interface in a default configuration of 9600,n,8,1 after power on or reset.

Controlling pulse output during reset

When the motion processor is in a reset state (when the reset line is held low) or immediately after a power on, the pulse outputs can be in an unknown state, causing undesirable motor movement. It is recommended that the enable line of any motor amplifier be held in a disabled state by the host processor or some logic circuitry until communication to the motion processor is established. This can be in the form of a delay circuit on the amplifier enable line after power up, or the enable line can be ANDed with the CP reset line.

Reducing noise and power consumption

To reduce the emission of electrical noise and reduce power consumption (caused by floating inputs), all unused input signals can be tied through a resistor to Vcc or directly to GND. The following CP pins can be tied if not used: 45, 48, 68-70, 73, 90, 91, 101, 102, 105, 107-109, 78-81.

Parallel word encoder input

When using parallel word input for motor position, it is useful to also decode this information into the User I/O space. This allows the current input value to be read using the chip instruction ReadIO for diagnostic purposes.

Using a non standard system clock frequency

It is often desirable to share a common clock among several components in a design. In the case of the PMD Motion Processors it is possible to use a clock below the standard value of 40MHz. In this case all system frequencies will be reduced as a fraction of the input clock verses the standard 40MHz clock. The list below shows the affected system parameters:-

• Serial baud rate

MC2500 Technical Specifications

• Maximum pulse rate

• Timing characteristics as shown in section 3.2

• Cycle time

For example, if an input clock of 34MHz is used with a serial baud rate of 9600 and the step range (SetStepRange) set to 625KHz the following timing changes will result:-

• Serial baud rate decreases to 9600 bps *34/40 = 8160 bps

• Maximum step rate decreases to 625 KHz *34/40 = 531.25 KHz

• Cycle time per axis increases to 102.4 µsec *40/34 = 120.48 µsec

MC2500 Technical Specifications

6.2 ISA Bus Interface

A complete, ready-to-use ISA (PC/AT) bus interface circuit has been provided to illustrate Navigator host interfacing, as well as to make it easier for the customer to build a Navigator development system.

The interface between the PMD Navigator chipset and the ISA (PC-AT) bus is shown on the following page.

Comments on Schematic

This interface uses a CPLD and two 74LS245s to buffer the data lines. This interface assumes a base address is assigned in the address space of A9-A0, 300-400 hex. These addresses are generally available for prototyping and other system-specific uses without interfering with system assignments. This interface occupies 16 addresses from XX0 to XXF hex though it does not use all the addresses. Four select lines are provided allowing the base address to be set from 300 to 3F0 hex for the select lines SW1-SW4 equal to 0- F respectively. The address assignments used are as follows, where BADR is the base address, 340 hex for example:

Address use 340h read-write data 342h write command -read status 344h write command -read status 348h write reset [Data = don't care]

The base address (BADR) is decoded in the 74LS688. It is combined with SA1, SA2, and SA3, (BADR+0,2,4) to form HSELN to select the I/O chip and the 245’s. (BADR+2,4) asserts HCMD.

Two addresses are used to be compatible with the first generation products, which used BADR+2 to write command and BADR+4 to read status.

B+8 and IOW* generate a reset pulse, -RS, for the CP chip. The reset instruction is OR'd with RESET on the bus to initialize the PMD chipset when the PC is reset.

MC2500 Technical Specifications

6.3 RS-232 Serial Interface

The interface between the Navigator chipset and an RS-232 serial port is shown in the following figure.

Comments on Schematic

S1 and S2 encode the characteristics of the serial port such as baud rate, number of stop bits, parity, etc. The CP will read these switches during initialization, but these parameters may also be set or changed using the connected directly to the serial port of a PC without requiring a null modem cable.

SetSerialPort chipset command. The DB9 connector wired as shown can be

MC2500 Technical Specifications

6.4 RS 422/485 Serial Interface

The interface between the Navigator chipset and an RS-422/485 serial port is shown in the following figure.

Comments on Schematic

Use the included table to determine the jumper setup that matches the chosen configuration. If using RS485, the last CP must have its jumpers set to RS485 LAST. The DB9 connector wiring is for example only. The DB9 should be wired according to the specification that accompanies the connector to which it is attached.

For correct operation, logic should be provided that contains the start up serial configuration for the chipset. Refer to the RS232 Serial Interface schematic for an example of the required logic.

Note that the RS485 interface cannot be used in point to point mode. It can only be used in a multidrop configuration where the chip SrlEnable line is used to control transmit/receive operation of the serial transceiver.

Chips in a multi-drop environment should not be operated at different baud rates. This will result in communication problems.

MC2500 Technical Specifications

6.5 12-bit A/D Interface

The following schematic shows a typical interface circuit between the Navigator chipset and a quad 12 bit 2’s complement A/D converter used as a position input device.

Comments on Schematic

The A/D converter samples all 4 axes and sequentially converts and stores the 2’s complement digital words. The data is read out sequentially, axis 1 to 4. DACRD- is used to perform the read and is also used to load the counter to FFh. The counter will be reloaded for each read and will not count significantly between reads. The counter will therefore start counting down after the last read

and will generate the cvt- pulse after 12.75 µsec. The conversions will take approximately 35 µsec, and the data will be available for the next set of reads after 50 µsec. The 12 bit words from the A/D

are extended to 16 bits with the 74LS244.

MC2500 Technical Specifications

6.6 16-bit A/D Input

The interface between the Navigator chipset and 16 bit A/D converters as parallel input position devices is shown in the following figure.

Comments on Schematic

The schematic shows a 16 bit A/D used to provide parallel position input to axis 1 and axis 2. The expansion to the remaining two axes is easily implemented. The 374 registers are required on the output of the A/D converters to make the 68-nanosecond access time of the CP. The worst-case timing of the A/D’s specify 83 nanoseconds for data on the bus and 83 nanoseconds from data to tri-state on the bus. Each time the data is read the 169 counter is set to 703 decimal. This provides a

35.2-microsecond delay before the next conversion. With a 10-microsecond conversion time the data will be available for the next set of reads after 50 microseconds. The delay is used to provide a position sample close to the actual position.

MC2500 Technical Specifications

6.7 RAM Interface

The following schematic shows an interface circuit between the Navigator chipset and external ram.

Comments on Schematic

The CP is capable of directly addressing 32K words of 16-bit memory. It will also use a 16 bit paging register to address up to 32K word pages. The schematic shows the paging and addressing for 128KB RAM chips, i.e. 4 pages per RAM chip. The page address decoding is shown for only 6 of the 16 possible paging bits. The decoding time from W/R and DS- to the memory output must not exceed 18 ns. for a read with no wait states. The writes provide 25 extra ns access time for W/R and DS- to reverse the CP data bus.

MC2500 Technical Specifications

6.8 User-defined I/O

The interface between the Navigator chipset and 16 bits of user output and 16 bits of user input is shown in the following figure.

Comments on Schematic

The schematic implements 1 word of user output registered in the 74LS377’s and 1 word of user inputs read via the 244’s. The schematic decodes the low 3 bits of the address to 8 possible UIO addresses UIO0 through UIO7. Registers and buffers are shown for only UIO0, but the implementation shown may be easily extended. The lower 8 address bits may be decoded to provide up to 256 user output words and 256 user input words of 16 bits.

MC2500 Technical Specifications

PMD MC2500 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual