PMD MC1451A, MC1451A-E, MC1151A, MC1151A-E, MC1251A Datasheet
...
Advanced Step Motor
j
Control Chipset
Features
Advanced control of up to 4 step motors
per chipset
High speed pulse and direction output
S-curve, trapezoidal, velocity contouring,
and electronic gearing trajectory modes
Optional incremental encoder feedback
Software & feature compatible with other
versions of PMD's chipset family
Available in 1, 2, or 4 axis configurations
32-bit position, velocity, acceleration and
erk trajectory profile registers
Pulse and direction output for each axis at
up to 1.5 Mpulses/sec
On-the -fly stall detection
Two travel-limit switches per axis
External motion breakpoint per axis
Intelligent easy-to-use packet-oriented
command protocol
Programmable pulse output modes
Chipset Developer's kit available
MC1451A, MC1451A-E
MC1251A, MC1251A-E
MC1151A, MC1151A-E
General Description
The MC1451A is a dedicated motion processor which functions
as a complete chip-based step motor controller . Packaged in a
2-IC chipset, this device performs trajectory generation and
pulse and direction signal generation for use in a wide variety of
stepper-based systems. The MC1451A provides an optional
third IC which allows incremental encoder signal input for
position verificat i on and on-the-fly stall detection. The MC1451A
is available in a one, a two, and a four-axis configuration.
Typical Configuration
Host
Processor
Amp
Amp
MC1451A
(I/O & CP
& ENC)
Amp
Amp
Performance Motion Dev ices, In c. 12 Waltham St. Le xington, M A 02421 te l: 781. 674.98 60 fax: 781.674.9 861
E
M
E
M
(MC1451A, MC1251A
E
M
E
M
Axis 1
Axis 2
only)
Axis 3
(MC1451A only)
Axis 4
(MC1451A only)
The MC1451A is functionally similar to other PMD motion
processors however it is dedicated to the control of step motors,
instead of servo motors. All of these devices provide
sophisticated trajectory generation and synch ronization features
allowing the creation of complex motion sequences.
In addition to pulse and direction circuitry which can output at
up to 1.5 mega pulses per second the chipset provides two limit
switches per axis, a programmabl e external signal b reakpoint
per axis, and an 'At Rest' output signal.
The chipset is controlled by a host processor which interfaces
with the chipset via an 8-bit bi-directional port. Communications
to/from the chi pset consist of packet-oriented messages. A host
interrupt line is provided so tha t t he chipset can signal the host
when special conditions occur such as stall detection.
The chipset is packaged in 2 68-pin PLCC packages. An
optional third 44 pin PLCC chip provides encoder input. All
chips are CMOS and are powered by 5 volts.
Doc. Rev. 12.02, Nov. 1997
www.pmdcorp.com
Table of Contents
Product Family Overview.......................................Page 3
Introduction........................................................... Page 3
Family Summary................................................... Page 3
Electrical Characteristics....................................... Page 4
Absolute Maximum Ratings..................................Page 5
Operating Ratings................................................. Page 5
DC Electrical Characteristics................................ Page 5
AC Electrical Characteristics................................Page 5
I/O Timing Diagrams............................................. Page 7
Pinouts....................................................................Page 11
MC1451A.............................................................. Page 11
MC1251A, MC1151A............................................ Page 12
Pin Descriptions.................................................... Page 13
Theory of Operations............................................. Page 17
Trajectory Profile Generation................................ Page 18
S-curve Point to Point....................................... Page 19
Trapezoidal Point to Point.................................Page 20
Velocity Contouring...........................................Page 20
Electronic Gear.................................................Page 21
Trajectory Control................................................. Page 21
Halting The Trajectory......................................Page 21
Motion Complete Status...................................Page 22
Parameter Loading & Updating............................Page 22
Manual Update.................................................Page 22
Breakpoints....................................................... Page 23
External Breakpoints and Homing.................... Page 23
Disabling Automatic Profile Update..................Page 24
Travel Limit Switches............................................ Page 24
Axis Timing........................................................... Page 24
Host Communications .......................................... Page 25
Electrical Interface............................................ Page 25
Packet Format ...................................................Page 25
Packet Checksum.............................................Page 26
Illegal Commands .............................................Page 26
Command Errors...............................................Page 26
Axis Addressing.................................................Page 26
Axis Status............................................................Page 27
Status Word ......................................................Page 27
Miscellaneous Mode Status Word.....................Page 27
Host Interrupts.......................................................Page 28
Pulse & Direction Signal Generation.....................Page 29
Pulse Generation Control...........................................Page 29
At Rest Indicator.........................................................Page 29
Encoder Position Feedback..................................Page 29
Stall Detection............................................................Page 30
Position Error.............................................................Page 30
Recovering From A Motion Error ...............................Page 30
Host Commands .....................................................Page 32
Command Summary.............................................Page 32
Command Reference............................................Page 34
Axis Control.......................................................Page 34
Profile Generation.............................................Page 35
Parameter Update.............................................Page 39
Interrupt Processing..........................................Page 41
Status/Mode......................................................Page 42
Pulse Generation ..............................................Page 43
Encoder.............................................................Page 44
Miscellaneous ...................................................Page 45
Application Notes ...................................................Page 48
ISA bus interfacing................................................Page 48
Performance Motion Devices, Inc. does not assume any responsibility for use of any circuitry described in this manual, nor does it make
any guarantee as to the accuracy of this manual. Performance Motion Devices, Inc. reserves the right to change the circuitry described in
this manual, or the manual itself, at any time.
The components described in this manual are not authorized for use in life-support systems without the express written permission of
Performance Motion Devices, Inc.
2
Product Family Overview
MC1401 series MC1231 series MC1241 series MC1451 series
# of axes 4, 2, or 1 2 or 1 2 or 1 4, 2, or 1
Motors Supported DC Servo Brushless Servo Stepper Stepper
Encoder Format Incremental (no dash version)
and Parallel ('-P' version)
Output Format DC servo Sinusoidally
S-curve profiling Yes Yes Yes Yes
Electronic gearing Yes Yes Yes Yes
On-the-fly changes Yes Yes Yes Yes
Limit switches Yes Yes Yes Yes
PID & feedforward Yes Yes - -
PWM output Yes Yes Yes -
DAC-compatible output Yes Yes Yes -
Pulse & direction output ---Yes
Index & Home signal Yes Yes Yes Yes
Chipset p/n's MC1401A, MC1401A-P (4 axes)
MC1201A, MC1201A-P (2 axes)
MC1101A, MC1101A-P (1 axis)
Developer's Kit p/n's: DK1401A, DK1401A-P DK1231A DK1241A DK1451A
* optional using third I.C. ('-E' version)
Incremental Incremental Incremental*
Microstepping Pulse and Direction
commutated
MC1231A (2 axes)
MC1131A (1 axis)
MC1241A (2 axes)
MC1141A (1 axis)
MC1451A, MC1451A-E (4 axes)
MC1251A, MC1251A-E (2 axes)
MC1151A, MC1151A-E (1 axis)
Introduction
This manual describes the operational characteristics of the MC1451A,
MC1251A, MC1151A, MC1451A-E, MC1251A-E, and MC1151A-E
Motion Processors. These devices are members of PMD's 1st
generation motion processor family, which consists of 16 separate
products organized into four groups.
Each of these devices are complete chip-based motion controllers.
They provide trajectory generation and related motion control functions.
Depending on the type of motor controlled they provide servo loop
closure, on-board commutation for brushless motors, and high speed
pulse and direction outputs. Together these products provide a
software-compatible family of dedicated motion processor chips which
can handle a large variety of system configurations.
Each of these chips utilize a similar architecture, consisting of a highspeed DSP (Digital Signal Processor) computation unit , along with an
ASIC (Application Specific Integrated Circuit). The computation unit
contains special on-board hardware such as a multiply instruction that
makes it well suited for the task of motion control.
Along with a similar hardware architecture these chips also share most
software commands, so that software written for one chipset may be reused with another, even though the type of motor may be different.
This manual describes the operation of the MC1451A, MC1251A,
MC1151A, MC1451A-E, MC1251A-E, and MC1151A-E chipsets. For
technical details on other members of PMD's first generation
motion processors see the corresponding product manual.
Family Summary
MC1401 series (MC1401A, MC1201A, MC1101A, MC1401A-P,
MC1201A-P, MC1101A-P)
encoder signals (standard version) or parallel word encoder signals
(-P version) and output a motor command in either PWM or DACcompatible format. These chipsets come in 1, 2 or 4 axis versions
and can be used with DC brushed motors, or brushless motors using
external commutation.
MC1231 series (MC1231A, MC1131A) -
incremental quadrature encoder signals and output sinusoidally
commutated motor signals appropriate for driving brushless motors.
They are available in one or two axis versions. Depending on the
motor type they output two or three phased signals per axis in either
PWM or DAC-compatible format.
MC1241 series (MC1241A, MC1141A)
internal microstepping generation for stepping motors. They are
available in a one or a two-axis version. Two phased signals are
output per axis in either PWM or DAC-compatible format. An
incremental encoder signal can be input to confirm motor position.
MC1451 series (MC1451A, MC1251A, MC1151A, MC1451A-E,
MC1251A-E, MC1151A-E) -
pulse and direction signal output appropriate for driving step motorbased systems. They are available in a one, two, or four-axis version
and are also available with quadrature encoder input.
Each of these chipsets has an associated Chipset Developer's
Kit available for it. For more information contact your PMD
representative.
- These chipsets take in incremental
These chipsets take in
- These chipsets provide
These chipsets provide very high speed
3
Electrical Characteristics
Overview
The MC1451A-consists of either two 68 pin PLCC's (standard version),
or these same two I.C.s with an additional 44 pin PLCC for incremental
encoder feedback (-E version). All of these devices are fabricated in
CMOS. The two 68 pin PLCCs are known as the I/O and the CP chips.
The 44-pin PLCC is known as the ENC chip.
The Peripheral Input/Output IC (I/O chip) is responsible for interfacing
to the host processor and for generating the high speed pulse and
direction output. The Command Processor IC (CP chip) is responsible
for all host command, trajectory, and related computations. The ENC
chip is responsible for incremental encoder feedback.
The following figure shows a typical system block diagram, along with
the pin connections between the I/O chip, CP chip, and ENC chip if it is
used.
Motor
(4 axis)
Amplifier
(1-4 axis)
I/O
Host
Processor
Data4-11
I/OAddr0-3
I/OWrite
I/OCntrl0-3
ClkOut
CP
Data4-11
I/OAddr0-3
I/OWrite
I/OCntrl0-3
ClkOut
Use of the ENC chip does not require a special version of the I/O or CP
chips. The CP chip automatically recognizes the presence or absence
of the ENC chip and functions accordingly.
The CP, I/O, and ENC chip (if used) form a complete chipset and
function together as one integrated motion processor. The major
components connected to the chipset are the step & direction
compatible amplifier (4, 2, or 1 axes), the optional encoder feedback
channels (4, 2, or 1 axes), and the host processor.
The chipset's pulse and direction output signals are connected to the
motor amplifier. Using this scheme the direction bit indicates whether
the motor should move in the positive or negative direction, and the
pulse signal indicates the desired motor speed. Pulse and direction
output is compatible with a wide variety of full, half, and microstepping
amplifiers.
Encoder
(1-4 axis)
ENC
Using the -E chipset parts it is possible to input quadrature encoder
feedback to the chipset. The encoder signals consist of the A and B
quadrature signals from the encoder.
The host processor is interfaced via an 8-bit bi-directional bus and
various control signals. Host communication is coordinated by a
ready/busy signal, which indicates when communication is allowed.
Interconnections between the I/O and the CP chip consist of a data bus
(8 bits) and various control and synchronization signals.
Interconnections between the CP and the ENC chip (if used) also
consist of a data bus (10 bits) and various control and synchronization
signals. Many of these signals are common between the I/O, CP, and
the ENC chips although there are no direct connections between just
the ENC and the I/O chip. The following table summarizes the signals
that must be interconnected for the chipset to function properly. For
each listed signal the I/O chip pin on the left side of the table is
connected to the CP chip pin in the middle which is connected to the
ENC chip pin on the right side.
I/O Chip
Signal
Name
I/O
Chip
Pin
CP Chip
Signal
Name
CP
Chip
Pin
ENC Chip
Signal
Name
ENC
Chip
Pin
- - Data2 58 CPData2 22
- - Data3 57 CPData3 19
CPData4 18 Data4 50 CPData4 9
CPData5 5 Data5 49 CPData5 31
CPData6 6 Data6 46 CPData6 41
CPData7 7 Data7 43 CPData7 42
CPData8 8 Data8 40 CPData8 44
CPData9 17 Data8 39 CPData9 1
CPData10 3 Data10 36 CPData10 12
CPData11 1 Data11 35 CPData11 2
CPAddr0 68 I/OAddr0 28 CPAddr0 24
CPAddr1 27 I/OAddr1 9 - CPAddr2 29 I/OAddr2 6 CPAddr2 20
CPAddr3 12 I/OAddr3 5 CPAddr3 23
CPCntr0 20 I/OCntr0 16 CPCntr0 15
CPCntr1 36 I/OCntr1 18 - CPCntr2 22 I/OCntr2 68 - CPCntr3 63 I/OCntr3 67 - CPWrite 2 I/OWrite 15 CPWrite 13
CPClk 46 ClkOut 19 CPClk 7
CPReset 43 Reset 17 - -
For a complete description of all pins see the 'Pin Descriptions'
section of this manual.
Unless specifically noted otherwise, the term 'MC1451' or
'MC1451A' refers to the MC1451A, MC1251A, MC1151A, MC1451AE, MC1251A-E, and MC1151A-E Motion Processors.
4
Absolute Maximum Ratings
Operating Ratings
Unless otherwise stated, all electrical specifications are for both
the I/O and CP chips.
Storage Temperature, Ts....................-55 deg. C to +150 deg. C
Supply Voltage, Vcc............................ -0.3 V to +7.0 V
Power Dissipation, Pd......................... 650 mW (I/O and CP
combined)
Operating Temperature, Ta .................0 deg. C to +70 deg. C*
Nominal Clock Frequency, Fclk...........25.0 Mhz
Supply Voltage, Vcc.............................4.75 V to 5.25 V
* Industrial and Military operating ranges also available. Contact your
PMD representative for more information.
DC Electrical Characteristics
(Vcc and Ta per operating ratings, Fclk = 25.0 Mhz)
Symbol Parameter Min. Max. Units Conditions
Vcc Supply Voltage 4.75 5.25 V
Idd Supply Current 100 mA open outputs
Input Voltages
Vih Logic 1 input voltage 2.0 Vcc + 0.3 V
Vil Logic 0 input voltage -0.3 0.8 V
Vihclk Logic 1 voltage for clock pin
(ClkIn)
Vihreset Logic 1 voltage for reset pin
(reset)
Output Voltages
Voh Logic 1 Output Voltage 2.4 V @CP Io = 300 uA
Vol Logic 0 Output Voltage 0.33 V @CP Io = 2 mA
Iout Tri-State output leakage current -20 20 uA 0 < Vout < Vcc
Iin Input current -50 50 uA 0 < Vi < Vcc
Iinclk Input current ClkIn -20 20 uA 0 < Vi < Vcc
3.0 Vcc+0.3 V
4.0 Vcc+0.3 V
@I/O Io = 4 mA
@I/O Io = 4 mA
AC Electrical Characteristics
(see reference timing diagrams)
(Vcc and Ta per operating ratings; Fclk = 25.0 Mhz)
(~ character indicates active low signal)
Timing Interval T# Min. Max. Units
Encoder and Index Pulse Timing
Motor-Phase Pulse Width T1 1.6 uS
Dwell Time Per State T2 0.8 uS
Index Pulse Setup and Hold
(relative to Quad A and Quad B low)
Reset Timing
Stable Power to Reset 0.25 Sec
Reset Low Pulse Width 1.0 uS
Clock Timing
Clock Frequency (Fclk) 6.7 25.6 Mhz
Clock Pulse Width T4 19.5 75 (note 2) nS
Clock Period T5 39 149 (note 2) nS
T3 0 uS
5
Timing Interval T# Min. Max. Units
Command Byte Write Timing
~HostSlct Hold Time T6 15 2000 (note 3) nS
~HostSlct Setup Time T7 10 nS
HostCmd Setup Time T8 10 nS
Host Cmd Hold Time T9 25 nS
HostRdy Delay Time T13 70 nS
~HostWrite Pulse Width T14 50 nS
Write Data Setup Time T15 35 nS
Write Data Hold Time T16 30 nS
Data Word Read Timing
~HostSlct Hold Time T6 15 2000 (note 3) nS
~HostSlct Setup Time T7 (read only) - 20 nS
HostCmd Setup Time T8 (read only) - 20 nS
HostCmd Hold Time T9 25 nS
Read Data Access Time T10 50 nS
Read Data Hold Time T11 10 nS
~HostRead high to HI-Z Time T12 50 nS
HostRdy Delay Time T13 70 nS
Read Recovery Time T17 60 nS
Data Word Write Timing
~HostSlct Hold Time T6 15 2000 (note 3) nS
~HostSlct Setup Time T7 10 nS
HostCmd Setup Time T8 10 nS
HostCmd Hold Time T9 25 nS
HostRdy Delay Time T13 70 nS
~HostWrite Pulse Width T14 50 nS
Write Data Setup Time T15 35 nS
Write Data Hold Time T16 30 nS
Write Recovery Time T18 60 nS
note 1 ~HostSlct and HostCmd may optionally be de-asserted if setup and hold times are met.
note 2 Chip-set performance figures and timing information valid at Fclk = 25.0 only. For timing information & performance parameters at Fclk <
25.0 Mhz, call PMD.
note 3 Two micro seconds maximum to release interface before chip set responds to command
note 4 ClkOut from CP is 1/4 frequency of ClkIn (CP chip).
6
I/O Timing Diagrams
The following diagrams show the MC1451A electrical interface timing. T#' values are listed in the above timing chart.
Quadrature Encoder Input Timing
Quad A
Quad B
~Index
ClkIn
T1
T1
T2 T2
T3
Clock Timing
T3
T4 T4 T5
Index = ~A * ~B * ~IN D
7
Command Byte Write TIming
~HostSlct
HostCmd
~HostWrite
HostData0-7
HostRdy
T7
T8
T6
T9
T14
T15
T16
T13
8
Data Word Read TImi ng
~HostSlct
HostCmd
~HostRead
HostData0-7
HostRdy
T7
T6
Note 1
T8
Note 1
T9
T17
T12
High-Z High-Z High-Z
High
Byte
T10
T11
Low
Byte
T13
9
Data Word Write TIming
~HostSlct
HostCmd
~HostWrite
HostData0-7
HostRdy
T7
T8
T14
T15
High
Byte
T16
T18
Note 1
Note 1
T6
T9
T14
T15
Low
Byte
T16
10
T13
Pinouts
9
10
(Top view)
26
27 43
4, 21, 25, 38, 55
28
Pulse1
42
Dir1
13
Home1
26
Pulse2
30
Dir2
23
Home2
40
Pulse3
35
Dir3
11
Home3
39
Pulse4
34
Dir4
10
Home4
46
CPClk
52
I/OClkIn
45
I/OClkOut
29
CPAddr2
12
CPAddr3
2
CPWrite
20
CPCntrl0
36
CPCntrl1
43
CPReset
1
I/O
VCC
I/O
GND
61
CPCntrl2
CPCntrl3
HostCmd
HostRdy
HostRead
HostWrite
HostSlct
HostIntrpt
HostData0
HostData1
HostData2
HostData3
HostData4
HostData5
HostData6
HostData7
CPData4
CPData5
CPData6
CPData7
CPData8
CPData9
CPData10
CPData11
CPAddr0
CPAddr1
9
60
10
1
CP
(Top view)
44
26
27 43
(Chip Outlines Not Drawn To Scale)
MC1451A & MC1451A-E Pinouts
4, 22, 33
22
63
41
37
51
47
48
44
56
50
61
53
65
67
62
64
60
18
5
6
7
8
17
3
1
68
27
AtRest1
55
AtRest2
54
AtRest3
53
AtRest4
24
ClkIn
19
ClkOut
17
Reset
16
I/OCntrl0
18
I/OCntrl1
68
I/OCntrl2
67
I/OCntrl3
VCC
CP
GND
61
Data2
Data3
Data4
Data5
Data6
Data7
Data8
Data9
Data10
Data11
I/OAddr0
I/OAddr1
I/OAddr2
I/OAddr3
I/OWrite
PosLimit1
PosLimit2
PosLimit3
PosLimit4
NegLimit1
NegLimit2
NegLimit3
NegLimit4
6
60
7
1
40
39
ENC
(Top view)
17
44
18 28
58
57
50
49
46
43
40
39
36
35
28
9
6
5
15
52
45
42
38
51
44
41
37
30
36
17
18
27
28
5
29
7
33
6
3, 14, 16, 25, 35
QuadA1
QuadB1
QuadA2
QuadB2
QuadA3
QuadB3
QuadA4
QuadB4
CPClk
I/OClkIn
I/OClkOut
10, 21, 32, 34, 43
VCC
ENC
GND
CPAddr0
CPAddr2
CPAddr3
CPWrite
CPCntrl0
CPData2
CPData3
CPData4
CPData5
CPData6
CPData7
CPData8
CPData9
CPData10
CPData11
29
24
20
23
13
15
22
19
9
31
41
42
44
1
12
2
14, 15, 32, 49, 54, 66
3, 34
11
MC1251A & MC1251A-E Pinouts
4, 21, 25, 38, 55
VCC
28
Pulse1
42
Dir1
13
Home1
26
Pulse2
30
Dir2
23
Home2
46
CPClk
52
I/OClkIn
45
I/OClkOut
29
CPAddr2
12
CPAddr3
2
CPWri t e
20
CPCntrl0
36
CPCntrl1
43
CPReset
I/O
GND
14, 15, 32, 49, 54, 66
CPCntrl2
CPCntrl3
HostCmd
HostRdy
HostRead
HostWrite
HostSlct
HostIntrpt
HostData0
HostData1
HostData2
HostData3
HostData4
HostData5
HostData6
HostData7
CPData4
CPData5
CPData6
CPData7
CPData8
CPData9
CPData10
CPData11
CPAddr0
CPAddr1
22
63
41
37
51
47
48
44
50
61
53
65
67
62
64
60
18
5
6
7
8
17
3
1
68
27
AtRest1
56
AtRest2
55
ClkIn
24
ClkOut
19
Reset
17
I/OCntrl0
16
I/OCntrl1
18
I/OCntrl2
68
I/OCntrl3
67
4, 22, 33
VCC
CP
GND
3, 34
Data2
Data3
Data4
Data5
Data6
Data7
Data8
Data9
Data10
Data11
I/OAddr0
I/OAddr1
I/OAddr2
I/OAddr3
I/OWrite
PosLimit1
PosLimit2
NegLimit1
NegLimit2
3, 14, 16, 25, 35
58
57
50
49
46
43
40
39
36
35
28
9
6
5
15
52
45
51
44
QuadA1
30
QuadB1
36
QuadA2
17
QuadB2
18
CPClk
7
I/OClkIn
33
I/OClkOut
6
VCC
ENC
CPData10
CPData11
GND
10, 21, 32, 34, 43
CPAddr0
CPAddr2
CPAddr3
CPWrite
CPCntrl0
CPData2
CPData3
CPData4
CPData5
CPData6
CPData7
CPData8
CPData9
24
20
23
13
15
22
19
9
31
41
42
44
1
12
2
MC1151A & MC1151A-E Pinouts
4, 21, 25, 38 , 55
VCC
28
Pulse1
42
Dir1
13
Home1
46
CPClk
52
I/OClkIn
45
I/OClkOut
29
CPAddr2
12
CPAddr3
2
CPWri t e
20
CPCntrl0
36
CPCntrl1
43
CPReset
I/O
GND
14, 15, 32, 49, 54, 66
CPCntrl2
CPCntrl3
HostCmd
HostRdy
HostRead
HostWrite
HostSlct
HostIntrpt
HostData0
HostData1
HostData2
HostData3
HostData4
HostData5
HostData6
HostData7
CPData4
CPData5
CPData6
CPData7
CPData8
CPData9
CPData10
CPData11
CPAddr0
CPAddr1
22
63
41
37
51
47
48
44
50
61
53
65
67
62
64
60
18
5
6
7
8
17
3
1
68
27
56
AtRest1
24
ClkIn
19
ClkOut
17
Reset
16
I/OCntrl0
18
I/OCntrl1
68
I/OCntrl2
67
I/OCntrl3
4, 22, 33
VCC
CP
GND
3, 34
Data2
Data3
Data4
Data5
Data6
Data7
Data8
Data9
Data10
Data11
I/OAddr0
I/OAddr1
I/OAddr2
I/OAddr3
I/OWrite
PosLimit1
NegLimit1
3, 14, 16, 25, 35
58
57
50
49
46
43
40
39
36
35
28
9
6
5
15
52
51
QuadA1
30
QuadB1
36
CPClk
7
I/OClkIn
33
I/OClkOut
6
VCC
ENC
CPData10
CPData11
GND
10, 21, 32, 34, 43
CPAddr0
CPAddr2
CPAddr3
CPWr ite
CPCntrl0
CPData2
CPData3
CPData4
CPData5
CPData6
CPData7
CPData8
CPData9
24
20
23
13
15
22
19
9
31
41
42
44
1
12
2
12
Pin Descriptions
The following tables provide pin descriptions for the MC1401 and MC1401-P series chipsets.
IC Pin Name Pin # Description/Functionality
I/O Chip Pinouts
I/O Pulse1
Pulse2
Pulse3
Pulse4
I/O Dir1
Dir2
Dir3
Dir4
I/O ~Home1
~Home2
~Home3
~Home4
I/O CPClk 46 I/O chip clock (input). This signal is connected directly to the ClkOut pin (CP chip) and
I/O I/OClkIn 52 Phase shifted clock (input). This signal is connected to I/OClkOut (I/O chip), and inputs a
I/O I/OClkOut 45 Phase shifted clock (output). This signal is connected to I/OClkIn (I/O chip), and outputs a
I/O CPAddr0
CPAddr1
CPAddr2
CPAddr3
I/O ~CPWrite 2 I/O chip to CP chip communication write (input). This signal is connected to the ~I/OWrite pin
I/O CPCntrl0
CPCntrl1
CPCntrl2
CPCntrl3
I/O HostCmd 41 Host Port Command (input). This signal is asserted high to write a host command to the chip
I/O HostRdy 37 Host Port Ready/Busy (output). This signal is used to synchronize communication between
28
26
40
39
42
30
35
34
13
23
11
10
68
27
29
12
20
36
22
63
Pulse signal for channels 1-4 (output). This signal is always a square wave, regardless of
pulse rate. Nominal 'step' occurs when signal goes from a high state to a low state.
NOTE: For MC1451A all 4 pins are valid. For MC1251A pins for axes 1 & 2 only are valid.
For MC1151A pins for axis 1 only are valid. Invalid axis pins can be left unconnected.
Direction signal for channels 1-4 (output). This signal indicates the direction of motion, and
works in conjunction with the pulse signal. A high level on this signal indicates a positive
direction move, and a low level indicates a negative direction move.
NOTE: For MC1451A all 4 pins are valid. For MC1251A pins for axes 1 & 2 only are valid.
For MC1151A pins for axis 1 only are valid. Invalid axis pins can be left unconnected.
Home signals for axis 1-4 (input). Each of these signals provide a general purpose input to
the external breakpoint mechanism. Using these signals it is possible to stop, start, or alter
the motion trajectory. See theory of operations for details.
An active home signal is recognized by the chipset as a low state.
NOTE: For MC1451A all 4 pins are valid. For MC1251A pins for axes 1 & 2 only are valid.
For MC1151A pin for axis 1 only is valid. Invalid axis pins can be left unconnected.
provides the clock signal for the I/O chip. The frequency of this signal is 1/4 the user-provided
ClkIn (CP chip) frequency.
phase shifted clock signal.
phase shifted clock signal.
I/O chip to CP chip communication address (input). These 4 signals are connected to the
corresponding I/OAddr0-3 pins (CP chip), and together provide addressing signals to
facilitate CP to I/O chip communication.
(CP chip) and provides a write strobe to facilitate CP to I/O chip communication.
I/O chip to CP chip communication control (mixed). These 4 signals are connected to the
corresponding I/OCntrl0-3 pins (CP chip), and provide control signals to facilitate CP to I/O
chip communication.
set. It is asserted low to read or write a host data word to the chipset
the DSP and the host. HostRdy will go low (indicating host port busy) at the end of a host
command write or after the second byte of a data write or read. HostRdy will go high
(indicating host port ready) when the command or data word has been processed and the
chip set is ready for more I/O operations. All host port communications must be made with
HostRdy high (indicating ready).
Typical busy to ready cycle is 82.5 uSec..
13
IC Pin Name Pin # Description/Functionality
I/O ~HostRead 51 Host Port Read data (input). Used to indicate that a data word is being read from the chip set
(low asserts read).
I/O ~HostWrite 47 Host Port Write data (input). Used to indicate that a data word or command is being written to
the chip set (low asserts write).
I/O ~HostSlct 48 Host Port Select (input). Used to select the host port for reading or writing operations (low
assertion selects port). ~HostSlct must remain inactive (high) when the host port is not in use.
I/O ~HostIntrpt 44 Host Interrupt (output). A low assertion on this pin indicates that a host interrupt condition
exists that may require special host action.
I/O HostData0
HostData1
HostData2
HostData3
HostData4
HostData5
HostData6
HostData7
I/O CPData4
CPData5
CPData6
CPData7
CPData8
CPData9
CPData10
CPData11
I/O ~CPReset 43 I/O chip set reset (input). When brought low this pin resets the I/O chip to its initial condition.
I/O Vcc 4, 21, 25, 38, 55 I/O chip supply voltage pin. All of these pins must be connected to the supply voltage. Supply
I/O GND 14, 15, 32, 49, 54,66I/O chip ground pin. All of these pins must be connected to the power supply return.
50
61
53
65
67
62
64
60
18
5
6
7
8
17
3
1
Host Port Data 0-7 (bi-directional, tri-stated). These signals form the 8 bit host data port used
during communication to/from the chip set. This port is controlled by ~HostSlct, ~HostWrite,
~HostRead and HostCmd.
I/O chip to CP chip data port (bi-directional). These 8 bits are connected to the corresponding
Data4-11 pins on the CP chip, and facilitate communication to/from the I/O and CP chips..
Reset should occur no less than 250 mSec after stable power has been provided to the chip
set. This signal should be connected to the ~Reset pin of the CP chip, which in turn should
be connected to the master reset signal.
voltage = 4.75 to 5.25 V
IC Pin Name Pin # Description/Functionality
CP Chip Pinouts
CP AtRest1
AtRest2
AtRest3
AtRest4
CP PosLimit1
PosLimit2
PosLimit3
PosLimit4
56
55
54
53
52
45
42
38
At Rest indicator signals for axes 1-4 (output). A high level on this signal indicates the axis is
at rest. A low signal indicates the axis is in motion.
This signal is useful for driving amplifiers with an input bit to control running and holding
torque.
NOTE: For MC1451A all 4 pins are valid. For MC1251A pins for axes 1 & 2 only are valid.
For MC1151A pin for axis 1 only is valid. Invalid axis pins can be left un connected.
Positive limit switch input for axis 1-4. These signals provide directional limit inputs for the
positive-side travel limit of the axis. Upon powerup these signals default to "active high"
interpretation, but the interpretation can be set explicitly using the SET_LMT_SENSE
command. If not used these signals should be tied low for the default interpretation, or tied
high if the interpretation is reversed.
NOTE: For MC1451A all 4 pins are valid. For MC1251A pins for axes 1 & 2 only are valid.
For MC1151A pin for axis 1 only is valid. Invalid axis pins can be left un connected.
14
IC Pin Name Pin # Description/Functionality
CP NegLimit1
NegLimit2
NegLimit3
NegLimit4
CP ClkIn 24 Clock In (input). This pin provides the chip set master clock (Fclk = 25.0 Mhz)
CP ClkOut 19 Clock Out (output). This pin provides a clock output which is 1/4 the ClkIn frequency. This pin
CP ~Reset 17 Master chip set reset (input). When brought low, this pin resets the chip set to its initial
CP I/OCntrl0
I/OCntrl1
I/OCntrl2
I/OCntrl3
CP Data2
Data3
Data4
Data5
Data6
Data7
Data8
Data9
Data10
Data11
CP I/OAddr0
I/OAddr1
I/OAddr2
I/OAddr3
CP I/OWrite 15 Write (output). This pin is connected to CPWrite on the I/O and on the ENC chip. It provides a
CP Vcc 4, 22, 33 CP chip supply voltage pin. All of these pins must be connected to the supply voltage. Supply
CP GND 3, 34 CP chip ground pin. All of these pins must be connected to the power supply return.
51
44
41
37
16
18
68
67
58
57
50
49
46
43
40
39
36
35
28
9
6
5
Negative limit switch input for axis 1-4. These signals provide directional limit inputs for the
negative-side travel limit of the axis. Upon powerup these signals default to "active high"
interpretation, but the interpretation can be set explicitly using the SET_LMT_SENSE
command. If not used these signals should be tied low for the default interpretation, or tied
high if the interpretation is reversed.
NOTE: For MC1451A all 4 pins are valid. For MC1251A pins for axes 1 & 2 only are valid.
For MC1151A pin for axis 1 only is valid. Invalid axis pins can be left un connected.
is connected to the CPClk signals of the I/O chip and ENC chip
condition. Reset should occur no less than 250 mSec after stable power has been provided
to the chip set.
The master reset signal should be connected to this pin as well as the ~CPReset pin of the
I/O chip
I/O and ENC chip to CP chip communication control (mixed). These signals provide various
inter-chip control signals for the I/O and ENC chips. For the I/O chip these four signals are
connected to the corresponding CPCntrl0-3 pins. For the ENC chip only I/OCntrl0 is used
which is connected to the CPCntrl0 pin.
CP to I/O and ENC chip Data4-11. (Bi-directional). These pins are connected to the
corresponding CPData4-11 pins on the I/O chip, and on the corresponding CPData2-11 pins
on the ENC chip. These signals are used to communicate between the CP and the I/O and
ENC chips.
Address0-3 (output). These signals provide various inter-chip address control signals for the
I/O and ENC chips. For the I/O chip these four signals are connected to the corresponding
CPAddr0-3 pins. For the ENC chip only I/OAddr0, I/OAddr2, and I/OAddr3 are used and they
are connected to the corresponding pins on the ENC chip.
control signal to the I/O and ENC chip to facilitate communication between these chips and
the CP chip
voltage = 4.75 to 5,.25 V
15
IC Pin Name Pin # Description/Functionality
ENC Chip Pinouts
ENC QuadA1
QuadB1
QuadA2
QuadB2
QuadA3
QuadB3
QuadA4
QuadB4
ENC CPClk 7 ENC chip clock (input). This signal is connected directly to the I/OClkOut pin (CP chip) and
ENC ENCClkIn 33 Phase shifted clock (input). This signal is connected to ENCClkOut (ENC chip), and inputs a
ENC ENCClkOut 6 Phase shifted clock (output). This signal is connected to ENCClkIn (ENC chip), and outputs a
ENC CPAddr0
CPAddr2
CPAddr3
ENC ~CPWrite 13 ENC chip to CP chip communication write (input). This signal is connected to the ~I/OWrite
ENC CPCntrl0 15 ENC chip to CP chip communication control (input). This signal is connected to the I/OCntrl0
ENC CPData2
CPData3
CPData4
CPData5
CPData6
CPData7
CPData8
CPData9
CPData10
CPData11
ENC Vcc 3, 14, 16, 25, 35 ENC chip supply voltage pin. All of these pins must be connected to the supply voltage.
ENC GND 10, 21, 32, 34, 43 ENC chip ground pin. All of these pins must be connected to the power supply return.
30
36
17
18
27
28
5
29
24
20
23
22
19
9
31
41
42
44
1
12
2
Quadrature A, B channels for axis 1 - 4 (input). Each of these 4 pairs of quadrature (A, B)
signals provide the position feedback for an incremental encoder. When the encoder is
moving in the positive, or forward direction, the A signal leads the B signal by 90 degs.
NOTE: Many encoders require a pull-up resistor on each of these signals to establish a
proper high signal (check the encoder electrical specifications)
NOTE: For MC1451A-E all 8 pins are valid. For MC1251A-E pins for axes 1 & 2 only are
valid. For MC1151A-E pins for axis 1 only are valid. Invalid axis pins can be left unconnected.
provides the clock signal for the ENC chip. The frequency of this signal is 1/4 the userprovided ClkIn (CP chip) frequency.
phase shifted clock signal.
phase shifted clock signal.
ENC chip to CP chip communication address (input). These 3 signals are connected to the
corresponding CPAddr0, 2, & 3 pins (CP chip), and together provide addressing signals to
facilitate CP to ENC chip communication.
NOTE: There is no CPAddr1 pin on the ENC chip.
pin (CP chip) and provides a write strobe to facilitate CP to ENC chip communication.
pin (CP chip), and provides control signals to facilitate CP to ENC chip communication.
ENC chip to CP chip data port (bi-directional). These 10 bits are connected to the
corresponding Data2-11 pins on the CP chip, and facilitate communication to/from the ENC
and CP chips.
Supply voltage = 4.75 to 5.25 V
16
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