PMD MC1241A, MC1141A Datasheet

Features

64

128

192

256

Phase A

Phase B

320

Internal generation of microstepping signals
2-phase as well as 3-phase st epper motors
64 microsteps per ful l step
S-curve, trapezoidal, and veloc ity profile
trajectory modes
Incremental encoder feedback
On-the-fly motor stall detection
Software & feature compatible with other
versions of PMD's chipset family
Available in 1 or 2 axis configurations
32-bit position, v elocity, acceleration and jerk

Advanced Microsteppin g

Motion Control Chipset

MC1241A
MC1141A

trajectory profile registers
Electronic Gearing
Two travel-limit switches per axis
Choice of PWM or DAC motor out put signals
Chipset Developer's Kit Available

Microstepping Waveforms

2-Phase Step per

90 Deg

Microsteps

3-Phase Step per

Phase A Phase B Phase C

General Description

The MC1241A is a dedicated motion processor which functions as a
complete chip-based stepper motor controller. Packaged in a 2-IC
chipset, this device performs trajectory profile generation and
microstepping signal generation. The chipset outputs PWM or
DAC-compatible motor command signals which directly drive the
windings of the stepping motor, eliminating the need for external
microstepping circuitry. The MC1241A also provides the ability to
input incremental encoder signals. It is available in a one, or a two-axis
configuration.

The MC1241A is functionally similar to other members of PMD's 1st
Generation Motion Processor Family however it adds the ability to
perform micrstepping signal generation. All of these devices provide
sophisticated trajectory generation allowing the creation of complex
motion sequences.

Both two and three-phase stepping motors are supported by the
MC1241A. An internal ROM-based lookup table is used to generate
the microstepping waveforms. The motor power level can be controlled
with a resolution of 16 bits. Changes to the motor power level can be
coordinated with other profile changes to optimize motor heat
dissipation under different load and acceleration conditions.

The chipset is controlled by a host processor which interfaces with the
chipset via an 8-bit, bi-directional port. Communications to/from the
chipset consist of packet-oriented messages.

The chipset is packaged in 2 68-pin PLCC packages. Both chips utilize

120 Deg

Performance Motion Dev ices, In c. 12 Waltham St. Le xington, M A 02421 te l: 781. 674.98 60 fax: [phone]

CMOS technology and are powered by 5 volts.

Doc. Rev. 11.03, Nov 1997

www.pmdcorp.com

Table of Contents

Product Family Overview.......................................Page 3

Introduction........................................................... Page 3

Family Summary................................................... Page 3

Electrical Characteristics....................................... Page 4

Absolute Maximum Ratings..................................Page 4

Operating Ratings................................................. Page 4

DC Electrical Characteristics................................ Page 5

AC Electrical Characteristics................................Page 5

I/O Timing Diagrams............................................. Page 7

Pinouts....................................................................Page 12

MC1241A, MC1141A Pinouts............................... Page 12

Pin Descriptions.................................................... Page 13

Theory of Operations............................................. Page 17

Operational Parameters.......................................Page 18

Trajectory Profile Generation................................ Page 18

S-curve Point to Point....................................... Page 19

Trapezoidal Point to Point.................................Page 20

Velocity Contouring...........................................Page 20

Electronic Gear.................................................Page 21

Trajectory Control..........................................................Page 21

Halting The Trajectory......................................Page 21

Motion Complete Status...................................Page 22

Parameter Loading & Updating............................Page 22

Manual Update.................................................Page 22

Breakpoints....................................................... Page 23

Disabling Automatic Profile Update..................Page 23

Travel Limit Switches........................................ Page 23

Axis Timing........................................................... Page 24

Host Communications .......................................... Page 25

Electrical Interface............................................ Page 25

Packet Format..................................................Page 25

Packet Checksum............................................. Page 26

Illegal Commands............................................. Page 26

Command Errors..............................................Page 26

Axis Addressing................................................ Page 27

Axis Status............................................................ Page 27

Status Word......................................................Page 27

Miscellaneous Mode Status Word.................... Page 27

Host Interrupts.......................................................Page 28

Encoder Position Feedback..................................Page 29

High Speed Position Capture............................Page 29

Position Capture ReadBack..............................Page 29

Stall Detection...................................................Page 29

Position Error....................................................Page 30

Recovering From A Motion Error......................Page 30

Microstepping........................................................Page 30

Microstepping Waveforms.................................Page 31

Motor Command Control...................................Page 31

AC Induction Motor Control...............................Page 31

Command Summary.........................................Page 32

Motor Output.........................................................Page 32

Motor Output Signal Interpretation....................Page 32

DAC16 Decoding...............................................Page 32

PWM Decoding.................................................Page 32

Motor Drive Configurations ...............................Page 33

3-Phase Drive Configuration.............................Page 33

Host Commands .....................................................Page 34

Command Summary.............................................Page 34

Command Reference............................................Page 36

Axis Control.......................................................Page 36

Profile Generation.............................................Page 37

Parameter Update.............................................Page 41

Interrupt Processing..........................................Page 43

Status/Mode......................................................Page 44

Motor Control....................................................Page 45

Encoder.............................................................Page 46

Miscellaneous ...................................................Page 48

Microstepping....................................................Page 49

Application Notes ...................................................Page 52

Interfacing MC1241A to ISA bus...........................Page 52

PWM Motor Interface............................................Page 54

16-Bit Serial DAC Motor interface.........................Page 56

Performance Motion Devices, Inc. does not assume any responsibility for use of any circuitry described in this manual, nor does it make
any guarantee as to the accuracy of this manual. Performance Motion Devices, Inc. reserves the right to change the circuitry described in
this manual, or the manual itself, at any time.

The components described in this manual are not authorized for use in life-support systems without the express written permission of
Performance Motion Devices, Inc..

2

Product Family Overview

MC1401 series MC1231 series MC1241 series MC1451 series

# of axes 4, 2, or 1 2 or 1 2 or 1 4, 2, or 1

Motors Supported DC Servo Brushless Servo Stepper Stepper

Encoder Format Incremental (no dash version)

and Parallel ('-P' version)

Output Format DC servo Sinusoidally

S-curve profiling Yes Yes Yes Yes

Electronic gearing Yes Yes Yes Yes

On-the-fly changes Yes Yes Yes Yes

Limit switches Yes Yes Yes Yes

PID & feedforward Yes Yes - -

PWM output Yes Yes Yes -

DAC-compatible output Yes Yes Yes -

Pulse & direction output ---Yes

Index & Home signal Yes Yes Yes Yes (-E version)

Chipset p/n's MC1401A, MC1401A-P (4 axes)

MC1201A, MC1201A-P (2 axes)
MC1101A, MC1101A-P (1 axis)

Developer's Kit p/n's: DK1401A, DK1401A-P DK1231A DK1241A DK1451A

Incremental Incremental Incremental (-E version)

Microstepping Pulse and Direction

commutated

MC1231A (2 axes)
MC1131A (1 axis)

MC1241A (2 axes)
MC1141A (1 axis)

MC1451A, MC1451A-E (4 axes)
MC1251A, MC1251A-E (2 axes)
MC1151A, MC1151A-E (1 axis)

Introduction

This manual describes the operational characteristics of the MC1241A
and MC1141A Motion Processors. These devices are members of
PMD's 1st generation motion processor family, which consists of 16
separate products organized into four groups.

Each of these devices are complete chip-based motion controllers.
They provide trajectory generation and related motion control functions.
Depending on the type of motor controlled they provide servo loop
closure, on-board commutation for brushless motors, and high speed
pulse and direction outputs. Together these products provide a
software-compatible family of dedicated motion processor chips which
can handle a large variety of system configurations.

Each of these chips utilize a similar architecture, consisting of a high­speed DSP (Digital Signal Processor) computation unit , along with an
ASIC (Application Specific Integrated Circuit). The computation unit
contains special on-board hardware such as a multiply instruction that
makes it well suited for the task of motion control.

Along with a similar hardware architecture these chips also share most
software commands, so that software written for one chipset may be re­used with another, even though the type of motor may be different.

This manual describes the operation of the MC1241A and
MC1141A chipsets. For technical details on other members of
PMD's 1st generation motion processors see the corresponding
product manual.

Family Summary

MC1401 series (MC1401A, MC1201A, MC1101A, MC1401A-P,
MC1201A-P, MC1101A-P)

encoder signals (standard version) or parallel word encoder signals
(-P version) and output a motor command in either PWM or DAC­compatible format. These chipsets come in 1, 2 or 4 axis versions
and can be used with DC brushed motors, or brushless motors using
external commutation.

MC1231 series (MC1231A, MC1131A) -

incremental quadrature encoder signals and output sinusoidally
commutated motor signals appropriate for driving brushless motors.
They are available in one or two axis versions. Depending on the
motor type they output two or three phased signals per axis in either
PWM or DAC-compatible format.

MC1241 series (MC1241A, MC1141A)

internal microstepping generation for stepping motors. They are
available in a one or a two-axis version. Two phased signals are
output per axis in either PWM or DAC-compatible format. An
incremental encoder signal can be input to confirm motor position.

MC1451 series (MC1451A, MC1251A, MC1151A, MC1451A-E,
MC1251A-E, MC1151A-E) -

pulse and direction signal output appropriate for driving step motor­based systems. They are available in a one, two, or four-axis version
and are also available with quadrature encoder input.

Each of these chipsets has an associated Chipset Developer's
Kit available for it. For more information contact your PMD
representative.

- These chipsets take in incremental

These chipsets take in

- These chipsets provide

These chipsets provide very high speed

3

Electrical Characteristics

Overview

Interconnections between the two chips consist of a data bus and
various control and synchronization signals. The following table
summarizes the signals that must be interconnected for the chipset to
function properly. For each listed signal the I/O chip pin on the left side
of the table is directly connected to the pin to the right.

The MC1241A consists of two 68 pin PLCC's both fabricated in CMOS.
The Peripheral Input/Output IC (I/O chip) is responsible for interfacing
to the host processor and to the position input encoders. The Command
Processor IC (CP chip) is responsible for all host command, trajectory,
and microstep computations, as well as for outputting the PWM and
DAC signals.

The following figure shows a typical system block diagram, along with
the pin connections between the I/O chip and the CP chip.

Motor

(2 axis)

Encoder

(1-2 axis)

I/O

Data4-11

I/OAddr0-3

I/OWrite

I/OCntrl0-3

ClkOut

Amplifier

(1-2 axis)

CP

I/O Chip Signal
Name

I/O Chip
Pin

CP Chip
Signal Name

CP Chip
Pin

CPData4 18 Data4 50
CPData5 5 Data5 49
CPData6 6 Data6 46
CPData7 7 Data7 43
CPData8 8 Data8 40
CPData9 17 Data8 39
CPData10 3 Data10 36
CPData11 1 Data11 35
CPAddr0 68 I/OAddr0 28
CPAddr1 27 I/OAddr1 9
CPAddr2 29 I/OAddr2 6
CPAddr3 12 I/OAddr3 5
CPCntr0 20 I/OCntr0 16
CPCntr1 36 I/OCntr1 18
CPCntr2 22 I/OCntr2 68
CPCntr3 63 I/OCntr3 67
CPWrite 2 I/OWrite 15
CPClk 46 ClkOut 19

For a complete description of all pins see the 'Pin Descriptions'
section of this manual.

Host

Processor

The CP and I/O chips function together as one integrated motion
processor. The major components connected to the chip set are the
optional encoder (2, or 1 axes), the motor amplifier (2, or 1 axes), and
the host processor.

The encoder signals are input to the I/O chip in quadrature format. Two
signals encode the position, and an optional index signal contains a
once-per-rotation locating signal.

The chipset's motor output signals are connected to the motor amplifier.
Two types of output are provided; PWM (pulse width modulation), and
DAC-compatible signals used with an external DAC (digital to analog
converter). In addition 2-phase as well as 3-phase stepping motors are
supported. Because the output signals are in microstepping format, two
phased signals are provided per axis, with the relative phasing of the
two signals depending on the motor type (2-phase or 3-phase).

The host processor is interfaced via an 8-bit bi-directional bus and
various control signals. Host communication is coordinated by a
ready/busy signal, which indicates when communication is allowed.

Absolute Maximum Ratings

Unless otherwise stated, all electrical specifications are for both
the I/O and CP chips.

Storage Temperature, Ts.....................-55 deg. C to +150 deg. C

Supply Voltage, Vcc.............................-0.3 V to +7.0 V

Power Dissipation, Pd..........................650 mW (I/O and CP

combined)

Operating Ratings

Operating Temperature, Ta .................0 deg. C to +70 deg. C*

Nominal Clock Frequency, Fclk...........25.0 Mhz

Supply Voltage, Vcc.............................4.75 V to 5.25 V

* Industrial and Military operating ranges also available. Contact your
PMD representative for more information

4

DC Electrical Characteristics

(Vcc and Ta per operating ratings, Fclk = 25.0 Mhz)

Symbol Parameter Min. Max. Units Conditions

Vcc Supply Voltage 4.75 5.25 V

Idd Supply Current 100 mA open outputs

Input Voltages

Vih Logic 1 input voltage 2.0 Vcc + 0.3 V

Vil Logic 0 input voltage -0.3 0.8 V

Vihclk Logic 1 voltage for clock pin

(ClkIn)

Vihreset Logic 1 voltage for reset pin

(reset)

Output Voltages

Voh Logic 1 Output Voltage 2.4 V @CP Io = 300 uA

Vol Logic 0 Output Voltage 0.33 V @CP Io = 2 mA

Iout Tri-State output leakage current -20 20 uA 0 < Vout < Vcc

Iin Input current -50 50 uA 0 < Vi < Vcc

Iinclk Input current ClkIn -20 20 uA 0 < Vi < Vcc

3.0 Vcc+0.3 V

4.0 Vcc+0.3 V

AC Electrical Characteristics

(see reference timing diagrams)
(Vcc and Ta per operating ratings; Fclk = 25.0 Mhz)
(~ character indicates active low signal)

@I/O Io = 4 mA

@I/O Io = 4 mA

Timing Interval T# Min. Max. Units
Encoder and Index Pulse Timing

Motor-Phase Pulse Width T1 1.6 uS
Dwell Time Per State T2 0.8 uS
Index Pulse Setup and Hold
(relative to Quad A and Quad B low)

Reset Timing

Stable Power to Reset 0.25 Sec
Reset Low Pulse Width 1.0 uS

Clock Timing

Clock Frequency (Fclk) 6.7 25.6 Mhz
Clock Pulse Width T4 19.5 75 (note 2) nS
Clock Period T5 39 149 (note 2) nS

T3 0 uS

5

Timing Interval T# Min. Max. Units
Command Byte Write Timing

~HostSlct Hold Time T6 15 2000 (note 3) nS
~HostSlct Setup Time T7 10 nS
HostCmd Setup Time T8 10 nS
Host Cmd Hold Time T9 25 nS
HostRdy Delay Time T13 70 nS
~HostWrite Pulse Width T14 50 nS
Write Data Setup Time T15 35 nS
Write Data Hold Time T16 30 nS

Data Word Read Timing

~HostSlct Hold Time T6 15 2000 (note 3) nS
~HostSlct Setup Time T7 (read only) - 20 nS
HostCmd Setup Time T8 (read only) - 20 nS
HostCmd Hold Time T9 25 nS
Read Data Access Time T10 50 nS
Read Data Hold Time T11 10 nS
~HostRead high to HI-Z Time T12 50 nS
HostRdy Delay Time T13 70 nS
Read Recovery Time T17 60 nS

Data Word Write Timing

~HostSlct Hold Time T6 15 2000 (note 3) nS
~HostSlct Setup Time T7 10 nS
HostCmd Setup Time T8 10 nS
HostCmd Hold Time T9 25 nS
HostRdy Delay Time T13 70 nS
~HostWrite Pulse Width T14 50 nS
Write Data Setup Time T15 35 nS
Write Data Hold Time T16 30 nS
Write Recovery Time T18 60 nS

DAC Interface Timing

I/OAddr Stable to ~I/OWrite setup time T19 35 nS
~I/OWrite Pulse Width T20 56 95 nS
Data Hold Time After ~I/OWrite T21 17 nS
ClkOut Low to I/OAddr stable T22 10 40 nS
ClkOut Low to ~I/OWrite Low T23 75 92 nS
ClkOut Low to Data Valid T24 92 nS
ClkOut Cycle Time T25 160 typical (note 4) nS
I/OAddr Stable to DACSlct High T26 66 nS
~I/OWrite Low to DACSlct High T27 44.5 nS

PWM Output Timing

PWM Output Frequency 97.6 Khz

note 1 ~HostSlct and HostCmd may optionally be de-asserted if setup and hold times are met.
note 2 Chip-set performance figures and timing information valid at Fclk = 25.0 only. For timing information & performance parameters at Fclk <

25.0 Mhz, call PMD.

note 3 Two micro seconds maximum to release interface before chip set responds to command
note 4 ClkOut from CP is 1/4 frequency of ClkIn (CP chip).

6

I/O Timing Diagrams

The following diagrams show the MC1241A electrical interface timing. T#' values are listed in the above timing chart.

Quadrature Encoder Input Timing

Quad A

Quad B

~Index

ClkIn

T1

T1

T2 T2

T3

Clock Timing

T3

T4 T4 T5

Index = ~A * ~B * ~IND

7

Command Byte Write TIming

~HostSlct

HostCmd

~HostWrite

HostData0-7

HostRdy

T7

T8

T6

T9

T14

T15

T16

T13

8

Data Word Read TImi ng

~HostSlct

HostCmd

~HostRead

HostData0-7

HostRdy

T7

T6

Note 1

T8

Note 1

T9

T17

T12

High-Z High-Z High-Z

High
Byte

T10

T11

Low

Byte

T13

9

Data Word Write TIming

~HostSlct

HostCmd

~HostWrite

HostData0-7

HostRdy

T7

T8

T14

T15

High
Byte

T16

T18

Note 1

Note 1

T6

T9

T14

T15

Low

Byte

T16

10

T13

ClkOut

I/OAddr

~I/OWrite

DAC Interface Timing

T25

T22

T19

T23

T20

Data 0-11,

DACAddr0,1

DACSlct

T24

T21

T27

T26

11

Pinouts

9

1

61

9

1

61

10

I/O

(Top view)

26

27 43

60

10

60

CP

(Top view)

44

26

27 43

44

MC1241A Pinouts

4, 21, 25, 38, 55

VCC

QuadA1

28

QuadB1

42

Index1

24

Home1

13

QuadA2

26

QuadB2

30

Index2

9

Home2

23

DACSlct

33

CPClk

46

I/OClkIn

52

I/OClkOut

45

CPAddr2

29

CPAddr3

12

CPWrite

2

CPCntrl0

20

CPCntrl1

36

CPCntrl2

22

CPCntrl3

63

CPAddr0

68

CPAddr1

27

HostCmd

41

HostRdy

37

I/O

GND

HostRead

HostWrite

HostSlct

HostIntrpt
HostData0
HostData1
HostData2
HostData3
HostData4
HostData5
HostData6
HostData7

CPData4
CPData5
CPData6
CPData7
CPData8

CPData9
CPData10
CPData11

51
47
48
44
50
61
53
65
67
62
64
60
18

5
6
7
8

17

3
1

56
55
54
53

30
29
24
19
17
16
18
68
67
64
63
62
61

8
7
2
1

PWMMag1A
PWMSign1A
PWMMag1B
PWMSign1B
PWMMag2A
PWMSign2A
PWMMag2B
PWMSign2B
DAC16Addr0
DAC16Addr1
ClkIn
ClkOut
Reset
I/OCntrl0
I/OCntrl1
I/OCntrl2
I/OCntrl3
DACLow0
DACLow1
DACLow2
DACLow3

4, 22, 33

VCC

CP

GND

Data0
Data1
Data2
Data3
Data4
Data5
Data6
Data7
Data8

Data9
Data10
Data11

I/OAddr0
I/OAddr1
I/OAddr2
I/OAddr3

I/OWrite
PosLimit1
PosLimit2

NegLimit1
NegLimit2

60
59
58
57
50
49
46
43
40
39
36
35
28

9
6

5
15
52
45
51
44

14, 15, 32, 49, 54, 66

3, 34

MC1141A Pinouts

4, 21, 25, 38, 55

VCC

28

QuadA1

42

QuadB1

24

Index1

13

Home1

33

DACSlct

46

CPClk

52

I/OClkIn

45

I/OClkOut

29

CPAddr2

12

CPAddr3

2

CPWrite

20

CPCntrl0

36

CPCntrl1

22

CPCntrl2

63

CPCntrl3

68

CPAddr0

27

CPAddr1

41

HostCmd

37

HostRdy

I/O

GND

14, 15, 32, 49, 54, 66

HostRead
HostWrite

HostSlct

HostIntrpt
HostData0
HostData1
HostData2
HostData3
HostData4
HostData5
HostData6
HostData7

CPData4
CPData5
CPData6
CPData7
CPData8

CPData9
CPData10
CPData11

51
47
48
44
50
61
53
65
67
62
64
60
18

5
6
7
8

17

3
1

8

56

7
55
30
29
24
19
17
16
18
68
67
64
63
62
61

PWMMag1A
PWMSign1A
PWMMag1B
PWMSign1B
DAC16Addr0
DAC16Addr1
ClkIn
ClkOut
Reset
I/OCntrl0
I/OCntrl1
I/OCntrl2
I/OCntrl3
DACLow0
DACLow1
DACLow2
DACLow3

12

4, 22, 33

VCC

CP

GND

3, 34

Data0
Data1
Data2
Data3
Data4
Data5
Data6
Data7
Data8

Data9
Data10
Data11

I/OAddr0
I/OAddr1
I/OAddr2
I/OAddr3

I/OWrite
PosLimit1
NegLimit1

60
59
58
57
50
49
46
43
40
39
36
35
28

9
6

5
15
52
51

Pin Descriptions

The following tables provide pin descriptions for the MC1241A-series chipsets.

IC Pin Name Pin # Description/Functionality
I/O Chip Pinouts

I/O QuadA1

QuadB1
QuadA2
QuadB2

I/O ~Index1

~Index2

28
42
26
30

24
9

Quadrature A, B channels for axis 1 - 2 (input). Each of these 2 pairs of quadrature (A, B)
signals provide the position feedback for an incremental encoder. When the encoder is
moving in the positive, or forward direction, the A signal leads the B signal by 90 degs.

NOTE: Many encoders require a pull-up resistor on each of these signals to establish a
proper high signal (check the encoder electrical specifications)

NOTE: For MC1241A all 4 pins are valid. For MC1141A pins for axes 1 only are valid. Invalid
axis pins can be left unconnected

NOTE: These signals are not required for normal operation, but may be used if desired to
confirm motor position.
Index encoder signals for axis 1-2 (input). Each of these 2 signals indicate the index flag
state from the encoder. A valid index pulse is recognized by the chip set when the index flag
transitions low, followed by the corresponding A and B channels of the encoder transitioning
low. The index pulse is recognized at the later of the A or B transitions. If not used this signal
must be tied high.

NOTE: For MC1241A both pins are valid. For MC1141A pins for axes 1 only are valid.
Invalid axis pins can be left unconnected.

NOTE: These signals are not required for normal operation, but may be used if desired to
confirm motor position.

I/O ~Home1

~Home2

I/O DACSlct 33 DAC Select (output). This signal is asserted high to select any of the available DAC output

I/O CPClk 46 I/O chip clock (input). This signal is connected directly to the ClkOut pin (CP chip) and

I/O I/OClkIn 52 Phase shifted clock (input). This signal must be connected to I/OClkOut (I/O chip), and inputs

I/O I/OClkOut 45 Phase shifted clock (output). This signal must be connected to I/OClkIn (I/O chip), and

I/O CPAddr0

CPAddr1
CPAddr2
CPAddr3

13
23

68
27
29
12

Home signals for axis 1-2 (input). Each of these signals provide a general purpose input to
the hardware position capture mechanism. A valid home signal is recognized by the chipset
when the home flag transitions low. These signals have a similar function as the ~Index
signals, but are not gated by the A and B encoder channels. For valid axis pins, If not used,
this signal must be tied high. See below for valid pin definitions for the MC1241A and
MC1141A.

NOTE: For MC1241A both pins are valid. For MC1141A pins for axes 1 only are valid.
Invalid axis pins can be left unconnected.

NOTE: These signals are not required for normal operation, but may be used if desired to
confirm motor position.

channels. For details on DAC decoding see description of DAC16Addr0-1 signals.

provides the clock signal for the I/O chip. The frequency of this signal is 1/4 the user-provided
ClkIn (CP chip) frequency.

a phase shifted clock signal.

outputs a phase shifted clock signal.
I/O chip to CP chip communication address (input). These 4 signals are connected to the
corresponding I/OAddr0-3 pins (CP chip), and together provide addressing signals to
facilitate CP to I/O chip communication.

13

IC Pin Name Pin # Description/Functionality

I/O ~CPWrite 2 I/O chip to CP chip communication write (input). This signal is connected to the ~I/OWrite pin

(CP chip) and provides a write strobe to facilitate CP to I/O chip communication.

I/O CPCntrl0

CPCntrl1
CPCntrl2
CPCntrl3

I/O HostCmd 41 Host Port Command (input). This signal is asserted high to write a host command to the chip

I/O HostRdy 37 Host Port Ready/Busy (output). This signal is used to synchronize communication between

I/O ~HostRead 51 Host Port Read data (input). Used to indicate that a data word is being read from the chip set

I/O ~HostWrite 47 Host Port Write data (input). Used to indicate that a data word or command is being written to

I/O ~HostSlct 48 Host Port Select (input). Used to select the host port for reading or writing operations (low

I/O ~HostIntrpt 44 Host Interrupt (output). A low assertion on this pin indicates that a host interrupt condition

I/O HostData0

HostData1
HostData2
HostData3
HostData4
HostData5
HostData6
HostData7

I/O CPData4

CPData5
CPData6
CPData7
CPData8
CPData9
CPData10
CPData11

I/O Vcc 4, 21, 25, 38, 55 I/O chip supply voltage pin. All of these pins must be connected to the supply voltage. Supply

I/O GND 14, 15, 32, 49, 54,66I/O chip ground pin. All of these pins must be connected to the power supply return.

20
36
22
63

50
61
53
65
67
62
64
60
18
5
6
7
8
17
3
1

I/O chip to CP chip communication control (mixed). These 4 signals are connected to the
corresponding I/OCntrl0-3 pins (CP chip), and provide control signals to facilitate CP to I/O
chip communication.

set. It is asserted low to read or write a host data word to the chipset

the DSP and the host. HostRdy will go low (indicating host port busy) at the end of a host
command write or after the second byte of a data write or read. HostRdy will go high
(indicating host port ready) when the command or data word has been processed and the
chip set is ready for more I/O operations. All host port communications must be made with
HostRdy high (indicating ready).

Typical busy to ready cycle is 67.5 uSec, although it can be longer when host port traffic is
high.

(low asserts read).

the chip set (low asserts write).

assertion selects port). ~HostSlct must remain inactive (high) when the host port is not in use.

exists that may require special host action.
Host Port Data 0-7 (bi-directional, tri-stated). These signals form the 8 bit host data port used
during communication to/from the chip set. This port is controlled by ~HostSlct, ~HostWrite,
~HostRead and HostCmd.

I/O chip to CP chip data port (bi-directional). These 8 bits are connected to the corresponding
Data4-11 pins on the CP chip, and facilitate communication to/from the I/O and CP chips..

voltage = 4.75 to 5.25 V

14

IC Pin Name Pin # Description/Functionality
CP Chip Pinouts

CP PWMMag1A

PWMMag1B
PWMMag2A
PWMMag2B

CP PWMSign1A

PWMSign1B
PWMSign2A
PWMSign2B

CP PosLimit1

PosLimit2

CP NegLimit1

NegLimit2

8
7
2
1

56
55
54
53

52
45

51
44

PWM motor output magnitude signals (output). When the chip set is in PWM output mode
these pins provide the Pulse Width Modulated magnitude signal to the motor amplifier. Two
phases of command signal are output per motor axis, indicated phase A and phase B, with
the axis number indicated 1 or 2.

NOTE: For MC1241A all four pins are valid. For MC1141A pins for axes 1 only are valid.
Invalid axis pins can be left unconnected.

The PWM resolution is 10 bits, frequency = 97.6 kHz.
PWM motor output direction signals (output). When the chip set is in PWM output mode
these pins provide the sign signal to the motor amplifier. Two phases of command signals are
output per motor axis, indicated phase A and phase B, with the axis number indicated 1 or 2.

NOTE: For MC1241A all four pins are valid. For MC1141A pins for axes 1 only are valid.
Invalid axis pins can be left unconnected.
Positive limit switch input for axis 1-2. These signals provide directional limit inputs for the
positive-side travel limit of the axis. Upon powerup these signals default to "active high"
interpretation, but the interpretation can be set explicitly using the SET_LMT_SENSE
command. (See Host Command Section for more info.) If not used these signals should be
tied low for the default interpretation, or tied high if the interpretation is reversed.

NOTE: For MC1241A both pins are valid. For MC1141A pins for axes 1 only are valid. Invalid
axis pins can be left un connected.
Negative limit switch input for axis 1-2. These signals provide directional limit inputs for the
negative-side travel limit of the axis. Upon powerup these signals default to "active high"
interpretation, but the interpretation can be set explicitly using the SET_LMT_SENSE
command. (See Host Command Section for more info.) If not used these signals should be
tied low for the default interpretation, or tied high if the interpretation is reversed.

NOTE: For MC1241A both pins are valid. For 1141 pins for axis 1 only are valid. Invalid axis
pins can be left un connected.

CP DAC16Addr0

DAC16Addr1

CP ClkIn 24 Clock In (input). This pin provides the chip set master clock (Fclk = 25.0 Mhz)

30
29

Axis Address used during 16-bit DAC motor command output. These signals encode the
motor output axis address as shown in the table below:

Dac16Addr1 Dac16Addr0 Addressed Encoder
Low Low Axis 1 phase A
Low High Axis 1 phase B
High Low Axis 2 phase A
High High Axis 2 phase B

To write a valid DAC motor command value DACSlct (I/O chip) and I/OAddr0-3 (CP chip)
must be high, and I/OWrite (CP chip) must be low. The 16 bit DAC data word is organized as
follows: High twelve bits are in Data0-11 (CP chip), and low 4 bits are in DACLow0-3 (CP
chip).

15

IC Pin Name Pin # Description/Functionality

CP ClkOut 19 Clock Out (output). This pin provides a clock output which is 1/4 the ClkIn frequency. This pin

is connected to I/OClkin (I/O chip).

CP ~Reset 17 Master chip set reset (input). When brought low, this pin resets the chip set to its initial

condition. Reset should occur no less than 250 mSec after stable power has been provided
to the chip set.

CP I/OCntrl0

I/OCntrl1
I/OCntrl2
I/OCntrl3

CP Data0

Data1
Data2
Data3
Data4
Data5
Data6
Data7
Data8
Data9
Data10
Data11

CP DACLow0

DACLow1
DACLow2
DACLow3

CP I/OAddr0

I/OAddr1
I/OAddr2
I/OAddr3

CP I/OWrite 15 Multi-purpose write (output). This pin is connected to CPWrite on the I/O chip. It has 2

16
18
68
67
60
59
58
57
50
49
46
43
40
39
36
35
64
63
62
61
28
9
6
5

I/O chip to CP chip communication control (mixed). These signals are connected to the
corresponding CPCntrl0-3 pins on the I/O chip, and provide control signals to facilitate CP to
I/O communication.

Multi-purpose Data0-11. (Bi-directional). These pins have 2 functions:

1) Pins Data4-11 (8 bits total) are connected to the corresponding CPData4-11 pins on the
I/O chip, and are used to communicate between the CP and I/O chips

2) Pins Data0-11 hold the high 12 bits of the DAC output value when the output mode is set
to 16-bit DAC.

DACLow0-3 (output). These pins hold the lowest 4 bits of the 16 bit DAC output word when
the output mode is set to 16 bit DAC. These pins, in conjunction with Data0-11 (providing the
high 12 bits) make up the 16-bit DAC output word.

Multi-purpose Address0-3 (output). These pins are connected to the corresponding CPAddr0­3 pins on the I/O chip. They have 2 functions; They provide addressing signals to facilitate
communication between the I/O chip and CP chip, and they are used during DAC data
decoding. To read a valid DAC value from Data0-Data11 (CP chip), DACSlct (I/O chip) and
I/OAddr0-3 (CP chip) must all be high, and I/OWrite (CP chip) must be low.

functions:

1) It provides a control signal to the I/O chip to facilitate communication between the I/O chip
and CP chip.

2) It is used during DAC data decoding to read a valid DAC value from Data0-Data11 (CP
chip), DACSlct (I/O chip) and I/OAddr0-3 (CP chip) must all be high, and I/OWrite (CP chip)
must be low.

CP Vcc 4, 22, 33 CP chip supply voltage pin. All of these pins must be connected to the supply voltage. Supply

voltage = 4.75 to 5,.25 V

CP GND 3, 34 CP chip ground pin. All of these pins must be connected to the power supply return.

16

Theory of Operations

Incremental E ncoder

Index B A

Home

1/a

1/a

1/a 1/a

Internal Block Diagram

PWM mag.

PWM dir . D A C add r es s

1/phase

PWM, DAC signal generator (2-4 channels)

Motor Output

Micr os tepping
Generator (2)

DAC data

2

16

Quadrature

decoder

counter (2)

Index capt ur e

register (2)

Host I/O controller

185

host int erruptDataControl

The above figure shows an internal block diagram for the MC1241A
motion processor.

Each axis provides programmable trajectory generation including
electronic gearing, trapezoidal point-to-point, and s-curve point to point
moves. In addition the chipset contains an internal microstepping signal
generator. The microstep generator outputs 2 phased signals per axis
with 64 usteps per full step. These signals can be used to directly drive
each coil of the stepper motor for smooth, microstepped motion.

The chipset calculates all trajectory information on a cycle-by-cycle
basis. Each cycle results in a new desired sine-wave frequency output
based on the trajectory generator mode and the specified trajectory
parameters.

Trajectory profile

generator (2)

System R eg i st er s ( 2)

Host command

1/a

PosLimit

Over-travel InputsHost I/O

1/a

NegLimit

The sine-wave microstepping signals are output in PWM format with a
separate magnitude and sign signal per phase, or as a digital word with
up to 16 bits of resolution that is constructed externally into an analog
signal using a DAC. In DAC mode two address bits indicate which of
the two axes and two phases are being loaded by the chipset.

Encoder feedback is available for each motor axis and can be used by
the host to check that the axis has achieved a desired position.
Additionally, the chipset can use the encoder information to
automatically detect a motor stall condition while a move is ongoing.

The following table summarizes the operational parameters of the
MC1241-series chipsets.

17

MC1241-Series Chipset Operational Parameters

Available configurations: 2 axes with internal microstepping generation (MC1241A)

1 axes with internal microstepping generation (MC1141A)
Operating Modes: Open loop (motor is controlled directly by trajectory generator)
Position Range: -1,073,741,824 to 1,073,741,823 usteps
Velocity Range: -16,384 to 16,383 usteps/cycle with a resolution of 1/65,536 usteps/cycle
Acceleration Range:

Jerk Range:
Start velocity range -32,768 to +32,767 steps/cycle with a resolution of 1/65,536 steps/cycle

Trajectory Profile Generator Modes: S-curve (host commands final position, max velocity, max acceleration, and jerk)

Electronic Gear Ratio Range: 32768:1 to 1:32768 (negative and positive direction)
Encoder Input Signals: A, B, Index
Microstepping Waveform: Sinusoidal
# Steps Per Full Step: 64
Microstep Lookup Rate: 15 kHz
Phasing: 90 degrees (used with 2-phase stepper motors)

# of Output Phases: 2 (all motor types)
PWM Frequency: 97.6 kHz
PWM resolution: 8 bits
Max Incremental. Encoder Rate: 1.75 Mcounts/sec
Profile Cycle Rate : 540 uSec*.
# of Limit Switch Inputs Per Axis 2 (one for each direction of travel)
Miscellaneous control lines: Home switch input (one per axis)
# of Position Capture Sources: 2 (Index, Home signals)
Capture Trigger Latency: 160 nSec
# of Host Commands: 80

S-curve profile: - 1/2 to + 1/2 usteps/cycle2 with a resolution of 1/65,536 usteps/cycle

All others: -16,384 to 16,383 usteps/cycle2 with a resolution of 1/65,536 usteps/cycle

-1/2 to +1/2 usteps/cycle3, with a resolution of 1/4,294,967,296 usteps/cycle

(used with trapezoidal and velocity profile modes only)

Trapezoidal (host commands final position, max velocity, starting velocity, and acceleration)

Velocity contouring (host commands max velocity, starting velocity, acceleration)

Electronic Gear (Encoder position is used as position command for corresponding axis).

120 degrees (used with 3-phase stepper motors or AC Induction motors)

3

2.
2

*Exact cycle time is 542.72 uSec, 540 is an approximation

Trajectory Profile Generation

The trajectory profile generator performs calculations to determine the
target position, velocity and acceleration on a continuous basis. These
calculations are performed taking into account the current profile mode,
as well as the current profile parameters set by the host. Four trajectory
profile modes are supported:

- S-curve point to point

- Trapezoidal point to point

- Velocity contouring

- Electronic Gear

The commands to select these profile modes are

SET_PRFL_S_CRV (to select the s-curve mode), SET_PRFL_TRAP
(to select the trapezoidal mode) SET_PRFL_VEL (to select the
velocity contouring mode) and SET_PRFL_GEAR (to select the
electronic gear mod).

Throughout this manual various command mnemonics will be
shown to clarify chipset usage or provide specific examples. See
the Host Communications section for a description of host
command nomenclature.

18