PMC-Sierra PM7344 User Manual

PMC-Sierra,Inc.

Quad T1/E1 Multi-PHY SATURN User Network Interface

PM7344

S/UNI-MPH

FEATURES

• Monolithic single-chip quad ATM Physical Layer User Network Interface (UNI) operating at 1.544 Mbit/s or

2.048 Mbit/s.

• Integrates a quad full-featured dualmode T1/E1 framer/transmitter for terminating four duplex 1.544 Mbit/s DS1 or four duplex 2.048 Mbit/s E1 signals. Recovers T1/E1 clock and data using a digital phase locked loop for high jitter tolerance.

• Implements the ATM Forum UNI Specification V3.1 for DS1 and E1 transmissi on rates.

• Implements the ATM phy s ica l la ye r for Broadband ISDN according to ITU-T Recommendation I.43 2.

• Implements direct mapping into f our T1 or E1 streams according to ITU-T Recommendation G.8 04.

• Provides UTOPIA L1-compliant, UTOPIA L2-compatible ATM-PHY interface with parity and multi-PHY control signals.

• Software-compatible with the PM4341A T1XC, PM6341 E1XC, PM4351 COMET, PM5346 S/UNI®-

LITE and PM7345 S/UNI-PDH.

• Application-compatible with the PM8313 D3MX, PM4314 QDSX, and PM7323 RCMP-200.

• Provides a generic 8-bit

microprocessor bus interface for configuration, control, and status monitoring.

• Low power, +5 V, CMOS technology.

• Packaged in a 128-pin rectangular

(14 mm by 20 mm) PQFP package.

T1 FRAMER/TRANSMITTER

• Supports SF or ESF format signals using B8ZS or AMI line code.

• Provides Loss Of Signal (LOS) detection and red, yellow and Alarm Indication Signal (AIS) alarm detect ion. Supports transmission of (AIS) or yellow alarm signal in all formats.

• Detects violations of the ANSI T1.403

12.5% pulse density rule over a moving 192-bit window.

• Supports line and path performance monitoring according to ANSI specifications. Accumulators are provided for counting ESF CRC-6 errors, framing bit errors, LCVs, and LOF, or frame alignment events.

• Provides ESF bit-oriented code detection/generation, and an HDLC interface for termina ting/generati ng the ESF datalink.

• Extracts/inserts the datalink in ESF mode.

E1 FRAMER/TRANSMITTER

• Supports G.704 2048 kbit/s format using HDB3 or AMI line coding.

• Supports CRC multiframe alignment or the signalling multiframe alignment.

• Declares red and AIS alarms using Q.516 recommended integration periods. Provides LOS detection, and indicates loss of frame alignment (OOF), loss of signalling, and loss of CRC multiframe alignment.

• Supports line and path performance monitoring according to ITU-T recommendations. Accumulators are provided for counting CRC-4 errors, FEBE, frame sync errors, and LCVs.

• Supports reception and transmis sion of remote alarm and AIS.

• Provides an HDLC interface for terminating/generating a datalink.

• Supports the timeslot 16 (64 kbit/s) datalink which may be used for common channel signalling, or any combination of the national bits.

APPLICATIONS

• ATM Switches Supporting DS1 or E1 UNI Ports

• ATM Switches Supporting DS3 or E3 Ports Carrying Multiplexed DS1 or E1 UNI Signals

• ATM Switches Supporting SONET/ SDH Ports Carrying Tributary Mapped DS1 or E1 UNI Signals

• ATM Customer Premise Equipment Supporting Multiple DS1 or E1 UNI Ports

BLOCK DIAGRAM

XCLK

TCLKO[4:1]

TDP/TDD[4:1]

TDN/TOHO[4:1]

RCLKI[4:1]

RDP/RDD[4:1]

RDN/RLCV/ROH[4:1]

Digital Transmit Interface

Digital

Receive

Interface

Pulse

Density Violation Detector

RCLKO

Pulse

Density

Enforcer

HDLC

Receiver

TDLUDR/

TDLCLK[4:1]

HDLC

Transmitter

Bit-oriented

Code

Receiver

RDLINT/

RDLSIG[4:1]

TDLINT/

TDLSIG[4:1]

Bit-oriented

Code

Transmitter

T1/E1

Framing Insertion

T1/E1

Framer

Performance

Monitor

RDLEOM/

RDLCLK[4:1]

TCLKI

In-band

Code

Detector

TFPI/TOHI

In-band

Loopback

Code

Generator

Alarms

Integrator

Transmit ATM Cell

Processor

Receive ATM Cell

Processor

Microprocessor

D[7:0]

A[10:0]

TDO

Access Port

Interface

ALE

CSB

TDI

TCK

JTAG Test

Transmit

ATM 4-Cell

FIFO

Receive

ATM 4-Cell

FIFO

WRB

RDB

TRSTB

TMS

TSOC TDAT[7:0] TXPRTY TCA[4:1] TWRENB[4]/TCAMPH TWRENB[3]/TWA[1] TWRENB[2]/TWA[0]

Multi-PHY

Interface

INTB

RSTB

MPHEN

TWRENB[1]/TWRMPHB TFCLK RSOC RDAT[7:0] RXPRTY RCA[4:1] RRDENB[4]/RCAMPH RRDENB[3]/RRA[1] RRDENB[2]/RRA[0] RRDENB[1]/RRDMPHB RFCLK

PM7344 S/UNI-MPH

Quad T1/E1 Multi-PHY SATURN User Network Interface

TYPICAL APPLICATIONS

DS3 PORT CARRYING MULTIPLEXED T1 ATM UNI SIGNALS

PM7344

S/UNI

-MPH

Quad T1/E1

Multi-PHY

UNI

∫

12.352 MHz

1.544 MHz

∫

PM7344

-MPH

Quad T1/E1

Multi-PHY

UNI

UTOPIA or SCI-PHY™

Multi-PHY

ATM Cell Bus

Microprocessor

Bus

SATURN

S/UNI

SATURN

T1 OR E1 MULTI-PHY ATM UNI

1.544 MHz Transmit Reference Clock

# 1

# 7

Crystal Oscillator Clock

12.352 MHz

6.312 MHz Optional Transmit Reference Clock

PM8313

D3MX

M13 Multiplexer/

Demultiplexer

44.736 MHz Transmit Reference Clock

DSX-3 Line Inter-

Microprocessor Bus

face with Clock

Recovery

DSX-3 Analog Interface

UTOPIA or SCI-PHY™

Multi-PHY

ATM Cell Bus

Head Office: PMC-Sierra, Inc. #105 - 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200

1.544 MHz Transmit Reference Clock

PM7344

-MPH

S/UNI

Quad T1/E1

Multi-PHY

SATURN

To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn: Document Coordinator

UNI

Quad DSX1/E1

Analog Line

or 12.352 MHz

All product documentation is available on our web site at: http://www.pmc-sierra.com For corpo rate info rmation, send email to: info@pmc-sierra.com

PM4314

QDSX

Interface

DSX-1 or E1

Analog

Interface

Crystal Oscillator Clock

37.056 MHz

Microprocessor Bus

of PMC-Sierra, Inc.