PMC-Sierra Pm25LV010, Pm25LV512 User Manual

PMC

FEATURES

Pm25LV512 / Pm25LV010

512 Kbit / 1 Mbit 3.0 Volt-only , Serial Flash Memory

With 25 MHz SPI Bus Interface

 Single Power Supply Operation

- Low voltage range: 2.7 V - 3.6 V

• Memory Organization

- Pm25L V512: 64K x 8 (512 Kbit)

- Pm25L V010: 128K x 8 (1 Mbit)

 Cost Effective Sector/Block Architecture

- Uniform 4 Kbyte sectors

- Uniform 32 Kbyte blocks (8 sectors per block)

- Two blocks with 32 Kbytes each (512 Kbit)

- Four blocks with 32 Kbytes each (1 Mbit)

- 128 pages per block

 Serial Peripheral Interface (SPI) Compatible

- Supports SPI Modes 0 (0,0) and 3 (1,1)

 High Performance Read

- 25 MHz clock rate (maximum)

 Page Mode for Program Operations

- 256 bytes per page

 Block Write Protection

- The Block Protect (BP1, BP0) bits allow part or entire

of the memory to be configured as read-only.

 Hardware Data Protection

- Write Protect (WP#) pin will inhibit write operations to the status register

• Page Program (up to 256 Bytes)

- Typical 2 ms per page program time

• Sector, Block and Chip Erase

- Typical 40 ms sector/block/chip erase time

 Single Cycle Reprogramming for Status Register

- Build-in erase before programming

 High Product Endurance

- Guarantee 100,000 program/erase cycles per single sector (preliminary)

- Minimum 20 years data retention

 Industrial Standard Pin-out and Package

- 8-pin JEDEC SOIC

- 8-contact WSON

- Optional lead-free (Pb-free) packages

GENERAL DESCRIPTION

The Pm25L V512/010 are 512 Kbit/1 Mbits 3.0 V olt-only serial Flash memories. These devices are designed to use a single low voltage, range from 2.7 Volt to 3.6 Volt, power supply to perform read, erase and program operations. The devices can be programmed in standard EPROM programmers as well.

The device is optimized for use in many commercial applications where low-power and low-voltage operation are essential. The Pm25L V512/010 is enabled through the Chip Enable pin (CE#) and accessed via a 3-wire interface consisting of Serial Data Input (Sl), Serial Data Output (SO), and Serial Clock (SCK). All write cycles are completely self-timed.

Block Write protection for top 1/4, top 1/2 or the entire memory array (1M) or entire memory array (512K) is enabled by programming the status register. Separate write enable and write disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence.

The Pm25L V512/010 are manufactured on PMC’s advanced nonvolatile CMOS technology, P-FLASH™. The devices are offered in 8-pin JEDEC SOIC and 8-contact WSON packages with operation frequency up to 25 MHz.

Programmable Microelectronics Corp.

Issue Date: February, 2004, Rev: 1.4

PMC Pm25LV512/010

CONNECTION DIAGRAMS

CE#

SO WP# GND

2 3 4

8-Pin SOIC

PIN DESCRIPTIONS

LOBMYSEPYTNOITPIRCSED

#ECTUPNI

KCSTUPNIkcolCataDlaireS

ISTUPNItupnIataDlaireS

Vcc

HOLD#

SCK

CE#

SO WP# GND

1 2

Top View

3 4

8 7 6 5

Vcc HOLD# SCK SI

8-Contact WSON

rofseirtiucriclanretnis'ecivedehtsetavitcawolseog#EC:elbanEpihC

otnisehctiwsdnaecivedehtstcelesedhgihseog#EC.noitarepoecived

tonsiecivedehtnehW.noitpmusnocrewopehtecuderotedomybdnats

ehtdna,)lS(niptupnilairesehtaivdetpeccaebtonlliwatad,detceles

.etatsecnadepmihgihaniniamerlliw)OS(niptuptuolaires

OSTUPTUOtuptuOataDlaireS

DNGdnuorG

ccVylppuSrewoPeciveD

#PWTUPNI

#DLOHTUPNI

Programmable Microelectronics Corp. Issue Date: February, 2004, Rev: 1.4

.ecneuqeslairesehtgnitteser

.detibihnieraretsigersutatsehtotsnoitarepoetirw

tuohtiwecivedretsamehthtiwnoitacinummoclairesesuaP:dloH

lla,"1"sitibNEPWdnawolotthguorbnip#PWehtnehW:tcetorPetirW

PMC Pm25LV512/010

PRODUCT ORDERING INFORMATION

Pm25LVxxx -25 S C E

Environmental Attribute

E = Lead-free (Pb-free) Package Blank = Standard Package

Temperature Range

C = Commercial (0°C to +85°C)

Package Type

S = 8-pin SOIC (8S) Q = 8-contact WSON (8Q)

Operating Speed

25 MHz

PMC Device Number

Pm25L V512 (512 Kbit) Pm25L V010 (1 Mbit)

Part Number Operating Frequency (MHz) Package Temperature Range

Pm25LV512-25SCE Pm25LV512-25SC Pm25LV512-25Q CE Pm25LV010-25SCE Pm25LV010-25SC Pm25LV010-25Q CE

Commercial

C to + 85oC)

Programmable Microelectronics Corp. Issue Date: February, 2004, Rev: 1.4

PMC Pm25LV512/010

BLOCK DIAGRAM

SPI Chip Block Diagram

High Voltage Generator

Control Logic

Instruction Decoder

Serial /Parallel convert Logic

Address Latch

& Counter

Y-DECODER

2KBit Page Buffer Status

Memory Arra

X-DECODER

Programmable Microelectronics Corp. Issue Date: February, 2004, Rev: 1.4

PMC Pm25LV512/010

SERIAL INTERFACE DESCRIPTION

Pm25L V512/010 can be driven by a microcontroller on the SPI bus as shown in Figure 1. The serial communication term definitions are in the following section.

MASTER: The device that generates the serial clock. SLA VE: Because the Serial Clock pin (SCK) is always an input, the Pm25L V512/010 always operates as a slave. TRANSMITTER/RECEIVER: The Pm25L V512/010 has separate pins designated for data transmission (SO) and

receptio n (S l).

MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CE# going low, the first byte will be received. This byte

contains the op-code that defines the operations to be performed. INV ALID OP-CODE: If an invalid op-code is received, no data will be shifted into the Pm25L V512/010, and the serial

output pin (SO) will remain in a high impedance state until the falling edge of CE# is detected again. This will reinitialize the serial communication.

Figure 1. Bus Master and SPI Memory Devices

SDO

SPI Interface with (0, 0) or (1, 1)

Bus Master

CS3 CS2 CS1

Note: 1. The Write Protect (WP#) and Hold (HOLD#) si

SDI SCK

SCK SO SI

SPI Memory

Device

CE# WP# HOLD# HOLD# HOLD#

SCK SO SI SCK SO SI

SPI Memory

Device

CE# WP# CE# WP#

nals should be driven, High or Low as appropriate.

SPI Memory

Device

Programmable Microelectronics Corp. Issue Date: February, 2004, Rev: 1.4

PMC Pm25LV512/010

SERIAL INTERFACE DESCRIPTION (CONTINUED)

SPI MODES

These devices can be driven by microcontroller with its SPI peripheral running in either of the two following modes: Mode 0 = (0, 0) Mode 3 = (1, 1)

For these two modes, input data is latched in on the rising edge of Serial Clock (SCK), and output data is

Figure 2. SPI Modes

available from the falling edge of Serial Clock (SCK). The difference between the two modes, as shown in

Figure 2, is the clock polarity when the bus master is in Stand-by mode and not transfering data:

- Clock remains at 0 (SCK = 0) for Mode 0 (0, 0)

- Clock remains at 1 (SCK = 1) for Mode 3 (1, 1)

Mode 0 (0 0)

Mode 3 (1 1)

SCK

Programmable Microelectronics Corp. Issue Date: February, 2004, Rev: 1.4

PMC Pm25LV512/010

DEVICE OPERATION

The Pm25L V512/010 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers.

The Pm25LV512/010 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 1. All instructions, addresses, and data are transferred with the MSB first and start with a highto-low transition.

Write is defined as program and/or erase in this specification. The following commands, P AGE PROGRAM, SECTOR ERASE, BLOCK ERASE, CHIP ERASE, and WRSR are write instructions for Pm25L V512/010.

Table 1. Instruction Set for the Pm25LV512/010

emaNnoitcurtsnItamroFnoitcurtsnIedoCxeHnoitarepO

NERW01100000h60hctaLelbanEetirWteS IDRW00100000h40hctaLelbanEetirWteseR

RSDR10100000h50retsigersutatSdaeR

RSRW10000000h10retsigeRsutatSetirW

DAER11000000h30yrarrAyromeMmorfataDdaeR

DAER_TSAF11010000hB0deepSrehgiHtayromeMmorfataDdaeR

GORP_GP01000000h20yarrAyromeMotnIataDmargorP

ESARE_ROTCES11101011h7DyarrAyromeMnirotceSenOesarE

ESARE_KCOLB00011011h8DyarrAyromeMnikcolBenOesarE

ESARE_PIHC11100011h7CyarrAyromeMeritnEesarE

DIDR11010101hBADItcudorPdnarerutcafunaMdaeR

READ PRODUCT ID (RDID): The RDID instruction allows the user to read the manufacturer and product ID of the device. The instruction code is followed by three dummy bytes, each bit being latched-in on Serial Data Input (SI) during the rising edge of Serial Clock (SCK). Then the first manufacturer ID (9Dh) is shifted out on Serial Data Output (SO), followed by the device ID (7Bh = Pm25L V512; 7Ch = Pm25LV010) and the second manufacturer ID (7Fh), each bit been shifted out during the falling edge of Serial Clock (SCK).

Table 2. Product Identification

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DIrerutcafunaMhD9

:DIeciveD

215VL52mPhB7 010VL52mPhC7

Programmable Microelectronics Corp. Issue Date: February, 2004, Rev: 1.4

PMC Pm25LV512/010

WRITE ENABLE (WREN): The device will power up in the write disable state when Vcc is applied. All write instructions must therefore be preceded by the WREN instruction.

WRITE DISABLE (WRDI): T o protect the device against inadvertent writes, the WRDI instruction disables all write commands. The WRDI instruction is independent of the status of the WP# pin.

READ ST ATUS REGISTER (RDSR): The RDSR instruction provides access to the status register. The READY/ BUSY and write enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. During internal write cycles, all other commands will be ignored except the RDSR instruction.

Table 3. Status Register Format

7tiB6tiB5tiB4tiB3tiB2tiB1tiB0tiB

NEPW XXX 1PB0PBNEWYDR

Table 4. Read Status Register Bit Definition

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.YDAERsiecivedehtsetacidni0=0tiB

)YDR(0tiB

)NEW(1tiB

)0PB(2tiB.5elbaTeeS

.YSUB

.DELBANEETIRWtonsiecivedehtsetacidni0=1tiB

.DELBANEETIRWsiecivedehtsetacidni1=1tiB

siecivedehtdnassergorpnisielcycetirwehtsetacidni1=0tiB

)1PB(3tiB.5elbaTeeS

.elcycetirwlanretninanitonsiecivednehws0era6-4stiB

.)#PW(niptcetorPetirWfonoitcnufehtskcolb0=NEPW

)NEPW(7tiB

.sliatedrof6elbaTeeS

.elcycetirwlanretninagniruds1era7-0stiB

.)#PW(niptcetorPetirWehtsetavitca1=NEPW

WRITE ST A TUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection for the Pm25L V010. The Pm25L V010 is divided into four blocks where the top quarter (1/4), top half (1/2), or all of the memory blocks can be protected (locked out) from write. The Pm25L V512 is divided into 2 blocks where all of the memory blocks can be protected (locked out) from write. Any of the locked-out blocks will therefore be READ only . The locked-out block and the corresponding status register control bits are shown in Table 5.

The three bits, BP0, BP1, and WPEN, are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g., WREN, RDSR).

Programmable Microelectronics Corp. Issue Date: February, 2004, Rev: 1.4

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