PMC RM7000A Datasheet

64-Bit MIPS RISC Microprocessor with Integrated L2 Cache

BLOCK DIAGRAM

RM7000A

FEATURES

• Dual-Issue symmetric supe rscalar microprocessor

• 400MHz max CPU frequency

• Capable of issuing two instructions

per clock cycle

• Integrated primary and secondary caches

• 16KB Instruction, 16KB Data, and

256KB on-chip secondary

• All are 4-way set associative with

32-byte line size

• Per-line locking in primary and

secondary caches

• Fast Packet Cache™ increases

system efficiency in networking applications

• Integrated external cache controller

• Allows up to 8Mbyte of external

• cache for applications with large

• data sets

• High-performance system interface

• 1000 Mbyte per-second peak

throughput

• 125 MHz max. freq., multiplexed

address/data bus (SysAD)

• Supports two outstanding reads with

out-of-order return

• High-performance floating-point unit

• 800 MFLOPS maximum

• IEEE754 compliant single and

double precision floating-point operations

• 64-bit MIPS instruction set architecture

• Data PREFETCH instruction allows

the processor to overlap cache mis s latency and instruction execution

• Single-cycle floating-point multiply-

add

• Integrated memory management unit

• Fully associative TLB

• 64/48 dual entries map 128/96

pages

• Variable page size

• Embedded applicati on enhanc em en ts

• Fourteen fully prioritized vectored

interrupts-10 external, 2 internal, 2 software

• Specialized DSP integer Multiply-

Accumulate instructions (MAD/MADU), and three-operand Multiply instruction (MUL)

• I and D Test/Break-point (Watch)

registers for emulation and debug

• Performance counter for system

and software tuning and debug

PACKAGING

• Fully Static 0.18µ CMOS design

with dynamic power down logic

• 304 pin TBGA package, 31x31 mm

DEVELOPMENT TOOLS

• Operating Systems:

• Linux by MontaVista and Red Hat

• VxWorks by Wind River Systems

• Nucleus by Accelerated Technology

• Neutrino by QNX Software Systems

• Compiler Suites

• Algorithmics

• Green Hills Software

Dual-Issue Superscalar

64-bit Integer Unit

System Control

PC Unit

Integer Multipli er

64-bit FP Unit

Double/Single IEEE754

Instr. Dispatch

I-Cache

16KB, 4-way, lockable

Fully Assoc., 48 or 64 Entry

Bus Interface U nit

SysA /D Bus

PMC- 2010739(R2) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE © Copyright PMC-Sierra, Inc. 2001

MMU

Int Ctlr

NMI, INT9 – INT0

System Cache (L2)

256KB, 4-way, lockable

D-Cache

16KB, 4-way, lockable

64-Bit MIPS RISC Microprocessor with Integrated L2 Cache

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

RM7000A

• Red Hat

• Evaluation Boards and Companion Chips

• Galileo Technology

• EV-64120A-7000: 32/64-bit,

• 33/66MHz PCI

• EV-64240-7000: 32/64-bit,

• 33/66MHz PCI

• Momentum Computer

• Ocelot: 6U RM7000 Compact PCI

• Single Board Computer

TYPICAL APPLICATION

• Logic Analyzers and Emulation

• HP

• Tektronix

• Corelis

• Crescent Heart Software

RM7000A

64-Bit

100MHz

APPLICATIONS

• Voice Gateways

• Multi-Service Access Platforms

• DSLAMs/Access Concentrators

• Remote Access Switches

•Web Switches

• Layer 3 Switches

• Backbone Switches/Routers

•RAIDs

• Set Top Boxe s

• Networked Printers

• Cellular Base Stations

L3 Cache

64-

bit

PCI-to-PCI

Bridge

PCI Bus

32/64-bit @ 33MHz

32-

bit

Ethernet

MAC

32-

bit

Ethernet

MAC

Marvell/Galileo

GT-64120A

64-

bit

8-bit

64-Bit

100MHz

Data

Buffer

SDRAM

Boot-Flash

Flash

Disk

Watchdog,

C & Control

Registers

Dual UART

Head Office: PMC-Sierra, Inc. 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200

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All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate informatio n, send email to: info@pmc-sierra.com