RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
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RM5261
RM5261™ Microprocessor with 64-Bit
System Bus
Data Sheet
Proprietary and Confidential
Issue 1, March 2001
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Document ID: PMC-2002241, Issue 1
RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
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Legal Information
Copyright
© 2001 PMC-Sierra, Inc.
The information is proprietary and confidential to PMC-Sierra, Inc., and for its customers’ internal use. In
any event, you cannot reproduce any part of this document, in any form, without the express written
consent of PMC-Sierra, Inc.
PMC-2002241 (R1)
Disclaimer
None of the information contained in this document constitutes an express or implied warranty by PMCSierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the
fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts
or systems, of an y of t he pr oducts of PMC-Si erra , Inc., or an y port io n ther eof, r efer red to i n this document .
PMC-Sierra, Inc. expressly disclaims all re presentations and war ra nties of any kind rega rdi ng the contents
or use of the information, including, but not limited to, express and implied warranties of accuracy,
completeness, merchantability, fitness for a particular use, or non-infringement.
In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential
damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or
reliance upon the infor ma tion, whether or not PMC-Sierra, Inc . has been a dvised of the possibility of such
damage.
Trademarks
RM5261 is a trademark of PMC-Sierra, Inc.
Contacting PMC-Sierra
PMC-Sierra, Inc.
105-8555 Baxter Place Burnaby, BC
Canada V5A 4V7
Tel: (604) 415-6000
Fax: (604) 415-6200
Document Information: document@pmc-sierra.com
Corporate Information: info@pmc-sierra.com
Technical Support: apps@pmc-sierra.com
Web Site: http: //www.pmc-sierra.com
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Revision History
RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
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Issue
No. Issue Date
1 March 2001 3828 T. Chapman Applied PMC-Sierra template to exi sting
ECN
Number Originator Details of Change
MPD (QED) FrameMaker document.
Revised Features list, Sections 3.14, 3.19,
3.21, 3.22, 3.23, 3.26, 3.27, 3.30, 3.32, 5,
6, 7, 9.3, 9.4, and packaging diagram
information.
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Document Conventions
The following conventions are used in this datasheet:
•All signal, pin, and bus names described in the text, such as ExtRqst*, are in boldface typeface.
•All bit and field names described in the text, such as Interrupt Mask, are in an italic-bold
typeface.
•All instruction names, such as MFHI, are in san serif typeface.
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Table of Contents
Legal Information ...........................................................................................................................2
Revision History .............................................................................................................................3
Document Conventions .................................................................................................................4
Table of Contents ..........................................................................................................................5
List of Figures ................................. ...... ....... ...................................... ....... ...... ....... ...... ..................7
List of Tables . ....... ...... ....... ...... ....... ...... ....... ...... ....... ...................................... ....... ...... ..................8
1 Features ......................................... ....................................................................... ..................9
2 Block Diagram ...... ....... ...... ....... ...... ....................................... ...... ....... ...... ....... ...... ....... .........10
3 Hardware Overview ...............................................................................................................11
3.1 Superscalar Dispatch ...................................................................................................11
3.2 CPU Registers .............................................................................................................11
3.3 Integer Unit ..................................................................................................................11
3.4 Pipeline ........................................................................................................................12
3.5 Register File .................................................................................................................12
3.6 ALU ..............................................................................................................................12
3.7 Integer Multiply/Divide ..................................................................................................13
3.8 Floating-Point Co-Processor ........................................................................................13
3.9 Floating-Point Unit .......................................................................................................13
3.10 Floating-Point General Register File ............................................................................15
3.11 System Control Co-processor (CP0) ............................................................................15
3.12 System Control Co-Processor Registers .....................................................................15
3.13 Virtual to Physical Address Mapping ............................................................................16
3.14 Joint TLB ......................................................................................................................17
3.15 Instruction TLB .............................................................................................................18
3.16 Data TLB ......................................................................................................................18
3.17 Cache Memory .............................................................................................................18
3.18 Instruction Cache .........................................................................................................19
3.19 Data Cache ..................................................................................................................19
3.20 Write buffer ..................................................................................................................21
3.21 System Interface ............. ...................................... ....... ...... ....... ...... ....... ......................21
3.22 System Address/Data Bus .... ....................................... ...... ....... ...... ....... ......................21
3.23 System Command Bus ................................................ ...... ....... ...... .............................21
3.24 Handshake Signals ......................................................................................................22
3.25 Non-overlapping System Interface ...............................................................................22
3.26 Enhanced Write Modes ................................................................................................23
3.27 External Requests ........................................................................................................24
3.28 Interrupt Handling ........................................................................................................24
3.29 Standby Mode .... ...... ....... ...................................... ....... ...... ....... ...... .............................24
3.30 JTAG Interface .............................................................................................................24
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3.31 Boot-Time Options .......................................................................................................24
3.32 Boot-Time Modes .........................................................................................................25
4 Pin Descriptions ....................................................................................................................26
5 Absolute Maximum Ratings ..................................................................................................29
6 Recommended Operating conditions ....................................................................................30
7 DC Electrical Characteristics .................................................................................................31
8 Power Consumption ..............................................................................................................32
9 AC Electrical Characteristics ................. ...... ....... ...... ....................................... ...... ....... ...... ...33
9.1 Capacitive Load Deration .............................................................................................33
9.2 Clock Parameters ........................................................................................................33
9.3 System Interface Parameters ............. ....... ...... ...... ....... ....................................... ...... ...34
9.4 Boot-Time Interface Parameters ..................................................................................34
10 Timing Diagrams ...................................................................................................................35
10.1 System Interface Timing ....................................... ....... ...... ....... ...... ....... ...... ....... ...... ...35
11 Packaging Information ..........................................................................................................36
12 RM5261 208-pin PQFP Package Pinou t ..... ....... ...... ...... ....... ...... ....... ...... .............................3 8
13 Ordering Information .............................................................................................................40
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List of Figures
Figure 1 Block Diagram .............................................................................................................10
Figure 2 CPU Registers .............................................................................................................11
Figure 3 Pipeline ........................................................................................................................12
Figure 4 CP0 Registers .............................................................................................................16
Figure 5 Kernel Mode Virtual Addressing (32-bit) .....................................................................17
Figure 6 Typical Embedded System Block Diagram .................................................................21
Figure 7 Processor Block Read .................................................................................................23
Figure 8 Processor Block Write .................................................................................................23
Figure 9 Clock Timing ................................................................................................................35
Figure 10 Input Timing ...............................................................................................................35
Figure 11 Output Timing ............................................................................................................35
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List of Tables
Table 1 Integer Multiply/Divide Operations ................................................................................13
Table 2 Floating-Point Instruction Cycles ..................................................................................14
Table 3 Cache Attributes ...........................................................................................................20
Table 4 Boot-Time Mode Bit Stream .........................................................................................25
Table 5 System Interface ...........................................................................................................26
Table 6 Clock/Control Interface .................................................................................................27
Table 7 Interrupt Interface .........................................................................................................27
Table 8 JTAG Interface .............................................................................................................27
Table 9 Initialization Interface ....................................................................................................28
Table 10 Power Supply .............................................................................................................28
Table 11 DC Electrical Characteristics ......................................................................................31
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1 Features
• Dual Issue superscalar microprocessor
• 200, 250, 266 MHz operating frequencies
• 320 Dhrystone 2.1 MIPS
• High-performance system interface
• 64-bit multiplexed system address/data bus for optimum price/performance
• High-performance write protocols maximize uncached write bandwidth
• Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9
• IEEE 1149.1 JTAG boundary scan
• Integrated on-chip caches
• 32KB instruction and 32KB data — 2 way set associative
• Virtually indexed, physically tagged
• Write-back and write-through on a per page basis
• Pipeline restart on first doubleword for data cache misses
• Integrated memory management unit
• Fully associative joint TLB (shared by I and D translations)
• 48 dual entries map 96 pages
• Variable page size (4 KB to 16 MB in 4x increments)
RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
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• High-performance floating-point unit: up to 530 MFLOPS
• Single cycle repeat rate for common single -pr ecision ope ra tions and some double-p recision operations
• Two cycle repeat rate for double-precision multiply and double precision combined
multiply-add operations
• Single cycle repeat rate for single-precision combined multiply-add operation
• MIPS IV instruction set
• Floating point multiply-add instruction increases performance in signal processing
and graphics applications
• Conditional moves to reduce branch frequency
• Index addr ess modes (register + register)
• Embedded application enhancements
• Specialized DSP integer Multiply-Accumulate instructions and 3-operand multiply
instruction
• I and D cache locking by set
• Optional dedicated exception vector for interrupts
• Fully static 0.25 micron CMOS design with power down logic
• Standby reduced power mode with WAIT instruction
• 2.5 V core with 3.3 V IOs
• 208-pin PQFP package
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2 Block Diagram
Figure 1 Block Diagram
Primary Data Cache
2-way Set Associative
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DTag
DTLB
ITag
ITLB
Primary Instruction Cache
2-way Set Associative
A/D Bus
Pad Bus
Store Buffer
Write Buffer
D Bus
Floating-Point
Load/Align
Floating-Point
Register File
Packer/Unpacker
Floating-Point
MultAdd, Add, Sub,
Cvt, Div, Sqrt
Read Buffer
Coprocessor 0
System/Memory
Control
PC Incrementer
Floating-Point Control
Branch PC Adder
ITLB Virtual
Program Counter Int Mult, Div, Madd
Pad Buffer
Joint TLB
Address Buffer
IVA
DVA
FP Bus
FA Bus
Instruction Dispatch Unit
FP
Instruction
Register
Load Aligner
Integer Register File
Integer Address/Adder
Shifter/Store Aligner
Logic Unit
DTLB Virtual
PLL/Clocks
Integer
Instruction
Register
Integer Bus
Integer Control
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3 Hardware Overview
The RM5261 offers a high-level of integration targeted at high-performance embedded
applications. The key elements of the RM5261 are briefly described below.
3.1 Superscalar Dispatch
The RM5261 has an asymmetric superscalar dispatch unit which allows it to issue an integer
instruction and a floating-point computation instruction simultaneously. Integer instructions
include alu, branch, load/store, and floating-point load/store, while floating-point computation
instructions include floating-point add, subtract, combined multiply-add, converts, etc. In
combination with its high- throug hput fully pipel ined fl oatin g-p oint exe cutio n unit, the supersc alar
capability of the RM5261 provides unparalleled price/performance in computationally intensive
embedded applications.
3.2 CPU Registers
The RM5261 CPU has a simple user-visible state consisting of 32 general purpose registers, two
special purpose registers for integer multiplication and division, a program counter, and no
condition code bits. Figure 2 shows the user visible state.
RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
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Figure 2 CPU Registers
General Purpose Registers
63 0
0 63 0
r1 HI
r2 63 0
• LO
•
•
• 63 0
r29 PC
r30
r31
3.3 Integer Unit
Like the RM5260, the RM5261 implements the MIPS IV Instruction Set Architecture, and is
therefore fully upward compatible with applications that run on processors implementing the
earlier generation MIPS I-III instruction sets. Additionally, the RM5261 includes three
implementation specific instructions not found in the baseline MIPS IV ISA but that are useful in
the embedded market place. Described in detail in a later section, these instructions are integer
multiply-accumulate and 3-operand integer multiply.
Multiply/Divide Registers
Program Counter
The RM5261 integer unit includes thirty-two general purpose 64-bit registers, a load/store
architecture with single cycle ALU operations (add, sub, logical, shift) and an autonomous
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multiply/divide unit. Additional register resources include: the HI/LO resul t registers for the twooperand integer multiply/divide operations, and the program counter (PC).
3.4 Pipeline
For integer operations, loads, stores, and other non-floating-point operations, the RM5261
implements a 5-stage int eger pi peli ne. In addi tion to t he in teger pipeli ne, the RM5261 impl emen ts
an extended 7-stage pipeline for floating-point operations.
The RM5261 multiplies the input SysClock by 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, or 9 to produce the
pipeline clock.
Figure 3 shows the RM5261 integer pipeline. As illustrated in the figure, up to five integer
instructions can be executing simultaneously.
Figure 3 Pipeline
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I0
I1
I2
I3
I4
1I-1R:
2I:
2R:
1A:
1A:
1A-2A:
2A:
2A-2D:
1D:
2W:
2I1I 1R 2R 1A 2A 1D 2D 1W 2W
Instruction cache access
Instruction virtual to physical address translation
Register file read, Bypass calculation, Instruction decode, Branch address calculation
Issue or slip decision, Branch decision
Data virtual address calculation
Integer add, logical, shift
Store Align
Data cache access and load align
Data virtual to physical address translation
Register file write
3.5 Register File
The RM5261 has thirty-two general purpose registers with register location 0 (r0) hard-wired to a
zero value. These registers are used for scalar integer operations and address calculation. The
register file has two read ports and one write port and is fully bypassed to minimize operation
latency in the pipeline.
2I1I 1R 2R 1A 2A 1D 2D 1W 2W
2I1I 1R 2R 1A 2A 1D 2D 1W 2W
2I1I 1R 2R 1A 2A 1D 2D 1W 2W
2I1I 1R 2R 1A 2A 1D 2D 1W 2W
one cycle
3.6 ALU
The RM5261 ALU consists of an integer adder/subtractor, a logic unit, and a shifter. The adder
performs address calculations in addition to arithmetic operations. The logic unit performs all
logical and zero s hift d ata moves . The shift er per forms s hifts and store align ment o perat ions. Eac h
of these units is optimized to perfor m all operations in a sing l e processor cycle.
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3.7 Integer Multiply/Divide
The RM5261 has a dedicated integer multiply/divide unit optimized for high-speed multiply and
multiply-accumulate operations. Table 1 shows the performance of the multiply/divide unit on
each operation.
Table 1 Integer Multiply/Divide Operations
Operand
Opcode
MULT/U, MAD/U
MUL 16 bit 3 2 1
DMULT, DMUL TU
DIV, DIVD any 36 36 0 DDIV,
DDIVU
Size Latency
16 bit 3 2 0 32 bit 4 3 0
32 bit 4 3 2 any 7 6 0
any 68 68 0
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Repeat
Rate
Stall
Cycles
The baseline MIPS IV ISA specifies that the results of a multiply or divide operation be placed in
the Hi and Lo registers. These values can then be transferred to the general purpose register file
using the Move-from-Hi and Move-from-Lo (
In addition to the baselin e MIPS IV integer multip ly instructi ons, the RM5261 also imple ments the
3-operand multiply in struc tion,
MUL. This instruction specifies that the multiply result go directly
to the integer register f ile rather th an the Lo register. The portion of the multiply that would have
normally gone into the Hi register is discarded. For applications where it is known that the upper
half of the multiply result is not required, using the
executing an explicit
MFLO instruction.
Also included in the RM5261 are the multiply-add instructions,
multiplies two operands and adds the resulting product to the current contents of the Hi and Lo
registers. The multiply-accumulate operation is the core primitive of almost all signal processing
algorithms allowing the RM5261 to eliminate the need for a separate DSP engine in many
embedded applications.
3.8 Floating-Point Co-Processor
The RM5261 incorporates a high-performance fully pipelined floating-point co-processor which
includes a floating-po int register file and autonomous execution units for multiply/a dd/convert and
divide/square root. The floating-point coprocessor is a tightly coupled execution unit, decoding
and executing instructions in parallel with, and in the case of floating-point loads and stores, in
cooperation with the integer unit. Th e s uperscalar capabili t ies of t he RM52 61 a ll ow f lo ati ng- point
computation instructions to issue concurrently with integer instructions.
MFHI/MFLO) instructi ons.
MUL instruction eliminates the necessity of
MADU/MAD. This inst ruction
3.9 Floating-Point Unit
The RM5261 floating-point execution unit supports single and double precision arithmetic, as
specified in the IEEE S tanda rd 754. The ex ecution uni t is broken i nto a separa te divide /square ro ot
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unit and a pipelined multiply/add unit. Overlap of the divide/square root and multiply/add
operations is supported.
The RM5261 maintains fully precise floating-point exceptions while allowing both overlapped
and pipelined operations. Precise exceptions are extremely important in object-oriented
programming environments and highly desirable for debugging in any environment.
Floating-point operations include:
• add
• subtract
• multiply
• divide
• square root
• reciprocal
• reciprocal square root
• conditional moves
• conversion between fixed-point and floating-point format
• conversion between floating-point formats
• floating-point compare.
Table 2 gives the latencies of the floating-point instructions in internal processor cycles.
Table 2 Floating-Point Instruction Cycles
Operation Latency Repeat Rate
fadd 4 1 fsub 4 1 fmult 4/5 1/2 fmadd 4/5 1/2 fmsub 4/5 1/2 fdiv 21/36 19/34 fsqrt 21/36 19/34 frecip 21/36 19/34 frsqrt 38/68 36/66 fcvt.s.d 4 1 fcvt.s.w 6 3 fcvt.s.l 6 3 fcvt.d.s 4 1 fcvt.d.w 4 1 fcvt.d.l 4 1 fcvt.w.s 4 1 fcvt.w.d 4 1 fcvt.l.s 4 1
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Operation Latency Repeat Rate
fcvt.l.d 4 1 fcmp 1 1 fmov 1 1 fmovc 1 1 fabs 1 1 fneg 1 1
Note: Numbers are represented as single/double precision format.
3.10 Floating-Point General Register File
The floating-point general register file (FGR) is made up of thirty-two 64-bit registers. With the
floating-point load and store double instructions (
take advantage of the 64-bit wide data cache and issue a floating-point co-processor load or store
doubleword instruction in every cycle.
The floating-point c ont rol register space co ntains two registers; one for det er m ini ng c onf iguration
and revision informat i on f o r the coprocessor and one for co ntrol and status inf ormat ion. These are
primarily used for diagnos ti c sof twa re, exception handling, stat e saving and restoring, and contr ol
of rounding modes. To support superscalar operation, the FGR has four read ports and two write
ports, and is fully bypassed to minimize operation latency in the pipeline. Three of the read ports
and one write port are used t o support the combi ned multi ply -add ins truct ion whil e the fo urth re ad
and second write port allows a concurrent floating-point load or store.
LDC1 and SDC1) the floating-point unit can
Released
3.11 System Control Co-processor (CP0)
The system control coprocessor, also called coprocessor 0 or CP0 in the MIPS architecture, is
responsible for the virtual memory sub-system, the exception control system, and the diagnostics
capability of the processor. In the MIPS architecture, the system control co-processor (and thus the
kernel software) is implementati on dependent.
The memory management unit co ntrol s the virtu al memory syste m page mapping . It co nsist s of a n
instruction address translation buffer, ITLB, a data address translation buffer, DTLB, a Joint
instruction and data ad dress transl ation buf fer , JTLB, and co-pr ocessor re gisters used by the virtual
memory mapping sub-system.
3.12 System Control Co-Processor Registers
The RM5261 incorporates all system control co-processor (CP0) registers on-chip. These registers
provide the path through which the virtual memory system’s page mapping is examined and
modified, exceptions are handled, and operating modes are controlled (kernel vs. user mode,
interrupts enabled or disabled, cache features). In addition, the RM5261 includes registers to
implement a real-t ime cyc le coun ti ng faci lity to ai d in ca che dia gnosti c tes ting a nd to assi st in data
error detection.
Figure 4 shows the CP0 registers.
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Figure 4 CP0 Registers
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* Register number
LLAddr
17*
47
0
PageMask
5*
EntryHi
10*
(entries protected
from TLBWR)
TagLo
28*
EntryLo0
2*
EntryLo1
3*
TLB
TagHi
29*
Used for memory
management
Index
0*
Random
1*
Wired
6*
PRId
15*
Config
16*
Context
4*
Count
9*
Status
12*
EPC
14*
ECC
26*
BadVAd dr
8*
Compare
11*
Cause
13*
XContext
20*
CacheErr
27*
ErrorEPC
30*
Used for exception
processing
3.13 Virtual to Physical Address Mappin g
The RM5261 provides three modes of virtual addressing:
• user mode
• kernel mode
• supervisor mode
This mechanism is available to system softw are to provide a secure environme nt for user
processes. Bits in the CP0 register Status determine which virtual addressing mode is used. In the
user mode, the RM5261 provides a single, uniform virtual address space of 1TB (2 GB in 32-bit
mode).
When operating in the kernel mode, four distinct virtual address spaces, totalling over 2.5TB (4
GB in 32-bit mode), are simultaneously available and are differentiated by the high-order bits of
the virtual address.
The RM5261 processors also support a supervisor mode in which the virtual address space over
2TB (2.5 GB in 32-bit mode) , divided into three regions based on the high-order bits of t he vi rtual
address.
When the RM5261 is configured as a 64-bit microprocessor, the virtual address space layout is an
upward compatible extension of the 32-bit virtual address space layout.
Figure 5 shows the address space layout for 32-bit operation.
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RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
Figure 5 Kernel Mode Virtual Addressing (32-bit)
0xFFFFFFFF Kernel virtual address space
(kseg3)
0xE0000000 0xDFFFFFFF Supervisor virtual address space
0xC0000000 0xBFFFFFFF Uncached kernel physical addr ess space
0xA0000000 0x9FFFFFFF Cached kernel physical address space
0x80000000 0x7FFFFFFF User virtual address space
Mapped, 0.5GB
(ksseg)
Mapped, 0.5GB
(kseg1)
Unmapped, 0.5GB
(kseg0)
Unmapped, 0.5GB
(kuseg)
Mapped, 2.0GB
Released
0x00000000
3.14 Joint TLB
For fast virtual-to-physical address translation, the RM5261 uses a large, fully associative TLB
that maps 96 virtual pages t o their corre spondin g physic al a ddress es. As indi cated by its name, the
joint TLB (JTLB) is used for both instruction and data translations. The JTLB is organized as 48
pairs of even-odd entrie s, an d maps a virt ual addr ess and ad dress space ide nti fier int o th e lar ge, 64
GB physical address space.
Two mechanisms are provided to assist in controlling the amount of mapped space and the
replacement characte ristic s of various memory regi ons. First, the page si ze can be conf igured, on a
per-entry bas is , to use page sizes in the ra nge of 4 KB to 16 MB (in multi pl es of 4 ). The CP0 Page
Mask register is loaded with the desired page size of a mapping, and that size is stored into the
TLB along with the virtual address when a new entry is written. Thus, operating systems can
create spec ial purpose maps; for example, an entire frame buffer can be m emory mapped using
only one TLB entry.
The second mechanism controls the replacement algorithm when a TLB miss occurs. The
RM5261 provides a random replacement algorithm to select a TLB entry to be written with a new
mapping; however , the pr ocessor als o provides a mech anism whereby a sys tem specifi c number of
mappings can be locked into the TLB, thereby avoiding random replacement. This mechanism
allows the operating system to guarantee t hat certain pages are always mapped for performance
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reasons and for deadlock avoidance. This mechanism also facilitates the design of real-time
systems by allowing deterministic access to critical software.
The JTLB also contains information that controls the cache coherency protocol for each page.
Specifically, each page has attribute bits to determine whether the coherency algorithm is one of
the followin g:
• uncached
• non-coherent write-back
• non-coherent write-through with write-allocate
• non-coherent write-through without write-allocate
• sharable
• exclusive
• update.
The non-coherent proto cols are used for both cod e and data on th e RM5261, wit h data usi ng write back or write-through depending on the application.
The coherency attributes generate coherent transaction types on the system interface. However, in
the RM5261 cache coherency is not supported. Hence the coherency attributes should never be
used.
3.15 Instruction TLB
The RM5261 implements a 2-entry instruction TLB (ITLB) to minimize contention for the JTLB,
eliminate the timing critical path of translating through a large associative array, and save power.
Each ITLB entry maps a 4 KB page. The ITLB improves performance by allowing instruction
address translation to occur in parallel with data address translation. When a miss occurs on an
instructio n address translation by the ITLB, the least-recently used ITLB entry is filled from the
JTLB. The operation of the ITLB is c ompletely transparent to the user.
3.16 Data TLB
The RM5261 implements a 4-entry data TLB (DTLB) for the same reasons cited above for the
ITLB. Each DTLB entry maps a 4 KB page. The DTLB improves performance by allowing data
address translation to occur in par al le l with instructio n address translat ion. When a miss occurs on
a data address translation by the DTLB, the DTLB is fil led from th e JTLB. The DTLB refill is
pseudo-LRU: the least recently used entry of the least recently used pair of entries is filled. The
operation of the DTLB is completely transparent to the user.
3.17 Cache Memory
The RM5261 incorporates on-chip instruction and data caches that can be accessed in a single
processor cycle. Each cache has its own 64-bit data path and both caches can be accessed
simultaneously. The cache subsystem provides the integer and floating-point units with an
aggregate bandwidth of 3.2 GB per second at an internal clock frequency of 200 MHz.
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3.18 Instruction Cache
The RM5261 incorporates a two-way set associative on-chip instruction cache. This virtually
indexed, physically tagged cache is 32 KB in size and is protected with word parity.
Since the cache is virtually indexed, the virtual-to-physical address translation occurs in parallel
with the cache access, further increasing performance by allowing these two operations to occur
simultaneously. The cache tag contains a 2 4-bit physic al ad dress, a valid bit, and a s ingle pari ty bit .
The instruction cache is 64-bits wide and can be accessed each processor cycle. Accessing 64 bits
per cycle allows the instruction cache to supply two instructions per cycle to the superscalar
dispatch unit. For typical code sequences where a floating-point load or store and a floating-point
computation instruction are being issued together in a loop, the entire bandwidth available from
the instruction cache will be consumed.
Cache miss refill writes 64 bits per cycle to minimize the cache miss penalty. The line size is eight
instructions (3 2 bytes) to maximi ze the p erfor mance of c ommunic ation betwe en the p rocess or and
the memory system.
Like the R4650, the RM5261 supports cache locking. The contents of one set of the cache, set A,
can be locked by setting a bit in the coprocessor 0 Status register. Locking the set prevents its
contents from bei ng ove rwrit ten b y a subs equent cach e miss . Refill wil l oc cur o nly i nto s et B. This
mechanism allows the programme r to lock critical code in to the cache thereby guaranteeing
deterministic behavior for the locked code sequence.
RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
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3.19 Data Cache
For fast, single cycle data access, the RM5261 includes a 32 KB on-chip data cache that is twoway set ass ociative w ith a fixed 32 -byte (eight words) line size.
The data cache is protected with byte parity and its tag is protected with a single parity bit. It is
virtually indexed and physically tagged to allow simultaneous address translation and data cache
access.
Cache protocols supported for the data cache are:
1. Uncached Data loads and instr uction fetches from unc ached memory space are brought in from the main
memory to the register file and the execution unit, respectfully. The caches are not accessed.
Data store s to uncached memory space go directly to the main memory without updating the
data cache.
2. Write-back Loads and instruction fetches first search the cache, reading main memory only if the desired
data is not cache resident. On data store operations, the cache is first searched to determine if
the target address is cache resident. If it is resident, the cache contents are updated, and the
cache line is marked for later write-back. If the cache lookup misses, the target cache line is
first brought into the cache and then the write is performed as above.
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RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
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3. Write-through with write allocate Loads and instruction fetches first search the cache, reading main memory only if the desired
data is not cache resident. On data store operations, the cache is first searched to determine if
the target address is cache resident. If it is resident, the cache contents are updated and main
memory is written, leaving the write-back bit of the cache line unchang ed. If the ca che lookup
misses, the target line is first brought into the cache and then the write is performed as above.
4. Write-through without write allocate Loads and instruction fetches first search the cache, reading main memory only if the desired
data is not cache resident. On data store operations, the cache is first searched to determine if
the target address is cache resident. If it is resident, the cache contents are updated and main
memory is written, leaving the write-back bit of the cache line unchang ed. If the ca che lookup
misses, then only main memory is writt en.
The most commonly used write policy is write-back, where a store to a cache line does not
immediately cause the main memory to be updated. This increases system performance by
reducing bus traffic and eliminating the bottleneck of waiting for each store operation to finish
before issuing a subsequent memory operation. Software can, however, select write-through on a
per-page basis when appropriate, such as for frame buffers.
Associated with the data cache is the store buffer. When the RM5261 executes a store instruction,
this single-entry buffer gets written w ith the stor e data while the tag comparison is performed. If
the tag matches, then th e data is written into the data cache in the next cy cle that the data cache is
not accessed (the next non-load cycle). The store buffer allows the RM5261 to execute a store
every processor cycle and to perform back-to-back stores without penalty. In the event of a store
immediately followed by a load to the same address, a combined merge and cache write occurs
such that no penalty is incurred. The RM5261 cache attributes for both the instruction and data
caches are summarized in Table 3.
T a ble 3 Cache Attributes
Characteristics Instruction Data
Size 32KB 32KB Organization 2-way set asso ciative 2-way set associativ e Line size 32B 32B Index vAddr
Tag pAddr Write policy n.a. write-back/write-through
Read order sub-block sub-block Write order sequential sequential miss restart after transfer of entire line first double Parity per-word per-byte Cache locking set A set A
11..0
31..12
vAddr
pAddr
11..0
31..12
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3.20 Write buffer
Writes to external memory, whether cache miss write-backs or store s to uncached or wri te-thr ough
addresses, use the on-chip write buffer. The write buffer holds up to four 64-bit address and data
pairs. The entire buffer is used for a data cache write-back and allows the processor to proceed in
parallel with the memory update. For uncached and write-through stores, the write buffer
significantly increases performance by decoupling the SysAD bus transfers from the instruction
execution stream.
3.21 System Interface
The system interface consists of a 64-bit Address/Data bus with 8 parity check bits and a 9-bit
command bus. In addition, there are 6 handshake signals and 6 interrupt inputs. The interface is
capable of transferring dat a be twee n the processor and memory at a peak rate of 800 MB/ sec with
a 100 MHz SysClock.
Figure 6 shows a typical embed ded syst em using t he RM5261. In th is exampl e, a bank of DRAMs
and a memory controller ASIC share the processor’s SysAD bus while the memory controller
provides separate ports to a boot ROM and an I/O system.
RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
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Figure 6 Typical Embedded System Block Diagram
DRAM
72
Latch
RM5261
72
23
3.22 System Address/Data Bus
The 64-bit System Address Data (SysAD) bus is used to transfer addresses and data between the
RM5261 and the rest of the system. It is protected with an 8-bit parity check bus (SysADC). The
system int erface is configurable to allow easy interfacing to memory and I/O systems of varying
frequencies.
The Block Write data rate, Non-block Write protocol, and Output Drive Strength are
programmable at Boot time via the Mode Control bits. The rate at which the processor receives
data is fully controlled by the external device.
Control
Address
Memory I/O
Controller
Flash/
Boot
Rom
8
x x
PCI Bus
3.23 System Command Bus
The RM5261 interface has a 9-bit System Command (SysCmd) bus. The command bus indicates
whether the SysAD bus carries address or data information on a per-clock basis. If the SysAD
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carries address, t he SysCmd bus indicates what type of transa ction is t o take place ( for example, a
read or write). If t he SysAD carries data, t he SysCmd bus pro vides inf ormation abou t the data (for
example, this is the last data word transmitted, or the data contains an error). The SysCmd bus is
bidirectional to support both processor requests and external requests to the RM5261. Processor
requests are initia ted by the RM5261 a nd responded to by an exter nal device . External r equests ar e
issued by an external device and require the RM5261 to respond.
The RM5261 supports one- to ei ght -by te tra nsf er s as well as block transfers on the SysAD bus. In
the case of a sub-double word tra nsfer , the thre e low-order ad dress bits give the byte ad dress of the
transfer, and the SysCmd bus indicates the number of bytes being transferred.
3.24 Handshake Signals
There are six handshake signals on t he s y st em int er fa ce. Two of these, RdRdy* an d WrRdy*, are
used by an external device to indicate to the RM5261 whether it can accept a new read or write
transaction. The RM5261 samples these signals before deasserting the address on read and write
requests.
ExtRqst* and Release* are used to transfer control of the SysAD and SysCmd buses from the
processor to an external device. When an external device needs to control the interface, it asserts
ExtRqst*. The RM5261 responds by asserting Release* to release the system interface to slave
state.
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ValidOut* and ValidIn* are used by the RM5261 and the external device respect ive ly t o indi ca te
that there is a valid address, command or data on the SysAD and SysCmd buses. The RM5261
asserts ValidOut* when it is driving these buses with a valid address, a command or data, and the
external device drives ValidIn* when it has control of the system interface and is driving a valid
address, command or data.
3.25 Non-overlapping System Interface
The RM5261 requires a non-o verlapping sy stem interfac e, compatible with t he R5000. This means
that only one processor request may be outstanding at a time and that t he r eque st must be serviced
by an external device before the RM5261 issues another request. The RM5261 can issue read and
write requests to an ex ternal device, whe reas an external device c an issue null and writ e reques ts to
the RM5261.
For processor reads the RM5261 asserts ValidOut* and simultaneously drives the address and
read command on the SysAD a nd SysCmd buses respectively. If the system interface has RdRdy*
asserted, then the processor tristates its driv ers and releases the system interface to the slave state
by asserting Release*. The external device can then begin sending data to the RM5261.
Figure 7 shows a processor block read request and the external agent read response. The read
latency is four cycles (ValidOut* to ValidIn*), and th e res ponse da ta pat tern is DDDD, i ndicat ing
that data can be transferred on every clock with no wait states in-between.
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Figure 7 Processor Block Read
SysClock
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SysAD
SysCmd
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
Addr
Read NData NData NData NEOD
Data0 Data1 Data2 Data3
Figure 8 shows a process or bloc k writ e using write respons e patt ern DDDD, or code 0, o f the b oottime mode select options.
Figure 8 Processor Block Write
SysClock
SysAD
SysCmd
ValidOut*
ValidIn*
Addr Data0 Data1 Data2 Data3
Write NData NData NData NEOD
RdRdy*
WrRdy*
Release*
3.26 Enhanced Write Modes
The RM5231 implements two enhancements to the original R4000 write mechanism: Write
Reissue and Pipeline Writes. The original R4000 allowed a write address cycle on the SysAD bus
only once every four SysClock cycles. Hence for a non-block write, this meant that two out of
every four cycles were wait states.
Pipelined write mode eliminates these two wait states by allowing the processor to drive a new
write address onto the bus immediately after the previous data cycle. This allows for higher
SysAD bus utilization. However, at high bus frequencies the processor may drive a subsequent
write onto the bus prior to the time the external agent deasserts WrRdy*, indicating that it can not
accept another write cycle. This can cause the write cycle to be missed.
Write re issue mode is an enhance ment to pipeli ned writ e mode and allo ws the proce ssor to re is sue
missed write cycles. If WrRdy* is deasserted during the issue phase of a write operation, the cycle
is aborted b y the processor and reissued at a later time.
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In write reissue mode, a write rate of one write every two bus cycles can be achieved. Pipelined
writes have the same two bus cycle write repeat rate, but can issue one additional write following
the deasse rtion of WrRdy*.
3.27 External Requests
The External Request pin , ExtRqs t*, is asserted by the external agent when it requi res mastership
of the system interface, either to perform an independent transfer or to write to the interrupt
register within the RM5261. An independent transfer is a data transfer between two external
agents or between an external agent and the memory or perip heral on the system interface.
Following the assertion of ExtRqst*, the RM5261 tri-states it s drive rs allo wing th e extern al agent
to use the system interface buses to complete an independent transfer. The external agent is
responsible for re turni ng mastershi p of th e syst em interfac e to th e RM5231 when it has complet ed
the independent transfer and does so by executing an External Null cycle.
3.28 Interrupt Handling
The RM5261 supports a dedicated interrupt vector. When enabled by the real time executive (by
setting a bit in th e Cause regis ter), int errupts vector to a s pecific a ddress tha t is not sha red with any
of the other exce ption types . Thi s capa bility eli minate s the need to go through the no rmal so ft ware
routine for exception decode and dispatch, thereby lowering interrupt latency.
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3.29 Standby Mode
The RM5261 provides a means to reduce the amount of power consumed by the internal core
when the CPU would otherwise not be performing any useful operations. This state is known as
Standby Mode.
Executing the
Mode. When the wait instruction completes the W pipe stage, and if the SysAD bus is currently
idle, the intern al proce ssor clock stops , ther eby f reezi ng th e p ipeline. The phase lock loop, or PLL,
internal timer/counter, and the “wake up” input pins: Int[5:0]*, NMI*, ExtReq*, Reset*, and
ColdReset* will continue to operat e in their normal fashion. If the SysAD bus is not idle when the
WAIT instruction completes the W pipe-stage, then the WAIT is treated as a NOP until the bus
operation is completed. Once the processor is in Standby, any interrupt, including the internally
generated timer interrupt, causes the processor to exit Standby mode and resume operation where
it left off. The
time executive.
WAIT instruction enables interrupts and causes the processor to enter Standby
WAIT instruction is typically inser ted in the idle loop of the oper ating syst em or real
3.30 JTAG Interface
The RM5261 interface supports JTAG Test Access Po rt (TAP) boundary scan in conformanc e with
the IEEE 1149.1 specification. The JTAG interface is especially helpful for checking the integrity
of the processors pin connections.
3.31 Boot-Time Options
Fundamental operational modes for the processor are initialized by the boot-time mode control
interface. This serial interface operates at a very low frequency (SysClock divided by 256). The
low frequency operation allows the initialization information to be kept in a low cost EPROM or
system interface ASIC.
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Immediately after the VccOK signal is asserted, the processor reads a serial bit stream of 256 bits
to initialize all the fundamental operational modes. ModeClock run continuously from the
assertion of VccOK.
3.32 Boot-Time Modes
The boot-time serial mode stream is defined in Table 4. Bit 0 is the bit presented to the processor
as the first bit in the stream when VccOK is asserted. Bit 255 is the last bit transferred.
Table 4 Boot-Time Mode Bit Stream
Mode
bit Description
0 reserved (must be zero) 14:13 Output driver strength - 100% = fastest
4:1 Write-back data rate
0: DDDD 1: DDxDDx 2: DDxxDDxx 3: DxDxDxDx 4: DDxxxDDxxx 5: DDxxxxDDxxxx 6: DxxDxxDxxDxx 7: DDxxxxxxDDxxxxxx 8: DxxxDxxxDxxxDxxx 9-15 reserved
7:5 Pclock to SysClock Multiplier
Mode Bits 7:5 Mode Bit 20=0 Mode Bit 20=1
000 Multiply by 2 n/a
001 Multiply by 3 n/a
010 Multiply by 4 n/a
011 Multiply by 5 Multiply by 2.5
100 Multiply by 6 n/a
101 Multiply by 7 Multiply by 3.5
110 Multiply by 8 n/a
111 Multiply by 9 Multiply by 4.5
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Mode
bit Description
00: 67% strength 01: 50% strength 10: 100% strength 11: 83% strength
15 Reserved: Must be zero
17:16 System configuration identifiers - software
visible in Config[21..20] register
8 Specifies byte ordering. Logically ORed
19:18 Reserved: Must be zero
with BigEndian input signal.
0: Little endian 1: Big endian
10:9 Non-Block Wri te Protocol
00: R4000 compatible 01: reserved 10: pipelined 11: write re-issue
11 Timer Interrupt Enable/Disable
0: Enable the timer interrupt on Int5* 1: Disable the timer interrupt on Int5*
20 Select Pclock to SysClock Multiply Mode
0: Integer Multipliers 1: Half-Integer Multipliers
21 External Bus Width
0: 64-bit 1: 32-bit
12 Reserved: Must be zero 255:22 Reserved: Must be zero
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4 Pin Descriptions
The following is a list of interface, interrupt, and miscellaneous pins available on the RM5261.
T able 5 System Interface
Pin Name Type Description
ExtRqst* Input External Request
Release* Output Release interface
RdRdy* Input Read Ready
WrRd y* Input Write R eady
ValidIn* Input Valid Input
ValidOut* Output Valid Output
SysAD[63:0] Input/Output System Address/Data bus
SysADC[7:0] Input/Output System Address/Data check bus
SysCmd[8:0] Input/Output System Command/Data identifier bus
SysCmdP Input/Output Reserved for system command/data identif ier bus parity
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Signals that the system interface is submitting an external request.
Signals that the processor is releasing the system interface to slave state.
Signals that an external agent can now accept a processor read.
Signals that an external agent can now accept a processor write request.
Signals that an external agent is now drivin g a valid address or data on
the SysAD bus and a valid command or data identifier on the SysCmd
bus.
Signals that the pro ce ss or is n ow d r iv ing a v ali d add res s or dat a o n the
SysAD bus and a valid comm and or data iden tifi er on the Sy sCm d bus .
A 64-bit address and data bus for communication between the processor and an external agent.
An 8-bit bus contain ing pari ty che ck bi ts for the SysAD bus durin g da ta cycles.
A 9-bit bus for command and data identifier transmission between the
processor and an external agent.
For the RM5261, unused on input and zero on output.
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RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
Table 6 Clock/Control Interface
Pin Name Type Description
SysClock Input System Clock
Master clock input used as the system interface reference clock. All
output timings are relative to this input clock. Pipeline operation
frequency is derived by multiplying this clock up by the factor selected
during boot initialization
VccP Input Quiet Vcc for PLL
Quiet Vcc for the internal phase locked loop. Must be connected to VccInt through a filt er circuit .
VssP Input Quiet Vss for PLL
Quiet Vss for the interna l phas e lock ed loop . Must be conn ected to Vss through a filter circuit.
Table 7 Interrupt Interface
Pin Name Type Description
Int[5:0]* Input Interrupt
Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register.
NMI* Input Non-maskable inte rrup t
Non-maskable interrupt, ORed with bit 6 of the interrupt register.
Released
Table 8 JTAG Interface
Pin Name Type Description
JTDI Input JTAG data in
JTAG serial data in.
JTCK Input JTAG clock input
JTAG serial clock input.
JTDO Output JTAG data out
JTAG serial data out.
JTMS Input JTAG command
JTAG command signal, signals that the incoming serial data is command data.
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Table 9 Initialization Interface
Pin Name Type Description
BigEndian Input Allows the system to change the processor addressing mode without
rewriting the mode ROM.
VccOK Input Vcc is OK
When asserted, this signal indicates to the RM5261 that the 3.3V
power supply has been a bove 3.0V for more than 1 00 m illis econd s and
will remain stable. The assertion of VccOK initiates the reading of the
boot-time mode control serial stream.
ColdReset* Input Cold reset
This signal must be asserted for a power on reset or a cold reset.
ColdReset must be de-asserted synchronously with SysClock.
Reset* Input Reset
This signal must be asserted for any reset sequence. It may be
asserted synchronously or asynchronously for a cold reset, or
synchronously to initiate a warm reset. Reset must be de-asserted
synchronously with SysClock.
ModeClock Output Boot mode clock
Serial boot-mode data clock output at the system clock frequency divided by 256.
ModeIn Input Boot mode data in
Serial boot-mode data input.
Table 10 Power Supply
Pin Name Type Description
VccInt Input Power supply for core. VccIO Input Power supply for I/O. Vss Input Ground return.
Note
1. An "*" at the end of the signal denotes active low.
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5 Absolute Maximum Ratings
Symbol Rating Limits Unit
V
TERM
T
CASE
T
STG
I
IN
I
OUT
Notes
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the d evic e. This is a stress rati ng on ly an d functional operation of the devi ce at th es e o r a ny
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. V
minimum = -2.0 V for pulse width less than 15 ns. VIN should not exceed 3.9 Volts.
IN
3. When VIN < 0V or VIN > VccIO
4. Not more than one output should be shorted at a time. Duration of the short should not exceed 30
seconds.
Terminal Voltage with respect to Vss
Operating Temperature Commercial 0 to +85 °C Industrial –45 to +85 °C Storage Temperature –55 to +125 °C
DC Input Current
DC Output Current
1
–0.5
2
to +3.9
3
±20
4
±20
V
mA
mA
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RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
6 Recommended Operating conditions
Grade Temperature Vss VccInt VccIO VccP
Commercial 0°C to +85°C (Case) 0 V 2.5 V ± 5% 3.15 V to 3.45 V 2.5 V ± 5% Industrial -40°C to +85°C (Case) 0 V 2.5 V ± 5% 3.15 V to 3.45 V 2.5 V ± 5%
Notes
1. VccIO should not exceed VccInt by greater than 1.2V during the power-up sequence.
2. Applying a logic high state to any I/O pin before VccInt becomes stable is not recommended.
3. As specified in IEEE 1149.1 (JT AG), the JTMS pin must be held high during reset to avoid entering JTAG
test mode.
4. VccP must be connected to VccInt through a passive filter circuit. See the RM5200 User’s Manual for
the recommended filter circuit.
Released
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RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
7 DC Electrical Characteristics
T a ble 11 DC Electrical Characteristics
Released
Parameter
V
OL
V
OH
V
OL
V
OH
V
IL
V
IH
I
IN
Minimum Maximum Conditions
0.2V |I
VccIO - 0.2V
0.4V |I
2.4V
-0.3V 0.8V
2.0V VccIO + 0.3V
±15 µA
±15 µA
OUT
OUT
VIN = 0
= VccIO
V
IN
|= 100 µA
| = 2 mA
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8 Power Consumption
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Conditions:
Max: VccInt = 2.625
Parameter
VccInt Power (mWatts)
Notes
1. Typical integer instruction mix with nominal supply voltage (untested).
2. Worst case instruction mix with maximum supply voltage.
3. I/O supply power is application dependent, but typically <20% of VccInt.
standby No SysAD bus activity 350 435 450 active R4000 write prot ocol with no FPU
Typ: VccInt = 2.5V
operation
Write re-issue or pipelined writes
with superscalar
CPU Clock Speed
200 MHz 250 MHz 266 MHz
Typ1Max2Typ1Max2Typ1Max
1600 3200 1850 3700 1900 3800
1750 3500 2025 4050 2075 4150
2
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RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
9 AC Electrical Characteristics
9.1 Capacitive Load Deration
Parameter Symbol Min Max Units
Load Derate C IO Power Derate 21 mW/25pF/MHz
IO Power Derate @ 20pF load 4.0 5.5 mW/MHz
9.2 Clock Parameters
Parameter Symbol
SysClock High t SysClock Low t
SysClock Frequency
SysClock Period t
Clock Jitter for SysClock t SysClock Rise Time t SysClock Fall Time t ModeClock Period t JTAG Clock Period t
Note
1. Operation of the RM5261 is only guaranteed w ith the Phase Lock Loop Enabled.
1
ModeCKP
JTAGCKP
SCH
SCL
SCP
JI
CR
CF
LD
Test
Conditions
Transition ≤ 5ns 3 3 3 ns
Transition ≤ 5ns 3 3 3 ns
Released
2 ns/25pF
CPU Speed
200 MHz 250 MHz 266 MHz
Min Max Min Max Min Max
25 100 25 125 33.3 106 MHz
40 40 30 ns
±200 ±150 ±150 ps
222ns
222ns
256 256 256 t
444t
Units
SCP
SCP
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9.3 System Interface Parameters
1
Parameter Symbol Conditions
Data Output
Data Setup
Data Hold
2,3
4
4
Notes
1. Timings are measured from 1.5 V of the clock to 1.5 V of the signal.
2. Capacitive load for all maximum output timings is 50 pF. Minimum output timings are for a
theoretical no load condition - untested.
3. Data Output timing applies to all signal pins whether tristate I/O or output only.
4. Setup and Hold parameters apply to all signal pins whether tristate I/O or input only.
5. Only mode 14:13 = 00 is tested and guaranteed.
t
t
t
DO
DS
DH
mode14:13 = 105 (fastest)
mode14:13 = 11
mode14:13 = 00
5
5
mode14:13 = 015 (slowest)
t
= see above table
rise
= see above table
t
fall
9.4 Boot-Time Interface Parameters
200–266 MHz
UnitsMin Max
1.0 4.5 ns
1.0 5.0 ns
1.0 5.5 ns
1.0 6.0 ns
2.5 ns
1.0 ns
Parameter Symbol Min Max Units
Mode Data Setup tDS(M) 4 SysClock cycles Mode Data Hold t
(M) 0 SysClock cycles
DH
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 34
Document ID: PMC-2002241, Issue 1
10 Timing Diagrams
Figure 9 Clock Timing
SysClock
t
Rise
10.1 System Interface Timing
(SysAD, SysCmd, ValidIn*, ValidOut*, etc.)
Figure 10 Input Timing
SysClock
RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
Released
t
t
High
t
Fall
Low
±t
JitterIn
Data
Figure 11 Output Timing
SysClock
Data
t
DS
t
DOmin
Data
t
DH
t
DOmax
DataData
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 35
Document ID: PMC-2002241, Issue 1
11 Packaging Information
4
D
D3
Pin #1 I.D.
D/2
A
3
2.00 DIA 4 PLACES
E/2
D
3
E
4
SEE
DETAIL “A”
11.0 REF.
10
208
1
E3
RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
Released
5
7
DA-B
75
H
E1
E1/2
0.20 4X
(E2)
D1/2
D1
(D2)
11.0 REF.
ODD LEAD SIDES
(b)
EVEN LEAD SIDES
e/2
3
X
X = A, B, OR D
0.20CA-B
SEATING
PLANE
D4X
11.0 REF.
12-16°
11
aaa
M
0.13/0.23
(N-4)X
SECTION C-C
C
8
B
3
TOP VIEW
SEE DETAIL “B”
e
b
DA-BC
8
11
WITH LEAD FINISH
b
0.13/0.19
b
1
BASE METAL
11
4.00 R.
4 PLACES
A
11
“COUNTRY OF ORIGIN” MARK
3.00 REF. DIA. 4 PLACES
C
0.076
0.10
A2
13
A1
DETAIL “B”
H
2
BOTTOM VIE W
0.40 MIN.
1.30 REF.
0.13/0.30 R
C
C
L
0.13
R. MIN.
11.0 REF.
DETAIL “A”
0° MIN.
GAGE PLANE
0.25
0-7°
All dimensions are in millimeters unless otherwise noted.
208PQ4
Symbol
A -- 3.70 4.07 A1 0.25 0.33 -A2 3.20 3.37 3.60 D 30.60 BSC To be determined at seating Plane C. D1 28.00 BSC Dimensions D1 and E1 do not include mold protrusion. Allowable mold
D2 25.00 REF. E 30.60 BSC To be determined at seating Plane C. E1 28.00 BSC Dimensions D1 and E1 do not include mold protrusion. Allowable mold
E2 25.00 REF. D3 21.0 REF. E3 21.0 REF. L 0.46 0.56 0.66 e 0.50 BSC b 0.17 0.22 0.27 b1 0.17 0.20 0.23
NoteMin Nominal Max
protrusion is 0.254 MM per side. Dimension D1 and E1 do include mold
mismatch and are determined at Datum Plane H.
protrusion is 0.254 MM per side. Dimension D1 and E1 do include mold
mismatch and are determined at Datum Plane H.
3
X
X = A, B, OR D
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 36
Document ID: PMC-2002241, Issue 1
RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
Released
208PQ4
Symbol
aaa 0.08
ThetaJa 13.7
ThetaJc 1.5
° C/W
° C/W
NoteMin Nominal Max
Notes
1. All dimensioning and tolerances confirm to ASME Y14.5–1994.
2. Datum Plane H located at the bottom of the mold parting line and coincident with where lead exits plastic
body.
3. Datums A–B and D to be determined where center line between leads exits plastic body at Datum Plane
H.
4. To be determined at seating Plane C.
5. Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.254 MM per side.
Dimension D1 and E1 do include mold mismatch and are determined at Datum Plane H.
6. “N” is number of terminals.
7. Package top dimensions are smaller than bottom dimensions by 0.20 millimeters and top of package will
not overhang bottom of package.
8. Dimensions b does not include Damabr protrusion. Allowable Damabr protrusion shall be 0.08 MM. Total
in excess of b dimension at maximum mate rial condition. Damabr can not be loca ted on the lower radius
or the foot. The dimension space be tween protru si on and an ad jacen t lead shall no t be less than 0.07 MM
for 0.4 MM and 0.50 MM pitch package.
9. All dimensions are in millimeters.
10. The o pti onal exposed heat shri nk is coincident with the top or bottom side of th e pa ck ag e an d n ot allowed
to protrude beyond th at surface .
11. These dimensions apply to the flat section of the lead between 0.10 MM and 0.25 MM from the lead tip.
12. This drawing conforms to JEDEC registered outline MS-029. But the heat slug dimension was not
specified on JEDEC.
13. A1 is defined as the distance from the seating plane to the lowest point of the package body.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 37
Document ID: PMC-2002241, Issue 1
RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
12 RM5261 208-pin PQFP Package Pinout
Pin Function Pin Function Pin Function Pin Function
1VccIO2NC 3NC 4VccIO 5 Vss 6 SysAD4 7 SysAD36 8 SysAD5 9 SysAD37 10 VccInt 11 Vss 12 SysAD6 13 SysAD38 14 VccIO 15 Vss 16 SysAD7 17 SysAD39 18 SysAD8 19 SysAD40 20 VccInt 21 Vss 22 SysAD9 23 SysAD41 24 VccIO 25 Vss 26 SysAD10 27 SysAD42 28 SysAD11 29 SysAD43 30 VccInt 31 Vss 32 SysAD12 33 SysAD44 34 VccIO 35 Vss 36 SysAD13 37 SysAD45 38 SysAD14 39 SysAD46 40 VccInt 41 Vss 42 SysAD15 43 SysAD47 44 VccIO 45 Vss 46 ModeClock 47 JTDO 48 JTDI 49 JTCK 50 JTMS 51 VccIO 52 Vss 53 NC 54 NC 55 NC 56 VccIO 57 Vss 58 ModeIn 59 RdRdy* 60 WrRdy* 61 ValidIn* 62 ValidOut* 63 Release* 64 VccP 65 VssP 66 SysClock 67 VccInt 68 Vss 69 VccIO 70 Vss 71 VccInt 72 Vss 73 SysCmd0 74 SysCmd1 75 SysCmd2 76 SysCmd3 77 VccIO 78 Vss 79 SysCmd4 80 SysCmd5 81 VccIO 82 Vss 83 SysCmd6 84 SysCmd7 85 SysCmd8 86 SysCmdP 87 VccInt 88 Vss 89 VccInt 90 Vss 91 VccIO 92 Vss 93 Int0* 94 Int1* 95 Int2* 96 Int3* 97 Int4* 98 Int5* 99 VccIO 100 Vss 101 NC 102 NC 103 NC 104 NC 105 VccIO 106 NMI* 107 ExtRqst* 108 Reset* 109 ColdReset* 110 VccOK 111 BigEndian 112 VccIO 113 Vss 114 SysAD16 115 SysAD48 116 VccInt 117 Vss 118 SysAD17 119 SysAD49 120 SysAD18 121SysAD50122VccIO 123Vss 124SysAD19 125 SysAD51 126 VccInt 127 Vss 128 SysAD20 129 SysAD52 130 SysAD21 131 SysAD53 132 VccIO 133 Vss 134 SysAD22 135 SysAD54 136 VccInt 137 Vss 138 SysAD23 139 SysAD55 140 SysAD24 141SysAD56142VccIO 143Vss 144SysAD25 145 SysAD57 146 VccInt 147 Vss 148 SysAD26 149 SysAD58 150 SysAD27 151 SysAD59 152 VccIO
Released
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 38
Document ID: PMC-2002241, Issue 1
RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
Released
Pin Function Pin Function Pin Function Pin Function
153 Vss 154 NC 155 NC 156 Vss 157 NC 158 NC 159 NC 160 NC 161VccIO162Vss 163SysAD28164SysAD60 165 SysAD29 166 SysAD61 167 VccInt 168 Vss 169 SysAD30 170 SysAD62 171 VccIO 172 Vss 173 SysAD31 174 SysAD63 175 SysADC2 176 SysADC6 177 VccInt 178 Vss 179 SysADC3 180 SysADC7 181VccIO182Vss 183SysADC0184SysADC4 185 VccInt 186 Vss 187 SysADC1 188 SysADC5 189 SysAD0 190 SysAD32 191 VccIO 192 Vss 193 SysAD1 194 SysAD33 195 VccInt 196 Vss 197 SysAD2 198 SysAD34 199 SysAD3 200 SysAD35 201VccIO202Vss 203NC 204NC 205 NC 206 NC 207 VccIO 208 Vss
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 39
Document ID: PMC-2002241, Issue 1
13 Ordering Information
RM5261 -123 A I
Valid Combinations
RM5261–200–Q
RM5261–250–Q
RM5261–266–Q
RM5261–200–QI (Contact Sales prior to design)
RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
Released
Temperature Grade:
(blank) = commercial
I = Industrial
Package Type:
Q = Power Quad 4 (PQ-4)
Device Maximum Speed
Device Type
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 40
Document ID: PMC-2002241, Issue 1
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