PMC RM5261-200-QI, RM5261-250-Q, RM5261-266-Q Datasheet

RM5261™ Microprocessor with 64-Bit System Bus Data Sheet

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RM5261

RM5261™ Microprocessor with 64-Bit

System Bus

Data Sheet

Proprietary and Confidential

Issue 1, March 2001

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002241, Issue 1

RM5261™ Microprocessor with 64-Bit System Bus Data Sheet

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any event, you cannot reproduce any part of this document, in any form, without the express written consent of PMC-Sierra, Inc.

PMC-2002241 (R1)

Disclaimer

None of the information contained in this document constitutes an express or implied warranty by PMCSierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of an y of t he pr oducts of PMC-Si erra , Inc., or an y port io n ther eof, r efer red to i n this document . PMC-Sierra, Inc. expressly disclaims all re presentations and war ra nties of any kind rega rdi ng the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement.

In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the infor ma tion, whether or not PMC-Sierra, Inc . has been a dvised of the possibility of such damage.

Trademarks

RM5261 is a trademark of PMC-Sierra, Inc.

Contacting PMC-Sierra

PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7

Tel: (604) 415-6000 Fax: (604) 415-6200

Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Web Site: http: //www.pmc-sierra.com

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Revision History

RM5261™ Microprocessor with 64-Bit System Bus Data Sheet

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Issue No. Issue Date

1 March 2001 3828 T. Chapman Applied PMC-Sierra template to exi sting

ECN Number Originator Details of Change

MPD (QED) FrameMaker document. Revised Features list, Sections 3.14, 3.19,

3.21, 3.22, 3.23, 3.26, 3.27, 3.30, 3.32, 5, 6, 7, 9.3, 9.4, and packaging diagram information.

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RM5261™ Microprocessor with 64-Bit System Bus Data Sheet

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Document Conventions

The following conventions are used in this datasheet:

•All signal, pin, and bus names described in the text, such as ExtRqst*, are in boldface typeface.

•All bit and field names described in the text, such as Interrupt Mask, are in an italic-bold

typeface.

•All instruction names, such as MFHI, are in san serif typeface.

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RM5261™ Microprocessor with 64-Bit System Bus Data Sheet

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Legal Information ...........................................................................................................................2

Revision History .............................................................................................................................3

Document Conventions .................................................................................................................4

Table of Contents ..........................................................................................................................5

List of Figures ................................. ...... ....... ...................................... ....... ...... ....... ...... ..................7

List of Tables . ....... ...... ....... ...... ....... ...... ....... ...... ....... ...................................... ....... ...... ..................8

1 Features ......................................... ....................................................................... ..................9

2 Block Diagram ...... ....... ...... ....... ...... ....................................... ...... ....... ...... ....... ...... ....... .........10

3 Hardware Overview ...............................................................................................................11

3.1 Superscalar Dispatch ...................................................................................................11

3.2 CPU Registers .............................................................................................................11

3.3 Integer Unit ..................................................................................................................11

3.4 Pipeline ........................................................................................................................12

3.5 Register File .................................................................................................................12

3.6 ALU ..............................................................................................................................12

3.7 Integer Multiply/Divide ..................................................................................................13

3.8 Floating-Point Co-Processor ........................................................................................13

3.9 Floating-Point Unit .......................................................................................................13

3.10 Floating-Point General Register File ............................................................................15

3.11 System Control Co-processor (CP0) ............................................................................15

3.12 System Control Co-Processor Registers .....................................................................15

3.13 Virtual to Physical Address Mapping ............................................................................16

3.14 Joint TLB ......................................................................................................................17

3.15 Instruction TLB .............................................................................................................18

3.16 Data TLB ......................................................................................................................18

3.17 Cache Memory .............................................................................................................18

3.18 Instruction Cache .........................................................................................................19

3.19 Data Cache ..................................................................................................................19

3.20 Write buffer ..................................................................................................................21

3.21 System Interface ............. ...................................... ....... ...... ....... ...... ....... ......................21

3.22 System Address/Data Bus .... ....................................... ...... ....... ...... ....... ......................21

3.23 System Command Bus ................................................ ...... ....... ...... .............................21

3.24 Handshake Signals ......................................................................................................22

3.25 Non-overlapping System Interface ...............................................................................22

3.26 Enhanced Write Modes ................................................................................................23

3.27 External Requests ........................................................................................................24

3.28 Interrupt Handling ........................................................................................................24

3.29 Standby Mode .... ...... ....... ...................................... ....... ...... ....... ...... .............................24

3.30 JTAG Interface .............................................................................................................24

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RM5261™ Microprocessor with 64-Bit System Bus Data Sheet

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3.31 Boot-Time Options .......................................................................................................24

3.32 Boot-Time Modes .........................................................................................................25

4 Pin Descriptions ....................................................................................................................26

5 Absolute Maximum Ratings ..................................................................................................29

6 Recommended Operating conditions ....................................................................................30

7 DC Electrical Characteristics .................................................................................................31

8 Power Consumption ..............................................................................................................32

9 AC Electrical Characteristics ................. ...... ....... ...... ....................................... ...... ....... ...... ...33

9.1 Capacitive Load Deration .............................................................................................33

9.2 Clock Parameters ........................................................................................................33

9.3 System Interface Parameters ............. ....... ...... ...... ....... ....................................... ...... ...34

9.4 Boot-Time Interface Parameters ..................................................................................34

10 Timing Diagrams ...................................................................................................................35

10.1 System Interface Timing ....................................... ....... ...... ....... ...... ....... ...... ....... ...... ...35

11 Packaging Information ..........................................................................................................36

12 RM5261 208-pin PQFP Package Pinou t ..... ....... ...... ...... ....... ...... ....... ...... .............................3 8

13 Ordering Information .............................................................................................................40

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RM5261™ Microprocessor with 64-Bit System Bus Data Sheet

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List of Figures

Figure 1 Block Diagram .............................................................................................................10

Figure 2 CPU Registers .............................................................................................................11

Figure 3 Pipeline ........................................................................................................................12

Figure 4 CP0 Registers .............................................................................................................16

Figure 5 Kernel Mode Virtual Addressing (32-bit) .....................................................................17

Figure 6 Typical Embedded System Block Diagram .................................................................21

Figure 7 Processor Block Read .................................................................................................23

Figure 8 Processor Block Write .................................................................................................23

Figure 9 Clock Timing ................................................................................................................35

Figure 10 Input Timing ...............................................................................................................35

Figure 11 Output Timing ............................................................................................................35

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RM5261™ Microprocessor with 64-Bit System Bus Data Sheet

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List of Tables

Table 1 Integer Multiply/Divide Operations ................................................................................13

Table 2 Floating-Point Instruction Cycles ..................................................................................14

Table 3 Cache Attributes ...........................................................................................................20

Table 4 Boot-Time Mode Bit Stream .........................................................................................25

Table 5 System Interface ...........................................................................................................26

Table 6 Clock/Control Interface .................................................................................................27

Table 7 Interrupt Interface .........................................................................................................27

Table 8 JTAG Interface .............................................................................................................27

Table 9 Initialization Interface ....................................................................................................28

Table 10 Power Supply .............................................................................................................28

Table 11 DC Electrical Characteristics ......................................................................................31

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1 Features

• Dual Issue superscalar microprocessor

• 200, 250, 266 MHz operating frequencies

• 320 Dhrystone 2.1 MIPS

• High-performance system interface

• 64-bit multiplexed system address/data bus for optimum price/performance

• High-performance write protocols maximize uncached write bandwidth

• Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9

• IEEE 1149.1 JTAG boundary scan

• Integrated on-chip caches

• 32KB instruction and 32KB data — 2 way set associative

• Virtually indexed, physically tagged

• Write-back and write-through on a per page basis

• Pipeline restart on first doubleword for data cache misses

• Integrated memory management unit

• Fully associative joint TLB (shared by I and D translations)

• 48 dual entries map 96 pages

• Variable page size (4 KB to 16 MB in 4x increments)

RM5261™ Microprocessor with 64-Bit System Bus Data Sheet

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• High-performance floating-point unit: up to 530 MFLOPS

• Single cycle repeat rate for common single -pr ecision ope ra tions and some double-p recision operations

• Two cycle repeat rate for double-precision multiply and double precision combined multiply-add operations

• Single cycle repeat rate for single-precision combined multiply-add operation

• MIPS IV instruction set

• Floating point multiply-add instruction increases performance in signal processing and graphics applications

• Conditional moves to reduce branch frequency

• Index addr ess modes (register + register)

• Embedded application enhancements

• Specialized DSP integer Multiply-Accumulate instructions and 3-operand multiply instruction

• I and D cache locking by set

• Optional dedicated exception vector for interrupts

• Fully static 0.25 micron CMOS design with power down logic

• Standby reduced power mode with WAIT instruction

• 2.5 V core with 3.3 V IOs

• 208-pin PQFP package

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2 Block Diagram

Figure 1 Block Diagram

Primary Data Cache

2-way Set Associative

RM5261™ Microprocessor with 64-Bit System Bus Data Sheet

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DTag DTLB

ITag ITLB

Primary Instruction Cache

2-way Set Associative

A/D Bus

Pad Bus

Store Buffer

Write Buffer

D Bus

Floating-Point

Load/Align

Floating-Point

Packer/Unpacker

Floating-Point

MultAdd, Add, Sub,

Cvt, Div, Sqrt

Read Buffer

Coprocessor 0

System/Memory

Control

PC Incrementer

Floating-Point Control

Branch PC Adder

ITLB Virtual

Program Counter Int Mult, Div, Madd

Pad Buffer

Joint TLB

Address Buffer

IVA

DVA

FP Bus

FA Bus

Instruction Dispatch Unit

Instruction

Load Aligner

Integer Register File

Integer Address/Adder

Shifter/Store Aligner

Logic Unit

DTLB Virtual

PLL/Clocks

Integer

Instruction

Integer Bus

Integer Control

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3 Hardware Overview

The RM5261 offers a high-level of integration targeted at high-performance embedded applications. The key elements of the RM5261 are briefly described below.

3.1 Superscalar Dispatch

The RM5261 has an asymmetric superscalar dispatch unit which allows it to issue an integer instruction and a floating-point computation instruction simultaneously. Integer instructions include alu, branch, load/store, and floating-point load/store, while floating-point computation instructions include floating-point add, subtract, combined multiply-add, converts, etc. In combination with its high- throug hput fully pipel ined fl oatin g-p oint exe cutio n unit, the supersc alar capability of the RM5261 provides unparalleled price/performance in computationally intensive embedded applications.

3.2 CPU Registers

The RM5261 CPU has a simple user-visible state consisting of 32 general purpose registers, two special purpose registers for integer multiplication and division, a program counter, and no condition code bits. Figure 2 shows the user visible state.

RM5261™ Microprocessor with 64-Bit System Bus Data Sheet

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Figure 2 CPU Registers

General Purpose Registers

63 0 0 63 0

r1 HI r2 63 0

• LO

•

• 63 0

r29 PC r30 r31

3.3 Integer Unit

Like the RM5260, the RM5261 implements the MIPS IV Instruction Set Architecture, and is therefore fully upward compatible with applications that run on processors implementing the earlier generation MIPS I-III instruction sets. Additionally, the RM5261 includes three implementation specific instructions not found in the baseline MIPS IV ISA but that are useful in the embedded market place. Described in detail in a later section, these instructions are integer multiply-accumulate and 3-operand integer multiply.

Multiply/Divide Registers

Program Counter

The RM5261 integer unit includes thirty-two general purpose 64-bit registers, a load/store architecture with single cycle ALU operations (add, sub, logical, shift) and an autonomous

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multiply/divide unit. Additional register resources include: the HI/LO resul t registers for the twooperand integer multiply/divide operations, and the program counter (PC).

3.4 Pipeline

For integer operations, loads, stores, and other non-floating-point operations, the RM5261 implements a 5-stage int eger pi peli ne. In addi tion to t he in teger pipeli ne, the RM5261 impl emen ts an extended 7-stage pipeline for floating-point operations.

The RM5261 multiplies the input SysClock by 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, or 9 to produce the pipeline clock.

Figure 3 shows the RM5261 integer pipeline. As illustrated in the figure, up to five integer instructions can be executing simultaneously.

Figure 3 Pipeline

RM5261™ Microprocessor with 64-Bit System Bus Data Sheet

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I0 I1 I2 I3 I4

1I-1R:

2I: 2R: 1A: 1A:

1A-2A:

2A:

2A-2D:

1D:

2W:

2I1I 1R 2R 1A 2A 1D 2D 1W 2W

Instruction cache access Instruction virtual to physical address translation Register file read, Bypass calculation, Instruction decode, Branch address calculation Issue or slip decision, Branch decision Data virtual address calculation Integer add, logical, shift Store Align Data cache access and load align Data virtual to physical address translation Register file write

3.5 Register File

The RM5261 has thirty-two general purpose registers with register location 0 (r0) hard-wired to a zero value. These registers are used for scalar integer operations and address calculation. The register file has two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline.

2I1I 1R 2R 1A 2A 1D 2D 1W 2W

one cycle

3.6 ALU

The RM5261 ALU consists of an integer adder/subtractor, a logic unit, and a shifter. The adder performs address calculations in addition to arithmetic operations. The logic unit performs all logical and zero s hift d ata moves . The shift er per forms s hifts and store align ment o perat ions. Eac h of these units is optimized to perfor m all operations in a sing l e processor cycle.

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