RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
RM5231A
RM5231A™ Microprocessor with 32-Bit
System Bus
Data Sheet
Proprietary and Confidential
Preliminary
Issue 2, September 2001
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
Legal Information
Copyright
© 2001 PMC-Sierra, Inc.
The information is proprietary and confidential to PMC-Sierra, Inc., and for its customers’ internal use. In
any event, you cannot reproduce any part of this document, in any form, without the express written
consent of PMC-Sierra, Inc.
PMC-2002174 (P2)
Disclaimer
None of the information contained in this document constitutes an express or implied warranty by PMCSierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the
fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts
or systems, of an y of t he pr oducts of PMC-Si erra , Inc., or an y port io n ther eof, r efer red to i n this document .
PMC-Sierra, Inc. expressly disclaims all representations and warranties of any ki nd regarding the contents
or use of the information, including, but not limited to, express and implied warranties of accuracy,
completeness, merchantability, fitness for a particular use, or non-infringement.
In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential
damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or
reliance upon the infor ma tion, whether or not PMC-Sierra, Inc . has been advised of the possib il it y of s uch
damage.
Trademarks
RM5231A is a trademark of PMC-Sierra, Inc.
Contacting PMC-Sierra
PMC-Sierra, Inc.
105-8555 Baxter Place Burnaby, BC
Canada V5A 4V7
Tel: (604) 415-6000
Fax: (604) 415-6200
Document Information: document@pmc-sierra.com
Corporate Information: info@pmc-sierra.com
Technical Support: apps@pmc-sierra.com
Web Site: http://www.pmc-sierra.com
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 2
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Revision History
Issue
No. Issue Date Details of Change
Preliminary
2 September 2001
1 March 2001 Applied PMC-Sierra template to existing MPD (QED) FrameMaker document.
Added 1.8 V to the feature: 1.65 V or 1.8 V core with 3.3 V or 2.5 V I/O (p9).
Changed recommended operating conditions VccInt to 1.57 V to 1.85 V and
VccP to 1.57 V to 1.85 V. Added VssP commercial and industrial values.
Modified Note 4.
Added reference to VccInt to Power Consumption table. Changed standby
modes to 350. Modified Note 1.
Modified SysClock Frequency and SysClock Period values in the Clock
Parameters table.
Revised the Absolute Maximum Ratings table to include industrial operating
temperatures. Revised the Recommended Operating conditions table (VccIO).
Revised the DC Electrical Characteristics section. Included 350 MHz Power
CPU Speed Power Consumption and Clock Parameter values. Revised the
System Interface Parameters table.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 3
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
Document Conventions
The following conventions are used in this datasheet:
• All signal, pin, and bus names described in the text, such as ExtRqst*, are in boldface
typeface.
• All bit and field names describe d in the text , such as Interrupt Mask, are in an italic -bold
typeface.
• All instruction names, such as MFHI, are in san serif typeface.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 4
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
Table of Contents
Legal Information ...........................................................................................................................2
Revision History .............................................................................................................................3
Document Conventions .................................................................................................................4
Table of Contents ..........................................................................................................................5
List of Figures ................................. ...... ....... ...................................... ....... ...... ....... ...... ..................7
List of Tables . ....... ...... ....... ...... ....... ...... ....... ...... ....... ...................................... ....... ...... ..................8
1 Features ............................ ....................................................................... ...............................9
2 Block Diagram .......................... ...... ....... ...... ....... ...... ....................................... ...... ....... .........10
3 Hardware Overview ...............................................................................................................11
3.1 Superscalar Dispatch ...................................................................................................11
3.2 CPU Registers .............................................................................................................11
3.3 Pipeline ........................................................................................................................11
3.4 Integer Unit ..................................................................................................................12
3.5 Register File .................................................................................................................12
3.6 ALU ..............................................................................................................................12
3.7 Integer Multiply/Divide ..................................................................................................12
3.8 Floating-Point Co-Processor ........................................................................................13
3.9 Floating-Point Unit .......................................................................................................13
3.10 Floating-Point General Register File ............................................................................15
3.11 System Control Coprocessor (CP0) .............................................................................16
3.12 System Control Co-Processor Registers .....................................................................16
3.13 Virtual to Physical Address Mapping ............................................................................17
3.14 Joint TLB ......................................................................................................................18
3.15 Instruction TLB .............................................................................................................19
3.16 Data TLB ......................................................................................................................19
3.17 Cache Memory .............................................................................................................19
3.18 Instruction Cache .........................................................................................................19
3.19 Data Cache ..................................................................................................................20
3.20 Write Buffer ..................................................................................................................21
3.21 System Interface ............. ...................................... ....... ...... ....... ...... ....... ......................22
3.22 System Address/Data Bus .... ....................................... ...... ....... ...... ....... ......................22
3.23 System Command Bus ................................................ ...... ....... ...... .............................22
3.24 Handshake Signals ......................................................................................................23
3.25 Non-overlapping System Interface ...............................................................................23
3.26 Enhanced Write Modes ................................................................................................24
3.27 External Requests ........................................................................................................25
3.28 Interrupt Handling ........................................................................................................25
3.29 Standby Mode .... ...... ....... ...................................... ....... ...... ....... ...... .............................25
3.30 JTAG Interface .............................................................................................................25
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 5
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
3.31 Boot-Time Options .......................................................................................................25
3.32 Boot-Time Modes .........................................................................................................26
4 Pin Descriptions ....................................................................................................................27
5 Absolute Maximum Ratings ..................................................................................................30
6 Recommended Operating Conditions ...................................................................................31
7 DC Electrical Characteristics .................................................................................................32
8 Power Consumption ..............................................................................................................33
9 AC Electrical Characteristics .................................... ...... ....... ...... ....................................... .. .34
9.1 Capacitive Load Deration .............................................................................................34
9.2 Clock Parameters ........................................................................................................34
9.3 System Interface Parameters ............. ....... ...... ...... ....... ....................................... ...... ...35
9.4 Boot-Time Interface Parameters ..................................................................................35
10 Timing Diagrams ...................................................................................................................36
10.1 System Interface Timing ....................................... ....... ...... ....... ...... ....... ...... ....... ...... ...36
11 Packaging Information ..........................................................................................................37
12 RM5231A 128 QFP Package Numerical Pinout ...................................................................38
13 RM5231A 128 QFP Package Alphabetical Pinout ................................................................39
14 Ordering Information .............................................................................................................40
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 6
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
List of Figures
Figure 1 Block Diagram .............................................................................................................10
Figure 2 CPU Registers .............................................................................................................11
Figure 3 Pipeline ........................................................................................................................12
Figure 4 CP0 Registers .............................................................................................................17
Figure 5 Kernel Mode Virtual Addressing (32-bit) .....................................................................18
Figure 6 Typical Embedded System Block Diagram ................................................................22
Figure 7 Processor Block Read .................................................................................................24
Figure 8 Processor Block Write .................................................................................................24
Figure 9 Clock Timing ................................................................................................................36
Figure 10 Input Timing ...............................................................................................................36
Figure 11 Output Timing ............................................................................................................36
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 7
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
List of Tables
Table 1 Integer Multiply/Divide Operations ................................................................................13
Table 2 Floating-Point Instruction Cycles ..................................................................................15
Table 3 Cache Attributes ...........................................................................................................21
Table 4 Boot Time Mode Bit Stream .........................................................................................26
Table 5 System Interface ...........................................................................................................27
Table 6 Clock/Control Interface .................................................................................................28
Table 7 Interrupt Interface .........................................................................................................28
Table 8 JTAG Interface .............................................................................................................28
Table 9 Initialization Interface ....................................................................................................29
Table 10 Power Supply .............................................................................................................29
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 8
Document ID: PMC-2002174, Issue 2
1 Features
• Dual Issue superscalar microprocessor
• 250, 300, and 350 MHz operating frequencies
• Up to 420 Dhrystone 2.1 MIPS
• System interface optimized for embedded applications
• 32-bit system interfa ce lowers total system cost
• High-performance write protocols maximize uncached write bandwidth
• Processor clock multipliers: 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9
• IEEE 1149.1 JTAG boundary scan
• Integrated on-chip caches
• 32 KB instruction and 32 KB data — 2 way set associative
• Per set locking
• Virtually indexed, physically tagged
• Write-back and write-through on a per page basis
• Pipeline restart on first doubleword for data cache misses
• Integrated memory management unit
• Fully associative joint TLB (shared by I and D translations)
• 48 dual entries map 96 pages
• Variable page size (4 KB to 16 MB in 4x increments)
• High-performance floating-point unit — up to 700 MFLOPS
• Single cycle repeat rate for common single-precision operations and some double precision operations
• Two cycle repeat rate for double-precision multiply and double precision combined
multiply-add operations
• Single cycle repeat rate for single-precision combined multiply-add operation
• MIPS IV instruction set
• Floating point multiply-add instruction increases performance in signal processing
and graphics applications
• Conditional moves to reduce branch frequency
• Index address modes (register + register)
• Embedded application enhancements
• Specialized DSP integer Multiply-Accumulate instructions and 3-operand multiply
instruction
• I and D cache locking by set
• Optional dedicated exception vector for interrupts
• Fully static 0.18 micron CMOS design with power down logic
• Standby reduced power mode with
• 1.65 V or 1.8 V core with 3.3 V or 2.5 V I/O
• 128-pin QFP package
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
WAIT instruction
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 9
Document ID: PMC-2002174, Issue 2
2 Block Diagram
Figure 1 Block Diagram
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
Primary Data Cache
2-way Set Associative
Store Buffer
Write Buffer
D Bus
Floating-Point
Load/Align
Floating-Point
Register File
Packer/Unpacker
Floating-Point
MultAdd, Add, Sub,
Cvt, Div, Sqrt
Read Buffer
DTag
DTLB
Coprocessor 0
System/Memory
Control
PC Incrementer
Floating-Point Control
Branch PC Adder
ITLB Virtual
Program Counter Int Mult, Div, Madd
Pad Buffer
Joint TLB
Address Buffer
IVA
ITag
ITLB
DVA
FP Bus
FA Bus
Primary Instruction Cache
2-way Set Associative
A/D Bus
Instruction Dispatch Unit
FP
Instruction
Register
Load Aligner
Integer Register File
Integer Address/Adder
Shifter/Store Aligner
Logic Unit
DTLB Virtual
PLL/Clocks
Pad Bus
Integer
Instruction
Register
Integer Bus
Integer Control
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 10
Document ID: PMC-2002174, Issue 2
3 Hardware Overview
The RM5231A offers a high-level of integration targeted at high-performance embedded
applications. The key elements of the RM5231A are briefly described below.
3.1 Superscalar Dispatch
The RM5231A has an asymmetric superscalar dispatch unit which allows it to issue an integer
instruction and a floating-point computation instruction simultaneously. Integer instructions
include alu, branch, load/store, and floating-point load/store, while floating-point computation
instructions include fl oat ing-point add, subtract, combined multiply-add, and converts. In
combination with its high- throug hput fully pipel ined fl oatin g-p oint exe cutio n unit, the supersc alar
capability of the RM5231A provides unparalleled price/perf ormance in computationally intensive
embedded applications.
3.2 CPU Registers
The RM5231A contains 32 general purpose registers, two special purpose registers for integer
multiplication and division , a progra m counte r , a nd no condi tion code bits. Fig ure 2 shows the u ser
visible state.
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
Figure 2 CPU Registers
General Purpose Registers
63 0
0 63 0
r1 HI
r2 63 0
•LO
•
•
• 63 0
r29 PC
r30
r31
3.3 Pipeline
For integer operations, loads, stores, and other non-floating-point operations, the RM5231A uses
the 5-stage pipeline. In addition to the integer pipeline, the RM5231A uses an extended 7-stage
pipeline for floating-point operations.
Figure 3 shows the RM5231A integer pipeline. As illustrated in the figure, up to five integer
instructions can be executing simultaneously.
Multiply/Divide Registers
Program Counter
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 11
Document ID: PMC-2002174, Issue 2
Figure 3 Pipeline
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
I0
I1
I2
I3
I4
1I-1R:
2I:
2R:
1A:
1A:
1A-2A:
2A:
2A-2D:
1D:
2W:
2I1I 1R 2R 1A 2A 1D 2D 1W 2W
Instruction cache ac ces s
Instruction virtual to physical address translation
Register file read, Bypass calculation, Instruction decode, Branch address calculation
Issue or slip decision, Branch decision
Data virtual address calculation
Integer add, logical, shift
Store Align
Data cache access and load align
Data virtual to physical address translation
Register file write
3.4 Integer Unit
The RM5231A integer unit includes thirty-two general purpose 64-bit registers, a load/store
architecture with single cycle ALU operations (add, sub, logical, shift) and an autonomous
multiply/divide unit. Additional register resources include: the HI/LO resul t registers for the twooperand integer multiply/divide operations, and the program counter (PC).
2I1I 1R 2R 1A 2A 1D 2D 1W 2W
2I1I 1R 2R 1A 2A 1D 2D 1W 2W
2I1I 1R 2R 1A 2A 1D 2D 1W 2W
2I1I 1R 2R 1A 2A 1D 2D 1W 2W
one cycle
The RM5231A implements the MIPS IV Instruction Set Architecture, and is therefore fully
upward compatible with applications that run on processors implementing the earlier generation
MIPS I-III instruction sets.
3.5 Register File
The RM5231A has thirty-two general purpose registers with register location 0 (r0) hard wired to
a zero value. These registers are used for scalar integer operations and address calculation. The
register file has two read ports and one write port and is fully bypassed to minimize operation
latency in the pipeline.
3.6 ALU
The RM5231A ALU consists of an integer adder/subtractor, a logic unit, and a shifter. The adder
performs address calculations in addition to arithmetic operations. The logic unit performs all
logical and zero s hift d ata moves . The shift er per forms s hifts and store align ment o perat ions. Eac h
of these units is optimized to perfor m all operations in a sing l e processor cycle.
3.7 Integer Multiply/Divide
The RM5231A has a dedicated i ntege r multi ply/di vide un it opt imized f or hig h-spee d multip ly a nd
multiply-accumulate operations. Table 1 shows the performance of the multiply/divide unit on
each operation
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 12
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
Table 1 Integer Multiply/Divide Operations
Operand
Opcode
MULT/U, MAD/U
MUL 16 bit 3 2 1
DMULT, DMUL TU
DIV, DIVD any 36 36 0 DDIV,
DDIVU
Size Latency
16 bit 3 2 0 32 bit 4 3 0
32 bit 4 3 2 any 7 6 0
any 68 68 0
Repeat
Rate
Stall
Cycles
The baseline MIPS IV ISA specifies that the results of a multiply or divide operation be placed in
the Hi and Lo registers. These values can then be transferred to the general pur pose regist er file
using the Move-from-Hi and Move-from-Lo (
MFHI/MFLO) instructi ons.
In addition to the baseline MIPS IV integer multiply instructions, the RM5231A also implements
the 3 opera nd multiply instruction,
MUL. This instruction specifies that the multiply result go
directly to the integer register file rather than the Lo register. The portion of the multiply that
would have normally gone i nto the Hi re gister i s discard ed. For applicat ions where i t is known tha t
the upper half of the multiply result is not required, using the
necessity of executing an explicit
MFLO instruction.
Also included in the RM5231A are the multiply-add instructions,
multiplies two operands and adds the resulting product to the current contents of the Hi and Lo
registers. The multiply-accumulate operation is the core primitive of almost all signal processing
algorithms allowing the RM5231A to eliminate the need for a separate DSP engine in many
embedded applications.
3.8 Floating-Point Co-Processor
The RM5231A incorporate s a hig h-p erfor mance fu lly pi pe lined float ing-p oint c o-proc ess or whic h
includes a floating-po int register file and autonomous execution units for multiply/a dd/convert and
divide/square root. The floating-point coprocessor is a tightly coupled execution unit, decoding
and executing instructions in parallel with, and in the case of floating-point loads and stores, in
cooperation with the integer unit. The superscalar capabilities of the RM5231A allow floatingpoint computation instructions to issue concurrently with integer instructions.
3.9 Floating-Point Unit
The RM5231A floating-point execution unit supports single and double precision arithmetic, as
specified in the IEEE S tanda rd 754. The ex ecution uni t is broken i nto a separa te divide /square ro ot
unit and a pipelined multiply/add unit. Overlap of the divide/square root and multiply/add
operations is supported.
MUL instruction eliminates the
MADU/MAD. This ins truction
The RM5231A maintains fully precise floating-point exceptions while allowing both overlapped
and pipelined operations. Precise exceptions are extremely important in object-oriented
programming environments and highly desirable for debugging in any environment.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 13
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Floating-point operations includes:
•add
• subtract
• multiply
• divide
• square root
• reciprocal
• reciprocal square root
• conditional moves
• conversion between fixed-point and floating-point format
• conversion between floating-point formats, and floating-point compare.
Table 2 gives the latencies of the floating-point instructions in internal processor cycles.
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 14
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Table 2 Floating-Point Instruction Cycles
Operation Latency Repeat Rate
fadd 4 1 fsub 4 1 fmult 4/5 1/2 fmadd 4/5 1/2 fmsub 4/5 1/2 fdiv 21/36 19/34 fsqrt 21/36 19/34 frecip 21/36 19/34 frsqrt 38/68 36/66 fcvt.s.d 4 1 fcvt.s.w 6 3 fcvt.s.l 6 3 fcvt.d.s 4 1 fcvt.d.w 4 1 fcvt.d.l 4 1 fcvt.w.s 4 1 fcvt.w.d 4 1 fcvt.l.s 4 1 fcvt.l.d 4 1 fcmp 1 1 fmov 1 1 fmovc 1 1 fabs 1 1 fneg 1 1
Note
1. Numbers are represented as single/double precision format.
Preliminary
3.10 Floating-Point General Register File
The floating-point general register file (FGR) is made up of thirty-two 64-bit registers. Wi th the
floating-point load and store double instructions (
take advantage of the 64-bit wide data cache and issue a floating-point co-processor load or store
doubleword instruction in every cycle.
The floating-point c ont rol register space contains two register s; one for determining conf iguration
and revision informat i on f o r the coprocessor and one for control and status i nformation. These are
primarily used for diagnos ti c sof twa re, exception handling, st at e sav ing and res tor ing, and control
of rounding modes. To support superscalar operation, the FGR has four read ports and two write
ports, and is fully bypassed to minimize operation latency in the pipeline. Three of the read ports
and one write port are used t o support the combi ned multi ply -add ins truct ion whil e the fo urth re ad
and second write port allows a concurrent floating-point load or store.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 15
Document ID: PMC-2002174, Issue 2
LDC1 and SDC1), the floating-point unit can
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
3.11 System Control Coprocessor (CP0)
The system control coprocessor, also called coprocessor 0 or CP0 in the MIPS architecture, is
responsible for the virtual memory sub-system, the exception control system, and the diagnostics
capability of the processor.
The memory management unit co ntrol s the virtu al memory syste m page mapping . It co nsist s of a n
instruction address translation buffer, ITLB, a data address translation buffer, DTLB, a Joint
instruction and data ad dress transl ation buf fer , JTLB, and co-pr ocessor re gisters used by the virtual
memory mapping sub-system.
3.12 System Control Co-Processor Registers
The RM5231A incorporates all system control coprocessor (CP0) registers on-chip. These
registers provide the path through which the virtual memory system’s page mapping is examined
and modified, exceptions are handled, and operating modes are controlled (kernel vs. user mode,
interrupts enabled or disabled, cache features). In addition, the RM5231A includes registers to
implement a real-t ime cyc le coun ti ng faci lity to ai d in ca che dia gnosti c tes ting a nd to assi st in data
error detection.
Preliminary
Figure 4 shows the CP0 registers.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 16
Document ID: PMC-2002174, Issue 2
Figure 4 CP0 Registers
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
LLAddr
17*
47
0
PageMask
5*
EntryHi
10*
TLB
(entries protected
from TLBWR)
TagL o
28*
EntryLo0
2*
EntryLo1
3*
TagHi
29*
Used for memory
management
Index
0*
Random
1*
Wired
6*
PRId
15*
Config
16*
Context
4*
Count
9*
Status
12*
EPC
14*
ECC
26*
BadVAddr
8*
Compare
11*
Cause
13*
XContext
20*
CacheErr
27*
ErrorEPC
30*
Used for exception
processing
* Register number
3.13 Virtual to Physical Address Mappin g
The RM5231A provides three modes of virtual addressing:
• user mode
•kernel mode
• supervisor mode
This mechanism is available to system softw are to provide a secure environme nt for user
processes . Bits in the C P0 Status register determine which virtual addressing mode is used. In the
user mode, the RM5231A provides a single, uniform virtual address space of 1TB (2 GB in 32-bit
mode).
When operating in the kernel mode, four distinct virtual address spaces, totalling over 2.5 TB (4
GB in 32-bit mode), are simultaneously available and are differentiated by the high-order bits of
the virtual address.
The RM5231A processor also supports a supervisor mode in which the virtual address space over
2 TB (2.5 GB in 32-bi t mode), div ided i nto t hree regio ns based o n the high- order bits of t he vir tual
address.
When the RM5231A is configured as a 64-bit microprocessor, the virtual address space layout is
an upward compatible extension of the 32-bit virtual address space layout.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 17
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Figure 5 shows the address space layout for 32-bit operation.
Figure 5 Kernel Mode Virtual Addressing (32-bit)
0xFFFFFFFF Kernel virtual address space
(kseg3)
0xE0000000 0xDFFFFFFF Supervisor virtual address space
0xC0000000 0xBFFFFFFF Uncached kernel physical addr ess space
0xA0000000 0x9FFFFFFF Cached kernel physical address space
0x80000000 0x7FFFFFFF User virtual address space
Mapped, 0.5GB
(ksseg)
Mapped, 0.5GB
(kseg1)
Unmapped, 0.5GB
(kseg0)
Unmapped, 0.5GB
(kuseg)
Mapped, 2.0GB
Preliminary
0x00000000
3.14 Joint TLB
For fast virtual-to-physical address translation, the RM5231A uses a large, fully associative TLB
that maps 96 virtual pages t o their corre spondin g physic al a ddress es. As indi cated by its name, the
joint TLB (JTLB) is used for both instruction and data translations. The JTLB is organized as 48
pairs of even-odd entrie s, an d maps a virt ual addr ess and ad dress space ide nti fier int o th e lar ge, 64
GB physical address space.
Two mechanisms are provided to assist in controlling the amount of mapped space and the
replacement characte ristic s of various memory regi ons. First, the page si ze can be conf igured, on a
per-entry bas is , to use page sizes in the range of 4 KB to 16 MB (i n mul ti pl es of 4). The CP0 Page
Mask register is loaded with the desired page size of a mapping, and that size is stored into the
TLB along with the virtual address when a new entry is written. Thus, operating systems can
create spec ial purpose maps; for example, an entire frame buffer can be m emory mapped using
only one TLB entry.
The second mechanism controls the replacement algorithm when a TLB miss occurs. The
RM5231A provides a random replacement algorithm to select a TLB entry to be written with a
new mapping. However, the processor also provides a mechanism whereby a system specific
number of mappings can be locked into the TLB, thereby avoiding random replacement. This
mechanism uses the Wired register to ‘lock’ certain TLB entries and allows the operating system
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 18
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
to guarantee that certain pages are always mapped for performance reasons and for deadlock
avoidance. This mechanism also facilitates the design of real-time systems by allowing
deterministic access to critical software.
The JTLB also contains information that controls the cache coherency protocol for each page.
Specifically, each page has attribute bits to determine the following coherency algorithms:
• uncached
• non-coherent write-back
• non-coherent write-through with write-allocate
• non-coherent write-through without write-allocate
• sharable
• exclusive
•update
The non-coherent protocols are used for both code and data on the RM5231A, with data using
write-back or write-through depending on the application. The coherency attributes generate
coherent transactio n type s on the system interface. However, in the RM5231A cache coherency is
not supported, hence the coherency attributes should never be used.
3.15 Instruction TLB
The RM5231A implements a 2-entry instruction TLB (ITLB) to minimize contention for the
JTLB, eliminate the timing critical path of translating through a large associative array, and save
power. Each ITLB entry maps a 4 KB page. The ITLB improves performance by allowing
instruction address translation to occur in parallel with data address translation. When a miss
occurs on an instruction address translation by the ITLB, the least-recently used ITLB entry is
filled from the JTLB. Th e operation of the ITLB is completely transparent to the user.
3.16 Data TLB
The RM5231A implements a 4-entry data TLB (DTLB) for the same reasons cited above for the
ITLB. Each DTLB entry maps a 4 KB page. The DTLB improves performance by allowing data
address translation to occur in par allel with instr uct ion address tran sl at ion . Wh en a miss occurs on
a data address translation by the DTLB, the DTLB is fil led from th e JTLB. The DTLB refill is
pseudo-LRU: the least recently used entry of the least recently used pair of entries is filled. The
operation of the DTLB is completely transparent to the user.
3.17 Cache Memory
The RM5231A incorporates on-chip instruction and data caches that can be accessed in a single
processor cycle. Each cache has its own 64-bit data path and both caches can be accessed
simultaneously. The cache subsystem provides the integer and floating-point units with an
aggregate bandwidth of over 3 GB per second at an internal clock frequency of 200 MHz.
3.18 Instruction Cache
The RM5231A incorporates a two-way set associative on-chip instruction cache. This virtually
indexed, physically tagged cache is 32 KB in size and is protected with word parity.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 19
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
Since the cache is virtually indexed, the virtual-to-physical address translation occurs in parallel
with the cache access, further increasing performance by allowing these two operations to occur
simultaneously. The cache tag contains a 24-bit physical address, a valid bit, and has a single
parity bit.
The instruction cache is 64-bits wide and can be accessed each processor cycle. Accessing 64 bits
per cycle allows the instruction cache to supply two instructions per cycle to the superscalar
dispatch unit. For typical code sequences where a floating-point load or store and a floating-point
computation instruction are being issued together in a loop, the entire bandwidth available from
the instruction cache is consumed.
Cache miss refill writes 64 bits per cycle to minimize the cache miss penalty. The line size is eight
instructions (3 2 bytes) to maximi ze the p erfor mance of c ommunic ation betwe en the p rocess or and
the memory system.
The RM5231A supports instructi on cache l ocking. The content s of one set of the cac he, set A, can
be locked by set ti ng a bit in the coprocessor 0 Status register. Locking the set prevents its c ontents
from being overwritten by a subsequent cache miss. A refill occurs only into set B. This
mechanism allows the programme r to lock critical code in to the cache thereby guaranteeing
deterministic behavior for the locked code sequence.
3.19 Data Cache
For fast, single cycle data access, the RM5231A includes a 32KB on-chip data cache that is twoway set ass ociative w ith a fixed 32 -byte (eight words) line size.
The data cache is protected with byte parity and its tag is protected with a single parity bit. It is
virtually indexed and physically tagged to allow simultaneous address translation and data cache
access.
Cache protocols supported for the data cache are:
1. Uncached Data loads and instruction fetches from uncached memory space are brought in from main
memory to the register file and the execution unit, respectfully. The caches are not accessed.
Data store s to uncached memory space go directly to the main memory without updating the
data cache.
2. Write-back Loads and instruction fetches first search the cache, reading main memory only if the desired
data is not cache resident. On data store operations, the cache is first searched to determine if
the target address is cache resident. If it is resident, the cache contents are updated, and the
cache line is marked for later write-back. If the cache lookup misses, the target cache line is
first brought into the cache and then the write is performed as above.
3. Write-through with write allocate Loads and instruction fetches first search the cache, reading main memory only if the desired
data is not cache resident. On data store operations, the cache is first searched to determine if
the target address is cache resident. If it is resident, the cache contents are updated and main
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 20
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
memory is written, leaving the write-back bit of the cache line unchang ed. If the ca che lookup
misses, the target line is first brought into the cache and then the write is performed as above.
4. Write-through without write allocate Loads and instruction fetches first search the cache, reading main memory only if the desired
data is not cache resident. On data store operations, the cache is first searched to determine if
the target address is cache resident. If it is resident, the cache contents are updated and main
memory is written, leaving the write-back bit of the cache line unchang ed. If the ca che lookup
misses, then only main memory is writt en.
The most commonly used write policy is write-back, where a store to a cache line does not
immediately cause main memory to be updated. This increases system performance by reducing
bus traffic and eliminating the bottleneck of waiting for each store operation to finish before
issuing a subsequent memory operation. Software can, however, select write-through on a perpage basis when appropriate, such as for frame buffers.
Associated with the data cache is the store buffer. When the RM5231A executes a store
instruction, this single-entry buffer gets wr itten with the store data while the t ag comparison is
performed. If the tag matches, then the data is written into the data cache in the next cycle that the
data cache is not accessed (the next non-load cycle). The store buffer allows the RM5231A to
execute a store every processor cycle and to perform back-to-back stores without penalty. In the
event of a store immediately followed by a load to the same address, a combined merge and cache
write occurs such that no penalty is incurred.
The RM5231A cache attri butes f or bot h the i nstru ction and d ata ca ches ar e summari zed in Table 3.
T a ble 3 Cache Attributes
Characteristics Instruction Data
Size 32KB 32KB Organization 2-way set asso ciative 2-way set associativ e Line size 32B 32B Index vAddr
Tag pAddr Write policy n.a. write-back/write-through
Read order sub-block sub-block write order sequential sequential miss restart after transfer of entire line first double Parity per-word per-byte Cache locking set A set A
3.20 Write Buffer
Writes to external memory, whether cache miss write-backs or st ores to uncach ed or write-t hrough
addresses, use the on-chip write buffer. The write buffer holds up to four 64-bit address and data
pairs. The entire buffer is used for a data cache write-back and allows the processor to proceed in
parallel with the memory update. For uncached and write-through stores, the write buffer
11..0
31..12
vAddr
pAddr
11..0
31..12
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 21
Document ID: PMC-2002174, Issue 2
significantly increases performance by decoupling the SysAD bus transfers from the instruction
execution stream.
3.21 System Interface
The system interface consists of a 32-bit Address/Data bus with 4 parity check bits and a 9-bit
command bus. In addition, there are 6 handshake signals and 6 interrupt inputs. The interface is
capable of transferring dat a be twee n the processor and memory at a peak rate of 400 MB/sec with
a 100 MHz SysClock.
Figure 6 shows a typical embedded system using the RM5231A. In this example, a bank of
DRAMs and a memory controller ASIC share the processor’s SysAD bus while the memory
controller provides separate ports to a boot ROM and an I/O system.
Figure 6 Typical Embedded System Block Diagram
DRAM
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
Control
Flash/
Address
Boot
Rom
36
Latch
RM5231A
36
23
3.22 System Address/Data Bus
The 32-bit System Address Data (SysAD) bus is used to transfer addresses and data between the
RM5231A and the rest of the system. It is protected with a 4-bit parity check bus (SysADC).
The system interface is configurable to allow easy interfacing to me mory and I/O systems of
varying frequencies. The Block Write data rate, Non-blocking Wr ite protocol, and the Output
Drive strength are programmable at Boot time via the Mode Control bits. The rate at which the
processor receives data is also ful ly controlled by the external device.
3.23 System Command Bus
The RM5231A interface has a 9-bit System Command (SysCmd) bus. The command bus
indicates whether the SysAD bus carries address or data information on a per- clock basis. If the
SysAD carries address, then the SysCmd bus also indicates what type of transaction is to take
place (for example, a read or write). If the SysAD carries data, then the SysCmd bus also give s
information abou t t he da ta (for example, this is the last data word tra nsm i tt ed, o r t he data contains
an error). The SysCmd bus is bidirectional to support both processor requests and external
requests to the RM5231A. Processor requests are initiated by the RM5231A and responded to by
an external device. Externa l requests are issued by an ext ernal devi ce and require the RM5231A to
respond.
Memory I/O
Controller
8
x x
PCI Bus
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 22
Document ID: PMC-2002174, Issue 2
The RM5231A supports one- to fou r-b yte transf ers as well as block transf ers on the SysAD bus. In
the case of a sub-word tra nsfer , t he two low-ord er address bits give t he byte addr ess of the t ransfer,
and the SysCmd bus indicates the number of bytes being transferred.
3.24 Handshake Signals
There are six handshake signals on t he system interface. Two of these, RdRdy* and WrRdy*, are
used by an external device to indicate to the RM5231A whether it can accept a new read or write
transaction. The RM5231A sampl es t hese signals before deasserting the ad dress on read and wri te
requests.
ExtRqst* and Release* are used to transfer control of the SysAD and SysCmd buses from the
processor to an external device. When an external device needs to control the interface, it asserts
ExtRqst*. The RM5231A responds by asserting Release* to release the system interfa ce to slave
state.
ValidOut* and ValidIn* are used by the RM5231A and the external device respectively to
indicate that there is a valid address, a command, or data on the SysAD and SysCmd buses. The
RM5231A asserts ValidOut* when it is driving these buses with a valid address, a command or
data, and the externa l age nt dri ves ValidIn* when it has control of the b use s and is dr iving a valid
address, a command, or data.
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
3.25 Non-overlapping System Interface
The RM5231A requires a non-overlapping system interface. This means that only one processor
request may be outstanding at a time and that the request must be serviced by an external device
before the RM5231A issues another request. The RM5231A can issue read and write requests to
an external device, whereas an external device can issue null and write requests to the RM5231A.
For processor reads the RM5231A asserts ValidOut* and simultaneously drives the address and
read command on the SysAD a nd SysCmd buses respectively. If the system interface has RdRdy*
asserted, then the processor tristates its driv ers and releases the system interface to the slave state
by asserting Release*. The external device can then begin sending data to the RM5231A.
Figure 7 shows a processor block read request and the external agent read response. The read
latency is four cycles (ValidOut* to ValidIn*), and the response data pattern is
“WWWWWWWW”, indicating that data can be transferred on every clock with no wait states inbetween. Figure 8 shows a processor block write using write response pattern
“WWWWWWWW”, or code 0, of the boot time mode select options.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 23
Document ID: PMC-2002174, Issue 2
Figure 7 Processor Block Read
SysClock
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
SysAD
SysCmd
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
Addr
Read NData NData NData NData NData NData NData NEOD
Figure 8 Processor Block Write
SysClock
SysAD
SysCmd
ValidOut*
ValidIn*
RdRdy*
Addr Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7
Write NData NData NData NData NData NData NData NEOD
Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7
WrRdy*
Release*
3.26 Enhanced Write Modes
The RM5231A implements two enhancements to the original R4000 write mechanism: Write
Reissue and Pipeline Writes. The original R4000 allowed a write address cycle on the SysAD bus
only once every four SysClock cycles. Hence for a non-block write, this meant that two out of
every four cycles were wait states.
Pipelined write mode eliminates these two wait states by allowing the processor to drive a new
write address onto the bus immediately after the previous write data cycle. This allows for higher
SysAD bus utilization. However, at high bus frequencies the processor may drive a subsequent
write onto the bus prior to the time the external agent deasserts WrRdy*, indicating that it can not
accept another write cycle. This can cause the write cycle to be missed.
Write re issue mode is an enhance ment to pipeli ned writ e mode and allo ws the proce ssor to re is sue
missed write cycles. If WrRdy* is deasserted during the issue phase of a write operation, the cycle
is aborted b y the processor and reissued at a later time.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 24
Document ID: PMC-2002174, Issue 2
In write reissue mode, a write rate of one write every two bus cycles can be achieved. Pipelined
writes have the same two bus cycle write repeat rate, but can issue one additional write following
the deasse rtion of
WrRdy*.
3.27 External Requests
The External Request pin , ExtRqst*, is asserted by the e xternal agent when it requires mastershi p
of the system interface, either to perform an independent transfer or to write to the interrupt
register within the RM5231A. An independent transfer is a data transfer between two external
agents or be tween an external age nt and memory or periph eral on the system interface. Following
the asserting of the ExtRqst*, the RM5231A tri-states its drivers allowing the external agent to
use the system interface buses to complete an independent transfer. The external agent is
responsible for returning mastership of the sy stem interface to the RM5231A when it has
completed the independent transfer and does so by executing an External Null cycle.
3.28 Interrupt Handling
The RM5231A supports a dedicated interrupt vector for real time interrupt handling. When
enabled by the real time executive by setting a bit in the Cause register, interrupts vector to a
specific address which is not shared with any of the other exception types. This capability
eliminates the need to go through the normal software routine for exception decode and dispatch,
thereby lowering interrupt latency.
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
3.29 Standby Mode
The RM5231A provides a means to reduce the amount of power consumed by the internal core
when the CPU is not performing any useful operations. This state is known as Standby Mode.
Executing the
When the
internal processor cl ock s stop, th ereby fr eezi ng the pipe line. The phas e lock lo op, or PLL, inte rnal
timer/counter , and t he “wake up” input pins : Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset*
continue to operate in their normal fashion. If the SysAD bus is not idle when the
instruction completes the W pipe-stage, then the
is completed. Once the processor is in Standby, any interrupt, including the internally generated
timer interrupt, causes the processor to exit Standby and resume operation where it left off. The
WAIT instruction is typically inserted in the idle loop of the operating system or real time
executive.
WAIT instruction enables interrupts causes the processor to enter Standby Mode.
WAIT instruction completes the W pipe st age, and if the SysAD bus is currently idle, the
3.30 JTAG Interface
The RM5231A interface supports JTAG Test Access Port (TAP) boundary scan in conformance
with the IEEE 1149.1 specification. The JTAG interface is especially helpful for checking the
integrity of the processors pin connections.
3.31 Boot-Time Options
Fundamental operational modes for the processor are initialized by the boot-time mode control
interface. This serial interface operates at a very low frequency (SysClock divided by 256). The
low frequency operation allows t he init ia liza tion i nformat ion to be kept in a l ow cost EPROM o r a
system interface ASIC.
WAIT
WAIT is treated as a NOP until the bu s operation
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 25
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Immediately after the VccOK signal is asserted, the processor reads a serial bit stream of 256 bits
to initialize all the fundamental operational modes. ModeClock runs continuously from the
assertion of VccOK.
3.32 Boot-Time Modes
The boot-time serial mode stream is defined in Table 4. Bit 0 is the bit presented to the processor
as the first bit in the stream when VccOK is asserted. Bit 255 is the last bit transferred.
Table 4 Boot Time Mode Bit Stream
Mode
bit Description
0 Reserved: Must be zero 15 Reserved: Must be zero 4:1 Write-back data rate (W = write data transfer, x = wait
state)
0: WWWWWWWW 1: WWxWWxWWxWWx 2: WWxxWWxxWWxxWWxx 3: WxWxWxWxWxWxWxWx 4: WWxxxWWxxxWWxxxWWxxx 5: WWxxxxWWxxxxWWxxxxWWxxxx 6: WxxWxxWxxWxxWxxWxxWxxWxx 7: WWxxxxxxWWxxxx xxW W xx xxxxWWxxxxxx 8: WxxxWxxxWxxxWx xxW x xxW xxxWxxxWxxx 9-15 reserved
7:5 Pclock to SysClock Multiplier
Mode Bits 7:5
000 Multiply by 2 n/a 001 Multiply by 3 n/a 010 Multiply by 4 n/a 011 Multiply by 5 Multiply by 2.5 100 Multiply by 6 n/a 101 Multiply by 7 Multiply by 3.5 110 Multiply by 8 n/a 111 Multiply by 9 Multiply by 4.5
8 Specifies byte ordering. Logically ORed with
BigEndian input signal.
0: Little endian 1: Big endian
10:9 Non-Block Wri te Protocol
00: R4000 compatible 01: reserved 10: pipelined 11: write re-issue
11 Timer Interrupt Enable/Disable
0: Enable the timer interrupt on Int5* 1: Disable the timer interrupt on Int5*
12 Reserved: Must be zero 255:23 Reserved: Must be zero 14:13 Output driver strength - 100% = fastest
00: 67% strength 01: 50% strength 10: 100% strength 11: 83% strength
Mode Bit 20=0 Mode Bit 20=1
Mode
bit Description
17:16 System configuration identifiers - software
visible in Config[21..20] register
19:18 Reserved: Must be zero
20 Select SysClock to PClock Multiply Mode
0: Integer Multipliers 1: Half-Integer Multipliers
21 Reserved: Must be one
22 VccIO Setting
0: VccIO = 3.3V 1: VccIO = 2.5V
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 26
Document ID: PMC-2002174, Issue 2
4 Pin Descriptions
The following is a list of interface, interrupt, and miscellaneous pins available on the RM5231A.
An ‘*’ at the end of the signal name denotes an active low signal.
T able 5 System Interface
Pin Name Type Description
ExtRqst* Input External Request
Release* Output Release Interface
RdRdy* Input Read Ready
WrRd y* Input Write R eady
ValidIn* Input Valid Input
ValidOut* Output Valid Output
SysAD[31:0] Input/Output System Address/Data bus
SysADC[3:0] Input/Output System Address/Data check bus
SysCmd[8:0] Input/Output System Command/Data identifier bus
SysCmdP Input/Output Reserved for system Command/Data identifier bus parity
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
Signals that the system interface is submitting an external request.
Signals that the processor is releasing the system interface to slave state.
Signals that an external agent can now accept a processor read.
Signals that an external agent can now accept a processor write request.
Signals that an external agent is now drivin g a valid address or data on
the SysAD bus and a valid command or data identifier on the SysCmd
bus.
Signals that the pro ce ss or is n ow d r iv ing a v ali d add res s or dat a o n the
SysAD bus and a valid comm and or data iden tifi er on the Sy sCm d bus .
A 32-bit address and data bus for communication between the processor and an external agent.
A 4-bit bus containing parity check bits for the SysAD bus during data cycles.
A 9-bit bus for command and data identifier transmission between the
processor and an external agent.
For the RM5231A, unused on input and zero on output.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 27
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Table 6 Clock/Control Interface
Pin Name Type Description
SysClock Input System Clock
Master clock input used as the system interface reference clock. All
output timings are relative to this input clock. Pipeline operation
frequency is derived by multiplying this clock up by the factor selected
during boot initialization.
VccP Input Quiet Vcc for PLL
Quiet Vcc for the internal phase locked loop. Must be connected to VccInt through a filt er circuit .
VssP Input Quiet Vss for PLL
Quiet Vss for the interna l phas e lock ed loop . Must be conn ected to Vss through a filter circuit.
Table 7 Interrupt Interface
Pin Name Type Description
Int[5:0]* Input Interrupt
Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register.
NMI* Input Non-maskable inte rrup t
Non-maskable interrupt, ORed with bit 6 of the interrupt register.
Preliminary
Table 8 JTAG Interface
Pin Name Type Description
JTDI Input JTAG data in
JTAG serial data in.
JTCK Input JTAG clock input
JTAG serial clock input.
JTDO Output JTAG data out
JTAG serial data out.
JTMS Input JTAG command
JTAG command signal, signals that the incoming serial data is command data.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 28
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
Table 9 Initialization Interface
Pin Name Type Description
BigEndian Input Allows the system to change the processor addressing mode without
rewriting the mode ROM.
VccOK Input Vcc is OK
When asserted, this signal indicates to the RM5231A that both power
supplies has been above the recommended value for more than 100
milliseconds and remains stable. The assertion of VccOK initiates the
reading of the boot-time mode control serial stream.
ColdReset* Input Cold reset
This signal must be asserted for a power on reset or a cold reset.
ColdReset must be de-asserted synchronously with SysClock.
Reset* Input Reset
This signal must be asserted for any reset sequence. It may be
asserted synchronously or asynchronously for a cold reset, or
synchronously to initiate a warm reset. Reset must be de-asserted
synchronously with SysClock.
ModeClock Output Boot mode clock
Serial boot-mode data clock output at the system clock frequency divided by 256
ModeIn Input Boot mode data in
Serial boot-mode data input.
Table 10 Power Supply
Pin Name Type Description
VccInt Input Power supply for core. VccIO Input Power supply for I/O. Vss Input Ground return.
Note
1. An "*" at the end of the signal name denotes active low.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 29
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
5 Absolute Maximum Ratings
Symbol Rating Limits Unit
V
TERM
T
CASE
T
STG
I
IN
I
OUT
Notes
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the d evic e. This is a stress rati ng on ly and functional operation of the de vi ce at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. V
minimum = -2.0 V for pulse width less than 15 ns. VIN should not exceed 3.9 Volts.
IN
3. When V
4. Not more than one output should be shorted at a time. Duration of the short should not exceed 30
seconds.
Terminal Voltage with respect to GND
Operating Temperature
Commercial 0 to +85 °C Industrial –45 to +85 °C Storage Temperature –55 to +125 °C
DC Input Current
DC Output Current
< 0V or VIN > VccIO.
IN
1
–0.5
±20
±20
2
to +3.9
3
4
V
mA
mA
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 30
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
6 Recommended Operating Conditions
Grade Temperature Vss VccInt VccIO VccP VssP
Commercial 0°C to +85°C
(Case)
Industrial -45°C to +85°C
(Case)
Notes
1. VccIO should not exceed VccInt by greater than 2.0 V during the power-up sequence.
2. Applying a logic high state to any I/O pin before VccInt becomes stable is not recommended.
3. As specified in IEE E 1149.1 (JTA G), the JTMS pin must be held high during reset to avoid entering JTAG
test mode.
4. VccP must be connected to VccInt through a passive filter circuit. VssP must be connected to Vss
through a passive filter circuit. See the RM5200 User’s Manual for the recommended filter circuit.
0 V 1.57 V to 1.85 V 3.15 V to 3.45 V
or 2.3 V to 2.7 V
0 V 1.57 V to 1.85 V 3.15 V to 3.45 V
or 2.3 V to 2.7 V
Preliminary
1.57 V to 1.85 V 0 V
1.57 V to 1.85 V 0 V
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 31
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
7 DC Electrical Characteristics
VccIO = 3.15 V – 3.45 V
Preliminary
Parameter
V
OL
V
OH
V
OL
V
OH
V
IL
V
IH
I
IN
VccIO = 2.3 V – 2.7 V
Parameter
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
IL
V
IH
I
IN
Minimum Maximum
0.2 V | I
VccIO - 0.2 V
0.4 V | I
2.4 V
-0.3 V 0.8 V
2.0 V VccIO + 0.3 V
±15 µA
±15 µA
Minimum Maximum
0.2 V | I
2.1 V
0.4 V | I
2.0
0.7 V | I
1.7 –0.3 V 0.7 V
1.7 V VccIO + 0.3 V
±15 µA
±15 µA
OUT
OUT
VIN = 0
= VccIO
V
IN
OUT
OUT
OUT
VIN = 0
= VccIO
V
IN
Conditions
|= 100 µA
| = 2 mA
Conditions
|= 100 µA
| = 1 mA
| = 2 mA
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 32
Document ID: PMC-2002174, Issue 2
8 Power Consumption
VccInt = 1.65 V
Parameter
VccInt
Power
(mWatts)
Notes
1. Maximum supply voltage (VccInt = 1.73 V) with maximum temperature (TCase).
2. Dhrystone 2.1 instruction mix.
3. VccIO supply power is application dependant, but typically <20% of VccInt.
standby 350 350 350 active
3
Conditions Max
Maximum with no FPU operation Maximum worst case instruction mi x 950 1150 1350
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
CPU Speed
± 5%
2
250 MHz 300 MHz 350 MHz
1
900 1100 1200
Max
1
Max
1
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 33
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
9 AC Electrical Characteristics
9.1 Capacitive Load Deration
Preliminary
Parameter Symbol Min Max
Load Derate C
9.2 Clock Parameters
Parameter Symbol
SysClock High t SysClock Low t SysClock
Frequency
SysClock Period t
Clock Jitter for SysClock
SysClock Rise Time
SysClock Fall Time
ModeClock Period
JTAG Clock Period
Note
1. Operation of the RM52 31A is onl y guar ante ed w ith the Phase Lock Loop enabled.
SCH
SCL
SCP
t
JI
t
CR
t
CF
t
ModeCKP
t
JTAGCKP
Units
LD
— 2 ns/25pF
CPU Speed
T est
Conditions
Transition ≤ 5ns 3 3 3 ns
Transition ≤ 5ns 3 3 3 ns
250 MHz 300 MHz 350 MHz
MinMaxMinMaxMinMax
33 125 33 125 33 125 MHz
830830830ns
±150 ±150 ±150 ps
222ns
222ns
256 256 256 t
444t
Units
SCP
SCP
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 34
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
9.3 System Interface Parameters
1
CPU Speed
250 MHz to 350 MHz
Parameter
Data Output
Data Setup
Data Hold
Notes
1. Timings are measured from 0.425 x VccIO of clock to 0.425 x VccIO of signal for 3.3V I/O. Timings are
measured from 0.48 x VccIO of clock to 0.48 x VccIO of signal for 2.5V I/O.
2. Capacitive load for all m aximum out put tim ings is 50 pF. Minimum ou tput timing s are for theo retical no load
condition-untested.
3. Data Output timing applies to all signal pins whether tristate I/O or output only.
4. Setup and Hold parameters apply to all signal pins whether tristate I/O or input only.
5. Only mode 14:13 = 10 is tested and guaranteed.
6. Data shown is for 3.3 V I/O. For 2.5 V I/O derate all times by .5 nS.
1
2,3
4
4
Symbol Conditions Min Max Units
t
t
t
DO
DS
DH
mode14..13 = 10
mode14..13 = 01
6
t
= see above table
rise
= see above table
t
fall
5,6
(fastest)
5,6
(slowest)
1.0 5.0 ns
1.0 6.0 ns
2.5 ns
1.0 ns
9.4 Boot-Time Interface Parameters
Parameter Symbol Min
Mode Data Setup t Mode Data Hold t
DS
DH
4 SysClock cycles 0 SysClock cycles
Max
Units
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 35
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
10 Timing Diagrams
Figure 9 Clock Timing
SysClock
t
t
High
t
Rise
t
Fall
Low
10.1 System Interface Timing (SysAD, SysCmd, ValidIn*, ValidOut*, etc.)
Figure 10 Input Timing
SysClock
±t
JitterIn
Preliminary
Data
Figure 11 Output Timing
SysClock
Data
t
DS
t
DOmin
Data
t
DH
t
DOmax
DataData
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 36
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
11 Packaging Information
6
1.60 (0.063)
31.45 (1.2 3 8)
30.95 (1.2 1 9)
(24.80 (0.976))
(19.80)
-D-
5
0.20 (0.008) M C A–B D
0.20 (0.008) M C A–B DSS
Preliminary
S
S
TOP VIEW
pin #1 ID
1
(1.60 (0.0 6 3 ))
28.10 (1.106)
27.90 (1.098)
D
0.80 (0.0315) (124X)
0.45 (0.018)
0.30 (0.012)
-D-
7
AFTER PLATING
5
-B-
(24.80 (0.976))
31.45 (1.238)
30.95 (1.219)
0.20 (0.008) M C A–B DSS
0.20 (0.008) M H A–B DSS
0.05 (0.002)
5°–16° ALL SIDES
0.23 (0.009)
0.13 (0.005)
A–B
6
4
-H-
DATUM PLANE
0.25 (0.010) MIN.
GAGE PLANE
DETAIL “A”
28.10 (1.106)
27.90 (1.098)
C0.864 x 45
3.67 (0.144)
3.17 (0.125)
BASE
PLANE
0.010 (0.004)
SEA TING PLANE
5
-A-
7
-E-
128
°
(4X)
0.20 (0.008) M H A–B DSS
0.05 (0.002)
4.07 (0.160) MAX.
-CSEE DETAIL “A”
Notes
1. Package dimensions conform to JEDEC MO–108(DB–1).
2. Controlling dimensions: millimeters. Dimensions in inches are shown in parentheses.
3. Dimensions and tolerancing per ANSI Y14.5 – 1982.
8
0.25
(1.60 (0.0 8 3 ))
0° MIN.
R0.13 (0.005) MIN.
R0.30 (0.01 2)
0.13 (0.00 5 )
0°–7
°
1.00 (0.039)
0.70 (0.027)
(128X)
4. Datum plane “H” is located at the mold parting line and is coincident with the lead exits the plastic body at bottom
of the parting line.
5. Datums “A–B” and “D” to be determined at datum plane “H”.
6. To be determined at the seating plane “C”.
7. These dimensions to be determined at datum plane “H”. Dimensions “D” and “E” do not include mold protrusion.
Allowable protrusion is 0.25/0.10” per side.
8. Lead width does not include dambar protrusion. Allowable dambar protrusion shall be 0.08 mm/0.003” total in excess
of this dimension at the maximum material condition. Dambar cannot be located on the lower radius of the foot.
9. Pin numbers start with Pin #1 and continue counter clockwise to pin #128 when viewed from the top.
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 37
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
12 RM5231A 128 QFP Package Numerical Pinout
Pin Function Pin Function Pin Function Pin Function
1 NC 33 ModeIn 65 NMI* 97 NC 2 NC 34 RdRdy* 66 ExtRqst* 98 NC 3 VccIO 35 WrRdy* 67 Reset* 99 NC 4 Vss 36 ValidIn* 68 ColdReset* 100 NC 5 SysAD4 37 ValidOut* 69 VccOK 101 VccIO 6 SysAD5 38 Release* 70 BigEndian 102 Vss 7 VccInt 39 VccP 71 VccIO 103 SysAD28 8 Vss 40 VssP 72 Vss 104 SysAD29
9 SysAD6 41 SysClock 73 SysAD16 105 VccInt 10 SysAD7 42 VccInt 74 VccInt 106 Vss 11 SysAD8 43 Vss 75 Vss 107 SysAD30 12 SysAD9 44 SysCmd0 76 SysAD17 108 SysAD31 13 VccIO 45 SysCmd1 77 SysAD18 109 SysADC2 14 Vss 46 SysCmd2 78 SysAD19 110 VccInt 15 SysAD10 47 SysCmd3 79 VccInt 111 Vss 16 SysAD11 48 VccIO 80 Vss 112 SysADC3 17 VccInt 49 Vss 81 SysAD20 113 VccIO 18 Vss 50 SysCmd4 82 SysAD21 114 Vss 19 SysAD12 51 SysCmd5 83 VccIO 115 SysADC0 20 SysAD13 52 Vss 84 Vss 116 SysADC1 21 SysAD14 53 SysCmd6 85 SysAD22 117 SysAD0 22 VccInt 54 SysCmd7 86 SysAD23 118 SysAD1 23 Vss 55 SysCmd8 87 SysAD24 119 VccInt 24 SysAD15 56 SysCmdP 88 SysAD25 120 Vss 25 VccIO 57 VccInt 89 VccInt 121 SysAD2 26 Vss 58 Vss 90 Vss 122 SysAD3 27 ModeClock 59 Int0* 91 SysAD26 123 VccIO 28 JTDO 60 Int1* 92 SysAD27 124 Vss 29 JTDI 61 Int2* 93 VccIO 125 NC 30 JTCK 62 Int3* 94 Vss 126 NC 31 JTMS 63 Int4* 95 NC 127 NC 32 VccIO 64 Int5* 96 NC 128 NC
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 38
Document ID: PMC-2002174, Issue 2
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
13 RM5231A 128 QFP Package Alphabetical Pinout
Function Pin Function Pin Function Pin Function Pin
BigEndian 70 SysAD1 118 SysADC1 116 VccIO 71
ColdReset* 68 SysAD2 121 SysADC2 109 VccIO 83
ExtRqst* 66 SysAD3 122 SysADC3 112 VccIO 93
Int0* 59 SysAD4 5 SysClock 41 VccIO 101 Int1* 60 SysAD5 6 SysCmd0 44 VccIO 113 Int2* 61 SysAD6 9 SysCmd1 45 VccIO 123 Int3* 62 SysAD7 10 SysCmd2 46 VccOK 69 Int4* 63 SysAD8 11 SysCmd3 47 VccP 39 Int5* 64 SysAD9 12 SysCmd4 50 Vss 4
JTCK 30 SysAD10 15 SysCmd5 51 Vss 8
JTDI 29 SysAD11 16 SysCmd6 53 Vss 14 JTDO 28 SysAD12 19 SysCmd7 54 Vss 18 JTMS 31 SysAD13 20 SysCmd8 55 Vss 23
ModeClock 27 SysAD14 21 SysCmdP 56 Vss 26
ModeIn 33 SysAD15 24 ValidIn* 36 Vss 43
NC 1 SysAD16 73 ValidOut* 37 Vss 49 NC 2 SysAD17 76 VccInt 7 Vss 52 NC 95 SysAD18 77 VccInt 17 Vss 58 NC 96 SysAD19 78 VccInt 22 Vss 72 NC 97 SysAD20 81 VccInt 42 Vss 75 NC 98 SysAD21 82 VccInt 57 Vss 80 NC 99 SysAD22 85 VccInt 74 Vss 84 NC 100 SysAD23 86 VccInt 79 Vss 90 NC 125 SysAD24 87 VccInt 89 Vss 94 NC 126 SysAD25 88 VccInt 105 Vss 102 NC 127 SysAD26 91 VccInt 110 Vss 106 NC 128 SysAD27 92 VccInt 119 Vss 111
NMI* 65 SysAD28 103 VccIO 3 Vss 114
RdRdy* 34 SysAD29 104 VccIO 13 Vss 120
Release* 38 SysAD30 107 VccIO 25 Vss 124
Reset* 67 SysAD31 108 VccIO 32 VssP 40
SysAD0 117 SysADC0 115 VccIO 48 WrRdy* 35
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 39
Document ID: PMC-2002174, Issue 2
14 Ordering Information
RM5231A -123 H I
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
Temperature Grade:
(blank) = commercial
I = Industrial
Package Type:
H = MQFP with internal heat spreader
Device Maximum Speed
Device Type
A = 0.18 micron process geometry
Valid Combinations
RM5231A–250–H
RM5231A–300–H
RM5231A–350–H
RM5231A–300–HI (contact sales prior to design)
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 40
Document ID: PMC-2002174, Issue 2
Loading...