PMC PM8621-BIAP Datasheet

PM8621

NSE-8G

NSE-8G™ Standard Product Data Sheet

Preliminary

8G Narrowband Switch Element

Data Sheet

Preliminary

Issue 1: May, 2001

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC- PMC-2010850, Issue 1

NSE-8G™ Standard Product Data Sheet

Preliminary

Legal Information

Copyright

The information is proprietary and confidential to PMC-Sierra, Inc., and for its customers’ internal use. In any event, you cannot reproduce any part of this document, in any form, without the express written consent of PMC-Sierra, Inc.

PMC-2010850, (P1)

Disclaimer

None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement.

In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage.

Trademarks

S/UNI is a registered trademark of PMC-Sierra, Inc. and NSE-8G, SBS, CHESS, TEMUX-84, AAL1gator-32, SPECTRA, FREEDM-336, and SBI are trademarks of PMC-Sierra, Inc.

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PMC-Sierra 8555 Baxter Place Burnaby, BC Canada V5A 4V7

Tel: (604) 415-6000 Fax: (604) 415-6200

Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Web Si te: http://www.pmc-sierra.com

NSE-8G™ Standard Product Data Sheet

Preliminary

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NSE-8G™ Standard Product Data Sheet

Preliminary

List of Registers

Register 000H: NSE-8G Master Reset..............................................................................58

Register 001H: NSE-8G Individual Channel Reset ...........................................................59

Register 002H: NSE-8G Master JTAG ID .........................................................................60

Register 003H: SBS Page select – Page 0 ....................................................................... 61

Register 004H: SBS Page select – Page 1 ....................................................................... 62

Register 005H: NSE-8G Master Interrupt Source .............................................................63

Register 006H: NSE-8G Master ILC Interrupt Source ......................................................65

Register 007H: NSE-8G Master R8TD Interrupt Source................................................... 66

Register 008H: NSE-8G Master T8TE Interrupt Source ...................................................67

Register 009H: NSE-8G Master Clock Monitor ................................................................. 68

Register 00AH: NSE-8G DCB CMP select........................................................................69

Register 00BH: NSE-8G Interrupt Enable Register ..........................................................70

Register 00CH: NSE-8G Subsystem Interrupt Enable Register ....................................... 71

Register 00DH: NSE-8G R8TD TIP register .....................................................................72

Register 00EH: SBS User Bit 0 ......................................................................................... 73

Register 00FH: SBS User Bit 1 .........................................................................................74

Register 010H: SBS User Bit 2 .........................................................................................75

Register 011H: NSE-8G FREE User Register...................................................................76

Register 012H: Correct R8TD_RX_C1 Pulse Monitor ......................................................77

Register 013H: Unexpected R8TD_RX_C1 Interrupt........................................................ 78

Register 014H: Missing R8TD_RX_C1 Interrupt............................................................... 79

Register 015H: Unexpected R8TD_RX_C1 Interrupt Enable ...........................................80

Register 016H: Missing R8TD_RX_C1 Interrupt Enable ..................................................81

Register 020H, 024H: CSTR #1 – 2 Control* ....................................................................82

Register 021H, 025H: CSTR #1 – 2* Interrupt Enable and CSU Lock Status .................. 83

Register 022H, 026H: CSTR #1 – 2* Interrupt Indication.................................................. 84

Register 044H: DCB Configuration port 11-6 Register......................................................85

Register 045H: DCB Configuration port 5-0 Register .......................................................86

Register 046H: DCB Configuration Output Register. ........................................................87

Register 047H: DCB Access Mode Register .....................................................................88

Register 048H: DCB C1 delay (RC1DLY) register. .......................................................... 91

Register 04AH: DCB Frame size Register ........................................................................92

Register 04CH: DCB Configuration Register ....................................................................93

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NSE-8G™ Standard Product Data Sheet

Preliminary

Register 04DH: DCB Interrupt status Register..................................................................96

Register 100H + N*20H, R8TD Control and Status...........................................................97

Register 101H + N*20H, R8TD Interrupt Status................................................................99

Register 102H + N*20H, R8TD Line Code Violation Count ............................................101

Register 103H + N*20H, RXLV and DRU Control ...........................................................102

Register 108H + N*20H, T8TE Control and Status .........................................................104

Register 109H + N*20H, T8TE Interrupt Status ..............................................................106

Register 10AH + N*20H: T8TE Time-slot Configuration #1 ............................................107

Register 10BH + N*20H: T8TE Time-slot Configuration #2 ............................................108

Register 10CH + N*20H, T8TE Test Pattern ...................................................................109

Register 10DH + N*20H, TXLV and PISO Control .......................................................... 110

Register 110H + N*20H, ILC Transmit FIFO Data........................................................... 111

Register 111h + N*20H, ILC Transmit Control Register .................................................112

Register 112h + N*20H, ILC Transmit Misc.Status and FIFO Synch Register................ 113

Register 113h + N*20H, ILC Receive FIFO Data Register.............................................. 115

Register 114h + N*20H, ILC Receive Control Register ................................................... 116

Register 115h + N*20H, ILC Receive Auxiliary, Status and FIFO Synch Register.......... 117

Register 116h + N*20H, ILC Interrupt Enable and Control Register ............................... 121

Register 117h + N*20H: ILC Interrupt Reason Register.................................................. 124

Register 800H: NSE-8G Master Test ..............................................................................126

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NSE-8G™ Standard Product Data Sheet

Preliminary

List of Figures

Figure 1 An OC-48 T1/E1 ADM (Individually Drop/Add any T1/E1 in STS-48) ..............14

Figure 2 An OC-48 T1/E1 ADM (Drop/Add up to STS-48 at STS-1 Granularity)............14

Figure 3 Any-Service-Any-Port TDM Access Solution ....................................................15

Figure 4 Any-Service-Any-Port DS0-Granularity PHY Card ...........................................16

Figure 5 NSE- 8G Block Diagram Showing Functional Blocks .......................................17

Figure 6 NSE-8G UBGA-480 Ball Diagram (Bottom-View) .............................................20

Figure 7 Analog Power Filter Circuit................................................................................39

Figure 8 Generic LVDS Link Block Diagram ...................................................................40

Figure 9 Character Alignment State Machine .................................................................47

Figure 10 Frame Alignment State Machine.....................................................................48

Figure 11 In-Band Signaling Channel Message Format ................................................. 52

Figure 12 In-Band Signaling Channel Header Format ....................................................52

Figure 13 Input Observation Cell (IN_CELL) ................................................................131

Figure 14 Output Cell (OUT_CELL) ..............................................................................132

Figure 15 Bidirectional Cell (IO_CELL) .........................................................................132

Figure 16 Layout of Output Enable and Bidirectional Cells...........................................133

Figure 17 Shutting Down a Link ....................................................................................135

Figure 18 “C1” Synchronization Control........................................................................137

Figure 19 TEMUX-84™/SBS/NSE/SBS/AAL1gator-32™ system DS0 Switching

with CAS .......................................................................................................138

Figure 20 CAS Multiframe Timing .................................................................................139

Figure 21 Switch Timing DSOs with CAS .....................................................................139

Figure 22 TEMUX-84/SBS/NSE/SBS/FREEDM-336 System DS0 Switch no

CAS...............................................................................................................140

Figure 23 Switch Timing - DSOs without CAS ..............................................................141

Figure 24 Non DS0 Switch Timing ................................................................................142

Figure 25 Architecture of the RAM Input Interface........................................................144

Figure 26 C1 Position in the First Row..........................................................................149

Figure 27 Transport Overhead Affected by ILC ............................................................155

Figure 28 Example Graph .............................................................................................158

Figure 29 Time:Space:Time Switching in one NSE-8G and four Single-Ported

SBSs .............................................................................................................158

Figure 30 Example Graph .............................................................................................160

Figure 31 Example Problem..........................................................................................161

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NSE-8G™ Standard Product Data Sheet

Preliminary

Figure 32 Merged Graph ...............................................................................................161

Figure 33 Relabeled Graph ...........................................................................................162

Figure 34 Boundary Scan Architecture .........................................................................163

Figure 35 TAP Controller Finite State Machine.............................................................164

Figure 36 Receive Interface Timing ..............................................................................167

Figure 37 Transmit Interface Timing .............................................................................168

Figure 38 CMP Timing ..................................................................................................169

Figure 39 Microprocessor Interface Read Timing .........................................................173

Figure 40 Microprocessor Interface Write Timing .........................................................175

Figure 41 NSE-8G Input Timing ....................................................................................176

Figure 42 RSTB Timing.................................................................................................177

Figure 43 JTAG Port Interface Timing...........................................................................179

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NSE-8G™ Standard Product Data Sheet

Preliminary

List of Tables

Table 1 Analog Power Filters ..........................................................................................39

Table 2 SBI336S Character Encoding ............................................................................43

Table 3 Serial TelecomBus Character Encoding ............................................................45

Table 4 Switching Control RAM Layout...........................................................................50

Table 5 In-band Message Header Fields ........................................................................52

Table 6 NSE-8G Register Map........................................................................................54

Table 7 TX FIFO Message Level ..................................................................................114

Table 8 RX FIFO Message Level ..................................................................................119

Table 9 RXFIFO Threshold Values ...............................................................................122

Table 10 RXFIFO Timeout Delay .................................................................................. 123

Table 11 Test Mode Register Memory Map .................................................................. 125

Table 12 Instruction Register (Length - 3 bits) ..............................................................127

Table 13 Identification Register.....................................................................................127

Table 14 Boundary Scan Register ................................................................................128

Table 15 Absolute Maximum Ratings............................................................................170

Table 16 D.C Characteristics ........................................................................................171

Table 17 Microprocessor Interface Read Access .........................................................173

Table 18 Microprocessor Interface Write Access..........................................................175

Table 19 NSE-8G Input Timing (Figure 40) ..................................................................176

Table 20 RSTB Timing (Figure 41 ) ..............................................................................177

Table 21 Serial SBI Bus Interface ................................................................................. 178

Table 22 JTAG Port Interface ( Figure 42) .................................................................... 178

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1 Features

The Narrowband Switch Element 8G (NSE-8G):

• Implements a Scaleable Bandwidth Interconnect (SBI™) DS0 granularity Space switch.

• Implements a SONET/SDH VT1.5/VT2/TU11/TU12 granularity Space switch for the serial

777.6 MHz LVDS TelecomBus.

• With an allied PM8610 SBS or PM8611 SBS-lite device, implements a DS0 granularity

Memory-Space-Memory switch.

• Supports 12 STS-12 equivalent serial ports via 777.6 MHz, 8B/10B encoded LVDS links

(each port can be either Serial TeleCombus or Serial SBI336S)

• When configured for SBI mode, switches DS0 or N*DS0 for all T1 and E1 tributaries and

aggregate columns for switching T1, E1, TVT1.5, TVT2, DS3 and E3 tributaries.

• When configured for the serial 777.6 MHz TelecomBus interface, switches any SONET/SDH

virtual tributary (VT) or tributary unit (TU) up to STS-1.

NSE-8G™ Standard Product Data Sheet

Preliminary

• Supports switching of arbitrary non-standard octet aggregates.

• Supports unicast, multicast, and broadcast for all switching modes.

• Provides 8 Gbit/s (96,768 DS0s, 4.032 T1s/VT1.5s, 3,024 E1s/VT2s, 144 DS3s/E3s)

switching.

• Works with SBS devices that support up to four 19.44 MHz SBI or one 77.76 MHz SBI336

bus that communicates with PMC-Sierra’s SBI device family. Alternatively, the SBS and SBS-lite devices support up to four 19.44 MHz STS-3 TelecomBuses or one 77.76 MHz STS12 TelecomBus for connection with PMC-Sierra’s SPECTRA family of devices.

• Can be combined in applications with PMC-Sierra’s CHESS™ chip set devices (PM5374

TSE and PM5307 TBS).

• Supports a microprocessor interface used to configure/control the NSE and make DS0-

granularity switch settings.

• Supports clean error checked 8 Mbit/s full-duplex, in-band communications channels from its

attached microprocessor to the attached microprocessors of each of the 12 attached SBS336S devices. This channel is used to initialize and control the SBSs, or other such devices, and to implement call-establishment set-up changes.

• Supports JTAG for all non-LVDS signals.

• Requires dual power supplies at 1.8V and 3.3V.

• Packaged as a 480 ball UBGA.

• In conjunction with the SBS or SBS-lite, supports “1+1” and “1:N” fabric redundancy.

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2 Applications

The PM8621 Narrowband Switch Element 8G (NSE-8G) supports a variety of flexible Layer 1/Layer 2 architectures in combination with the following PMC-Sierra devices:

• PM8610 SBS and PM8611 SBS-lite (SBI Serializer and Memory switching stage).

• SBI bus devices (TEMUX™/TEMAP, FREEDM devices, S/UNI®-IMA devices,

AAL1gator™ devices and other future devices).

• CHESS™ chip set devices (PM5374 TSE, PM5307 TBS, PM5315 SPECTRA™-2488, and

PM7390 S/UNI®-MACH48).

These architectures include:

• T1/E1 SONET ADMs.

• TDM ASAP applications.

• PHY cards with DS0 (and above) level switching.

NSE-8G™ Standard Product Data Sheet

Preliminary

• PSTN replacement switching cores, as part of any-service-any-port applications, and

• Voice Gateways.

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3 References

1. ANSI - T1.105-1995, “Synchronous Optical Network (SONET) – Basic Description

including Multiplex Structure, Rates, and Formats”, 1995.

2. Telcordia - SONET Transport Systems: Common Generic Criteria, GR-253-CORE, Issue 2,

Revision 2, January 1999.

3. ITU, Recommendation G.707 - "Digital Transmission Systems – Terminal equipments -

General", March 1996.

4. IEEE 802.3, “Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access

Method and Physical Layer Specifications”, Section 36.2, 1998.

5. A.X. Widmer and P.A. Franaszek, “A DC-Balanced, Partitioned-Block, 8B/10B Transmission

Code,” IBM Journal of Research and Development, Vol. 27, No 5, September 1983, pp 440-

451.

NSE-8G™ Standard Product Data Sheet

Preliminary

6. U.S. Patent No. 4,486,739, P.A. Franaszek and A.X. Widmer, “Byte Oriented DC Balanced

(0,4) 8B/10B Partitioned Block Transmission Code,” December 4, 1984.

7. IEEE Std 1596.3-1996, “IEEE Standard for Low-Voltage Differential Signals (LVDS) for

Scalable Coherent Interface (SCI)”, Approved March 21, 1996

8. L.R. Ford, D.R. Fulkerson, “Flows in Networks'', Maximum Cardinality Matchings in

Bipartite Graphs

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4 Application Examples

Figure 1 illustrates an OC-48 SONET Ring Add/Drop Multiplexer. The PM5363 TUPP-622 devices align all paths to transport frames in preparation for VT1.5/VT2 granularity switching. The PM8610 SBI336 Bus Serializer (SBS™) an PM8621 Narrowband Switching Element 8G (NSE-8G™) devices support VT1.5/VT2 and above switching. The Add and Drop buses are provided by the SBSs that are not in the SONET Ring path. In this case, they connect to T1 and E1 mapper ports.

Figure 1 An OC-48 T1/E1 ADM (Individually Drop/Add any T1/E1 in STS-48)

NSE-8G™ Standard Product Data Sheet

Preliminary

SPECTRA-

2488

4 X

TUPP-

622

4 X

SBS

NSE20G

4 X

SBS

**

42 required to terminate

4 X

TUPP-

622

4 X

TEMAP

-84

SPECTRA-

2488

4 X

OCTAL

-LIU **

links for all 4 TEMAPS

Figure 2 illustrates another OC-48 SONET Ring ADM. In this application, the network of three PM5310 TelecomBus Serializers (TBSs) from PMC-Sierra’s CHESS™ chip set add, drop, and groom traffic at STS-1 granularities. The four TUPP-622 devices align any dropped STS-1s (paths to transport frames). The virtual tributary (VT) or tributary unit (TU) switching solution is provided by the SBS-NSE-8G-SBS network below the TUPP-622s. Four SBSs support up to an STS-48 amount of add/drop traffic.

Figure 2 An OC-48 T1/E1 ADM (Drop/Add up to STS-48 at STS-1 Granularity)

SPECTA-

2488

TBS TBS

SPECTA-

2488

TBS

4 X

TUPP-

622

4 X

SBS

NSE8G

SBS

SBI device SBI device SBI device SBI device SBI device SBI device SBI device SBI device SBI device SBI device SBI device SBI device SBI device SBI device SBI device SBI device

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NSE-8G™ Standard Product Data Sheet

Preliminary

Figure 3 illustrates the organization of the access line size card(s) from a SONET Any Service Any Port (ASAP) product. All traffic from the NSE-8G to the SBI link layer devices is pathaligned. See Figure 4 for a description of the PHY line cards compatible with the system in Figure 3.

Figure 3 Any-Service-Any-Port TDM Access Solution

SBS-

lite

SBS

NSE8G

SBS

FREEDM-

336

4 X

IMA-84

12 X

AAL1gator-

32

4 X

TEMUX-84

H-MVIP

Any-PHY

(Packet)

Any-PHY

(Cell)

Any-PHY

(Cell)

Processors

DSP

T1/E1/DS0/N*DS0 Layer 2 Processing

Figure 4 shows the organization of a SONET PHY card compatible with Figure 3. As shown, both Figure 3 and Figure 4 have NSE-8Gs, but only one instance of this device is required to connect all the SBSs. A likely packaging of this combined system would place the NSE-8G (and a standby NSE-8G) on separate fabric cards. In Figure 4, PM8315 TEMUXs align paths to transport frames. Note: Figure 3 assumes this alignment.

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NSE-8G™ Standard Product Data Sheet

Figure 4 Any-Service-Any-Port DS0-Granularity PHY Card

Preliminary

4 X

TEMUX-84

4 X

TEMUX-84

4 X

TEMUX-84

4 X

TEMUX-84

SPECTRA-

2488

TBS

SONET/T1/E1 Termination - VT/TU/DS0 Switching

SBS

NSE8G

SBS

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5 Block Diagram

The NSE-8G is organized as a DS0 granularity space switch. Alternatively, the NSE-8G is organized as a self aligning (with respect to STS-12 boundaries in TelecomBus mode) VT1.5/VT2 granularity space switch.

Figure 5 NSE- 8G Block Diagram Showing Functional Blocks

NSE-8G™ Standard Product Data Sheet

Preliminary

RP[0]

RN[0]

RP[1]

RN[1]

RP[11]

RN[11]

RC1FP

CMP

SYSCLK

LVDS

Receiver

(RXLV)

LVDS

Receiver

(RXLV)

LVDS

Receiver

(RXLV)

Data

Recovery

Unit

(DRU)

Data

Recovery

Unit

(DRU)

Data

Recovery

Unit

(DRU)

Receive

8B/10B

Decoder

(R8TD)

Receive

8B/10B

Decoder

(R8TD)

Receive

8B/10B

Decoder

(R8TD)

1/2

In-Band

Link

Controller

(ILC)

1/2

In-Band

Link

Controller

(ILC)

1/2

In-Band

Link

Controller

(ILC)

DS0 Crossbar Switch

(DCB)

Microprocessor Interface

1/2

In-Band

Link

Controller

(ILC)

1/2

In-Band

Link

Controller

(ILC)

1/2

In-Band

Link

Controller

(ILC)

Transmit

8B/10B

Encoder

(T8TE)

Transmit

8B/10B

Encoder

(T8TE)

Transmit

8B/10B

Encoder

(T8TE)

JTAG

Transmit Serializer

(PISO)

Transmit Serializer

(PISO)

Transmit Serializer

(PISO)

Clock

Synthesis

Unit

LVDS

Transmitt

er

(TXLV)

LVDS

Transmitt

er

(TXLV)

LVDS

Transmitt

er

(TXLV)

Tx

Ref

TP[0]

TN[0]

TP[1]

TN[1]

TP[11]

TN[11]

CSB

RSTB

A[11:0]

D[31:0]

ALE

RDB

WRB

INTB

TRSTB

TDI

TCK

TMS

TDO

The R8TD, in combination with the RXLV and DRU receive, decode and align incoming SBI336/STS-12-equivalent LVDS links. Outputs are provided to the primary switching flow and to the in-band signaling channel. These provide all analog and digital functions to terminate a full-duplex 777.6 MHz serial SBI336S or 777.6 MHz serial TelecomBus on LVDS.

A 12 X 12 DS0 Crossbar Switch(DCB) stage switches data and control signals between the 12 ports. The switching instructions are stored in two pages of ram configured as offline and online allowing the user to modify the offline page.

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NSE-8G™ Standard Product Data Sheet

Preliminary

The T8TE, in combination with the PISO and TXLV perform 8B/10B coding and emits the LVDS bit streams. These provide all analog and digital functions to launch a full-duplex 777.6 MHz serial SBI336S bus or 777.6 MHz serial TelecomBus on LVDS.

The microprocessor bus interface and in-band signaling units (ILC) provide a clean (error checked) channel between the NSE-8G and SBSs. This can be used to send messages between the NSE-8G microprocessor-and the SBS microprocessors in a user defined format.

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6 Description

The PM8621 NSE-8G is a monolithic CMOS integrated circuit packaged in a 480 ball UBGA that performs DS0 and above granularity space switching on 12 SBI336 streams carried as serial SBI336S in 8B/10B coding over LVDS at 777.6 Mbit/s. The NSE-8G also performs VT1.5/VT2 and above granularity switching on 12 STS-12/STM-4 SONET/SDH streams, carried as Serial TelecomBus signals in 8B/10B coding over LVDS at 777.6 Mbit/s.

The NSE-8G is typically used with up to 12 PM8610 SBS or PM8611 SBS-lite devices to provide Memory-Space-Memory switching systems. As each SBS supports either four SBI buses at 19.44 MHz or one SBI336 bus at 77.76 MHz, the overall system supports any mixture of SBI and SBI336 byte serial buses, ranging from 48 19.44 MHz SBI buses to 12 SBI336 77.76 MHz buses that do not exceed an aggregate bandwidth of STS-144, or about 7.5 Gbit/s. In TelecomBus mode, the SBS devices support the same range of flexibility for 48 19.44 MHz and 12 77.76 MHz TelecomBuses at VT1.5/VT2 granularity

Central to the NSE-8G is a 12 x 12 cross bar switch. Every clock cycle, the cross bar switches a byte of data with control signals from each input port to an output port. The byte of data may be a DS0 channel from a T1/E1 or may be one byte of a column comprising a T1, E1, DS3, E3, VT1.5, VT2 or STS-1.

NSE-8G™ Standard Product Data Sheet

Preliminary

In order for switching to take place, all input and output streams must be synchronized. This is done via the RC1FP input signal. When switching T1s, E1s, VTs and other higher order units, only SBI336 multiframe alignment is required. The same applies for TelecomBus mode where only frame alignment is required.

An in-band control link over the serial LVDS interface allows the NSE-8G to communicate with the microprocessors attached to the SBS, SBS-lite or other serial SBI336S devices. The effective bandwidth of each inband link to each device is 8 Mbit/s. The inband link provides error detection on 32 byte user messages and some near realtime control signals between devices. Using the near realtime control signals the NSE-8G is able to synchronize page switching, indicate switchover between working or protected links and exchange three user defined signals (software) and eight Auxilliary signals (software). The User and Auxilliary signals can be used to indicates things like interrupts or can be used for handshaking between the end point microprocessors. The message format is left to the user of the devices. The only constraint is that each message is a maximum of 32 bytes long.

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NSE-8G™ Standard Product Data Sheet

Preliminary

7 Pin Diagram

The NSE-8G is packaged in a 35 mm x 35 mm 480 ball UBGA.

Figure 6 NSE-8G UBGA-480 Ball Diagram (Bottom-View)

Upper Left

34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18

A VSS VSS VSS VSS VDDO VSS NC VSS NC VSS

Reserved

VSS

Reserved

VSS

Reserved

VSS VDDI

B VSS AVDH VDDO VDDO VDDO VDDI NC NC NC VDDI

C VSS AVDH AVDH VDDO VDDI

D VSS AVDH AVDH AVDH VDDO

E RESK1 RES1 NC NC

F VSS NC NC AVDL1

GNCNCNCNC

H VSS NC NC AVDH

JNCNCNCNC

K VSS NC NC VDDI

LNCNCNCNC

M VSS NC NC AVDH

N VDDI AVDL2 NC NC

P VSS NC NC VDDI

Reserved

NC NC VDDI NC

Reserved

VDDI VDDO NC NC

Reserved Reserved Reserved Reserved Reserved Reserved

Reserved

Reserved Reserved Reserved Reserved

VDDI

Reserved Reserved Reserved

VDDO

VDDO VDDI

RSTB

VDDI

RNCNCNCNC

T NC NC AVDL4 AVDL3

U NC NC AVDL5 CSU_AV

DH

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NSE-8G™ Standard Product Data Sheet

Preliminary

Upper Right

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

NC SYSCLK NC VSS NC VSS NC VSS

Reserved

VSS

Reserved

VSS NC VSS VSS VSS VSS A

NC NC NC TCK TMS NC VDDI

Reserved

NC VDDI NC VDDI T DI TDO NC

NC RC1FP VDDI TRSTB VDDI VDDO VDDI CMP

Reserved Reserved Reserved Reserved Reserved

Reserved Reserved Reserved Reserved

Reserved

VDDO

Reserved Reserved

NC VDDO VDDO VDDO VSS B

VDDI VDDO VDDO AVDH VSS C

NC VDDO AVDH AVDH VSS D

AVDH ATB0[1] AVDH AVDH E

ATB1[1] TN[1] TP[1] VSS F

TN[3] TP[3] TN[2] TP[2] G

AVDH VDDI NC VSS H

RP[1] RN[1] TN[4] TP[4] J

VDDI RP[2] RN[2] VSS K

VDDI AVDL14 RP[3] RN[3] L

AVDH RP[4] RN[4] VSS M

TN[6] TP[6] TN[5] TP[5] N

VDDI TN[7] TP[7] VSS P

RP[5] RN[5] TN[8] TP[8] R

AVDH VDDI AVDL13 VSS T

RP[7] RN[7] RP[6] RN[6] U

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Lower Left

VNCNCNCNC

W VSS AVDL6 VDDI AVDH

YNCNCNCNC

AA VSS NC NC VDDI

AB NC NC NC NC

AC VSS NC NC AVDH

AD NC NC AVDL7 VDDI

AE VSS NC NC VDDI

AF NC NC NC NC

AG VSS NC VDDI AVDH

NSE-8G™ Standard Product Data Sheet

Preliminary

AH NC NC NC NC

AJ VSS NC NC ATB1[2]

AK AVDH AVDH ATB0[2] AVDH

AL VSS AVDH AVDH VDDO ALE NC VDDI VDDO A[6] A[2] VDDI VDDO D[27] VDDI NC NC VDDI

AM VSS AVDH VDDO VDDO CSB RDB VDDI A[9] A[5] A[3] D[31] D[29] VDDI D[25] VDDI D[21] D[20]

AN VSS VDDO VDDO VDDO INTB WRB NC A[10] A[7] A[4] A[0] D[30] D[28] D[26] NC D[22] D[19]

AP VSS VSS VSS VSS NC VSS A[11] VSS A[8] VSS A[1] VSS NC VSS D[24] D[23] D[18]

34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 22 Document ID: PMC-2010850, Issue 1

Lower Right

NSE-8G™ Standard Product Data Sheet

Preliminary

CSU_AVDHAVDL12 RP[8] RN[8] V

AVDL10 AVDL11 TN[9] T P[9] W

TN[10] TP[10] TN[11] TP[11] Y

VDDI TN[12] TP[12] VSS AA

RP[9] RN[9] AVDL9 VDDI AB

AVDH RP[10] RN[10] VSS AC

RP[11] RN[11] RP[12] RN[12] AD

VDDI NC NC VSS AE

NC NC NC NC AF

AVDH NC NC VSS AG

NC NC NC NC AH

AVDL8 NC NC VSS AJ

NC NC RES2 RESK2 AK

D[17] VDDO D[13] D[11] D[8] VDDO D[5] D[3] D[0] VDDO NC NC VDDO AVDH AVDH AVDH VSS AL

VDDI D[15] VDDI D[10] D[9] D[7] NC D[2] D[1] NC NC NC NC VDDO AVDH AVDH VSS AM

D[16] D[14] D[12] NC VDDI D[6] D[4] VDDI NC NC NC NC VDDO VDDO VDDO AVDH VSS AN

NC VSS VDDI VSS VDDI VSS NC VSS NC VSS NC VSS VDDO VSS VSS VSS VSS AP

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 23 Document ID: PMC-2010850, Issue 1

8 Pin Description

8.1 Pin Description Table

Pad Name Type Pin No. Function

LVDS Ports (128 Balls)

RP[1]

RN[1]

RP[2]

RN[2]

RP[3]

RN[3]

RP[4]

RN[4]

RP[5]

RN[5]

RP[6]

RN[6]

RP[7]

RN[7]

RP[8]

RN[8]

RP[9]

RN[9]

RP[10]

RN[10]

RP[11]

RN[11]

RP[12]

RN[12]

Analog LVDS Input

J4

J3

K3

K2

L2

L1

M3

M2

R4

R3

U2

U1

U4

U3

V2

V1

AB4

AB3

AC3

AC2

AD4

AD3

AD2

AD1

NSE-8G™ Standard Product Data Sheet

Preliminary

Receive Serial Data. The differential receive serial data

links (RP[11:0]/RN[11:0]) carry the receive SBI336S or SONET/SDH STS-12 frame data from upstream sources in bit serial format. Each differential pair RP[X]/RN[X] carries a constituent SBI336 or STS-12 stream. Data on RP[X]/RN[X] is encoded in an 8B/10B format extended from IEEE Std. 802.3. The 8B/10B character bit ‘a’ is transmitted first and the bit ‘j’ is transmitted last. All RP[X]/RN[X] differential pairs must be frequency locked and phase aligned (within a certain tolerance) to each other. RP[11:0]/RN[11:0] are nominally 777.6 Mbit/s data streams.

Any unused or N/C, but available inputs should be tied low using a 10 k resistor.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 24 Document ID: PMC-2010850, Issue 1

Pad Name Type Pin No. Function

TP[1]

TN[1]

TP[2]

TN[2]

TP[3]

TN[3]

TP[4]

TN[4]

TP[5]

TN[5]

TP[6]

TN[6]

TP[7]

TN[7]

TP[8]

TN[8]

TP[9]

TN[9]

TP[10]

TN[10]

TP[11]

TN[11]

TP[12]

TN[12]

NSE-8G Control and Clocking (5 Balls)

SYSCLK Input A16

Analog LVDS Output

F2

F3

G1

G2

G3

G4

J1

J2

N1

N2

N3

N4

P2

P3

R1

R2

W1

W2

Y3

Y4

Y1

Y2

AA2

AA3

Transmit Serial Data. The differential transmit working serial data links (TP[11:0]/TN[11:0]) carry the transmit SBI336S or SONET/SDH STS-12 frame data to a downstream sinks in bit serial format. Each differential pair carries a constituent STS-12 stream. Data on TP[X]/TN[X] is encoded in an 8B/10B format extended from IEEE Std. 802.3. The 8B/10B character bit ‘a’ is transmitted first and the bit ‘j’ is transmitted last. All TP[X]/TN[X] differential pairs are frequency locked and phase aligned (within a certain tolerance) to each other. TP[11:0]/TN[11:0] are nominally 777.6 Mbit/s data streams.

System Clock. The system clock signal (SYSCLK) is the master clock for the NSE-8G device. SYSCLK must be a

77.76 MHz clock, with a nominal 50% duty cycle.

CMP and RC1FP are sampled on the rising edge of SYSCLK.

NSE-8G™ Standard Product Data Sheet

Preliminary

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 25 Document ID: PMC-2010850, Issue 1

NSE-8G™ Standard Product Data Sheet

Pad Name Type Pin No. Function

RC1FP Input D16

Reserved Output C17 Reserved pin, must be left floating

CMP Input D10

Receive Serial Interface Frame Pulse. The receive serial interface frame pulse signal (RC1FP) provides system timing for the receive serial interface. RC1FP is supplied in common to all devices in a system containing one or more NSE-20G devices. In TelecomBus mode, RC1FP is set high once every four frames, in SBI mode without any DS0 switching, or when switching DS0s (WITHOUT CAS) RC1FP is also set high once every four frames, or multiple thereof. When in SBI mode switching DS0s WITH CAS RC1FP indicates signaling multiframe alignment by pulsing once every 48 frames or multiples thereof.

A software configurable delay from RC1FP is used to indicate that the C1 multiframe boundary 8B/10B characters have been delivered on all the receive serial data links (RP[32:1]/RN[32:1]) and are ready for processing by the time-space-time switching elements.

RC1FP is sampled on the rising edge of SYSCLK.

Connection Memory Page. The connection memory page select signal (CMP) controls the selection of the connection memory page in the NSE. When CMP is set high, connection memory page 1 is selected. When CMP is set low, connection memory page 0 is selected. Changes to the connection memory page selection are synchronized to the boundary of the next C1FP frame or multiframe depending on the mode:

4-Frame SBI/SBI336 mode:

CMP is sampled at the C1 byte position of the incoming bus on the first frame of the four-frame multiframe. Changes to the connection memory page selection are synchronized to the frame boundary (A1 byte position) of the next four-frame multiframe.

48-Frame SBI/SBI336 mode:

CMP is sampled at the C1 byte position of the incoming bus on the first frame of the 48-frame multiframe. Changes to the connection memory page selection are synchronized to the frame boundary (A1 byte position) of the next 48-frame multiframe.

TelecomBus mode:

CMP is sampled at the C1 byte position of every frame on the incoming bus. Changes to the connection memory pate selection are synchronized to the frame boundary (A1 byte position) of the next frame.

Preliminary

CMP is sampled on the rising edge of SYSCLK at the RC1FP frame position.

RSTB Input B18

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 26 Document ID: PMC-2010850, Issue 1

Reset Enable Bar. The active low reset signal (RSTB) provides an asynchronous reset for the NSE. RSTB is a Schmitt triggered input with an integral pull-up resistor

Pad Name Type Pin No. Function

Microprocessor Interface (49 Balls)

CSB Input AM30

RDB Input AM29

WRB Input AN29

Chip Select Bar. The active low chip select signal (CSB) controls microprocessor access to registers in the NSE8G device. CSB is set low during NSE-8G Microprocessor Interface Port register accesses. CSB is set high to disable microprocessor accesses.

If CSB is not required (i.e. register accesses controlled using RDB and WRB signals only), CSB should be connected to an inverted version of the RSTB input.

Read Enable Bar. The active low read enable bar signal (RDB) controls microprocessor read accesses to registers in the NSE-8G device. RDB is set low and CSB is also set low during NSE-8G Microprocessor Interface Port register read accesses. The NSE-8G drives the D[31:0] bus with the contents of the addressed register while RDB and CSB are low.

Write Enable Bar. The active low write enable bar signal (WRB) controls microprocessor write accesses to registers in the NSE-8G device. WRB is set low and CSB is also set low during NSE-8G Microprocessor Interface Port register write accesses. The contents of D[31:0] are clocked into the addressed register on the rising edge of WRB while CSB is low.

NSE-8G™ Standard Product Data Sheet

Preliminary

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 27 Document ID: PMC-2010850, Issue 1

Pad Name Type Pin No. Function

D[31] D[30] D[29]

D[28]

D[27]

D[26]

D[25] D[24]

D[23] D[22]

D[21]

D[20]

D[19] D[18]

D[17] D[16]

D[15] D[14]

D[13] D[12]

D[11] D[10] D[9]

D[8]

D[7]

D[6]

D[5] D[4]

D[3] D[2]

D[1] D[0]

A[11 A[10]

A[9]

A[8]

A[7]

A[6]

A[5]

A[4]

A[3]

A[2]

A[1]

A{0]

I/O

Input AP28

AM24 AN23 AM23

AN22

AL22

AN21

AM21 AP20

AP19 AN19

AM19

AM18

AN18 AP18

AL17 AN17

AM16 AN16

AL15 AN15

AL14 AM14 AM13

AL13

AM12

AN12

AL11 AN11

AL10 AM10

AM9 AL9

AN27

AM27

AP26

AN26

AL26

AM26

AN25

AM25

AL25

AP24

AN24

Microprocessor Data Bus. The bi-directional data bus, D[31:0] is used during NSE-8G Microprocessor Interface Port register reads and write accesses. D[31] is the most significant bit of the data words and D[0] is the least significant bit.

Microprocessor Address Bus. The microprocessor address bus (A[11:0]) selects specific Microprocessor Interface Port registers during NSE-8G register accesses.

NSE-8G™ Standard Product Data Sheet

Preliminary

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 28 Document ID: PMC-2010850, Issue 1

Pad Name Type Pin No. Function

ALE Input AL30

INTB Open Drain

Output

JTAG Port (5 Balls)

TCK Input B14

TMS Input B13

TDI Input C12

TDO Tri-state C11

TRSTB Input D14

AN30

Address Latch Enable. The address latch enable signal (ALE) is active high and latches the address bus (A[11:0]) when it is set low. The internal address latches are transparent when ALE is set high. ALE allows the NSE-8G to interface to a multiplexed address/data bus. ALE has an integral pull up resistor.

Interrupt Request Bar. The active low interrupt enable signal (INTB) output goes low when an NSE-8G interrupt source is active and that source is unmasked. INTB returns high when the interrupt is acknowledged via an appropriate register access. INTB is an open drain output.

Test Clock. The JTAG test clock signal (TCK) provides timing for test operations that are carried out using the IEEE P1149.1 test access port.

Test Mode Select. The JTAG test mode select signal (TMS) controls the test operations that are carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull-up resistor.

Test Data Input. The JTAG test data input signal (TDI) carries test data into the NSE-8G via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull-up resistor.

Test Data Output. TheJTAG test data output signal (TDO) carries test data out of the NSE-8G via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tri-state output which is inactive except when scanning of data is in progress.

Test Reset Bar. The active low JTAG test reset signal (TRSTB) provides an asynchronous NSE-8G test access port reset via the IEEE P1149.1 test access port. TRSTB is a Schmitt triggered input with an integral pull-up resistor.

Note that when TRSTB is not being used, it must be connected to the RSTB input.

NSE-8G™ Standard Product Data Sheet

Preliminary

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 29 Document ID: PMC-2010850, Issue 1

PMC PM8621-BIAP Datasheet

Table of Contents

List of Registers

List of Tables

8.1 Pin Description Table