PMC PM8610-BIAP Datasheet

PM8610

SBS Telecom Standard Product Data Sheet

Preliminary

SBI Bus Serializer (SBS)

Telecom Standard Product

Data Sheet

Preliminary

Issue 3: May, 2001

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use Document ID: PMC-2000168, Issue 3

SBS Telecom Standard Product Data Sheet

Preliminary

Legal Information

Copyright

The information is proprietary and confidential to PMC-Sierra, Inc., and for its customers’ internal use. In any event, you cannot reproduce any part of this document, in any form, without the express written consent of PMC-Sierra, Inc.

PMC-2000168, (A3)

Disclaimer

None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement.

In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage.

Trademarks

SBI, SPECTRA, TEMUX, AAL1gator, and FREEDM are trademarks of PMC-Sierra, Inc.

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Tel: (604) 415-6000 Fax: (604) 415-6200

Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Web Si te: http://www.pmc-sierra.com

SBS Telecom Standard Product Data Sheet

Preliminary

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SBS Telecom Standard Product Data Sheet

Preliminary

List of Registers

Register 000H: SBS Master Reset....................................................................................92

Register 001H: SBS Master Configuration........................................................................93

Register 002H: SBS Version/Part Number........................................................................ 96

Register 003H: SBS Part Number/Manufacturer ID..........................................................97

Register 004H: SBS Master Bypass Register ................................................................... 98

Register 005H: SBS Master SPE Control #1 ..................................................................100

Register 006H: SBS Master SPE Control #2 ..................................................................101

Register 007H: SBS Receive Synchronization Delay .....................................................102

Register 008H: SBS In-Bank Link User Bits....................................................................103

Register 009H: SBS Receive Configuration....................................................................104

Register 00AH: SBS Transmit Configuration ..................................................................106

Register 00BH: SBS Transmit J1 Configuration..............................................................108

Register 00CH: SBS Transmit V1 Configuration.............................................................109

Register 00DH: SBS Transmit H1-H2 Pointer Value....................................................... 110

Register 00EH: SBS Transmit Alternate H1-H2 Pointer Value........................................ 111

Register 00FH: SBS Transmit H1-H2 Pointer Selection .................................................112

Register 010H: SBS Master Interrupt Source .................................................................113

Register 011H: SBS Interrupt Register............................................................................ 116

Register 012H: SBS Interrupt Enable Register ............................................................... 118

Register 013H: SBS Loopback Configuration .................................................................120

Register 014H: SBS Master Signal Monitor #1, Accumulation Trigger ........................... 121

Register 015H: SBS Master Signal Monitor #2 ...............................................................123

Register 016H: SBS Master Interrupt Enable .................................................................125

Register 017H: SBS Free User Register......................................................................... 128

Register 020H: ISTA Incoming Parity Configuration .......................................................129

Register 021H: ISTA Incoming Parity Status ...................................................................131

Register 022H: ISTA TelecomBus Configuration.............................................................132

Register 028H: IMSU Configuration ................................................................................ 133

Register 029H: IMSU Interrupt Status and Memory Page Update Register ...................134

Register 02AH: IMSU Indirect Time Switch Address.......................................................135

Register 02BH: IMSU Indirect Time Switch Data ............................................................ 137

Register 030H: ICASM CAS Enable Indirect Access Address Register .........................138

Register 031H: ICASM CAS Enable Indirect Access Control Register ...........................139

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SBS Telecom Standard Product Data Sheet

Preliminary

Register 032H: ICASM CAS Enable Indirect Access Data Register ...............................140

Register 038H: ISTT Tributary Translator Control RAM Indirect Access Address

Register ..................................................................................................................141

Register 039H: ISTT Tributary Translator Control RAM Indirect Access Control

Register ..................................................................................................................142

Register 03AH: ISTT Tributary Translator Control RAM Indirect Access Data

Register ..................................................................................................................143

Register 040H: OSTT Tributary Translator Control RAM Indirect Access Address

Register ..................................................................................................................144

Register 041H: OSTT Tributary Translator Control RAM Indirect Access Control

Register ..................................................................................................................145

Register 042H: OSTT Tributary Translator Control RAM Indirect Access Data

Register ..................................................................................................................146

Register 048H: OMSU Configuration ..............................................................................147

Register 049H: OMSU Interrupt Status and Memory Page Update Register .................148

Register 04AH: OMSU Indirect Time Switch Address.....................................................149

Register 04BH: OMSU Indirect Time Switch Data ..........................................................151

Register 050H: OCASM CAS Enable Indirect Access Address Register........................152

Register 051H: OCASM CAS Enable Indirect Access Control Register ......................... 153

Register 052H: OCASM CAS Enable Indirect Access Data Register ............................. 154

Register 060H: OSTA Outgoing Configuration and Parity..............................................155

Register 061H: OSTA Outgoing J1 Configuration ........................................................... 157

Register 062H: OSTA Outgoing V1 Configuration ..........................................................158

Register 063H: OSTA H1-H2 Pointer Value ....................................................................159

Register 064H: OSTA Alternate H1-H2 Pointer Value .....................................................160

Register 065H: OSTA H1-H2 Pointer Selection ..............................................................161

Register 066H: OSTA Tributary Output Enable Indirect Access Address Register .........162

Register 067H: OSTA Tributary Output Enable Indirect Access Control Register ..........163

Register 068H: OSTA Tributary Output Enable Indirect Access Data Register ..............164

Register 070h: WPP Indirect Address .............................................................................165

Register 071h: WPP Indirect Data................................................................................... 167

Register 071h (IADDR = 0h): WPP Monitor STS-1 path Configuration ..........................168

Register 071h (IADDR = 1h): WPP Monitor PRBS[22:7] Accumulator ...........................170

Register 071h (IADDR = 2h): WPP Monitor PRBS[6:0] Accumulator .............................171

Register 071h (IADDR = 4h): WPP Monitor Error count .................................................172

Register 071h (IADDR = 8h): WPP Generator STS-1 path Configuration ......................173

Register 071h (IADDR = 9h): WPP Generator PRBS[22:7] Accumulator ....................... 175

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SBS Telecom Standard Product Data Sheet

Preliminary

Register 071h (IADDR = Ah): WPP Generator PRBS[6:0] Accumulator.........................176

Register 072h: WPP Generator Payload Configuration .................................................. 177

Register 073h: WPP Monitor Payload Configuration ......................................................179

Register 074h: WPP Monitor Byte Error Interrupt Status................................................181

Register 075h: WPP Monitor Byte Error Interrupt Enable...............................................182

Register 079h: WPP Monitor Synchronization Interrupt Status.......................................183

Register 07Ah: WPP Monitor Synchronization Interrupt Enable .....................................184

Register 07Bh: WPP Monitor Synchronization State ......................................................185

Register 07Ch: WPP Performance Counters Transfer Trigger ....................................... 186

Register 080h: PPP Indirect Address ..............................................................................187

Register 081h: PPP Indirect Data.................................................................................... 189

Register 081h (IADDR = 0h): PPP Monitor STS-1 path Configuration ...........................190

Register 081h (IADDR = 1h): PPP Monitor PRBS[22:7] Accumulator ............................192

Register 081h (IADDR = 2h): PPP Monitor PRBS[6:0] Accumulator ..............................193

Register 081h (IADDR = 4h): PPP Monitor Error count ..................................................194

Register 081h (IADDR = 8h): PPP Generator STS-1 path Configuration .......................195

Register 081h (IADDR = 9h): PPP Generator PRBS[22:7] Accumulator ........................197

Register 081h (IADDR = Ah): PPP Generator PRBS[6:0] Accumulator..........................198

Register 082h: PPP Generator Payload Configuration ...................................................199

Register 083h: PPP Monitor Payload Configuration .......................................................201

Register 084h: PPP Monitor Byte Error Interrupt Status.................................................203

Register 085h: PPP Monitor Byte Error Interrupt Enable................................................204

Register 089h: PPP Monitor Synchronization Interrupt Status........................................205

Register 08Ah: PPP Monitor Synchronization Interrupt Enable ......................................206

Register 08Bh: PPP Monitor Synchronization State........................................................207

Register 08Ch: PPP Performance Counters Transfer Trigger ........................................208

Register 090H: WILC Transmit FIFO Data High .............................................................209

Register 091H: WILC Transmit FIFO Data Low ..............................................................210

Register 093H: WILC Transmit Control Register ............................................................211

Register 095H: WILC Transmit Status and FIFO Synch Register...................................212

Register 096H: WILC Receive FIFO Data High ..............................................................214

Register 097H: WILC Receive FIFO Data Low ...............................................................215

Register 099H: WILC Receive FIFO Control Register ....................................................216

Register 09AH: WILC Receive Auxiliary Register ........................................................... 217

Register 09BH: WILC Receive Status and FIFO Synch Register ...................................218

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SBS Telecom Standard Product Data Sheet

Preliminary

Register 09DH: WILC Interrupt Enable and Control Register. ........................................222

Register 09FH: WILC Interrupt Reason Register ............................................................224

Register 0A0H: PILC Transmit FIFO Data High .............................................................. 225

Register 0A1H: PILC Transmit FIFO Data Low...............................................................226

Register 0A3H: PILC Transmit Control Register ............................................................. 227

Register 0A5H: PILC Transmit Status and FIFO Synch Register ...................................228

Register 0A6H: PILC Receive FIFO Data High............................................................... 230

Register 0A7H: PILC Receive FIFO Data Low................................................................231

Register 0A9H: PILC Receive FIFO Control Register..................................................... 232

Register 0AAH: PILC Receive Auxiliary Register............................................................233

Register 0ABH: PILC Receive Status and FIFO Synch Register....................................234

Register 0ADH: PILC Interrupt Enable and Control Register.......................................... 238

Register 0AFH: PILC Interrupt Reason Register ............................................................240

Register 0B0H: TW8E Control and Status ...................................................................... 241

Register 0B1H: TW8E Interrupt Status............................................................................243

Register 0B2H: TW8E Time-slot Configuration #1 ..........................................................244

Register 0B3H: TW8E Time-slot Configuration #2 ..........................................................245

Register 0B4H: TW8E Test Pattern ................................................................................. 246

Register 0B5H: TW8E Analog Control ............................................................................247

Register 0B8H: TP8E Control and Status .......................................................................248

Register 0B9H: TP8E Interrupt Status.............................................................................250

Register 0BAH: TP8E Time-slot Configuration #1 .......................................................... 251

Register 0BBH: TP8E Time-slot Configuration #2 .......................................................... 252

Register 0BCH: TP8E Test Pattern .................................................................................253

Register 0BDH: TP8E Analog Control.............................................................................254

Register 0C0H: RW8D Control and Status......................................................................255

Register 0C1H: RW8D Interrupt Status...........................................................................258

Register 0C2H: RW8D LCV Count..................................................................................260

Register 0C3H: RW8D Analog Control............................................................................261

Register 0C8H: RP8D Control and Status.......................................................................262

Register 0C9H: RP8D Interrupt Status............................................................................265

Register 0CAH: RP8D LCV Count ..................................................................................267

Register 0CBH: RP8D Analog Control ............................................................................268

Register 0D0H: CSTR Control ........................................................................................269

Register 0D1H: CSTR Configuration and Status ............................................................270

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SBS Telecom Standard Product Data Sheet

Preliminary

Register 0D2H: CSTR Interrupt Status............................................................................271

Register 0E0H: REFDLL Configuration ...........................................................................272

Register 0E3H: REFDLL Control Status..........................................................................273

Register 0E8H: SYSDLL Configuration...........................................................................275

Register 0EBH: SYSDLL Control Status .........................................................................276

Register 100H: Master Test.............................................................................................279

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SBS Telecom Standard Product Data Sheet

Preliminary

List of Figures

Figure 1 OC-48 T1/E1 ADM (Individually Drop/Add any T1/E1 in STS-48)....................21

Figure 2 OC-48 T1/E1 ADM (Drop/Add up to STS-48 at STS-1 Granularity) .................21

Figure 3 Any-Service-Any-Port NxDS0 TDM Access Solution........................................22

Figure 4 Any-Service-Any-Port T1/E1 Channelized PHY Card ......................................22

Figure 5 Quad 19 MHz SBI Bus/TelecomBus SBS Block Diagram ................................23

Figure 6 77 MHz SBI Bus/TelecomBus SBS Block Diagram ..........................................24

Figure 7 Loopback Block Diagram .................................................................................. 25

Figure 8 Pin Diagram ...................................................................................................... 28

Figure 9 Character Alignment State Machine .................................................................81

Figure 10 Frame Alignment State Machine.....................................................................82

Figure 11 In-Band Signaling Channel Message Format ................................................. 85

Figure 12 In-Band Signaling Channel Header Format ....................................................85

Figure 13 Input Observation Cell (IN_CELL) ................................................................289

Figure 14 Output Cell (OUT_CELL) ..............................................................................290

Figure 15 Bidirectional Cell (IO_CELL) .........................................................................290

Figure 16 Layout of Output Enable and Bidirectional Cells...........................................291

Figure 17 “C1” Synchronization Control........................................................................293

Figure 18 TEMUX™-84/SBS/NSE/SBS/AAL1gator™-32 System DS0 Switching

with CAS .......................................................................................................294

Figure 19 CAS Multiframe timing ..................................................................................295

Figure 20 Switch Timing DSOs with CAS .....................................................................295

Figure 21 TEMUX-84/SBS/NSE/SBS/FREEDM-336 System DS0 Switching No

CAS...............................................................................................................296

Figure 22 Switch Timing - DSOs without CAS ..............................................................296

Figure 23 Non DS0 Switch Timing ................................................................................297

Figure 24 Example Graph .............................................................................................299

Figure 25 Time:Space:Time Switching in one NSE-20G and four Single-Ported

SBSs .............................................................................................................300

Figure 26 Example Graph .............................................................................................301

Figure 27 Example Problem..........................................................................................302

Figure 28 Merged Graph ...............................................................................................302

Figure 29 Relabeled Graph ...........................................................................................303

Figure 30 Boundary Scan Architecture .........................................................................305

Figure 31 TAP Controller Finite State Machine.............................................................306

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SBS Telecom Standard Product Data Sheet

Preliminary

Figure 32 Incoming SBI336 Functional Timing .............................................................309

Figure 33 Incoming SBI Functional Timing ...................................................................310

Figure 34 Incoming 77 MHz TelecomBus Functional Timing .......................................312

Figure 35 Incoming 19 MHz TelecomBus Functional Timing .......................................312

Figure 36 Incoming TelecomBus to LVDS Functional Timing ......................................313

Figure 37 Incoming SBI Bus to LVDS Timing with DS0 Switching ...............................313

Figure 38 Transmit TelecomBus Functional Timing......................................................314

Figure 39 Transmit SBI336 Functional Timing Diagram ...............................................315

Figure 40 Receive TelecomBus Functional Timing.......................................................315

Figure 41 Receive SBI336 Functional Timing ............................................................... 316

Figure 42 Receive LVDS Link Timing ...........................................................................317

Figure 43 Outgoing Synchronization Timing .................................................................318

Figure 44 Outgoing 77.76 MHz TelecomBus Functional Timing ..................................318

Figure 45 Outgoing 19.44 MHz TelecomBus Functional Timing ..................................319

Figure 46 Outgoing SBI336 Functional Timing .............................................................320

Figure 47 Outgoing SBI Bus Functional Timing ............................................................320

Figure 48 Microprocessor Interface Read Timing .........................................................324

Figure 49 Microprocessor Interface Write Timing .........................................................326

Figure 50 SBS Incoming Timing....................................................................................328

Figure 51 SBS Receive Timing ..................................................................................... 330

Figure 52 SBS Outgoing Timing....................................................................................332

Figure 53 SBS Outgoing Bus Collision Avoidance Timing............................................333

Figure 54 SBS Transmit Timing ....................................................................................334

Figure 55 JTAG Port Interface Timing...........................................................................335

Figure 56 352 Pin UBGA 27 mm x 27 mm Body...........................................................337

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SBS Telecom Standard Product Data Sheet

Preliminary

List of Tables

Table 1 Structure for Carrying Multiplexed Links ............................................................55

Table 2 T1/TVT1.5 Tributary Column Numbering ...........................................................55

Table 3 E1/TVT2 Tributary Column Numbering .............................................................. 56

Table 4 T1/E1 Link Rate Information...............................................................................57

Table 5 T1/E1 Clock Rate Encoding ...............................................................................57

Table 6 DS3/E3 Link Rate Information............................................................................58

Table 7 DS3/E3 Clock Rate Encoding ............................................................................58

Table 8 T1 Framing Format.............................................................................................60

Table 9 T1 Channel Associated Signaling bits................................................................61

Table 10 E1 Framing Format ..........................................................................................63

Table 11 E1 Channel Associated Signaling bits .............................................................64

Table 12 DS3 Framing Format........................................................................................65

Table 13 DS3 Block Format ............................................................................................65

Table 14 DS3 Multi-frame Stuffing Format......................................................................66

Table 15 E3 Framing Format ..........................................................................................66

Table 16 E3 Frame Stuffing Format ................................................................................67

Table 17 Transparent VT1.5/TU11 Format .....................................................................68

Table 18 Transparent VT2/TU12 Format ........................................................................69

Table 19 Fractional Rate Format.....................................................................................71

Table 20 Structure for Carrying Multiplexed Links in SBI336..........................................72

Table 21 SBI336S Character Encoding ..........................................................................76

Table 22 Serial TelecomBus Character Encoding ..........................................................77

Table 23 In-band Message Header Fields ......................................................................85

Table 24 Test Mode Register Memory Map .................................................................. 278

Table 25 Instruction Register (Length - 3 bits) ..............................................................280

Table 26 Identification Register.....................................................................................281

Table 27 Boundary Scan Register ................................................................................282

Table 28 Absolute Maximum Ratings............................................................................321

Table 29 D.C Characteristics ........................................................................................322

Table 30 Microprocessor Interface Read Access (Figure 48).......................................324

Table 31 Microprocessor Interface Write Access (Figure 49) .......................................326

Table 32 SBS Incoming Timing (Figure 50) ..................................................................327

Table 33 SBS Receive Timing (Figure 51)....................................................................328

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SBS Telecom Standard Product Data Sheet

Preliminary

Table 34 SBS Outgoing Timing with 77.76 MHz SREFCLK (Figure 52) ......................331

Table 35 SBS Outgoing Timing with 19.44 MHz SREFCLK (Figure 52) ......................331

Table 36 SBS Outgoing Bus Collision Avoidance Timing (Figure 53) ..........................332

Table 37 SBS Transmit Timing (Figure 54)...................................................................333

Table 38 JTAG Port Interface (Figure 55) .....................................................................335

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1 Features

• The PM8610 SBI336 Bus Serializer (SBS) is a: ° Scalable Bandwidth Interconnect (SBI) converter and Time Division Multiplexer (TDM)

SBI switch.

° Quad byte-wide 19.44 MHz SBI bus to 777.6 MHz serial SBI336S converter. ° Byte-wide 77.76 MHz SBI336 bus to 777.6 MHz serial SBI336S converter. ° DS0, NxDS0, T1, E1, TVT1.5, TVT2, DS3 and E3 granular quad SBI to serial SBI336S

switch. Supports subrate link switching with the restriction that subrate links must be symmetric in both the transmit and receive directions.

° DS0, NxDS0, T1, E1, TVT1.5, TVT2, DS3 and E3 granular SBI336 to serial SBI336S

switch. Supports subrate link switching with the restriction that subrate links must be symmetric in both the transmit and receive directions.

Note: The byte-wide 77.76 MHz SBI336 bus interface can be used instead of the serial SBI336S interface. All converter and switch capabilities can be used with the byte-wide SBI interface.

SBS Telecom Standard Product Data Sheet

Preliminary

° VT channelized TelecomBus to TelecomBus converter and TDM switch. This requires

the telecombus J1 byte to be in a fixed location corresponding to a value of 0 or 522 that is immediately following the C1 octets.

° Quad byte-wide 19.44 MHz TelecomBus to serial 777.6 MHz TelecomBus converter. ° Byte-wide 77.76 MHz TelecomBus to serial 777.6 MHz TelecomBus converter. ° VT1.5, VT2, STS-1 quad 19.44 MHz TelecomBus to serial TelecomBus switch. ° VT1.5, VT2, STS-1 77.76 MHz TelecomBus to serial TelecomBus switch.

Note: The byte-wide 77.76 MHz TelecomBus interface can be used instead of the serial TelecomBus interface. All converter and switch capabilities can be used with the bytewide TelecomBus interface.

• Can be used with the Narrowband Switch Elements, NSE-20G to implement a DS0 granularity SBI Memory:Space:Memory switch scalable to 20 Gbit/s and the NSE-8G to implement a switch scalable to 8 Gbit/s. In TelecomBus mode, can implement a 20 Gbit/s VT1.5/VT2 granularity Memory:Space:Memory switch.

• Integrates two independent DS0 granularity Memory Switches. One switch is placed between the incoming 77.76 MHz byte wide SBI336 bus (or quad multiplexed 19.44 MHz SBI buses) and the transmit working and protect Serial SBI336S link (or the 77.76 MHz byte wide transmit SBI336 bus). The transmit working and protect links transmit the same data. The other switch is placed between the receive working or protect Serial SBI336S link (or the

77.76 MHz byte wide receive SBI336 bus) and the outgoing 77.76 MHz byte wide SBI336 bus (or quad multiplexed 19.44 MHz SBI buses).

• Provides 125 µS nominal latency in DS0 mode. Channel Associated Signaling (CAS) latency through the SBS in DS0 mode is two T1 multiframes (6 mS) or two E1 multiframes (4 mS).

• Provides less than 16 µS nominal latency in TelecomBus mode or SBI mode without DS0 level switching.

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• Permits any receive or incoming byte from an input port to be mapped to any outgoing or transmit byte, respectively, on the associated output port through the Memory switch.

• Supports redundant working and protect serial SBI336S links in support of a redundant Memory:Space:Memory switch with the NSE.

• Encodes and decodes byte wide SBI and SBI336 bus control signals for all SBI supported link types and clock modes for transport over the serial SBI336S interface.

• Encodes data from the incoming SBI bus or TelecomBus stream to a working and protect

777.6 Mbit/s LVDS serial links with 8B/10B-based encoding.

• Decodes data from a working and protect 777.6 MHz LVDS serial links with 8B/10B-based encoding to the outgoing SBI bus or TelecomBus stream.

• In SBI mode, switches Channel Associated Signaling bits (CAS) with all DS0 data.

• Uses 8B/10B-based line coding protocol on the serial links to provide transition density

guarantee and DC balance and to offer a greater control character vocabulary than the standard 8B/10B protocol.

• Provides optional pseudo-random bit sequence (PRBS) generation for each outgoing LVDS serial data link for off-line link verification. PRBS can be inserted with STS-1 granularity.

• Provides PRBS detection for each incoming LVDS serial link for off-line link verification. PRBS is verified with STS-1 granularity.

• Provides pins to coordinate updating of the connection map of the time-slot interchange blocks in the local device, peer SBS devices and companion NSE switch device.

• Can communicate with the NSE switch device over an in-band communications channel in the LVDS links. This channel includes mechanisms for central control and configuration.

• Derives all internal timing from a single 77.76 MHz system clock and a system frame pulse.

• Implemented in 1.8 V/3.3 V 0.18 µm CMOS and packaged in a 352 ball 27 mm x 27 mm

UBGA package.

• Consumes low power at 1.4 W.

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2 Applications

• T1/E1 SONET/SDH Cross-connects

• T1/E1 SONET/SDH Add-Drop Multiplexers

• OC-48 Multiservice Access Multiplexers

• Channelized OC-12/OC-48 Any Service Any Port Switches

• Serial Backplane Board Interconnect

• Shelf to Shelf Cabled Serial Interconnect

• Voice Gateways

SBS Telecom Standard Product Data Sheet

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3 References

1. IEEE 802.3, “Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications”, Section 36.2, 1998.

2. A.X. Widmer and P.A. Franaszek, “A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code,” IBM Journal of Research and Development, Vol. 27, No 5, September 1983, pp 440-

451.

3. U.S. Patent No. 4,486,739, P.A. Franaszek and A.X. Widmer, “Byte Oriented DC Balanced (0,4) 8B/10B Partitioned Block Transmission Code,” December 4, 1984.

4. Telcordia - SONET Transport Systems: Common Generic Criteria, GR-253-CORE, Issue 2, Revision 2, January 1999.

5. ITU, Recommendation G.707 - "Digital Transmission Systems – Terminal equipments General", March 1996.

SBS Telecom Standard Product Data Sheet

Preliminary

6. ITU, Rec Recommendation O.151 – “Error Performance Measuring Equipment Operating at the Primary Rate and Above", October 1992.

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4 Application Examples

Figure 1 and Figure 2 show a PM8610 SBI336 Bus Serializer (SBS) connected to a TelecomBus to implement a T1 or E1 Add/Drop function. When connected to a TelecomBus, the SBS and the PM8620 or PM8621 Narrowband Switching Element (NSE) implements a T1/E1 Memory:Space:Memory switch. The SBS requires all path pointer justifications to be translated into tributary pointer movements so that J1 is fixed to the location following C1 or H3. In both examples, J1 alignment is performed with the TUPP-622. Switching within the SBS and NSE is done using Transparent Virtual Tributary, TVT, mapping across the serial SBI336S LVDS links.

Figure 1 OC-48 T1/E1 ADM (Individually Drop/Add any T1/E1 in STS-48)

SBS Telecom Standard Product Data Sheet

Preliminary

SPECTRA-

2488

4 X

TUPP-

622

4 X

SBS

NSE

4 X

SBS

4 X

TUPP-

622

1 X

TEMAP

-84

Figure 2 OC-48 T1/E1 ADM (Drop/Add up to STS-48 at STS-1 Granularity)

SPECTRA-

2488

TBS TBS

TBS

4 X

TUPP-

622

4 X

SBS

NSE

SPECTRA-

2488

SBS

TEMUX84 TEMUX84 TEMUX84 TEMUX84 TEMUX84 TEMUX84 TEMUX84 TEMUX84 TEMUX84 TEMUX84 TEMUX84 TEMUX84 TEMUX84 TEMUX84 TEMUX84 TEMUX84

SPECTRA-

2488

11 X

OCTLIU

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SBS Telecom Standard Product Data Sheet

Preliminary

Figure 3 and Figure 4 show examples of the SBS used to implement high density T1/E1 Channelized Physical Interface cards and NxDS0 Multiservice access cards using SBS and NSE devices. DS0, NxDS0, T1, E1, Transparent VTs, E3, DS3 and sub-rate links can be switched between the Physical Layer and Layer 2 devices using SBS and NSE devices.

Figure 3 Any-Service-Any-Port NxDS0 TDM Access Solution

SBS

NSE

SBS

FREEDM-

336

4 X

IMA-84

12 X

AAL1gator-

32

11 X

OCTLIU

Serial

Clock and

Data

Figure 4 Any-Service-Any-Port T1/E1 Channelized PHY Card

TBS

4 X

TEMUX-84

SBS

Any-PHY

(Packet)

Any-PHY

(Cell)

Any-PHY

(Cell)

Processors

DSP

SPECTRA-

2488

TBS

4 X

TEMUX-84

4 X

TEMUX-84

4 X

TEMUX-84

SBS

NSE

SBS

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 22 Document ID: PMC-2000168, Issue 3

5 Block Diagram

Figure 5 Quad 19 MHz SBI Bus/TelecomBus SBS Block Diagram

SBS Telecom Standard Product Data Sheet

Preliminary

IDATA[4:1][7:0]

IDP[4:1]

IPL[4:1] IV5[4:1]

IC1FP[4:1]

ITPL[4:1]

ITAIS[4:1]

SREFCLK19

SREFCLK

SYSCLK

JUST_REQ[4:1]

ODATA[4:1][7:0]

ODP[4:1]

OPL[4:1] OV5[4:1]

OC1FP[4:1]

OTPL[4:1]

OTAIS[4:1]

OACTIVE[4:1]

ODETECT[4:1]

Incoming

SBI336

Timing

Adaptor

(ISTA)

Outgoing

SBI336

Timing Adaptor (OSTA)

Incoming

CAS

Expand

(ICASE)

Outgoing

CAS

Merge

(OCASM)

ICMP

Incoming

Memory

Switch

Unit

(IMSU)

Outgoing

Memory

Switch

Unit

(OMSU)

Incoming

CAS

Merge

(ICASM)

Outgoing

CAS

Expand

(OCASE)

Incoming

SBI

Tributary

Translator

(ISTT)

Outgoing

SBI

Tributary

Translator

(OSTT)

1/2

Working

PRBS

Processor

(WPP)

1/2

Protect

PRBS

Processor

(PPP)

1/2

Working

PRBS

Processor

(WPP)

1/2

Protect

PRBS

Processor

(PPP)

1/2 Working In-Band

Link

Controller

(WILC)

1/2

Protect

In-Band

Link

Controller

(PILC)

1/2

Working

In-Band

Link

Controller

(WILC)

1/2

Protect

In-Band

Link

Controller

(PILC)

IUSER

Transmit

Working

8B/10B

Serializer

Encoder

(TWPS)

(TW8E)

Transmit

Protect

8B/10B

Serializer

Encoder

Receive Working

8B/10B Decoder (RW8D)

Receive

Protect

8B/10B Decoder

(RP8D)

(TP8E)

(TPPS)

Tx

Ref

Working

Data

Recovery

Unit

(WDRU)

Protect

Data

Recovery

Unit

(PDRU)

TC1FP

Transmit Working

LVDS

Interface

(TWLV)

Transmit

Protect

LVDS

Interface

(TPLV)

Clock

Synthesis

Unit

Receive

Working

LVDS

Interface

(RWLV)

Receive

Protect

LVDS

Interface

(RPLV)

TDATA[7:0] TDP TPL TV5 TJUST_REQ TTPL TTAIS

TPWRK

TNWRK

TPPROT

TNPROT

RPWRK

RNWRK

RPPROT

RNPROT

RDATA[7: 0] RDP RPL RV5 RJUST_REQ RTPL RTAIS

Microprocessor Interface

A[8:0]

OCMP

D[15:0]

CSB

RSTB

ALE

RDB

WRB

INTB

RWSEL

OUSER

RC1FP

JTAG

TDI

TCK

TMS

TRSTB

TDO

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 23 Document ID: PMC-2000168, Issue 3

SBS Telecom Standard Product Data Sheet

Figure 6 77 MHz SBI Bus/TelecomBus SBS Block Diagram

Preliminary

IDATA[1][7:0]

IDP[1]

IPL[1] IV5[1]

IC1FP[1]

ITPL[1]

ITAIS[1]

SREFCLK

SYSCLK

JUST_REQ[1]

ODATA[1][7:0]

ODP[1]

OPL[1] OV5[1]

OC1FP[1]

OTPL[1]

OTAIS[1]

OACTIVE[1]

ODETECT[1]

Incoming

SBI336

Timing

Adaptor

(ISTA)

Outgoing

SBI336

Timing Adaptor (OSTA)

Incoming

CAS

Expand

(ICASE)

Outgoing

CAS

Merge

(OCASM)

ICMP

Incoming

Memory

Switch

Unit

(IMSU)

Outgoing

Memory

Switch

Unit

(OMSU)

Incoming

CAS

Merge

(ICASM)

Outgoing

CAS

Expand

(OCASE)

Incoming

SBI

Tributary

Translator

(ISTT)

Outgoing

SBI

Tributary

Translator

(OSTT)

1/2

Working

PRBS

Processor

(WPP)

1/2

Protect

PRBS

Processor

(PPP)

1/2

Working

PRBS

Processor

(WPP)

1/2

Protect

PRBS

Processor

(PPP)

1/2 Working In-Band

Link

Controller

(WILC)

1/2

Protect

In-Band

Link

Controller

(PILC)

1/2

Working

In-Band

Link

Controller

(WILC)

1/2

Protect

In-Band

Link

Controller

(PILC)

IUSER

Transmit

Working

8B/10B

Serializer

Encoder

(TWPS)

(TW8E)

Transmit

Protect

8B/10B

Serializer

Encoder

Receive Working

8B/10B

Decoder

(RW8D)

Receive

Protect 8B/10B

Decoder

(RP8D)

(TP8E)

(TPPS)

Tx

Ref

Working

Data

Recovery

Unit

(WDRU)

Protect

Data

Recovery

Unit

(PDRU)

TC1FP

Transmit Working

LVDS

Interface

(TWLV)

Transmit

Protect

LVDS

Interface

(TPLV)

Clock

Synthesis

Unit

Receive

Working

LVDS

Interface

(RWLV)

Receive

Protect

LVDS

Interface

(RPLV)

TDATA[7:0] TDP TPL TV5 TJUST_REQ TTPL TTAIS

TPWRK

TNWRK

TPPROT

TNPROT

RPWRK

RNWRK

RPPROT

RNPROT

RDATA[7: 0] RDP RPL RV5 RJUST_REQ RTPL RTAIS

Microprocessor Interface

A[8:0]

OCMP

CSB

RSTB

D[15:0]

ALE

RDB

WRB

INTB

RWSEL

OUSER

RC1FP

JTAG

TDI

TCK

TMS

TRSTB

TDO

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 24 Document ID: PMC-2000168, Issue 3

6 Loopback Configurations

Figure 7 Loopback Block Diagram

SBS Telecom Standard Product Data Sheet

Preliminary

IDATA[4:1][7:0]

IDP[4:1]

IPL[4:1] IV5[4:1]

IC1FP[4:1]

ITPL[4:1]

ITAIS[4:1]

SREFCLK19

SREFCLK

SYSCLK

JUST_REQ[4:1]

ODATA[4:1][7:0]

ODP[4:1]

OPL[4:1] OV5[4:1]

OC1FP[4:1]

OTPL[4:1]

OTAIS[4:1]

OACTIVE[4:1]

ODETECT[4:1]

Incoming

SBI336

Timing

Adaptor

(ISTA)

Outgoing

SBI336

Timing Adaptor (OSTA)

Incoming

CAS

Expand

(ICASE)

Outgoing

CAS

Merge

(OCASM)

ICMP

Incoming

Memory

Switch

Unit

(IMSU)

Outgoing

Memory

Switch

Unit

(OMSU)

Incoming

CAS

Merge

(ICASM)

Outgoing

CAS

Expand

(OCASE)

Incoming

SBI

Tributary

Translator

(ISTT)

Outgoing

SBI

Tributary

Translator

(OSTT)

1/2

Working

PRBS

Processor

(WPP)

1/2

Protect

PRBS

Processor

(PPP)

1/2

Working

PRBS

Processor

(WPP)

1/2

Protect

PRBS

Processor

(PPP)

1/2 Working In-Band

Link

Controller

(WILC)

1/2

Protect

In-Band

Link

Controller

(PILC)

1/2

Working

In-Band

Link

Controller

(WILC)

1/2

Protect

In-Band

Link

Controller

(PILC)

IUSER

Transmit

Working

8B/10B

Serializer

Encoder

(TWPS)

(TW8E)

Transmit

Protect

8B/10B

Serializer

Encoder

Receive Working

8B/10B

Decoder

(RW8D)

Receive

Protect 8B/10B

Decoder

(RP8D)

(TP8E)

(TPPS)

Tx

Ref

Working

Data

Recovery

Unit

(WDRU)

Protect

Data

Recovery

Unit

(PDRU)

TC1FP

Transmit Working

LVDS

Interface

(TWLV)

Transmit

Protect

LVDS

Interface

(TPLV)

Clock

Synthesis

Unit

Receive

Working

LVDS

Interface

(RWLV)

Receive

Protect

LVDS

Interface

(RPLV)

TDATA[7:0] TDP TPL TV5 TJUST_REQ TTPL TTAIS

TPWRK

TNWRK

TPPROT

TNPROT

RPWRK

RNWRK

RPPROT

RNPROT

RDATA[7: 0] RDP RPL RV5 RJUST_REQ RTPL RTAIS

Microprocessor Interface

A[8:0]

OCMP

CSB

RSTB

D[15:0]

ALE

RDB

WRB

INTB

RWSEL

OUSER

RC1FP

JTAG

TDI

TCK

TMS

TRSTB

TDO

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 25 Document ID: PMC-2000168, Issue 3

7 Description

The PM8610 SBI336 Bus Serializer (SBS) is a monolithic integrated circuit that implements conversion between a byte-serial 19.44 MHz SBI bus or 77.76 MHz SBI336 bus and a redundant

777.6 Mbit/s bit-serial 8B/10B-base SBI336S bus.

In TelecomBus mode, the SBS implements conversion between any 19.44 MHz TelecomBus or

77.76 MHz TelecomBus format and a redundant 777.6 Mbit/s bit-serial 8B/10B-base serial TelecomBus format. In line with the bus conversion is a DS0 granular switch allowing any input DS0 to be output on any output DS0. The redundant 777.6 Mbit/s serial interfaces can be disabled and a byte-wide SBI336 bus can be enabled in its place with all the DS0 level switching capabilities.

The SBS can be used to connect and switch high density T1/E1 framer devices supporting an SBI bus with link layer devices supporting an SBI bus over a serial backplane. Placing a PM8620 or PM8621 Narrowband Switch Element (NSE) between the framer and link layer devices allows up to 20 Gbit/s NxDS0 switches to be constructed.

SBS Telecom Standard Product Data Sheet

Preliminary

In the ingress direction, the SBS connects an incoming SBI stream to a pair of redundant serial SBI336S LVDS links through a DS0 memory switch. The incoming SBI bus can be either a single 77.76 MHz SBI bus (SBI336) or four 19.44 MHz SBI buses (SBI). In TelecomBus mode an incoming 77.76 MHz TelecomBus or four 19.44 MHz TelecomBuses that have the J1 path fixed and all high order pointer justifications converted to tributary pointer justifications can be switched through a VT granular switch to a pair of redundant serial LVDS TelecomBus format links. The incoming data is encoded into an extended set of 8B/10B characters and transferred onto two redundant 777.6 Mbit/s serial LVDS links. SBI or TelecomBus frame boundaries, pointer justification events and master timing controls are marked by 8B/10B control characters. Incoming SPEs may be optionally overwritten with the locally generated X

23

+ X18 + 1 pseudorandom bit sequence (PRBS) pattern for diagnosis of downstream equipment. The PRBS processor is configurable to handle any combination of SPEs and can be inserted independently into either of the redundant LVDS links. A DS0 memory switch provides arbitrary mapping of streams on the incoming SBI bus stream(s) to the working and protect LVDS links. In TelecomBus mode, a VT1.5/VT2 memory switch provides arbitrary mapping of tributaries on the incoming TelecomBus stream(s) to the working and protect LVDS links. Multi-cast is supported.

In the egress direction, the SBS connects two independent 777.6 Mbit/s serial LVDS links to an outgoing SBI Bus. Each link contains a constituent SBI336S stream. Bytes on the links are carried as 8B/10B characters. The SBS decodes the characters into data and control signals for a single 77.76 MHz SBI336 bus or four 19.44 MHz SBI buses. Alternatively the SBS decodes two independent 777.6 Mbit/s TelecomBus formatted serial LVDS links characters into a single 77.76 MHz or quad 19.44 MHz TelecomBuses. A PRBS processor is provided to monitor the decoded payload for the X

23

+ X18 + 1 pattern in each SPE. The PRBS processor is configurable to handle any combination of SPEs in the serial LVDS link. Data on the outgoing SBI bus stream(s) may be sourced from either of the LVDS links.

An In-band signaling link over the serial LVDS links allows this device to be controlled by a companion switching device, a Narrowband Switching Element, PM8620 NSE-20G. This link can be used as communication link between a central processor and the local microprocessor.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 26 Document ID: PMC-2000168, Issue 3

SBS Telecom Standard Product Data Sheet

Preliminary

Three loopbacks are provided on the SBS. The outgoing-to-incoming loopback allows data entering the SBS on the receive interface to be looped back from the output of the OCASM to the input of the ICASE and then returned to the transmit interface. The transmit 8B/10B-to-receive 8B/10B loopback allows data entering on the incoming bus to be looped back from the output of the TW8E and TP8E to the input of the RW8D and RP8D, respectively. Only the data looped back on the active link (working or protect) will make it back to the outgoing bus. The transmit to receive loopback allows data entering on the incoming bus to be looped back from the output of the ICASM to the input of the OCASE and then returned to the outgoing bus.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 27 Document ID: PMC-2000168, Issue 3

SBS Telecom Standard Product Data Sheet

Preliminary

8 Pin Diagram

The SBS is packaged in a 352-pin UBGA package having a body size of 27 mm by 27 mm and a ball pitch of 1 mm.

Figure 8 Pin Diagram

2625242322212019181716151413121110987654321

VSS VSS TC1FP NC NC TDATA[7]ODATA[1

A

VSS DVDDO VSS

B

VSS VSS DVDDO NC NC NC TDATA[5]ODATA[1

C

VSS VSS AVDH DVDDO TJ UST_

D

VSS NC AVDH NC NC

E

RESK RES NC NC IDATA[1][3]IDATA[1][5]NC ITPL[1]

F

VSS NC NC NC IDATA[1][6]IDP[1] IV5[ 1] IPL[1]

G

TNPROT TPPROT NC NC DVDDO IC1FP[1] ITAIS[1]

H

VSS NC NC AVDH NC DVDDI ODATA[2

J

TPWRK TNWRK NC NC NC ODATA[2

K

VSS NC NC NC

L

RPWRK RNWRK ATB0 ATB1 OPL[2] OC1FP[ 2]TDO NC

M

RPPROT RNPROT NC AVDL DVDDO INTB NC VSS

N

AVDL AVDL NC

P

ITPL[4] ITAIS[4] AVDL IV5[4] ODATA[3

R

VSS IPL[4] IC1FP[4] AVDH

T

IDATA[4]

IDATA[4][

[6]

U

V

W

Y

AA

AB

AC

AD

AE

AF

7]

VSS IDATA[4][3]IDATA[4][4]IDATA[4][

ITAIS[2] IDATA[4][0]IDATA[4][2]IDATA[4][

VSS IC1FP[2] ITPL[2] AVDH

WRB RDB DVDDI ALE A[2] A[1] JUST_R

VSS CSB AVDH DVDDO NC A[3] NC IDATA[3][

VSS VSS AVDH DVDDO RSTB

VSS VSS DVDDO RWSEL ODET EC

VSS DVDDO VSS OACTIV

VSS VSS RC1FP

TDATA[0]TDATA[2]TDATA[4

CSU_AV DH

DVDDI IDP[4] NC ODP[3]

5]

1]

E[4]

OC1FP[4 ]

]

TDATA[1]TDATA[3]TDATA[6]DVDDO TPL OACTIV

REQ

JUST_R EQ[4]

OV5[4] NC D[14 ] ODATA[4

T[4]

OTAIS[4] ODP[4] D[15] NC ODAT A[4

OPL[4] NC DVDDI

TTPL TTAIS ODATA[1

][1]

ODP[1]

ODATA[1 ][2]

][0]

OTPL[4] DVDDO NC

ODATA[4 ][5]

ODATA[

ODATA[1

][3]

1][5]

NC

TDP TV5 DVDDI ODATA[1

NC NC OT AIS[1] OTPL[1] NC

ODETEC T[1]

E[1]

VSS VSS OPL[1] R JUST_

][7]

NC OV5[1] OC 1FP[1]RDATA[3]RDATA[6]RV5 O TPL[2] ICMP OD ETEC

][6]

ODATA[1

NC DVDDO RDATA[0]RDATA[5]RPL NC DVDDO N C SYSCL K NC DVDDO NC IDAT A[1][1]NC

][4]

352 UBGA

BOTTOM VIEW

ODATA[4 ][6]

NC ODATA[

][7]

ODATA[4

][4]

][1]

NC D[13] D[10] VSS VSS IDP[2]

ODATA[4 ][3]

IUSER2 DVDDO NC

ODATA[ 4][2]

D[12] D[9] IPL[2] IDATA[2][6]IDATA[2][1]D[7] ITPL[3] IDP[3] D[4] IDATA[3][3]D[1] A[6] DVDDO VSS A[5]

4][0]

NC D[11] NC IV5[2] IDATA[2][7]IDATA[2][3]IDATA[2][0]DVDDI IC1FP[3] IDATA[3][7]IDATA[3][6]IDATA[3][2]D[0] VSS DVDDO VSS

REQ

RDATA[1]RDATA[4]RDATA[7

D[8] ITAIS[3] DVDDO D[5]

IDATA[2][ 4]

IDATA[2][5]IDATA[2][

RDATA[2]NC RDP RTAIS NC DVDDI JUST_R

RTPL OTAIS[2] OCMP

]

T[2]

D[2] A[7] DVDDO NC A[4] DVDDI

IDATA[3][ 4]

NC IV5[3] IPL[3] D[6]

2]

EQ[2]

OACTIV

SREFCL

E[2]

K19

SREFCLKNC DVDDO VSS IDATA[1][

ODATA[2 ][4]

TRSTB TMS TCK VSS

][2]

ODATA[3 ][7]

DVDDO OTPL[3] O PL[3] OACTIV

NC OC1FP[3]OV5[3] NC

IDATA[3][ 1]

D[3] A[8] VSS VSS

IDATA[3][ 5]

NC VSS VSS

VSS DVDDO VSS

0]

IDATA[1][2]IDATA[1][4]IDATA[1][

][2]

ODATA[2 ][6]

ODATA[3 ][0]

ODATA[3 ][5]

A[0]

7]

ODATA[2 ][0]

ODATA[2

][1]

][3]

ODATA[2

][5]

][7]

ODP[2] OV5[2]

ODETEC

TDI

T[3]

ODATA[3

][3]

][1]

ODATA[3

][6]

][4]

E[3]

OTAIS[3]

JUST_R EQ[1]

OUSER2

EQ[3]

0]

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

2625242322212019181716151413121110987654321

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 28 Document ID: PMC-2000168, Issue 3

9 Pin Description

Pin Name Type Pin No. Function

Receive Serial Data Interface (5 Signals)

RPWRK RNWRK

RPPROT RNPROT

Analog LVDS Input

M26 M25

N26 N25

SBS Telecom Standard Product Data Sheet

Preliminary

Receive Working Serial Data. In SBI336 mode, the differential

receive working serial data link (RPWRK/RNWRK) carries the receive 77.76 MHz SBI336 data from an upstream working source, in bit serial format, SBI336S.

In TelecomBus mode, RPWRK/RNWRK carries the receive 77.76 MHz TelecomBus from an upstream working source, in bit serial format.

Data on RPWRK/RNWRK is encoded in an 8B/10B format extended from IEEE Std. 802.3. The 8B/10B character bit ‘a’ is expected first and the bit ‘j’ is expected last.

RPWRK/RNWRK are nominally 777.6 Mbit/s data streams.

Receive Protect Serial Data. In SBI336 mode, the differential receive protect serial data link (RPPROT/RNPROT) carries the receive 77.76 MHz SBI336 data from an upstream protect source, in bit serial format, SBI336S.

In TelecomBus mode, RPPROT/RNPROT carries the receive

77.76 MHz TelecomBus from an upstream protection source, in bit serial format.

Data on RPPROT/RNPROT is encoded in an 8B/10B format extended from IEEE Std. 802.3. The 8B/10B character bit ‘a’ is expected first and the bit ‘j’ is expected last.

RPPROT/RNPROT are nominally 777.6 Mbit/s data streams.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 29 Document ID: PMC-2000168, Issue 3

Pin Name Type Pin No. Function

RC1FP Input AF24

Receive SBI336 Interface (14 Signals)

RDATA[7] RDATA[6] RDATA[5] RDATA[4] RDATA[3] RDATA[2] RDATA[1] RDATA[0]

RDP Input A8

Input B9

C10 D11 B10 C11 A10 B11 D12

Receive Serial Frame Pulse. The receive serial SBI336S frame pulse signal (RC1FP) provides system timing of the receive serial interface. When using the receive parallel interface, this signal indicates the first C1 byte on the bus.

Using the Receive Serial Interface:

When using the receive serial interface, RC1FP is set high once every multiframe (4 frames for SBI without CAS, 48 frames for SBI with CAS, and 4 frames for TelecomBus), or multiple thereof. The RC1FP_DLY[13:0] bits (register 007H) are used to align the C1 frame boundary 8B/10B character on the receive serial interface (RPWRK/RNWRK and RPPROT/RNPROT) with RC1FP.

Using the Receive Parallel Interface:

In SBI mode, this signal also indicates multiframe alignment which occurs every 4 frames, therefore this signal is pulsed every fourth C1 octet to produce a 2KHz multiframe signal. The frame pulse does not need to be repeated every 2KHz as the SBS will flywheel in its absence.

When using the SBI bus in synchronous mode the RC1FP signal can be used to indicate T1 and E1 multiframe alignment by pulsing on 48 SBI frame boundaries. This must be done if CAS is to be switched along with the data.

In TelecomBus mode, this signal may also be pulsed to indicate the J1 byte position and the byte following J1. The J1 byte position must be locked to an offset of either 0 or 522. The byte following J1 is used to indicate multiframe alignment and should only pulse once every 4 frames marking the frame with the V1s.

RC1FP is sampled on the rising edge of SYSCLK.

Receive Data (RDATA[7:0]). This is the receive SBI336 data bus when configured for SBI336 byte-wide interface instead of the Serial SBI336S interface. When in TelecomBus mode this is the data bus for 77.76 MHz TelecomBus. The receive data bus is a time division multiplexed bus which transports tributaries by assigning them to fixed octets within the SBI or TelecomBus structure.

In SBI336 mode, multiple devices can drive this bus at uniquely assigned tributary columns within the SBI336 bus structure.

RDATA[7:0] is sampled on the rising edge of SYSCLK.

RDATA[7:0] have integral pull-up resistors.

Receive Data Parity (RDP). This is the receive data bus parity when configured for the Receive byte-wide interface. This signal carries the even or odd parity for the receive bus signals. In SBI336 mode, the parity calculation encompasses the RDATA[7:0], RPL and RV5 signals. In TelecomBus mode, the parity calculation encompasses the RDATA[7:0] and optionally the RC1FP and RPL signals.

Multiple devices can drive this signal at uniquely assigned tributary columns within the fixed structure. This parity signal is intended to detect multiple sources in the column assignment.

RDP is sampled on the rising edge of SYSCLK.

RDP has an integral pull-up resistor.

SBS Telecom Standard Product Data Sheet

Preliminary

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 30 Document ID: PMC-2000168, Issue 3

PMC PM8610-BIAP Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Table of Contents

List of Registers

List of Figures

List of Tables