PMC PM8351 Datasheet
PMC-Sierra,Inc.
8-Channel 1.0-1.25 Gbps Transceiver
PM8351 OctalPHY™
FEATURES
• Eight independent 1.0-1.25 Gbit/s
transceivers
• Ultra low power operation: 1.25 Watts
typical
• Integrated serializ er/dese rializ er, cloc k
synthesis, clock recovery , and 8B/10B
encode/decode logic
• Physical Coding Sublayer (PCS) logic
for Gigabit Ethernet
• Optional receive FIFO which
synchronizes incoming data to local
clock domain
• Dual Data Rate (DDR) parallel
interface with cloc k forwarding to halve
ASIC terminal count and simplify
timing
• Extensive control of loopback, BIST,
and operating modes via 802.3
compliant MDC/MDIO serial interface
• Built-in packet gener ator/ ch eck er
• “Trunking” feature to de-skew and
align received para llel data across
eight channels
• IEEE 1149.1 JTAG testing support
• IEEE 802.3z Gigabit Ethernet and
ANSI X3T11 FibreChannel support
• High speed outputs which feature
programmable output cur rent to
directly drive dual-terminated line
• 2.5 V, 0.25 µ CMOS technology w ith
3.3V tolerant I/O
• Direct interface to optical modules,
coax, or serial backplanes
• Small footprint 19x19 mm, 289-pin
PBGA
APPLICATIONS
• High speed serial backplanes
• Gigabit Ethernet links
• FibreChannel links
• Intra-system interconnect
• ASIC to PMD link
GENERAL DESCRIPTION
The OctalPHYTM is an octal PHYsical
layer transceiver ideal for systems
requiring large numbers of po int-to-point
gigabit links. It provides eight individual
serial channels capable of operation at
up to 1.25 Gbps, which may be grouped
together to form a single 12.5 Gbps
bidirectional link.
The OctalPHY includes 8B/10B block
coding logic (compliant with 802.3z
Gigabit Ethernet and FibreChannel
requirements) which produces run length
limited data streams for serial transmission.
A receive FIFO optionally aligns all
incoming parallel data to the local clock
domain, adding or removing IDLE
sequences as require d. This simp lifies
implementation of the upstream ASIC by
removing the requirement to deal with
multiple clock domains.
When trunking is enable d, t he OctalPH Y
can remove cable skew differences
equivalent to several meters, presenting
8-byte data vectors at the receive
interface exactly as they were transmitted.
EXAMPLE ARCHITECTURE
The first figure on the next page shows
the OctalPHY in a switch application.
This implementat ion uses eight ch annels
of 1.25 Gbaud per linecard, requiring
only 32 signal pins per linecard and 128
for the switch card, providing up to
32 Gbps total payload capacity to the
switch fabric.
The 5-bit DDR interface of the OctalPHY
saves pins on the switch device. An
additional OctalPH Y operated in trunkin g
mode creates a cost effective 10 Gbps
uplink, capable of directly driving copper
or various optical transports.
The dotted lines in the figure depict the
system clock domains. Note that even
though the recovered clock from any or
all serial links may be asynchronous to
the local clock, the OctalPHY bridges
these domains so that the switch fabric
and linecards ma y b e designed in only a
single clock domain .
The OctalPHY creates a highly
integrated and cost effective physical
layer solution for Gigabit Ethernet or
FibreChannel external interfaces.
BLOCK DIAGRAM
Transmit Channel A (1 of 8)
Parallel
Data In
TX Byte
Clock
Parallel
Data Out
RX Byte
Clock
REFCLK
PMC-2000672 (R3) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE © Copyright PMC-Sierra, Inc. 2001
FIFO
FIFO
Clock Synthesizer
PLL LOCK
PCS
Receive Channel A (1 of 8)
PCS
10B/8B
Decoder
8B/10B
Encoder
10
10
Deserialize &
Byte Align
MDC/MDIO
Serial
Management Static Controls
Serializer
Clock
Recovery
Common Control Logic
Serial
Transmit
Data
Serial
Receive
Data
8-Channel 1.0-1.25 Gbps Transceiver
32 GBPS SWITCH APPLICATION
Switch Card
PM8351
PM8351
Serial Point-to-point
Backplane: 8Gbps
Per line card
PM8351
PM8351
Switch clock domain
PM8351 OctalPHY™
Line Card
PM8351
PM8351
PM8351
PM8351
Line card clock domain
MAC/Packet processor
MAC/Packet processor
MAC/Packet processor
MAC/Packet processor
RX data clock domains
PM8351
Uplink clock domain
PM8351
EYE DIAGRAM
Produced by the OctalPHY when driving a 50 Ohm cable, terminated at both near and far ends.
JITTER
Jitter histogram of the OctalPHY showing 6.8 picoseconds, 1 σ jitter with all channels operating.
Gigabit Ethernet
or Fibre Channel
Interfaces
10 Gbps
(trunked)
uplink
Head Office:
PMC-Sierra, Inc.
8555 Baxter Place
Burnaby, B.C. V5A 4V7
Canada
Tel: 604.415.6000
Fax: 604.415.6200
100.0 ps/div
To order documentation,
send email to:
document@pmc-sierra.com
or contact the head office,
Attn: Document Coordinator
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
All product documentation is available
on our web site at:
http://www.pmc-sierra.com
For corpo rate information,
send email to:
info@pmc-sierra.com
© Copyrigh t PMC-Sierra,
Inc. 2001. All rights reserved.
SATURN and S/UNI are
registered trademarks of
PMC-Sierra, Inc. POS-PHY
Level 3 is a trademark of
PMC-Sierra, Inc.
Loading...