PMC PM8315-PI Datasheet

STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
PM8315
TEMUX
INTEGRATED VT/TU MAPPER AND M13
MULTIPLEXER
DATASHEET
PROPRIETARY AND CONFIDENTIAL
ISSUE 7: MAY 2001
PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX

CONTENTS

1 FEATURES .............................................................................................. 1
2 APPLICATIONS ..................................................................................... 15
3 REFERENCES....................................................................................... 16
4 APPLICATION EXAMPLES ................................................................... 20
5 BLOCK DIAGRAM ................................................................................. 21
5.1 TOP LEVEL BLOCK DIAGRAM .................................................. 21
5.2 M13 MULTIPLEXER MODE BLOCK DIAGRAM ......................... 23
5.3 VT/TU MAPPER ONLY MODE BLOCK DIAGRAM..................... 23
5.4 DS3 FRAMER ONLY BLOCK DIAGRAM.................................... 24
6 DESCRIPTION ...................................................................................... 26
7 PIN DIAGRAM ....................................................................................... 31
8 PIN DESCRIPTION................................................................................ 32
9 FUNCTIONAL DESCRIPTION............................................................... 70
9.1 T1 FRAMER (T1-FRMR)............................................................. 70
9.2 E1 FRAMER (E1-FRMR)............................................................. 70
1.3 PERFORMANCE MONITOR COUNTERS (T1/E1-PMON)......... 77
1.4 BIT ORIENTED CODE DETECTOR (RBOC).............................. 78
1.5 HDLC RECEIVER (RDLC) .......................................................... 78
1.6 T1 ALARM INTEGRATOR (ALMI)............................................... 79
1.7 ELASTIC STORE (ELST)............................................................ 80
1.8 SIGNALING ELASTIC STORES (RX-SIG-ELST AND
TX_SIG-ELST) ............................................................................ 80
PROPRIETARY AND CONFIDENTIAL i
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
1.9 SIGNALING EXTRACTOR (SIGX).............................................. 81
1.10 RECEIVE PER-CHANNEL SERIAL CONTROLLER (RPSC)...... 82
1.11 BASIC TRANSMITTER (XBAS) .................................................. 82
1.12 E1 TRANSMITTER (E1-TRAN)................................................... 83
1.13 TRANSMIT PER-CHANNEL SERIAL CONTROLLER (TPSC).... 83
1.14 SIGNALING ALIGNER (SIGA) .................................................... 83
1.15 BIT ORIENTED CODE GENERATOR (XBOC)........................... 84
1.16 HDLC TRANSMITTERS (TDPR)................................................. 84
1.17 T1 AUTOMATIC PERFORMANCE REPORT GENERATION
(APRM)........................................................................................ 85
1.18 RECEIVE AND TRANSMIT DIGITAL JITTER ATTENUATOR
(RJAT, TJAT) ............................................................................... 86
1.19 TIMING OPTIONS (TOPS) ......................................................... 92
1.20 PSEUDO RANDOM BINARY SEQUENCE GENERATION
AND DETECTION (PRBS).......................................................... 93
1.21 PSEUDO RANDOM PATTERN GENERATION AND
DETECTION (PRGD).................................................................. 93
1.22 DS3 FRAMER (DS3-FRMR) ....................................................... 93
1.23 PERFORMANCE MONITOR ACCUMULATOR (DS3-PMON) .... 96
1.24 DS3 TRANSMITTER (DS3-TRAN).............................................. 96
1.25 M23 MULTIPLEXER (MX23)....................................................... 97
1.26 DS2 FRAMER (DS2-FRMR) ....................................................... 98
1.27 M12 MULTIPLEXER (MX12)..................................................... 100
1.28 TRIBUTARY PAYLOAD PROCESSOR (VTPP) ........................ 101
1.29 RECEIVE TRIBUTARY PATH OVERHEAD PROCESSOR
(RTOP)...................................................................................... 104
PROPRIETARY AND CONFIDENTIAL ii
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
1.30 RECEIVE TRIBUTARY DEMAPPER (RTDM)........................... 106
1.31 PARALLEL IN TO SERIAL OUT CONVERTER (PISO)............. 108
1.32 DS3 MAPPER DROP SIDE (D3MD)..........................................110
1.33 TRANSMIT TRIBUTARY PATH OVERHEAD PROCESSOR
(TTOP) .......................................................................................113
1.34 TRANSMIT REMOTE ALARM PROCESSOR (TRAP)...............114
1.35 TRANSMIT TRIBUTARY MAPPER (TTMP)...............................115
1.36 SERIAL IN TO PARALLEL OUT CONVERTER (SIPO)..............116
1.37 DS3 MAPPER ADD SIDE (D3MA) .............................................116
1.38 EGRESS SYSTEM INTERFACE (ESIF) ....................................118
1.39 INGRESS SYSTEM INTERFACE (ISIF) ................................... 124
1.40 EXTRACT SCALEABLE BANDWIDTH INTERCONNECT
(EXSBI) ..................................................................................... 129
1.41 INSERT SCALEABLE BANDWIDTH INTERCONNECT
(INSBI)....................................................................................... 130
1.42 SCALEABLE BANDWIDTH INTERCONNECT PISO
(SBIPISO).................................................................................. 130
1.43 SCALEABLE BANDWIDTH INTERCONNECT SIPO
(SBISIPO).................................................................................. 131
1.44 JTAG TEST ACCESS PORT..................................................... 131
1.45 MICROPROCESSOR INTERFACE .......................................... 131
10 NORMAL MODE REGISTER DESCRIPTION ..................................... 162
11 TEST FEATURES DESCRIPTION ...................................................... 163
11.1 JTAG TEST PORT .................................................................... 172
12 OPERATION ........................................................................................ 185
12.1 DS3 FRAME FORMAT.............................................................. 185
PROPRIETARY AND CONFIDENTIAL iii
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
12.2 SERVICING INTERRUPTS....................................................... 187
12.3 USING THE PERFORMANCE MONITORING FEATURES ...... 187
12.4 USING THE INTERNAL FDL TRANSMITTER .......................... 192
12.5 USING THE INTERNAL DATA LINK RECEIVER ...................... 196
12.6 T1 AUTOMATIC PERFORMANCE REPORT FORMAT ............ 200
12.7 USING THE PER-CHANNEL SERIAL CONTROLLERS........... 202
12.8 T1/E1 FRAMER LOOPBACK MODES...................................... 204
12.9 DS3 LOOPBACK MODES ........................................................ 207
12.10 TELECOM BUS MAPPER/DEMAPPER LOOPBACK MODES. 210
12.11 SBI BUS DATA FORMATS .........................................................211
12.12 H-MVIP DATA FORMAT ............................................................ 230
12.13 SERIAL CLOCK AND DATA FORMAT ...................................... 236
12.14 PRGD PATTERN GENERATION .............................................. 237
12.15 JTAG SUPPORT ....................................................................... 241
13 FUNCTIONAL TIMING......................................................................... 249
13.1 DS3 LINE SIDE INTERFACE TIMING ...................................... 249
13.2 DS3 SYSTEM SIDE INTERFACE TIMING................................ 251
13.3 TELECOM DROP BUS INTERFACE TIMING........................... 253
13.4 TELECOM ADD BUS INTERFACE TIMING.............................. 256
13.5 SONET/SDH SERIAL ALARM PORT TIMING .......................... 257
13.6 SBI DROP BUS INTERFACE TIMING ...................................... 259
13.7 SBI ADD BUS INTERFACE TIMING ......................................... 260
13.8 EGRESS H-MVIP LINK TIMING ............................................... 260
13.9 INGRESS H-MVIP LINK TIMING .............................................. 261
PROPRIETARY AND CONFIDENTIAL iv
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
13.10 EGRESS SERIAL CLOCK AND DATA INTERFACE TIMING.... 262
13.11 INGRESS SERIAL CLOCK AND DATA INTERFACE TIMING .. 267
14 ABSOLUTE MAXIMUM RATINGS....................................................... 271
15 D.C. CHARACTERISTICS ................................................................... 272
16 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS..... 275
17 TEMUX TIMING CHARACTERISTICS ................................................ 279
18 ORDERING AND THERMAL INFORMATION.......................................311
19 MECHANICAL INFORMATION ............................................................ 312

LIST OF FIGURES

FIGURE 1 - CHANNELIZED DS3 CIRCUIT EMULATION APPLICATION.... 20
FIGURE 2 - HIGH DENSITY FRAME RELAY APPLICATION....................... 20
FIGURE 3 - TEMUX BLOCK DIAGRAM....................................................... 22
FIGURE 4 - M13 MULTIPLEXER BLOCK DIAGRAM................................... 23
FIGURE 5 - VT/TU MAPPER BLOCK DIAGRAM......................................... 24
FIGURE 6 - DS3 FRAMER ONLY MODE BLOCK DIAGRAM...................... 25
FIGURE 7 - PIN DIAGRAM .......................................................................... 31
FIGURE 8 - CRC MULTIFRAME ALIGNMENT ALGORITHM....................... 74
FIGURE 9 - DJAT JITTER TOLERANCE T1 MODES .................................. 88
FIGURE 10 - DJAT JITTER TOLERANCE E1 MODES.................................. 89
FIGURE 11 - DJAT MINIMUM JITTER TOLERANCE VS. XCLK ACCURACY T1
MODES ....................................................................................... 90
FIGURE 12 - DJAT MINIMUM JITTER TOLERANCE VS. XCLK ACCURACY E1
MODES ....................................................................................... 90
PROPRIETARY AND CONFIDENTIAL v
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
FIGURE 13 - DJAT JITTER TRANSFER T1 MODES..................................... 91
FIGURE 14 - DJAT JITTER TRANSFER E1 MODES..................................... 92
FIGURE 17 - CLOCK MASTER: NXCHANNEL.............................................119
FIGURE 18 - CLOCK MASTER: CLEAR CHANNEL.....................................119
FIGURE 19 - CLOCK SLAVE: EFP ENABLED............................................. 120
FIGURE 20 - CLOCK SLAVE: EXTERNAL SIGNALING .............................. 120
FIGURE 21 - CLOCK SLAVE: CLEAR CHANNEL ....................................... 121
FIGURE 22 - CLOCK SLAVE: H-MVIP......................................................... 121
FIGURE 23 - CLOCK MASTER: SERIAL DATA AND H-MVIP CCS ............. 123
FIGURE 24 - CLOCK MASTER: FULL T1/E1............................................... 124
FIGURE 25 - CLOCK MASTER: NXCHANNEL............................................ 125
FIGURE 26 - CLOCK MASTER: CLEAR CHANNEL.................................... 125
FIGURE 28 - CLOCK SLAVE: EXTERNAL SIGNALING .............................. 126
FIGURE 29 - CLOCK SLAVE: H-MVIP......................................................... 126
FIGURE 30 - CLOCK SLAVE: SERIAL DATA AND H-MVIP CCS................. 128
FIGURE 31 - DS3 FRAME STRUCTURE..................................................... 185
FIGURE 32 - FER COUNT VS. BER (E1 MODE)......................................... 189
FIGURE 33 - CRCE COUNT VS. BER (E1 MODE)...................................... 190
FIGURE 34 - FER COUNT VS. BER (T1 ESF MODE)................................. 190
FIGURE 35 - CRCE COUNT VS. BER (T1 ESF MODE).............................. 191
FIGURE 36 - CRCE COUNT VS. BER (T1 SF MODE) ................................ 192
FIGURE 37 - TYPICAL DATA FRAME.......................................................... 199
FIGURE 38 - EXAMPLE MULTI-PACKET OPERATIONAL SEQUENCE ..... 199
FIGURE 39 - T1/E1 LINE LOOPBACK......................................................... 205
PROPRIETARY AND CONFIDENTIAL vi
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
FIGURE 40 - T1/E1 DIAGNOSTIC DIGITAL LOOPBACK............................ 206
FIGURE 41 - PER-CHANNEL LOOPBACK................................................. 207
FIGURE 42 - DS3 DIAGNOSTIC LOOPBACK DIAGRAM ........................... 208
FIGURE 43 - DS3 LINE LOOPBACK DIAGRAM.......................................... 209
FIGURE 44 - DS2 LOOPBACK DIAGRAM................................................... 209
FIGURE 45 - TELECOM DIAGNOSTIC LOOPBACK DIAGRAM ................. 210
FIGURE 46 - TELECOM LINE LOOPBACK DIAGRAM ................................211
FIGURE 47 - PRGD PATTERN GENERATOR ............................................. 237
FIGURE 48 - BOUNDARY SCAN ARCHITECTURE .................................... 241
FIGURE 49 - TAP CONTROLLER FINITE STATE MACHINE ...................... 243
FIGURE 50 - INPUT OBSERVATION CELL (IN_CELL) ............................... 246
FIGURE 51 - OUTPUT CELL (OUT_CELL).................................................. 247
FIGURE 52 - BIDIRECTIONAL CELL (IO_CELL)......................................... 247
FIGURE 53 - LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL
CELLS....................................................................................... 248
FIGURE 54 - RECEIVE BIPOLAR DS3 STREAM........................................ 249
FIGURE 55 - RECEIVE UNIPOLAR DS3 STREAM ..................................... 249
FIGURE 56 - TRANSMIT BIPOLAR DS3 STREAM ..................................... 250
FIGURE 57 - TRANSMIT UNIPOLAR DS3 STREAM................................... 250
FIGURE 58 - FRAMER MODE DS3 TRANSMIT INPUT STREAM............... 251
FIGURE 59 - FRAMER MODE DS3 TRANSMIT INPUT STREAM WITH
TGAPCLK ................................................................................. 251
FIGURE 60 - FRAMER MODE DS3 RECEIVE OUTPUT STREAM............. 252
FIGURE 61 - FRAMER MODE DS3 RECEIVE OUTPUT STREAM WITH
RGAPCLK ................................................................................. 252
PROPRIETARY AND CONFIDENTIAL vii
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
FIGURE 62 - TELECOM DROP BUS TIMING - STS-1 SPES / AU3 VCS.... 253
FIGURE 63 - TELECOM DROP BUS TIMING - LOCKED STS-1
SPES / AU3 VCS....................................................................... 254
FIGURE 64 - TELECOM DROP BUS TIMING - AU4 VC.............................. 255
FIGURE 65 - OUTPUT BUS TIMING - LOCKED STS-1 SPES / AU3 VCS.. 256
FIGURE 66 - OUTPUT BUS TIMING - LOCKED AU4 VC CASE ................. 257
FIGURE 67 - REMOTE SERIAL ALARM PORT TIMING.............................. 258
FIGURE 68 - SBI DROP BUS T1/E1 FUNCTIONAL TIMING ....................... 259
FIGURE 69 - SBI DROP BUS DS3 FUNCTIONAL TIMING ......................... 259
FIGURE 70 - SBI ADD BUS JUSTIFICATION REQUEST FUNCTIONAL
TIMING...................................................................................... 260
FIGURE 71 - EGRESS 8.192 MBPS H-MVIP LINK TIMING ........................ 261
FIGURE 72 - INGRESS 8.192 MBPS H-MVIP LINK TIMING....................... 261
FIGURE 73 - T1 EGRESS INTERFACE CLOCK MASTER: NXCHANNEL
MODE........................................................................................ 262
FIGURE 74 - E1 EGRESS INTERFACE CLOCK MASTER : NXCHANNEL
MODE........................................................................................ 262
FIGURE 75 - T1 AND E1 EGRESS INTERFACE CLOCK MASTER: CLEAR
CHANNEL MODE...................................................................... 263
FIGURE 76 - T1 EGRESS INTERFACE CLOCK SLAVE: EFP ENABLED
MODE........................................................................................ 263
FIGURE 77 - E1 EGRESS INTERFACE CLOCK SLAVE : EFP ENABLED
MODE........................................................................................ 263
FIGURE 78 - T1 EGRESS INTERFACE CLOCK SLAVE: EXTERNAL
SIGNALING MODE ................................................................... 264
FIGURE 79 - E1 EGRESS INTERFACE CLOCK SLAVE : EXTERNAL
SIGNALING MODE ................................................................... 264
PROPRIETARY AND CONFIDENTIAL viii
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
FIGURE 80 - T1 EGRESS INTERFACE 2.048 MHZ CLOCK SLAVE: EFP
ENABLED MODE...................................................................... 265
FIGURE 81 - T1 EGRESS INTERFACE 2.048 MHZ CLOCK SLAVE:
EXTERNAL SIGNALING MODE ............................................... 266
FIGURE 82 - T1 AND E1 EGRESS INTERFACE CLOCK SLAVE: CLEAR
CHANNEL MODE...................................................................... 266
FIGURE 83 - T1 INGRESS INTERFACE CLOCK MASTER : FULL
CHANNEL MODE...................................................................... 267
FIGURE 84 - E1 INGRESS INTERFACE CLOCK MASTER : FULL
CHANNEL MODE...................................................................... 267
FIGURE 85 - T1 INGRESS INTERFACE CLOCK MASTER: NXCHANNEL
MODE........................................................................................ 268
FIGURE 86 - E1 INGRESS INTERFACE CLOCK MASTER: NXCHANNEL
MODE........................................................................................ 268
FIGURE 87 - T1 AND E1 INGRESS INTERFACE CLOCK MASTER: CLEAR
CHANNEL MODE...................................................................... 268
FIGURE 88 - T1 INGRESS INTERFACE CLOCK SLAVE: EXTERNAL
SIGNALING MODE ................................................................... 269
FIGURE 89 - E1 INGRESS INTERFACE CLOCK SLAVE: EXTERNAL
SIGNALING MODE ................................................................... 269
FIGURE 90 - T1 INGRESS INTERFACE 2.048 MHZ CLOCK SLAVE:
EXTERNAL SIGNALING MODE ............................................... 270
FIGURE 91 - DS3 TRANSMIT INTERFACE TIMING ................................... 281
FIGURE 92 - DS3 RECEIVE INTERFACE TIMING...................................... 284
FIGURE 93 - LINE SIDE TELECOM BUS INPUTTIMING............................ 286
FIGURE 94 - TELECOM BUS OUTPUT TIMING ......................................... 287
FIGURE 95 - TELECOM BUS TRISTATE OUTPUT TIMING ....................... 287
FIGURE 96 - SBI ADD BUS TIMING ............................................................ 289
FIGURE 97 - SBI DROP BUS TIMING ......................................................... 291
PROPRIETARY AND CONFIDENTIAL ix
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
FIGURE 98 - SBI DROP BUS COLLISION AVOIDANCE TIMING ............... 291
FIGURE 99 - H-MVIP EGRESS DATA & FRAME PULSE TIMING............... 293
FIGURE 100 - H-MVIP INGRESS DATA TIMING ........................................... 294
FIGURE 101 - XCLK INPUT TIMING.............................................................. 295
FIGURE 102 - EGRESS INTERFACE TIMING - CLOCK SLAVE: EFP
ENABLED MODE...................................................................... 297
FIGURE 103 - EGRESS INTERFACE TIMING - CLOCK SLAVE: EXTERNAL
SIGNALING MODE ................................................................... 298
FIGURE 104 - EGRESS INTERFACE INPUT TIMING - CLOCK MASTER :
NXCHANNEL MODE................................................................. 299
FIGURE 105 - EGRESS INTERFACE INPUT TIMING - CLOCK MASTER :
CLEAR CHANNEL MODE......................................................... 300
FIGURE 106 - EGRESS INTERFACE INPUT TIMING - CLOCK MASTER :
SERIAL DATA AND HMVIP CCS MODE................................... 301
FIGURE 107 - EGRESS INTERFACE INPUT TIMING - CLOCK SLAVE : CLEAR
CHANNEL MODE...................................................................... 302
FIGURE 108 - INGRESS INTERFACE TIMING - CLOCK SLAVE MODES ... 304
FIGURE 109 - INGRESS INTERFACE TIMING - CLOCK MASTER MODES 305
FIGURE 110 - TRANSMIT LINE INTERFACE TIMING .................................. 306
FIGURE 111 - REMOTE SERIAL ALARM PORT TIMING.............................. 308
FIGURE 112 - JTAG PORT INTERFACE TIMING.......................................... 310
FIGURE 113 - 324 PIN PBGA 23X23MM BODY............................................ 312

LIST OF TABLES

TABLE 1 - E1-FRMR FRAMING STATES .................................................. 75
TABLE 2 - PATH SIGNAL LABEL MISMATCH STATE ............................. 105
PROPRIETARY AND CONFIDENTIAL x
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
TABLE 3 - ASYNCHRONOUS T1 TRIBUTARY MAPPING ...................... 106
TABLE 4 - ASYNCHRONOUS E1 TRIBUTARY MAPPING ...................... 107
TABLE 5 - DESYNCHRONIZER CLOCK GENERATION ALGORITHM... 109
TABLE 6 - ASYNCHRONOUS DS3 MAPPING TO STS-1 (STM-0/AU3) ..110
TABLE 7 - DS3 AIS FORMAT. ................................................................... 111
TABLE 8 - DS3 DESYNCHRONIZER CLOCK GAPPING ALGORITHM...113
TABLE 9 - DS3 SYNCHRONIZER BIT STUFFING ALGORITHM. ............118
TABLE 10 - REGISTER MEMORY MAP .................................................... 132
TABLE 11 - INSTRUCTION REGISTER .................................................... 172
TABLE 12 - IDENTIFICATION REGISTER................................................. 173
TABLE 13 - BOUNDARY SCAN CHAIN..................................................... 173
TABLE 14 - PMON COUNTER SATURATION LIMITS (E1 MODE) ........... 188
TABLE 15 - PMON COUNTER SATURATION LIMITS (T1 MODE) ........... 188
TABLE 16 - PERFORMANCE REPORT MESSAGE STRUCTURE AND
CONTENTS............................................................................... 200
TABLE 17 - PERFORMANCE REPORT MESSAGE STRUCTURE
NOTES...................................................................................... 201
TABLE 18 - PERFORMANCE REPORT MESSAGE CONTENTS............. 202
TABLE 19 - STRUCTURE FOR CARRYING MULTIPLEXED LINKS......... 213
TABLE 20 - T1/TVT1.5 TRIBUTARY COLUMN NUMBERING ................... 213
TABLE 21 - E1/TVT2 TRIBUTARY COLUMN NUMBERING...................... 214
TABLE 22 - SBI T1/E1 LINK RATE INFORMATION................................... 217
TABLE 23 - SBI T1/E1 CLOCK RATE ENCODING.................................... 217
TABLE 24 - DS3 LINK RATE INFORMATION ............................................ 218
PROPRIETARY AND CONFIDENTIAL xi
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
TABLE 25 - DS3 CLOCK RATE ENCODING ............................................. 218
TABLE 26 - T1 FRAMING FORMAT........................................................... 219
TABLE 27 - T1 CHANNEL ASSOCIATED SIGNALING BITS..................... 221
TABLE 28 - E1 FRAMING FORMAT .......................................................... 222
TABLE 29 - E1 CHANNEL ASSOCIATED SIGNALING BITS..................... 224
TABLE 30 - DS3 FRAMING FORMAT........................................................ 225
TABLE 31 - DS3 BLOCK FORMAT ............................................................ 225
TABLE 32 - DS3 MULTI-FRAME STUFFING FORMAT ............................. 226
TABLE 33 - TRANSPARENT VT1.5/TU11 FORMAT.................................. 227
TABLE 34 - TRANSPARENT VT2/TU12 FORMAT..................................... 229
TABLE 35 - DATA AND CAS T1 H-MVIP FORMAT .................................... 230
TABLE 36 - DATA AND CAS E1 H-MVIP FORMAT WITH SONET/SDH
E1 MAPPING ............................................................................ 231
TABLE 37 - DATA AND CAS E1 H-MVIP FORMAT IN G.747 MODE ......... 231
TABLE 38 - CCS T1 H-MVIP FORMAT ...................................................... 232
TABLE 39 - CCS E1 H-MVIP FORMAT WITH SONET/SDH E1
MAPPING.................................................................................. 233
TABLE 40 - CCS E1 H-MVIP FORMAT IN G.747 MODE ........................... 235
TABLE 41 - PSEUDO RANDOM PATTERN GENERATION (PS BIT = 0).. 239
TABLE 42 - REPETITIVE PATTERN GENERATION (PS BIT = 1)............. 240
TABLE 43 - ABSOLUTE MAXIMUM RATINGS ......................................... 271
TABLE 44 - D.C. CHARACTERISTICS ...................................................... 272
TABLE 45 - MICROPROCESSOR INTERFACE READ ACCESS.............. 275
TABLE 46 - MICROPROCESSOR INTERFACE WRITE ACCESS ............ 277
PROPRIETARY AND CONFIDENTIAL xii
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
TABLE 47 - RTSB TIMING ......................................................................... 279
TABLE 48 - DS3 TRANSMIT INTERFACE TIMING ................................... 279
TABLE 49 - DS3 RECEIVE INTERFACE TIMING...................................... 283
TABLE 50 - LINE SIDE TELECOM BUS INPUT TIMING (FIGURE 96) ..... 285
TABLE 51 - TELECOM BUS OUTPUT TIMING (FIGURE 97 TO
FIGURE 98)............................................................................... 286
TABLE 52 - SBI ADD BUS TIMING (FIGURE 96) ...................................... 288
TABLE 53 - SBI DROP BUS TIMING (FIGURE 97 TO FIGURE 98).......... 289
TABLE 54 - H-MVIP EGRESS TIMING (FIGURE 99) ................................ 292
TABLE 55 - H-MVIP INGRESS TIMING (FIGURE 100) ............................. 293
TABLE 56 - XCLK INPUT (FIGURE 101) ................................................... 295
TABLE 57 - EGRESS INTERFACE TIMING - CLOCK SLAVE: EFP
ENABLED MODE (FIGURE 102).............................................. 296
TABLE 58 - EGRESS INTERFACE TIMING - CLOCK SLAVE: EXTERNAL
SIGNALING (FIGURE 103)....................................................... 297
TABLE 59 - EGRESS INTERFACE INPUT TIMING - CLOCK MASTER :
NXCHANNEL MODE (FIGURE 104)......................................... 299
TABLE 60 - EGRESS INTERFACE INPUT TIMING - CLOCK MASTER :
CLEAR CHANNEL MODE (FIGURE 104)................................. 300
TABLE 61 - EGRESS INTERFACE INPUT TIMING - CLOCK MASTER :
SERIAL DATA AND HMVIP CCS MODE (FIGURE 104) ........... 301
TABLE 62 - EGRESS INTERFACE INPUT TIMING - CLOCK SLAVE : CLEAR
CHANNEL MODE (FIGURE 104).............................................. 302
TABLE 63 - INGRESS INTERFACE TIMING - CLOCK SLAVE MODES
(FIGURE 108) ........................................................................... 303
TABLE 64 - INGRESS INTERFACE TIMING - CLOCK MASTER MODES
(FIGURE 109) ........................................................................... 305
TABLE 65 - TRANSMIT LINE INTERFACE TIMING (FIGURE 110)........... 306
PROPRIETARY AND CONFIDENTIAL xiii
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
TABLE 66 - REMOTE SERIAL ALARM PORT TIMING.............................. 307
TABLE 67 - JTAG PORT INTERFACE ....................................................... 309
TABLE 68 - ORDERING AND THERMAL INFORMATION..........................311
TABLE 69 - THERMAL INFORMATION – THETA JA VS. AIRFLOW ..........311
PROPRIETARY AND CONFIDENTIAL xiv
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
1 FEATURES
Integrates 28 T1 framers, 21 E1 framers, a SONET/SDH VT1.5/VT2/TU11/TU12 bit asynchronous mapper, a full featured M13 multiplexer with DS3 framer, and a SONET/SDH DS3 mapper in a single monolithic device for terminating DS3 multiplexed T1 streams, SONET/SDH mapped T1 streams or SONET/SDH mapped E1 streams.
Seven T1 modes of operation:
Up to 28 T1 streams mapped as bit asynchronous VT1.5 virtual tributaries
into a STS-1 SPE or TU-11 tributary units into a STM-1/VC3 or TU-11 tributary units into a TUG3 in a STM-1/VC4.
Single STS-1, AU3 or TUG3 Bit Asynchronous VT1.5 or TU-11 Mapper
with ingress or egress per tributary link monitoring.
Up to 28 T1 streams M13 multiplexed into a serial DS3.
Up to 28 T1 streams M13 multiplexed into a DS3, the DS3 is
asynchronously mapped into a STS-1 SPE.
DS3 M13 Multiplexer with ingress or egress per link monitoring.
Up to 28 DS3 multiplexed T1 streams are mapped as bit asynchronous
VT1.5 virtual tributaries or TU-11 tributary units, providing a transmultiplexing (“transmux”) function between DS3 and SONET/SDH.
Up to 21 T1 streams mapped as bit asynchronous TU-12 tributary units
into a STM-1/VC3 or TUG3 from a STM-1/VC4.
Three E1 modes of operation:
Up to 21 E1 streams mapped as bit asynchronous VT2 virtual tributaries
into a STS-1 SPE or TU-12 tributary units into a STM-1/VC3 or TUG3 from a STM-1/VC4.
Single STS-1, AU3 or TUG3 Bit Asynchronous VT2 or TU-12 Mapper with
ingress or egress per tributary link monitoring.
Up to 21 E1 streams multiplexed into a DS3 following the ITU-T G.747
recommendation. This E1 mode of operation is restricted to using the serial clock and data or HMVIP system interfaces.
PROPRIETARY AND CONFIDENTIAL 1
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
Up to 28 VT1.5/TU11 or 21 VT2/TU12 tributaries can be passed between the line SONET/SDH bus and the SBI bus as transparent virtual tributaries with pointer processing.
When adding and dropping T1 or E1 tributaries the mapper and demapper blocks allow for up to 28 VT1.5/TU11 or 21 VT2/TU12 tributaries to be processed from any tributary location within the full STS-3/STM-1. On the telecom DROP bus side this requires that the STS-3/STM-1 be in locked mode such that the J1 bytes immediately follow the C1 bytes.
Supports transfer of PCM data to/from 1.544MHz and 2.048MHz serial interface system-side devices. Also supports a fractional T1 or E1 system interface with independent ingress/egress Nx64Kb/s rates. Supports a 2.048 MHz system-side interface for T1 mode without external clock gapping.
Supports 8Mb/s H-MVIP on the system interface for all T1 or E1 links, a separate 8Mb/s H-MVIP system interface for all T1 or E1 CAS channels and a separate 8Mb/s H-MVIP system interface for all T1 or E1 CCS and V5.1/V5.2 channels.
Supports a byte serial Scaleable Bandwidth Interconnect (SBI) bus interface for high density system side device interconnection of up to 84 T1 streams, 63 E1 streams or 3 DS3 streams. This interface also supports transparent virtual tributaries when used with the SONET/SDH mapper.
Provides jitter attenuation in the T1 or E1 receive and transmit directions.
Provides two independent de-jittered T1 or E1 recovered clocks for system
timing and redundancy.
Provides per-DS0 line loopback and per link diagnostic and line loopbacks.
Provides an on-board programmable binary sequence generator and detector
for error testing at DS3 rates. Includes support for patterns recommended in ITU-T O.151.
Also provides PRBS generators and detectors on each tributary for error testing at DS1, E1 and NxDS0 rates as recommended in ITU-T O.151 and O.152.
Provides robbed bit signaling extraction and insertion on a per-DS0 basis.
Provides programmable idle code substitution, data and sign inversion, and
digital milliwatt code insertion on a per-DS0 basis.
PROPRIETARY AND CONFIDENTIAL 2
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
Supports the M23 and C-bit parity DS3 formats.
Standalone unchannelized DS3 framer mode for access to the entire DS3
payload.
When configured to operate as a DS3 Framer, gapped transmit and receive clocks can be optionally generated for interface to link layer devices which only need access to payload data bits.
DS3 Transmit clock source can be selected from either an external oscillator or from the receive side clock (loop-timed).
Provides a SONET/SDH Add/Drop bus interface with integrated VT1.5, TU­11, VT2 and TU-12 mapper for T1and E1 streams. Also provides a DS3 mapper.
Register level compatibility with the PM4388 TOCTL Octal T1 Framer, the PM6388 EOCTL Octal E1 Framer, the PM4351 COMET E1/T1 transceiver and the PM8313 D3MX M13 Multiplexer/Demultiplexer.
Provides a generic 8-bit microprocessor bus interface for configuration, control and status monitoring. Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.
Low power 2.5V/3.3V CMOS technology. All pins are 5V tolerant.
324-pin fine pitch PBGA package (23mm x 23mm). Supports industrial
temperature range (-40oC to 85oC) operation.
Each one of 28 T1 receiver sections:
Frames to DS-1 signals in SF and ESF formats.
Frames to TTC JT-G.704 multiframe formatted J1 signals. Supports the
alternate CRC-6 calculation for Japanese applications.
Accepts gapped data streams to support higher rate demultiplexing.
Provides Red, Yellow, and AIS alarm integration.
Provides ESF bit-oriented code detection and an HDLC/LAPD interface for
terminating the ESF facility data link.
Indicates signaling state change, and two superframes of signaling debounce on a per-DS0 basis.
PROPRIETARY AND CONFIDENTIAL 3
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
Provides an HDLC interface with 128 bytes of buffering for terminating the facility data link.
Provides performance monitoring counters sufficiently large as to allow performance monitor counter polling at a minimum rate of once per second. Optionally, updates the performance monitoring counters and interrupts the microprocessor once per second, timed to the receive line.
Provides an optional elastic store which may be used to time the ingress streams to a common clock and frame alignment, or to facilitate per-DS0 loopbacks.
Provides DS-1 robbed bit signaling extraction, with optional data inversion, programmable idle code substitution, digital milliwatt code substitution, bit fixing, and two superframes of signaling debounce on a per-channel basis.
A pseudo-random sequence user selectable from 211 –1, 215 –1 or220 –1, may be detected in the T1 stream in either the ingress or egress directions. The detector counts pattern errors using a 24-bit non-saturating PRBS error counter. The pseudo-random sequence can be the entire T1 or any combination of DS0s within a framed T1.
Line side interface is either from the DS3 interface via the M13 multiplex or from the SONET/SDH Drop bus via the VT1.5, TU-11, VT2 or TU-12 demapper.
System side interface is either serial clock and data, MVIP or SBI bus.
Frames in the presence of and detects the “Japanese Yellow” alarm.
Provides external access for up to two de-jittered recovered T1 clocks.
Each one of 21 E1 receiver sections:
Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals. The framing procedures are consistent ITU-T G.706 specifications.
Provides an HDLC interface with 128 bytes of buffering for terminating the national use bit data link.
Extracts 4-bit codewords from the E1 national use bits as specified in ETS 300 233.
V5.2 link indication signal detection.
PROPRIETARY AND CONFIDENTIAL 4
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
Provides performance monitoring counters sufficiently large as to allow performance monitor counter polling at a minimum rate of once per second. Optionally, updates the performance monitoring counters and interrupts the microprocessor once per second, timed to the receive line.
Provides a two-frame elastic store buffer for backplane rate adaptation that performs controlled slips and indicates slip occurrence and direction.
Frames to the E1 signaling multiframe alignment when enabled and extracts channel associated signaling. Alternatively, a common channel signaling data link may be extracted from timeslot 16.
Can be programmed to generate an interrupt on change of signaling state.
Provides trunk conditioning which forces programmable trouble code
substitution and signaling conditioning on all channels or on selected channels.
A pseudo-random sequence user selectable from 211 –1, 215 –1 or220 –1, may be detected in the E1 stream in either the ingress or egress directions. The detector counts pattern errors using a 24-bit non-saturating PRBS error counter. The pseudo-random sequence can be the entire E1 or any combination of timeslots within the framed E1.
Line side interface is from the SONET/SDH Drop bus via the VT2 or TU-12 demapper.
System side interface is either serial clock and data, MVIP or SBI bus.
Provides external access for up to two de-jittered recovered E1 clocks.
Each one of 28 T1 transmitter sections:
May be timed to its associated receive clock (loop timing) or may derive its timing from a common egress clock or a common transmit clock; the transmit line clock may be synthesized from an N*8kHz reference.
Provides minimum ones density through Bell (bit 7), GTE or “jammed bit 8” zero code suppression on a per-DS0 basis.Provides a 128 byte buffer to allow insertion of the facility data link using the host interface.
Supports transmission of the alarm indication signal (AIS) or the Yellow alarm signal in both SF and ESF formats.
PROPRIETARY AND CONFIDENTIAL 5
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
Provides a digital phase locked loop for generation of a low jitter transmit clock.
Provides a FIFO buffer for jitter attenuation and rate conversion in the transmitter.
Automatically generates and transmits DS-1 performance report messages to ANSI T1.231and ANSI T1.408 specifications.
Supports the alternate ESF CRC-6 calculation for Japanese applications.
A pseudo-random sequence user selectable from 211 –1, 215 –1 or 220 –1,
may be inserted into the T1 stream in either the ingress or egress directions. The pseudo-random sequence can be inserted into the entire T1 or any combination of DS0s within the framed T1.
Line side interface is through either DS3 Interface via the M13 multiplex or the SONET/SDH Add bus via the VT1.5, TU-11, VT2 or TU-12 mapper.
System side interface is either serial clock and data, MVIP or SBI bus.
Each one of 21 E1 transmitter sections:
Provides a FIFO buffer for jitter attenuation and rate conversion in the transmit path.
Transmits G.704 basic and CRC-4 multiframe formatted E1.
Supports unframed mode and framing bit, CRC, or data link by-pass.
Provides signaling insertion, programmable idle code substitution, digital
milliwatt code substitution, and data inversion on a per channel basis.
Provides trunk conditioning which forces programmable trouble code substitution and signaling conditioning on all channels or on selected channels.
Provides a digital phase locked loop for generation of a low jitter transmit clock.
A pseudo-random sequence user selectable from 211 –1, 215 –1 or 220 –1, may be inserted into the E1 stream in either the ingress or egress directions. The pseudo-random sequence can be inserted into the entire E1 or any combination of timeslots within the framed E1.
PROPRIETARY AND CONFIDENTIAL 6
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
Optionally inserts a datalink in the E1 national use bits.
Supports 4-bit codeword insertion in the E1 national use bits as specified in
ETS 300 233
Supports transmission of the alarm indication signal (AIS) and the Yellow alarm signal.
Line side interface is through the SONET/SDH Add bus via the VT2 or TU-12 mapper.
System side interface is either serial clock and data, MVIP or SBI bus.
SONET/SDH Tributary Path Processing Section:
Interfaces with a byte wide Telecom Add/Drop bus, interfacing directly with the PM5362 TUPP-PLUS and PM5342 SPECTRA-155.
Compensates for pleisiochronous relationships between incoming and outgoing higher level (STS-1, AU4, AU3) synchronous payload envelope frame rates through processing of the lower level tributary pointers.
Optionally frames to the H4 byte in the path overhead to determine tributary multi-frame boundaries and generates change of loss-of-frame status interrupts.
Detects loss of pointer (LOP) and re-acquisition for each tributary and optionally generates interrupts.
Detects tributary path alarm indication signal (AIS) and return to normal state for each tributary and optionally generates interrupts
Detects tributary elastic store underflow and overflow and optionally generates interrupts.
Provides individual tributary path signal label register that hold the expected label and detects tributary path signal label mismatch alarms (PSLM) and return to matched state for each tributary and optionally generates interrupts.
Detects tributary path signal label unstable alarms (PSLU) and return to stable state for each tributary and optionally generates interrupts.
Detects assertion and removal of tributary extended remote defect indications (RDI) for each tributary and optionally generates interrupts.
PROPRIETARY AND CONFIDENTIAL 7
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
Calculates and compares the tributary path BIP-2 error detection code for each tributary and configurable to accumulate the BIP-2 errors on block or bit basis in internal registers.
Allows insertion of all-zeros or all-ones tributary idle code with unequipped indication and valid pointer into any tributary under SW control.
Allows SW to force the AIS insertion on a per tributary basis.
Inserts valid H4 byte and all-zeros fixed stuff bytes. Remaining path overhead
bytes (J1, B3, C2,G1, F2, Z3, Z4, Z5) are set to all-zeros.
Inserts valid pointers and all-zeros transport overhead bytes on the outgoing telecom Add bus, with valid control signals.
Support in-band error reporting by updating the FEBE, RDI and auxiliary RDI bits in the V5 byte with the status of the incoming stream and remote alarm pins.
Calculates and inserts the tributary path BIP-2 error detection code for each tributary.
SONET/SDH VT/TU Mapper Section:
Inserts up to 28 bit asynchronous mapped VT1.5 virtual tributaries into an STS-1 SPE from T1 streams.
Inserts up to 28 bit asynchronous mapped TU-11 tributary units into a STM­1/VC4 TUG3 or STM-1/VC3 from T1 streams.
Inserts up to 21 bit asynchronous mapped VT2 virtual tributaries into an STS­1 SPE from E1 streams.
Inserts up to 21 bit asynchronous mapped TU-12 tributary units into an STM­1/VC4 TUG3 or STM-1/VC3 from E1 or T1 streams.
Bit asynchronous mapping assigns stuff control bits for all streams independently using an all digital control loop. Stuff control bits are dithered to produce fractional mapping jitter at the receiving desynchronizer.
Sets all fixed stuff bits for asynchronous mappings to zeros or ones per microprocessor control
PROPRIETARY AND CONFIDENTIAL 8
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
Extracts up to 28 bit asynchronous mapped VT1.5 virtual tributaries from an STS-1 SPE into T1 streams via an optional elastic store.
Extracts up to 28 bit asynchronous mapped TU-11 tributary units from an STM-1/VC4 TUG3 or STM-1/VC3 into T1 streams via an optional elastic store.
Extracts up to 21 bit asynchronous mapped VT2 virtual tributaries from an STS-1 SPE into E1 streams via an optional elastic store.
Extracts up to 21 bit asynchronous mapped TU-12 tributary units from an STM-1/VC4 TUG3 or STM-1/VC3 into E1 or T1 streams via an optional elastic store.
Demapper ignores all transport overhead bytes, path overhead bytes and stuff (R) bits
Performs majority vote C-bit decoding to detect stuff requests.
SONET/SDH DS3 Mapper Section:
Maps a DS3 stream into an STS-1 SPE (AU3).
Sets all fixed stuff (R) bits to zeros or ones per microprocessor control
Extracts a DS3 stream from an STS-1 SPE (AU3).
Demapper ignores all transport overhead bytes, path overhead bytes and
stuff (R) bits
Performs majority vote C-bit decoding to detect stuff requests
Complies with DS3 to STS-1 asynchronous mapping standards
DS3 Receiver Section:
Frames to a DS3 signal with a maximum average reframe time of less than
1.5 ms (as required by TR-TSY-000009 Section 4.1.2 and TR-TSY-000191 Section 5.2).
Decodes a B3ZS-encoded signal and indicates line code violations. The definition of line code violation is software selectable.
PROPRIETARY AND CONFIDENTIAL 9
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
Provides indication of M-frame boundaries from which M-subframe boundaries and overhead bit positions in the DS3 stream can be determined by external processing.
Detects the DS3 alarm indication signal (AIS) and idle signal. Detection algorithms operate correctly in the presence of a 10-3 bit error rate.Extracts
valid X-bits and indicates far end receive failure (FERF).Accumulates up to 65,535 line code violation (LCV) events per second, 65,535 P-bit parity error events per second, 1023 F-bit or M-bit (framing bit) events per second, 65,535 excessive zero (EXZ) events per second, and when enabled for C-bit parity mode operation, up to 16,383 C-bit parity error events per second, and 16,383 far end block error (FEBE) events per second.
Detects and validates bit-oriented codes in the C-bit parity far end alarm and control channel.
Terminates the C-bit parity path maintenance data link with an integral HDLC receiver having a 128-byte deep FIFO buffer with programmable interrupt threshold. Supports polled or interrupt-driven operation. Selectable none, one or two address match detection on first byte of received packet.
Programmable pseudo-random test-sequence detection–(up to 2
32
-1 bit
length patterns conforming to ITU-T O.151 standards) and analysis features.
DS3 Transmit Section:
Provides the overhead bit insertion for a DS3 stream.
Provides a bit serial clock and data interface, and allows the M-frame
boundary and/or the overhead bit positions to be located via an external interface
Provides B3ZS encoding.
Generates an B3Zs encoded 100… repeating pattern to aid in pulse mask
testing.
Inserts far end receive failure (FERF), the DS3 alarm indication signal (AIS) and the idle signal when enabled by internal register bits.
Provides optional automatic insertion of far end receive failure (FERF) on detection of loss of signal (LOS), out of frame (OOF), alarm indication signal (AIS) or red alarm condition.
PROPRIETARY AND CONFIDENTIAL 10
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
Provides diagnostic features to allow the generation of line code violation error events, parity error events, framing bit error events, and when enabled for the C-bit parity application, C-bit parity error events, and far end block error (FEBE) events.
Supports insertion of bit-oriented codes in the C-bit parity far end alarm and control channel.
Optionally inserts the C-bit parity path maintenance data link with an integral HDLC transmitter. Supports polled and interrupt-driven operation.
Provides programmable pseudo-random test sequence generation (up to 232-1 bit length sequences conforming to ITU-T O.151 standards) or any
repeating pattern up to 32 bits. The test pattern can be framed or unframed. Diagnostic abilities include single bit error insertion or error insertion at bit
error rates ranging from 10-1 to 10-7.
M23 Multiplexer Section:
Multiplexes 7 DS2 bit streams into a single M23 format DS3 bit stream.
Performs required bit stuffing/destuffing including generation and
interpretation of C-bits.
Includes required FIFO buffers for rate adaptation in the multiplex path.
Allows insertion and detection of per DS2 payload loopback requests
encoded in the C-bits to be activated under microprocessor control.
Internally generates DS2 clock for use in integrated M13 or C-bit parity multiplex applications. Alternatively accepts external DS2 clock reference.
Allows per DS2 alarm indication signal (AIS) to be activated or cleared for either direction under microprocessor control.
Allows DS2 alarm indication signal (AIS) to be activated or cleared in the demultiplex direction automatically upon loss of DS3 frame alignment or signal.
Supports C-bit parity DS3 format.
PROPRIETARY AND CONFIDENTIAL 11
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
DS2 Framer Section:
Frames to a DS2 (ANSI T1.107 section 8) signal with a maximum average reframe time of less than 7 ms (as required by TR-TSY-000009 Section 4.1.2 and TR-TSY-000191 Section 5.2).
Detects the DS2 alarm indication signal (AIS) in 9.9 ms in the presence of a 10-3 bit error rate.
Extracts the DS2 X-bit remote alarm indication (RAI) bit and indicates far end receive failure (FERF).
Accumulates up to 255 DS2 M-bit or F-bit error events per second.
DS2 Transmitter Section:
Generates the required X, F, and M bits into the transmitted DS2 bit stream. Allows inversion of inserted F or M bits for diagnostic purposes.
Provides for transmission of far end receive failure (FERF) and alarm indication signal (AIS) under microprocessor control.
Provides optional automatic insertion of far end receive failure (FERF) on detection of out of frame (OOF), alarm indication signal (AIS) or red alarm condition.
M12 Multiplexer Section:
Multiplexes four DS1 bit streams into a single M12 format DS2 bit stream.
Performs required bit stuffing including generation and interpretation of C-
bits.
Includes required FIFO buffers for rate adaptation in the multiplex path.
Performs required inversion of second and fourth multiplexed DS1 streams
as required by ANSI T1.107 Section 7.2.
Allows insertion and detection of per DS1 payload loopback requests encoded in the C-bits to be activated under microprocessor control.
Allows per tributary alarm indication signal (AIS) to be activated or cleared for either direction under microprocessor control.
PROPRIETARY AND CONFIDENTIAL 12
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
Allows automatic tributary AIS to be activated upon DS2 out of frame.
Synchronous System Interfaces:
Provides seven 8Mb/s H-MVIP data interfaces for synchronous access to all the DS0s of all 28 T1 links or all timeslots of all 21 E1s. T1 DS0s are bundled from four T1 links in sequential order (i.e. 1-4, 5-8, 9-12, 13-16, 17-20, 21-24, 25-28). In normal mode, E1 timeslots are bundled from 4 E1 links in sequential order (i.e. 1-4, 5-8, 9-12, 13-16, 17-20 and 21 by itself). In G.747 mode, E1 timeslots are bundled from 3 E1 links in sequential order, spaced by a reserved timeslot on every 4th frame (i.e. 1-3/X, 4-6/X, 7-9/X, 10-12/X, 13-15/X, 16-18/X, 19-21/X).
Provides seven 8Mb/s H-MVIP interfaces for synchronous access to all channel associated signaling (CAS) bits for all T1 DS0s or E1 timeslots. The CAS bits occupy one nibble of every byte on the H-MVIP interfaces and are repeated over the entire T1 or E1 multi-frame.
Provides a single 8Mb/s H-MVIP interface for common channel signaling (CCS) channels as well as V5.1 and V5.2 channels. In T1 mode DS0 24 is available through this interface. In E1 mode timeslots 15, 16 and 31 are available through this interface.
All links accessed via the H-MVIP interface will be synchronously timed to the common HMVIP clock and frame alignment signals, CMV8MCLK, CMVFP, CMVFPC.
H-MVIP access for Channel Associated Signaling is available with the Scaleable Bandwidth Interconnect bus as an optional replacement for CAS access over the SBI bus as well as with the H-MVIP data interface. Common Channel Signaling H-MVIP access is available with the SBI bus, serial PCM and H-MVIP data interfaces.
Compatible with H-MVIP PCM backplanes supporting 8.192 Mbit/s.
Scaleable Bandwidth Interconnect (SBI) Bus:
Provides a high density byte serial interconnect for all framed and unframed TEMUX links. Utilizes an Add/Drop configuration to asynchronously mutliplex up to 84 T1s, 63 E1s or 3 DS3s, equivalent to three TEMUXs, with multiple payload or link layer processors.
External devices can access unframed DS3, framed unchannelized DS3, unframed (clear channel) T1s, framed T1s, unframed (clear channel) E1s,
PROPRIETARY AND CONFIDENTIAL 13
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
framed E1s, transparent virtual tributaries or transparent tributary units over this interface.
Framed and unframed T1 access can be selected on a per T1 basis. Framed and unframed E1 access can be selected on a per E1 basis.
Synchronous access for T1 DS0 channels or E1 timeslots is supported in a locked format mode.
Transparent VT/TU access can be selected only when tributaries are mapped into SONET/SDH.
Transparent VT1.5s and TU-11s can be selected on a per tributary basis in combination with framed and unframed T1s. Transparent VT2s and TU-12s can be selected on a per tributary basis in combination with framed and unframed E1s.
Channel associated signaling bits for channelized T1 and E1 are explicitly identified across bus.
Transmit timing is mastered either by the TEMUX or a layer 2 device connecting to the SBI bus. Timing mastership is selectable on a per tributary basis, where a tributary is either an individual T1, E1 or a DS3.
PROPRIETARY AND CONFIDENTIAL 14
STANDARD PRODUCT
DATASHEET
PMC-1981125 ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
2 APPLICATIONS
High density T1 interfaces for multiplexers, multi-service switches, routers and digital modems.
High density E1 interfaces for multiplexers, multi-service switches, routers and digital modems.
Frame Relay switches and access devices (FRADS)
SONET/SDH Add Drop Multiplexers
SONET/SDH Terminal Multiplexers
M23 Based M13 Multiplexer
C-Bit Parity Based M13 Multiplexer
Channelized and Unchannelized DS3 Frame Relay Interfaces
PROPRIETARY AND CONFIDENTIAL 15
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