TABLE 65- TRANSMIT LINE INTERFACE TIMING (FIGURE 110)........... 306
PROPRIETARY AND CONFIDENTIALxiii
STANDARD PRODUCT
DATASHEET
PMC-1981125ISSUE 7HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
TABLE 66- REMOTE SERIAL ALARM PORT TIMING.............................. 307
TABLE 67- JTAG PORT INTERFACE ....................................................... 309
TABLE 68- ORDERING AND THERMAL INFORMATION..........................311
TABLE 69- THERMAL INFORMATION – THETA JA VS. AIRFLOW ..........311
PROPRIETARY AND CONFIDENTIALxiv
STANDARD PRODUCT
DATASHEET
PMC-1981125ISSUE 7HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
1 FEATURES
• Integrates 28 T1 framers, 21 E1 framers, a SONET/SDH
VT1.5/VT2/TU11/TU12 bit asynchronous mapper, a full featured M13
multiplexer with DS3 framer, and a SONET/SDH DS3 mapper in a single
monolithic device for terminating DS3 multiplexed T1 streams, SONET/SDH
mapped T1 streams or SONET/SDH mapped E1 streams.
• Seven T1 modes of operation:
• Up to 28 T1 streams mapped as bit asynchronous VT1.5 virtual tributaries
into a STS-1 SPE or TU-11 tributary units into a STM-1/VC3 or TU-11
tributary units into a TUG3 in a STM-1/VC4.
• Single STS-1, AU3 or TUG3 Bit Asynchronous VT1.5 or TU-11 Mapper
with ingress or egress per tributary link monitoring.
• Up to 28 T1 streams M13 multiplexed into a serial DS3.
• Up to 28 T1 streams M13 multiplexed into a DS3, the DS3 is
asynchronously mapped into a STS-1 SPE.
• DS3 M13 Multiplexer with ingress or egress per link monitoring.
• Up to 28 DS3 multiplexed T1 streams are mapped as bit asynchronous
VT1.5 virtual tributaries or TU-11 tributary units, providing a
transmultiplexing (“transmux”) function between DS3 and SONET/SDH.
• Up to 21 T1 streams mapped as bit asynchronous TU-12 tributary units
into a STM-1/VC3 or TUG3 from a STM-1/VC4.
• Three E1 modes of operation:
• Up to 21 E1 streams mapped as bit asynchronous VT2 virtual tributaries
into a STS-1 SPE or TU-12 tributary units into a STM-1/VC3 or TUG3
from a STM-1/VC4.
• Single STS-1, AU3 or TUG3 Bit Asynchronous VT2 or TU-12 Mapper with
ingress or egress per tributary link monitoring.
• Up to 21 E1 streams multiplexed into a DS3 following the ITU-T G.747
recommendation. This E1 mode of operation is restricted to using the
serial clock and data or HMVIP system interfaces.
PROPRIETARY AND CONFIDENTIAL1
STANDARD PRODUCT
DATASHEET
PMC-1981125ISSUE 7HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
• Up to 28 VT1.5/TU11 or 21 VT2/TU12 tributaries can be passed between the
line SONET/SDH bus and the SBI bus as transparent virtual tributaries with
pointer processing.
• When adding and dropping T1 or E1 tributaries the mapper and demapper
blocks allow for up to 28 VT1.5/TU11 or 21 VT2/TU12 tributaries to be
processed from any tributary location within the full STS-3/STM-1. On the
telecom DROP bus side this requires that the STS-3/STM-1 be in locked
mode such that the J1 bytes immediately follow the C1 bytes.
• Supports transfer of PCM data to/from 1.544MHz and 2.048MHz serial
interface system-side devices. Also supports a fractional T1 or E1 system
interface with independent ingress/egress Nx64Kb/s rates. Supports a 2.048
MHz system-side interface for T1 mode without external clock gapping.
• Supports 8Mb/s H-MVIP on the system interface for all T1 or E1 links, a
separate 8Mb/s H-MVIP system interface for all T1 or E1 CAS channels and
a separate 8Mb/s H-MVIP system interface for all T1 or E1 CCS and
V5.1/V5.2 channels.
• Supports a byte serial Scaleable Bandwidth Interconnect (SBI) bus interface
for high density system side device interconnection of up to 84 T1 streams,
63 E1 streams or 3 DS3 streams. This interface also supports transparent
virtual tributaries when used with the SONET/SDH mapper.
• Provides jitter attenuation in the T1 or E1 receive and transmit directions.
• Provides two independent de-jittered T1 or E1 recovered clocks for system
timing and redundancy.
• Provides per-DS0 line loopback and per link diagnostic and line loopbacks.
• Provides an on-board programmable binary sequence generator and detector
for error testing at DS3 rates. Includes support for patterns recommended in
ITU-T O.151.
• Also provides PRBS generators and detectors on each tributary for error
testing at DS1, E1 and NxDS0 rates as recommended in ITU-T O.151 and
O.152.
• Provides robbed bit signaling extraction and insertion on a per-DS0 basis.
• Provides programmable idle code substitution, data and sign inversion, and
digital milliwatt code insertion on a per-DS0 basis.
PROPRIETARY AND CONFIDENTIAL2
STANDARD PRODUCT
DATASHEET
PMC-1981125ISSUE 7HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
• Supports the M23 and C-bit parity DS3 formats.
• Standalone unchannelized DS3 framer mode for access to the entire DS3
payload.
• When configured to operate as a DS3 Framer, gapped transmit and receive
clocks can be optionally generated for interface to link layer devices which
only need access to payload data bits.
• DS3 Transmit clock source can be selected from either an external oscillator
or from the receive side clock (loop-timed).
• Provides a SONET/SDH Add/Drop bus interface with integrated VT1.5, TU11, VT2 and TU-12 mapper for T1and E1 streams. Also provides a DS3
mapper.
• Register level compatibility with the PM4388 TOCTL Octal T1 Framer, the
PM6388 EOCTL Octal E1 Framer, the PM4351 COMET E1/T1 transceiver
and the PM8313 D3MX M13 Multiplexer/Demultiplexer.
• Provides a generic 8-bit microprocessor bus interface for configuration,
control and status monitoring. Provides a standard 5 signal P1149.1 JTAG
test port for boundary scan board test purposes.
• Low power 2.5V/3.3V CMOS technology. All pins are 5V tolerant.
• 324-pin fine pitch PBGA package (23mm x 23mm). Supports industrial
temperature range (-40oC to 85oC) operation.
Each one of 28 T1 receiver sections:
• Frames to DS-1 signals in SF and ESF formats.
• Frames to TTC JT-G.704 multiframe formatted J1 signals. Supports the
alternate CRC-6 calculation for Japanese applications.
• Accepts gapped data streams to support higher rate demultiplexing.
• Provides Red, Yellow, and AIS alarm integration.
• Provides ESF bit-oriented code detection and an HDLC/LAPD interface for
terminating the ESF facility data link.
• Indicates signaling state change, and two superframes of signaling debounce
on a per-DS0 basis.
PROPRIETARY AND CONFIDENTIAL3
STANDARD PRODUCT
DATASHEET
PMC-1981125ISSUE 7HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
• Provides an HDLC interface with 128 bytes of buffering for terminating the
facility data link.
• Provides performance monitoring counters sufficiently large as to allow
performance monitor counter polling at a minimum rate of once per second.
Optionally, updates the performance monitoring counters and interrupts the
microprocessor once per second, timed to the receive line.
• Provides an optional elastic store which may be used to time the ingress
streams to a common clock and frame alignment, or to facilitate per-DS0
loopbacks.
• Provides DS-1 robbed bit signaling extraction, with optional data inversion,
programmable idle code substitution, digital milliwatt code substitution, bit
fixing, and two superframes of signaling debounce on a per-channel basis.
• A pseudo-random sequence user selectable from 211 –1, 215 –1 or220 –1, may
be detected in the T1 stream in either the ingress or egress directions. The
detector counts pattern errors using a 24-bit non-saturating PRBS error
counter. The pseudo-random sequence can be the entire T1 or any
combination of DS0s within a framed T1.
• Line side interface is either from the DS3 interface via the M13 multiplex or
from the SONET/SDH Drop bus via the VT1.5, TU-11, VT2 or TU-12
demapper.
• System side interface is either serial clock and data, MVIP or SBI bus.
• Frames in the presence of and detects the “Japanese Yellow” alarm.
• Provides external access for up to two de-jittered recovered T1 clocks.
Each one of 21 E1 receiver sections:
• Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals.
The framing procedures are consistent ITU-T G.706 specifications.
• Provides an HDLC interface with 128 bytes of buffering for terminating the
national use bit data link.
• Extracts 4-bit codewords from the E1 national use bits as specified in
ETS 300 233.
• V5.2 link indication signal detection.
PROPRIETARY AND CONFIDENTIAL4
STANDARD PRODUCT
DATASHEET
PMC-1981125ISSUE 7HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
• Provides performance monitoring counters sufficiently large as to allow
performance monitor counter polling at a minimum rate of once per second.
Optionally, updates the performance monitoring counters and interrupts the
microprocessor once per second, timed to the receive line.
• Provides a two-frame elastic store buffer for backplane rate adaptation that
performs controlled slips and indicates slip occurrence and direction.
• Frames to the E1 signaling multiframe alignment when enabled and extracts
channel associated signaling. Alternatively, a common channel signaling data
link may be extracted from timeslot 16.
• Can be programmed to generate an interrupt on change of signaling state.
• Provides trunk conditioning which forces programmable trouble code
substitution and signaling conditioning on all channels or on selected
channels.
• A pseudo-random sequence user selectable from 211 –1, 215 –1 or220 –1, may
be detected in the E1 stream in either the ingress or egress directions. The
detector counts pattern errors using a 24-bit non-saturating PRBS error
counter. The pseudo-random sequence can be the entire E1 or any
combination of timeslots within the framed E1.
• Line side interface is from the SONET/SDH Drop bus via the VT2 or TU-12
demapper.
• System side interface is either serial clock and data, MVIP or SBI bus.
• Provides external access for up to two de-jittered recovered E1 clocks.
Each one of 28 T1 transmitter sections:
• May be timed to its associated receive clock (loop timing) or may derive its
timing from a common egress clock or a common transmit clock; the transmit
line clock may be synthesized from an N*8kHz reference.
• Provides minimum ones density through Bell (bit 7), GTE or “jammed bit 8”
zero code suppression on a per-DS0 basis.Provides a 128 byte buffer to
allow insertion of the facility data link using the host interface.
• Supports transmission of the alarm indication signal (AIS) or the Yellow alarm
signal in both SF and ESF formats.
PROPRIETARY AND CONFIDENTIAL5
STANDARD PRODUCT
DATASHEET
PMC-1981125ISSUE 7HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
• Provides a digital phase locked loop for generation of a low jitter transmit
clock.
• Provides a FIFO buffer for jitter attenuation and rate conversion in the
transmitter.
• Automatically generates and transmits DS-1 performance report messages to
ANSI T1.231and ANSI T1.408 specifications.
• Supports the alternate ESF CRC-6 calculation for Japanese applications.
• A pseudo-random sequence user selectable from 211 –1, 215 –1 or 220 –1,
may be inserted into the T1 stream in either the ingress or egress directions.
The pseudo-random sequence can be inserted into the entire T1 or any
combination of DS0s within the framed T1.
• Line side interface is through either DS3 Interface via the M13 multiplex or
the SONET/SDH Add bus via the VT1.5, TU-11, VT2 or TU-12 mapper.
• System side interface is either serial clock and data, MVIP or SBI bus.
Each one of 21 E1 transmitter sections:
• Provides a FIFO buffer for jitter attenuation and rate conversion in the
transmit path.
• Transmits G.704 basic and CRC-4 multiframe formatted E1.
• Supports unframed mode and framing bit, CRC, or data link by-pass.
• Provides signaling insertion, programmable idle code substitution, digital
milliwatt code substitution, and data inversion on a per channel basis.
• Provides trunk conditioning which forces programmable trouble code
substitution and signaling conditioning on all channels or on selected
channels.
• Provides a digital phase locked loop for generation of a low jitter transmit
clock.
• A pseudo-random sequence user selectable from 211 –1, 215 –1 or 220 –1,
may be inserted into the E1 stream in either the ingress or egress directions.
The pseudo-random sequence can be inserted into the entire E1 or any
combination of timeslots within the framed E1.
PROPRIETARY AND CONFIDENTIAL6
STANDARD PRODUCT
DATASHEET
PMC-1981125ISSUE 7HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
• Optionally inserts a datalink in the E1 national use bits.
• Supports 4-bit codeword insertion in the E1 national use bits as specified in
ETS 300 233
• Supports transmission of the alarm indication signal (AIS) and the Yellow
alarm signal.
• Line side interface is through the SONET/SDH Add bus via the VT2 or TU-12
mapper.
• System side interface is either serial clock and data, MVIP or SBI bus.
SONET/SDH Tributary Path Processing Section:
• Interfaces with a byte wide Telecom Add/Drop bus, interfacing directly with
the PM5362 TUPP-PLUS and PM5342 SPECTRA-155.
• Compensates for pleisiochronous relationships between incoming and
outgoing higher level (STS-1, AU4, AU3) synchronous payload envelope
frame rates through processing of the lower level tributary pointers.
• Optionally frames to the H4 byte in the path overhead to determine tributary
multi-frame boundaries and generates change of loss-of-frame status
interrupts.
• Detects loss of pointer (LOP) and re-acquisition for each tributary and
optionally generates interrupts.
• Detects tributary path alarm indication signal (AIS) and return to normal state
for each tributary and optionally generates interrupts
• Detects tributary elastic store underflow and overflow and optionally
generates interrupts.
• Provides individual tributary path signal label register that hold the expected
label and detects tributary path signal label mismatch alarms (PSLM) and
return to matched state for each tributary and optionally generates interrupts.
• Detects tributary path signal label unstable alarms (PSLU) and return to
stable state for each tributary and optionally generates interrupts.
• Detects assertion and removal of tributary extended remote defect indications
(RDI) for each tributary and optionally generates interrupts.
PROPRIETARY AND CONFIDENTIAL7
STANDARD PRODUCT
DATASHEET
PMC-1981125ISSUE 7HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
• Calculates and compares the tributary path BIP-2 error detection code for
each tributary and configurable to accumulate the BIP-2 errors on block or bit
basis in internal registers.
• Allows insertion of all-zeros or all-ones tributary idle code with unequipped
indication and valid pointer into any tributary under SW control.
• Allows SW to force the AIS insertion on a per tributary basis.
bytes (J1, B3, C2,G1, F2, Z3, Z4, Z5) are set to all-zeros.
• Inserts valid pointers and all-zeros transport overhead bytes on the outgoing
telecom Add bus, with valid control signals.
• Support in-band error reporting by updating the FEBE, RDI and auxiliary RDI
bits in the V5 byte with the status of the incoming stream and remote alarm
pins.
• Calculates and inserts the tributary path BIP-2 error detection code for each
tributary.
SONET/SDH VT/TU Mapper Section:
• Inserts up to 28 bit asynchronous mapped VT1.5 virtual tributaries into an
STS-1 SPE from T1 streams.
• Inserts up to 28 bit asynchronous mapped TU-11 tributary units into a STM1/VC4 TUG3 or STM-1/VC3 from T1 streams.
• Inserts up to 21 bit asynchronous mapped VT2 virtual tributaries into an STS1 SPE from E1 streams.
• Inserts up to 21 bit asynchronous mapped TU-12 tributary units into an STM1/VC4 TUG3 or STM-1/VC3 from E1 or T1 streams.
• Bit asynchronous mapping assigns stuff control bits for all streams
independently using an all digital control loop. Stuff control bits are dithered to
produce fractional mapping jitter at the receiving desynchronizer.
• Sets all fixed stuff bits for asynchronous mappings to zeros or ones per
microprocessor control
PROPRIETARY AND CONFIDENTIAL8
STANDARD PRODUCT
DATASHEET
PMC-1981125ISSUE 7HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
• Extracts up to 28 bit asynchronous mapped VT1.5 virtual tributaries from an
STS-1 SPE into T1 streams via an optional elastic store.
• Extracts up to 28 bit asynchronous mapped TU-11 tributary units from an
STM-1/VC4 TUG3 or STM-1/VC3 into T1 streams via an optional elastic
store.
• Extracts up to 21 bit asynchronous mapped VT2 virtual tributaries from an
STS-1 SPE into E1 streams via an optional elastic store.
• Extracts up to 21 bit asynchronous mapped TU-12 tributary units from an
STM-1/VC4 TUG3 or STM-1/VC3 into E1 or T1 streams via an optional
elastic store.
• Demapper ignores all transport overhead bytes, path overhead bytes and
stuff (R) bits
• Performs majority vote C-bit decoding to detect stuff requests.
SONET/SDH DS3 Mapper Section:
• Maps a DS3 stream into an STS-1 SPE (AU3).
• Sets all fixed stuff (R) bits to zeros or ones per microprocessor control
• Extracts a DS3 stream from an STS-1 SPE (AU3).
• Demapper ignores all transport overhead bytes, path overhead bytes and
stuff (R) bits
• Performs majority vote C-bit decoding to detect stuff requests
• Complies with DS3 to STS-1 asynchronous mapping standards
DS3 Receiver Section:
• Frames to a DS3 signal with a maximum average reframe time of less than
1.5 ms (as required by TR-TSY-000009 Section 4.1.2 and TR-TSY-000191
Section 5.2).
• Decodes a B3ZS-encoded signal and indicates line code violations. The
definition of line code violation is software selectable.
PROPRIETARY AND CONFIDENTIAL9
STANDARD PRODUCT
DATASHEET
PMC-1981125ISSUE 7HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
• Provides indication of M-frame boundaries from which M-subframe
boundaries and overhead bit positions in the DS3 stream can be determined
by external processing.
• Detects the DS3 alarm indication signal (AIS) and idle signal. Detection
algorithms operate correctly in the presence of a 10-3 bit error rate.Extracts
valid X-bits and indicates far end receive failure (FERF).Accumulates up to
65,535 line code violation (LCV) events per second, 65,535 P-bit parity error
events per second, 1023 F-bit or M-bit (framing bit) events per second,
65,535 excessive zero (EXZ) events per second, and when enabled for C-bit
parity mode operation, up to 16,383 C-bit parity error events per second, and
16,383 far end block error (FEBE) events per second.
• Detects and validates bit-oriented codes in the C-bit parity far end alarm and
control channel.
• Terminates the C-bit parity path maintenance data link with an integral HDLC
receiver having a 128-byte deep FIFO buffer with programmable interrupt
threshold. Supports polled or interrupt-driven operation. Selectable none,
one or two address match detection on first byte of received packet.
• Programmable pseudo-random test-sequence detection–(up to 2
32
-1 bit
length patterns conforming to ITU-T O.151 standards) and analysis features.
DS3 Transmit Section:
• Provides the overhead bit insertion for a DS3 stream.
• Provides a bit serial clock and data interface, and allows the M-frame
boundary and/or the overhead bit positions to be located via an external
interface
• Provides B3ZS encoding.
• Generates an B3Zs encoded 100… repeating pattern to aid in pulse mask
testing.
• Inserts far end receive failure (FERF), the DS3 alarm indication signal (AIS)
and the idle signal when enabled by internal register bits.
• Provides optional automatic insertion of far end receive failure (FERF) on
detection of loss of signal (LOS), out of frame (OOF), alarm indication signal
(AIS) or red alarm condition.
PROPRIETARY AND CONFIDENTIAL10
STANDARD PRODUCT
DATASHEET
PMC-1981125ISSUE 7HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
• Provides diagnostic features to allow the generation of line code violation
error events, parity error events, framing bit error events, and when enabled
for the C-bit parity application, C-bit parity error events, and far end block
error (FEBE) events.
• Supports insertion of bit-oriented codes in the C-bit parity far end alarm and
control channel.
• Optionally inserts the C-bit parity path maintenance data link with an integral
HDLC transmitter. Supports polled and interrupt-driven operation.
• Provides programmable pseudo-random test sequence generation (up to
232-1 bit length sequences conforming to ITU-T O.151 standards) or any
repeating pattern up to 32 bits. The test pattern can be framed or unframed.
Diagnostic abilities include single bit error insertion or error insertion at bit
error rates ranging from 10-1 to 10-7.
M23 Multiplexer Section:
• Multiplexes 7 DS2 bit streams into a single M23 format DS3 bit stream.
• Performs required bit stuffing/destuffing including generation and
interpretation of C-bits.
• Includes required FIFO buffers for rate adaptation in the multiplex path.
• Allows insertion and detection of per DS2 payload loopback requests
encoded in the C-bits to be activated under microprocessor control.
• Internally generates DS2 clock for use in integrated M13 or C-bit parity
multiplex applications. Alternatively accepts external DS2 clock reference.
• Allows per DS2 alarm indication signal (AIS) to be activated or cleared for
either direction under microprocessor control.
• Allows DS2 alarm indication signal (AIS) to be activated or cleared in the
demultiplex direction automatically upon loss of DS3 frame alignment or
signal.
• Supports C-bit parity DS3 format.
PROPRIETARY AND CONFIDENTIAL11
STANDARD PRODUCT
DATASHEET
PMC-1981125ISSUE 7HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
DS2 Framer Section:
• Frames to a DS2 (ANSI T1.107 section 8) signal with a maximum average
reframe time of less than 7 ms (as required by TR-TSY-000009 Section 4.1.2
and TR-TSY-000191 Section 5.2).
• Detects the DS2 alarm indication signal (AIS) in 9.9 ms in the presence of a
10-3 bit error rate.
• Extracts the DS2 X-bit remote alarm indication (RAI) bit and indicates far end
receive failure (FERF).
• Accumulates up to 255 DS2 M-bit or F-bit error events per second.
DS2 Transmitter Section:
• Generates the required X, F, and M bits into the transmitted DS2 bit stream.
Allows inversion of inserted F or M bits for diagnostic purposes.
• Provides for transmission of far end receive failure (FERF) and alarm
indication signal (AIS) under microprocessor control.
• Provides optional automatic insertion of far end receive failure (FERF) on
detection of out of frame (OOF), alarm indication signal (AIS) or red alarm
condition.
M12 Multiplexer Section:
• Multiplexes four DS1 bit streams into a single M12 format DS2 bit stream.
• Performs required bit stuffing including generation and interpretation of C-
bits.
• Includes required FIFO buffers for rate adaptation in the multiplex path.
• Performs required inversion of second and fourth multiplexed DS1 streams
as required by ANSI T1.107 Section 7.2.
• Allows insertion and detection of per DS1 payload loopback requests
encoded in the C-bits to be activated under microprocessor control.
• Allows per tributary alarm indication signal (AIS) to be activated or cleared for
either direction under microprocessor control.
PROPRIETARY AND CONFIDENTIAL12
STANDARD PRODUCT
DATASHEET
PMC-1981125ISSUE 7HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
• Allows automatic tributary AIS to be activated upon DS2 out of frame.
Synchronous System Interfaces:
• Provides seven 8Mb/s H-MVIP data interfaces for synchronous access to all
the DS0s of all 28 T1 links or all timeslots of all 21 E1s. T1 DS0s are bundled
from four T1 links in sequential order (i.e. 1-4, 5-8, 9-12, 13-16, 17-20, 21-24,
25-28). In normal mode, E1 timeslots are bundled from 4 E1 links in
sequential order (i.e. 1-4, 5-8, 9-12, 13-16, 17-20 and 21 by itself). In G.747
mode, E1 timeslots are bundled from 3 E1 links in sequential order, spaced
by a reserved timeslot on every 4th frame (i.e. 1-3/X, 4-6/X, 7-9/X, 10-12/X,
13-15/X, 16-18/X, 19-21/X).
• Provides seven 8Mb/s H-MVIP interfaces for synchronous access to all
channel associated signaling (CAS) bits for all T1 DS0s or E1 timeslots. The
CAS bits occupy one nibble of every byte on the H-MVIP interfaces and are
repeated over the entire T1 or E1 multi-frame.
• Provides a single 8Mb/s H-MVIP interface for common channel signaling
(CCS) channels as well as V5.1 and V5.2 channels. In T1 mode DS0 24 is
available through this interface. In E1 mode timeslots 15, 16 and 31 are
available through this interface.
• All links accessed via the H-MVIP interface will be synchronously timed to the
common HMVIP clock and frame alignment signals, CMV8MCLK, CMVFP,
CMVFPC.
• H-MVIP access for Channel Associated Signaling is available with the
Scaleable Bandwidth Interconnect bus as an optional replacement for CAS
access over the SBI bus as well as with the H-MVIP data interface. Common
Channel Signaling H-MVIP access is available with the SBI bus, serial PCM
and H-MVIP data interfaces.
• Compatible with H-MVIP PCM backplanes supporting 8.192 Mbit/s.
Scaleable Bandwidth Interconnect (SBI) Bus:
• Provides a high density byte serial interconnect for all framed and unframed
TEMUX links. Utilizes an Add/Drop configuration to asynchronously mutliplex
up to 84 T1s, 63 E1s or 3 DS3s, equivalent to three TEMUXs, with multiple
payload or link layer processors.
framed E1s, transparent virtual tributaries or transparent tributary units over
this interface.
• Framed and unframed T1 access can be selected on a per T1 basis. Framed
and unframed E1 access can be selected on a per E1 basis.
• Synchronous access for T1 DS0 channels or E1 timeslots is supported in a
locked format mode.
• Transparent VT/TU access can be selected only when tributaries are mapped
into SONET/SDH.
• Transparent VT1.5s and TU-11s can be selected on a per tributary basis in
combination with framed and unframed T1s. Transparent VT2s and TU-12s
can be selected on a per tributary basis in combination with framed and
unframed E1s.
• Channel associated signaling bits for channelized T1 and E1 are explicitly
identified across bus.
• Transmit timing is mastered either by the TEMUX or a layer 2 device
connecting to the SBI bus. Timing mastership is selectable on a per tributary
basis, where a tributary is either an individual T1, E1 or a DS3.
PROPRIETARY AND CONFIDENTIAL14
STANDARD PRODUCT
DATASHEET
PMC-1981125ISSUE 7HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PM8315 TEMUX
2 APPLICATIONS
• High density T1 interfaces for multiplexers, multi-service switches, routers
and digital modems.
• High density E1 interfaces for multiplexers, multi-service switches, routers
and digital modems.
• Frame Relay switches and access devices (FRADS)
• SONET/SDH Add Drop Multiplexers
• SONET/SDH Terminal Multiplexers
• M23 Based M13 Multiplexer
• C-Bit Parity Based M13 Multiplexer
• Channelized and Unchannelized DS3 Frame Relay Interfaces
PROPRIETARY AND CONFIDENTIAL15
Loading...
+ 299 hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.