PMC PM7389 Datasheet

Preliminary

Frame Engine and Datalink Manager

PM7389

FREEDM 84A1024

FEATURES

• Single-chip multi-channel packet processor supportin g a maxi mum aggregate bandwidth of 156 Mbit/s for line rate throughp ut tran sfers of pac ket sizes from 40 to 9.6 Kbytes, for up to an aggregate of 84 T1s, 63 E1s, or 3 DS-3s.

• Provides simultaneous support of PPP, Frame Relay, Multilink-PPP and Multilink-Frame Relay protocols. Alternative protocols supported via HDLC termination an d full pac ket store of the data within the HDLC structure.

MULTILINK PPP AND FRAME RELAY BUNDLES

• Capable of supporting fragment sizes from 1 to 9.6 Kbytes.

BLOCK DIAGRAM

SYSCLK

PMCTEST

SCAN_EN

DDLL-

Insert

SBI

(INSBI)

Extract

SBI

(EXSBI)

DLLTEST

140

ACIFP

CIFPOUT

ADATA[7:0]

ADP

APL AV5

AJUST_REQ

AACTIVE

ADETECT[1:0]

REFCLK

DDATA[7:0]

DDP

DPL DV5

DC1FP

RSTB

• Support for 3 egress fragmentation sizes (128, 256, and 512 bytes) configurable on a per multilink bundle. Optionally full packet transfers are supported on a per bundle basis.

• Supports up to 42 multilink bundles with up to 12 member links per bundl e. These bundles are composed of independent HDLC channels.

• Support for up to 100ms of intra bundle skew in the receive direction when supporting the minimum fragment size.

• Support for PPP header compression as per RFC 1661.

PPP

• Support for 16 COS levels in accordance with RFC 2686.

• Either 12 bit or 24 bit sequence number, with short and long fragment header formats, is supported.

]

[

TCLK[8]

Transmit

Channel

Assigner

(TCAS-12)

Receive Channel

Assigner

(RCAS-12)

RCLK[0]

RCLK[4]

RD[8]

TD[4]

TD[0]

]

[

C R

TDO

TDI

JTAG

Tx HDLC

Processor /

Partial Packet

Buffer

(THDL-12)

Performance

Monitor (PM-12)

Rx HDLC

Processor /

Partial Packet

Buffer

(RHDL-12)

TCK

TMS

TRSTB

Fragment

Builder

(RFRAG)

AD[31:0]

BCLK

ADSB

Microprocessor I/F (BUMP2)

Manager

(EQM-12)

RS DRAM Controller

(RS_DRAMC)

RSWEB

RSDAT[31:0]

RSADD[12:0]

BURSTB

CSB

Egress

Queue

Frame

Builder

(FRMBLD)

RSCSB

RSRASB

BLAST

RSCASB

READYB

BTERMB

DQM

RSBS[1:0]

• Link Control protocol packets are identified by the PID as control protocols and will be forwarded to the Any-PHY interface.

FRAME RELAY

• Link layer address lookup can be performed based on HDLC channel and 10 bit DLCI for HDLC channels supporting Frame Relay protocols.

• The lookup algorithm can support a maximum of 16 K c onnection identifiers (CIs) amongst multilink FR bundles. The connection identifiers are ignored in singlelink FR channels.

• Control frames are identified and forwarded to Any-PHY interface.

• 12 bit sequence numbers supported.

• FECN, BECN, and DE ingress processing as per FRF.12.

INTLOB

WRDONEB

INTHIB

BUSPOL

TXCLK TXADDR[15:0] TPA TXDATA[15:0] TXPRTY TRDY TSX TEOP TMOD TERR

CCDAT[35:0] CCADD[17:0] CCWEB

CCSELB CCBSELB[1:0]

CBDAT[47:0] CBADD[12:0] CBWEB

CBCSB

CBRASB

CBCASB

CBBS[1:0] RXCLK

RXADDR[3:0] RPA RENB RXDATA[15:0] RXPRTY RVAL RSX RSOP REOP RMOD RERR

Fragment

Builder

(TFRAG)

Ingress

Queue

Manager

(EQM-12)

Tx A NY-PHY I/F (TAPI-12)

SRAM

Controller

(SRAMC)

CB DRAM Controller

(CB_DRAMC)

Rx ANY-PHY

I/F

(RAPI-12)

Data

Control

PMC-1991477 (r2) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE © Copyright PMC-Sierra, Inc. 2001

Preliminary PM7389 FREEDM 84A1024

Frame Engine and Datalink Manager

HDLC

• Support for up to 1024 bidirectional HDLC channels, with individual HDLC channel speeds rangin g from 56 Kbi t/s to 52 Mbit/s. In a channelized application, the number of time-slots assigned to an HDLC chan nel is programmable from 1 to 24 (for T1/J1) and from 1 to 31 (for E1).

• The 1024 HDLC channels can be assigned to a mixture of physical links via the 19.44 MHz SBI interface. The SBI transports the equivalen t of 3 STS1 synchronous payload envelopes (SPE). Each STS-1 SPE can be individually configured to carry 28 T1/J1s, 21 E1s or 1 DS3.

• For each channel, supports programmable flag se quence detection and generation, bit stuffing and destuffing, and validation and generation of either CRC-CCITT or CRC-32 frame check sequences.

• For each channel, the receiver checks for packet abort sequences, octet

aligned packet leng th and fo r minimum and maximum packet length.

INTERFACES

• 52 MHz 16 bit Any-PHY Level 2 packet interface for transfer of packet, frame or fragment data using an external controller. The interface is capable of supporting full datagram transfer on a per Any-PHY channel basis, or fragmented packets or frames on a per Any-PHY channel basis.

• A 19.44 MHz SBI bus supporting up to 84 links.

• 3 separate clock and data interfaces to support 3 links of arbitrary da ta rate up to 52 MHz (e.g., DS3/E3). The device can be configured to process da ta from either the clock and data interfaces or from the SBI on a per clock-datalink/SPE basis.

• A 100 MHz, 48-bit SDRAM interface for ingress and egress per packet/fragment storage.

• A 100 MHz, 32-bit SDRAM interface for ingress re-sequencing data. structures.

• A 100 MHz, 36-bit SSRAM interface for Ingress/Egress Context storag e.

• Provides a standard 5 signal P1149.1 JTAG test por t for bounda ry scan.

• A 32-bit microprocessor interface for configuration and status monitoring.

TECHNOLOGIES

• 40 mm x 40 mm, 520 pin (1.27 mm pitch) enhanced ball grid array (SBG A) package.

• Low power 0.18 mm CMOS technology using 1.8 V c ore power and

3.3 V I/O.

APPLICATIONS

• IETF PPP interfaces for routers.

• Frame Relay interfac es for ATM or

Frame Relay switch es and multiplexers.

• Internet/Intranet access equipm en t.

TYPICAL APPLICATION

OC-12 MULTISERVICE ARCHITECTURE

TelecomBus SBI

PM8316

TEMUX-84

PM8316

TEMUX-84

PM5313

OC-12

SPECTRA-

622

PM8316

TEMUX-84

PM8316

TEMUX-84

H-MVIP

PM7389

FREEDM-

84A1024

VoATM DSP

Any-PHY

(Packet)

PM7341

S/UNI-IMA-

PM73122

AAL1gator-

PM73122

AAL1gator-

Packet/Cell

Internetworking

APPI

Function

Any-PHY

(Cell)

Any-PHY

PM7326

S/UNI-APEX

PM7324

S/UNI-

ATLAS

Head Office: PMC-Sierra, Inc. 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200

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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

All product documentation is available on our web site at: http://www.pmc-sierra.com For corpo rate information, send email to: info@pmc-sierra.com

PMC-1991477 (r2)

SBI, and PMC-Sierra are trademarks of PMC-Sierra, Inc.