PMC PM7385-BI Datasheet

DATA SHEET

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

PM7385

FREEDM™-84A672

FRAME ENGINE AND DATALINK

MANAGER 84A672

DATA SHEET

PROPRIETARY AND CONFIDENTIAL

ISSUE 6: AUGUST 2001

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

DATA SHEET

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

REVISION HISTORY

Issue No. Issue Date Details of Change

Issue 1 Jan 7, 1999 Creation of Document.

Issue 2 July 8, 1999 Update as per issue 3 of the engineering document (PMC-

981263).

Issue 3 January, 2000 Update as per issue 4 of the engineering document (PMC-

981263), for GCA release.

Issue 4 June 2000 Re-issue to coincide with production release of Rev C of

device. Minor corrections and changes to some DC and AC
timing parameters.

Issue 5 October 2000 Re-issue to coincide with Issue 6 of the Eng Doc.

DEFAULT_DRV register bit changed to PERM_DRV and
description changed. (See PREP #4938.) Change bars have
been kept to show both Issue 4 and Issue 5 changes.

Issue 6 August 2001 Patent information included. Change bars apply to previous

issue.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE i

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PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

CONTENTS

1 FEATURES...............................................................................................1

2 APPLICATIONS........................................................................................3

3 REFERENCES .........................................................................................4

4 BLOCK DIAGRAM....................................................................................5

5 DESCRIPTION .........................................................................................6

6 PIN DIAGRAM ..........................................................................................9

7 PIN DESCRIPTION ................................................................................10

8 FUNCTIONAL DESCRIPTION................................................................39

8.1 SCALEABLE BANDWIDTH INTERCONNECT (SBI) INTERFACE39

8.2 HIGH-LEVEL DATA LINK CONTROL (HDLC) PROTOCOL.........40

8.3 SBI EXTRACTER AND PISO.......................................................41

8.4 RECEIVE CHANNEL ASSIGNER ................................................41

8.4.1 Line Interface.................................................................43

8.4.2 Priority Encoder .............................................................44

8.4.3 Channel Assigner ..........................................................44

8.4.4 Loopback Controller.......................................................44

8.5 RECEIVE HDLC PROCESSOR / PARTIAL PACKET BUFFER ...44

8.5.1 HDLC Processor............................................................45

8.5.2 Partial Packet Buffer Processor.....................................45

8.6 RECEIVE ANY-PHY INTERFACE................................................47

8.6.1 FIFO Storage and Control..............................................48

8.6.2 Polling Control and Management...................................49

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ii

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PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

8.7 TRANSMIT ANY-PHY INTERFACE .............................................49

8.7.1 FIFO Storage and Control..............................................49

8.7.2 Polling Control and Management...................................50

8.8 TRANSMIT HDLC CONTROLLER / PARTIAL PACKET BUFFER52

8.8.1 Transmit HDLC Processor.............................................52

8.8.2 Transmit Partial Packet Buffer Processor ......................53

8.9 TRANSMIT CHANNEL ASSIGNER..............................................55

8.9.1 Line Interface.................................................................57

8.9.2 Priority Encoder .............................................................57

8.9.3 Channel Assigner ..........................................................58

8.10 SBI INSERTER AND SIPO ..........................................................58

8.11 PERFORMANCE MONITOR .......................................................59

8.12 JTAG TEST ACCESS PORT INTERFACE...................................59

8.13 MICROPROCESSOR INTERFACE .............................................59

9 NORMAL MODE REGISTER DESCRIPTION ........................................64

9.1 MICROPROCESSOR ACCESSIBLE REGISTERS .....................64

10 TEST FEATURES DESCRIPTION .......................................................181

10.1 TEST MODE REGISTERS.........................................................181

10.2 JTAG TEST PORT .....................................................................183

10.2.1 Identification Register ..................................................183

10.2.2 Boundary Scan Register..............................................184

11 OPERATIONS.......................................................................................201

11.1 JTAG SUPPORT........................................................................201

12 FUNCTIONAL TIMING..........................................................................208

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PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

12.1 SBI DROP BUS INTERFACE TIMING .......................................208

12.2 SBI ADD BUS INTERFACE TIMING..........................................209

12.3 RECEIVE LINK TIMING.............................................................209

12.4 TRANSMIT LINK TIMING ..........................................................210

12.5 RECEIVE APPI TIMING.............................................................210

12.6 TRANSMIT APPI TIMING ..........................................................214

13 ABSOLUTE MAXIMUM RATINGS........................................................218

14 D.C. CHARACTERISTICS....................................................................219

15 FREEDM-84A672 TIMING CHARACTERISTICS.................................221

16 ORDERING AND THERMAL INFORMATION ......................................233

17 MECHANICAL INFORMATION.............................................................234

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DATA SHEET

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

LIST OF FIGURES

FIGURE 1 – HDLC FRAME...............................................................................40

FIGURE 2 – CRC GENERATOR.......................................................................41

FIGURE 3 – PARTIAL PACKET BUFFER STRUCTURE ..................................46

FIGURE 4 – PARTIAL PACKET BUFFER STRUCTURE ..................................53

FIGURE 5 – INPUT OBSERVATION CELL (IN_CELL) ...................................198

FIGURE 6 – OUTPUT CELL (OUT_CELL)......................................................199

FIGURE 7 – BI-DIRECTIONAL CELL (IO_CELL)............................................199

FIGURE 8 – LAYOUT OF OUTPUT ENABLE AND BI-DIRECTIONAL CELLS200

FIGURE 9 – BOUNDARY SCAN ARCHITECTURE ........................................202

FIGURE 10 – TAP CONTROLLER FINITE STATE MACHINE ........................204

FIGURE 11 – T1/E1 DROP BUS FUNCTIONAL TIMING ................................208

FIGURE 12 – DS3 DROP BUS FUNCTIONAL TIMING ..................................208

FIGURE 13 – DS3 ADD BUS ADJUSTMENT REQUEST FUNCTIONAL TIMING

..............................................................................................................209

FIGURE 14 – RECEIVE LINK TIMING............................................................210

FIGURE 15 – TRANSMIT LINK TIMING .........................................................210

FIGURE 16 – RECEIVE APPI TIMING (NORMAL TRANSFER) ..................... 211

FIGURE 17 – RECEIVE APPI TIMING (AUTO DESELECTION) ....................212

FIGURE 18 – RECEIVE APPI TIMING (OPTIMAL RESELECTION)...............213

FIGURE 19 – RECEIVE APPI TIMING (BOUNDARY CONDITION) ...............214

FIGURE 20 – TRANSMIT APPI TIMING (NORMAL TRANSFER)...................215

FIGURE 21 – TRANSMIT APPI TIMING (SPECIAL CONDITIONS)................216

FIGURE 22 – TRANSMIT APPI TIMING (POLLING).......................................217

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PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

FIGURE 23 – SBI FRAME PULSE TIMING.....................................................222

FIGURE 24 – SBI DROP BUS TIMING ...........................................................223

FIGURE 25 – SBI ADD BUS TIMING..............................................................224

FIGURE 26 – SBI ADD BUS COLLISION AVOIDANCE TIMING ....................224

FIGURE 27 – RECEIVE DATA TIMING...........................................................225

FIGURE 28 – TRANSMIT DATA TIMING.........................................................225

FIGURE 29 – RECEIVE ANY-PHY PACKET INTERFACE TIMING.................227

FIGURE 30 – TRANSMIT ANY-PHY PACKET INTERFACE TIMING ..............228

FIGURE 31 – MICROPROCESSOR READ ACCESS TIMING .......................229

FIGURE 32 – MICROPROCESSOR WRITE ACCESS TIMING......................231

FIGURE 33 – JTAG PORT INTERFACE TIMING............................................232

FIGURE 34 – 352 PIN ENHANCED BALL GRID ARRAY (SBGA) ..................234

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DATA SHEET

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

LIST OF TABLES

TABLE 1 – SBI INTERFACE SIGNALS (30)......................................................10

TABLE 2 – CLOCK/DATA INTERFACE SIGNALS (15) .....................................16

TABLE 3 – ANY-PHY PACKET INTERFACE SIGNALS (70) .............................18

TABLE 4 – MICROPROCESSOR INTERFACE SIGNALS (31).........................30

TABLE 5 – MISCELLANEOUS INTERFACE SIGNALS (111)............................32

TABLE 6 – PRODUCTION TEST INTERFACE SIGNALS (31)..........................34

TABLE 7 – POWER AND GROUND SIGNALS (64)..........................................36

TABLE 8 – SBI SPE/TRIBUTARY TO RCAS LINK MAPPING...........................42

TABLE 9 – TRANSMIT POLLING......................................................................51

TABLE 10 – SBI SPE/TRIBUTARY TO TCAS LINK MAPPING.........................55

TABLE 11 – NORMAL MODE MICROPROCESSOR ACCESSIBLE REGISTERS59

TABLE 12 – SPE TYPE CONFIGURATION ......................................................90

TABLE 13 – FASTCLK FREQUENCY SELECTION..........................................91

TABLE 14 – SPE TYPE CONFIGURATION ......................................................92

TABLE 15 – FASTCLK FREQUENCY SELECTION..........................................93

TABLE 16 – SBI MODE SPE1 CONFIGURATION ..........................................100

TABLE 17 – SBI MODE SPE2 CONFIGURATION ..........................................103

TABLE 18 – SBI MODE SPE3 CONFIGURATION ..........................................106

TABLE 19 – CRC[1:0] SETTINGS................................................................... 115

TABLE 20 – CRC[1:0] SETTINGS...................................................................126

TABLE 21 – FLAG[2:0] SETTINGS .................................................................131

TABLE 22 – LEVEL[3:0]/TRANS SETTINGS ..................................................133

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DATA SHEET

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

TABLE 23 – SBI MODE SPE1 CONFIGURATION ..........................................147

TABLE 24 – SBI MODE SPE2 CONFIGURATION ..........................................150

TABLE 25 – SBI MODE SPE3 CONFIGURATION ..........................................153

TABLE 26 – TRIB_TYP ENCODING ...............................................................168

TABLE 27 – TRIB_TYP ENCODING ...............................................................180

TABLE 28 – TEST MODE REGISTER MEMORY MAP...................................182

TABLE 29 – INSTRUCTION REGISTER.........................................................183

TABLE 30 – BOUNDARY SCAN CHAIN .........................................................184

TABLE 31 – FREEDM-84A672 ABSOLUTE MAXIMUM RATINGS .................218

TABLE 32 – FREEDM-84A672 D.C. CHARACTERISTICS.............................219

TABLE 33 – CLOCKS AND SBI FRAME PULSE (FIGURE 23).......................221

TABLE 34 – SBI DROP BUS (FIGURE 24) .....................................................222

TABLE 35 – SBI ADD BUS (FIGURE 25 TO FIGURE 26)...............................223

TABLE 36 – CLOCK/DATA INPUT (FIGURE 27).............................................225

TABLE 37 – CLOCK/DATA OUTPUT (FIGURE 28).........................................225

TABLE 38 – ANY-PHY PACKET INTERFACE (FIGURE 29 TO FIGURE 30)..226

TABLE 39 – MICROPROCESSOR INTERFACE READ ACCESS (FIGURE 31)

..............................................................................................................228

TABLE 40 – MICROPROCESSOR INTERFACE WRITE ACCESS (FIGURE 32)

..............................................................................................................230

TABLE 41 – JTAG PORT INTERFACE (FIGURE 33)......................................231

TABLE 42 – FREEDM-84A672 ORDERING INFORMATION..........................233

TABLE 43 – FREEDM-84A672 THERMAL INFORMATION ............................233

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE viii

DATA SHEET

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

1 FEATURES

· Single-chip multi-channel HDLC controller with a 50 MHz, 16 bit “Any-PHY”
Packet Interface (APPI) for transfer of packet data using an external
controller.

· Supports up to 672 bi-directional HDLC channels assigned to a maximum of
84 channelised or unchannelised links conveyed via a Scaleable Bandwidth
Interconnect (SBI) interface.

· Data on the SBI interface is divided into 3 Synchronous Payload Envelopes
(SPEs). Each SPE can be configured independently to carry data for either
28 T1/J1 links, 21 E1 links, or 1 unchannelised DS-3 link.

· Links in an SPE can be configured individually to operate in clear channel
mode, in which case, all framing bit locations are assumed to be carrying
HDLC data.

· Links in an SPE can be configured individually to operate in channelised
mode, in which case, the number of time-slots assigned to an HDLC channel
is programmable from 1 to 24 (for T1/J1 links) and from 1 to 31 (for E1 links).

· Supports three bi-directional HDLC channels each assigned to an
unchannelised link with arbitrary rate link of up to 51.84 MHz when SYSCLK
is running at 45 MHz. Each link may be configured individually to replace one
of the SPEs conveyed on the SBI interface.

· For each channel, the HDLC receiver supports programmable flag sequence
detection, bit de-stuffing and frame check sequence validation. The receiver
supports the validation of both CRC-CCITT and CRC-32 frame check
sequences.

· For each channel, the receiver checks for packet abort sequences, octet
aligned packet length and for minimum and maximum packet length. The
receiver supports filtering of packets that are larger than a user specified
maximum value.

· Alternatively, for each channel, the receiver supports a transparent mode
where each octet is transferred transparently on the receive APPI. For
channelised links, the octets are aligned with the receive time-slots.

· For each channel, time-slots are selectable to be in 56 kbits/s format or 64
kbits/s clear channel format.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 1

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PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

· For each channel, the HDLC transmitter supports programmable flag
sequence generation, bit stuffing and frame check sequence generation. The
transmitter supports the generation of both CRC-CCITT and CRC-32 frame
check sequences. The transmitter also aborts packets under the direction of
the external controller or automatically when the channel underflows.

· Alternatively, for each channel, the transmitter supports a transparent mode
where each octet is inserted transparently from the transmit APPI. For
channelised links, the octets are aligned with the transmit time-slots.

· Supports per-channel configurable APPI burst sizes of up to 256 bytes for
transfers of packet data.

· The FREEDM maintains packet level performance metrics such as number of
received packets, number of received packets with frame check sequence
errors, number of transmitted packets, number of receive aborted packets,
and number of transmit aborted packets.

· Provides 32 Kbytes of on-chip memory for partial packet buffering in both the
transmit and the receive directions. This memory may be configured to
support a variety of different channel configurations from a single channel with
32 Kbytes of buffering to 672 channels, each with a minimum of 48 bytes of
buffering.

· Provides a 16 bit microprocessor interface for configuration and status
monitoring.

· Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board
test purposes.

· Supports 3.3 Volt tolerant I/O.

· Low power 2.5 Volt 0.25 mm CMOS technology.

· 352 pin enhanced ball grid array (SBGA) package.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 2

DATA SHEET

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

2 APPLICATIONS

· IETF PPP interfaces for routers

· Frame Relay interfaces for ATM or Frame Relay switches and multiplexors

· FUNI or Frame Relay service inter-working interfaces for ATM switches and

multiplexors.

· Internet/Intranet access equipment.

· Packet-based DSLAM equipment.

· Packet over SONET.

· PPP over SONET.

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PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

3 REFERENCES

1. International Organization for Standardization, ISO Standard 3309-1993,
“Information Technology – Telecommunications and information exchange between
systems – High-level data link control (HDLC) procedures – Frame structure”,
December 1993.

2. RFC-1662 – “PPP in HDLC-like Framing” Internet Engineering Task Force, July

1994.

3. PMC-1981125 – “High Density T1/E1 Framer with Integrated VT/TU Mapper and

M13 Multiplexer (TEMUX) Data Sheet”, PMC-Sierra Inc.

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DATA SHEET

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 5

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DATA SHEET

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

5 DESCRIPTION

The PM7385 FREEDM-84A672 Frame Engine and Datalink Manager device is a
monolithic integrated circuit that implements HDLC processing for a maximum of
672 bi-directional channels.

The FREEDM-84A672 may be configured to support channelised T1/J1/E1 or
unchannelised traffic on up to 84 links conveyed via a Scaleable Bandwidth
Interconnect (SBI) interface. The SBI interface transports data in three
Synchronous Payload Envelopes (SPEs), each of which may be configured
independently to carry either 28 T1/J1 links, 21 E1 links or a single DS-3 link.

For channelised T1/J1/E1 links, the FREEDM-84A672 allows up to 672 bi­directional HDLC channels to be assigned to individual time-slots within each
independently timed T1/J1 or E1 link. The channel assignment supports the
concatenation of time-slots (N x DS0) up to a maximum of 24 concatenated time­slots for a T1/J1 link and 31 concatenated time-slots for an E1 link. Time-slots
assigned to any particular channel need not be contiguous within a T1/J1 or E1
link. Unchannelised DS-3 links are assigned to a single HDLC channel.

Additionally, links may be configured independently to operate in an unframed or
“clear channel” mode, in which the bit periods which are normally reserved for
framing information in fact carry HDLC data. In unframed mode, links operate as
unchannelised (i.e. the entire link is assigned to a single HDLC channel)
regardless of link rate.

The FREEDM-84A672 supports mixing of channelised T1/J1/E1 and
unchannelised or unframed links. The total number of channels in each direction
is limited to 672. The maximum possible data rate over all links is 134.208 Mbps
(which occurs with three DS-3 links running in unframed mode).

The FREEDM-84A672 supports three independently timed bidirectional clock/
data links, each carrying a single unchannellised HDLC stream. The links can be
of arbitrary frame format and can operate at up to 51.84 MHz provided SYSCLK
is running at 45 MHz. When activated, each link replaces one of the SPEs
conveyed on the SBI interface. (The maximum possible data rate when all three
clock/data links are activated is 155.52 Mbps.)

The FREEDM-84A672 provides a low latency “Any-PHY” packet interface (APPI)
to allow an external controller direct access into the 32 Kbyte partial packet
buffers. Up to seven FREEDM-84A672 devices may share a single APPI. For
each of the transmit and receive APPI, the external controller is the master of the
FREEDM-84A672 device sharing the APPI from the point of view of device

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 6

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PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

selection. The external controller is also the master for channel selection in the
transmit direction. In the receive direction, however, each FREEDM-84A672
device retains control over selection of its respective channels. The transmit and
receive APPI is made up of three groups of functional signals – polling, selection
and data transfer. The polling signals are used by the external controller to
interrogate the status of the transmit and receive 32 Kbyte partial packet buffers.
The selection signals are used by the external controller to select a FREEDM­84A672 device, or a channel within a FREEDM-84A672 device, for data transfer.
The data transfer signals provide a means of transferring data across the APPI
between the external controller and a FREEDM-84A672 device.

In the receive direction, polling and selection are done at the device level.
Polling is not decoupled from selection, as the receive address pins serve as
both a device poll address and to select a FREEDM-84A672 device. In response
to a positive poll, the external controller may select that FREEDM-84A672 device
for data transfer. Once selected, the FREEDM-84A672 prepends an in-band
channel address to each partial packet transfer across the receive APPI to
associate the data with a channel. A FREEDM-84A672 must not be selected
after a negative poll response.

In the transmit direction, polling is done at the channel level. Polling is
completely decoupled from selection. To increase the polling bandwidth, up to
two channels may be polled simultaneously. The polling engine in the external
controller runs independently of other activity on the transmit APPI. In response
to a positive poll, the external controller may commence partial packet data
transfer across the transmit APPI for the successfully polled channel of a
FREEDM-84A672 device. The external controller must prepend an in-band
channel address to each partial packet transfer across the transmit APPI to
associate the data with a channel.

In the receive direction, the FREEDM-84A672 performs channel assignment and
packet extraction and validation. For each provisioned HDLC channel, the
FREEDM-84A672 delineates the packet boundaries using flag sequence
detection, and performs bit de-stuffing. Sharing of opening and closing flags, as
well as sharing of zeros between flags are supported. The resulting packet data
is placed into the internal 32 Kbyte partial packet buffer RAM. The partial packet
buffer acts as a logical FIFO for each of the assigned channels. An external
controller transfers partial packets out of the RAM, across the receive APPI bus,
into host packet memory. The FREEDM-84A672 validates the frame check
sequence for each packet, and verifies that the packet is an integral number of
octets in length and is within a programmable minimum and maximum lengths.
Receive APPI bus latency may cause one or more channels to overflow, in which
case, the packets are aborted. The FREEDM-84A672 reports the status of each
packet on the receive APPI at the end of each packet transfer.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 7

DATA SHEET

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

Alternatively, in the receive direction, the FREEDM-84A672 supports a
transparent operating mode. For each provisioned transparent channel, the
FREEDM-84A672 directly transfers the received octets onto the receive APPI
verbatim. If the transparent channel is assigned to a channelised link, then the
octets are aligned to the received time-slots.

In the transmit direction, an external controller provides packets to transmit using
the transmit APPI. For each provisioned HDLC channel, an external controller
transfers partial packets, across the transmit APPI, into the internal 32 Kbyte
transmit partial packet buffer. The partial packets are read out of the partial
packet buffer by the FREEDM-84A672 and a frame check sequence is optionally
calculated and inserted at the end of each packet. Bit stuffing is performed
before being assigned to a particular link. The flag or idle sequence is
automatically inserted when there is no packet data for a particular channel.
Sequential packets are optionally separated by a single flag (combined opening
and closing flag) or up to 128 flags. Zeros between flags are not shared in the
transmit direction although, as stated previously, they are accepted in the receive
direction. Transmit APPI bus latency may cause one or more channels to
underflow, in which case, the packets are aborted. The FREEDM-84A672
generates an interrupt to notify the host of aborted packets. For normal traffic, an
abort sequence is generated, followed by inter-frame time fill characters (flags or
all-ones bytes) until a new packet is sourced on the transmit APPI. The
FREEDM-84A672 will not attempt to re-transmit aborted packets.

Alternatively, in the transmit direction, the FREEDM-84A672 supports a
transparent operating mode. For each provisioned transparent channel, the
FREEDM-84A672 directly inserts the transmitted octets provided on the transmit
APPI. If the transparent channel is assigned to a channelised link, then the
octets are aligned to the transmitted time-slots. If a channel underflows due to
excessive transmit APPI bus latency, an abort sequence is generated, followed
by inter-frame time fill characters (flags or all-ones bytes) to indicate idle channel.
Data resumes immediately when the FREEDM-84A672 receives new data on the
transmit APPI.

The FREEDM-84A672 is configured, controlled and monitored using the
microprocessor interface. The FREEDM-84A672 is implemented in low power

2.5 Volt 0.25 mm CMOS technology. All FREEDM-84A672 I/O are 3.3 volt
tolerant. The FREEDM-84A672 is packaged in a 352 pin enhanced ball grid
array (SBGA) package.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 8

DATA SHEET

PM7385 FREEDM-84A672

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

WITH ANY-PHY PACKET INTERFACE

6 PIN DIAGRAM

The FREEDM-84A672 is manufactured in a 352 pin enhanced ball grid array
(SBGA) package.

2625242322212019181716151413121110987654321

VSS VSS N.C. D[2] D[6] VDD2V5 D[12] A[2] A[5] A[9] ALE CSB VSS VSS N.C. N.C. N.C. N.C. N.C. N.C. VDD2V5 N.C. N.C. N.C. VSS VSS

A

ADATA

DDATA

[7]

ADATA

N.C.

DDATA

TDAT[1] N.C.

TA[12]/

TWRB N.C. TA[10] TA[8] TA[6] VSS VDD3V3 VSS

TRS

DDATA

VDD3V3

[4]

ADATA

[6]

DDATA

[7]

DDATA

N.C. DDP N.C. VDD3V3 N.C. APL TCLK[2]

[1]

DDATA

ADATA

[4]

DDATA

[5]

ADATA

[6]

N.C. ADP N.C. VDD3V3 VSS DPL

[2]

[1]

ADATA

DDATA

[3]

ADATA

[5]

C1FP DV5 VSS VDD3V3 VSS

[2]

[0]

ADATA

VDD2V5

[3]

TA[3] N.C. TA[1] TA[0]

VDD2V5 N.C. N.C. N.C.

N.C. N.C. N.C. N.C.

N.C. N.C. N.C. SYSCLK

VDD3V3 N.C. N.C. VSS

TCK N.C. N.C. N.C.

SBI3_EN N.C. TDO TMS

TD[1] VDD2V5 SBI1_EN FASTCLK

C1FP_OUT

TCLK[1] TD[0] SBI2_EN

AACTIVE N.C. VSS VSS

[0]

VSS VDD3V3 VSS TPA2[2] D[3] D[7] D[10] D[13] A[3] A[7] A[10] RDB N.C. VDD2V5 N.C. N.C. N.C.

B

TPA2[1] VSS VDD3V3 N.C. D[0] D[4] D[8] D[11] D[14] A[4] A[8] WRB INTB N.C. N.C. N.C. N.C. N.C. TRDB N.C. N.C. N.C. N.C. VDD3V3 VSS N.C.

C

TPA1[0] TPA2[0] N.C. VDD3V3 N.C. D[1] D[5] D[9] VDD3V3 D[15] A[6] A[11] VDD3V3 N.C. N.C. N.C. N.C. VDD3V3 TA[11] TA[9] TA[7] N.C. VDD3V3 N.C. TA[5] N.C.

D

TXADDR

TXADDR

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

TPA1[2] N.C. N.C. RSTB TA[4] N.C.

[9]

[12]

TXADDR

TXADDR

TXADDR

[6]

TXADDR

[3]

TXCLK

TXDATA

[13]

TXDATA

[9]

N.C.

TXDATA

[7]

VSS VDD2V5

VSS

TXDATA

[2]

TEOP TERR RVAL RENB N.C. N.C. N.C. RCLK[0]

TRDY RPA RMOD

REOP RERR

RXPRTY

RXDATA

[12]

VDD2V5 RSX

RXDATA

[7]

RXDATA

[3]

N.C. VSS VDD3V3 N.C.

VSS VDD3V3 VSS RXCLK

VSS VSS N.C.

TPA1[1] N.C. N.C. TA[2] N.C.

[8]

[11]

TXADDR

TXADDR

VDD2V5

[5]

[10]

TXADDR

TXADDR

TXADDR

[2]

[4]

[7]

TXDATA

TXADDR

VDD3V3 VDD3V3 N.C. N.C. N.C.

[15]

[1]

TXDATA

TXDATA

TXADDR

[11]

[14]

[0]

TXDATA

TXDATA

TXDATA

[8]

[10]

[12]

N.C. TSX TXPRTY N.C. N.C. N.C. N.C.

TXDATA

TXDATA

[5]

[6]

TXDATA

TXDATA

VDD3V3 VDD2V5 RCLK[2] N.C. VSS

[4]

[3]

TXDATA

TXDATA

TMOD RD[0] RD[1] RCLK[1] RD[2]

[1]

[0]

RXDATA

[15]

RXDATA

VDD3V3 VDD3V3 TDI TRSTB N.C.

[14]

RXDATA

RXDATA

RXDATA

[13]

[11]

[9]

RXDATA

RXDATA

RXDATA

[10]

[8]

[6]

RXDATA

RXDATA

[5]

[2]

RXDATA

RXDATA

N.C. AV5 REFCLK TD[2] TCLK[0]

[4]

[1]

RXDATA

[0]

N.C. VDD3V3 N.C.

RXADDR

RXADDR

[2]

PMCTEST

RXADDR

N.C. VDD2V5 N.C. N.C. TDAT[9] N.C. N.C. TDAT[5] VSS VSS

[0]

[1]

N.C. N.C.

TDAT

[15]

TDAT

N.C.

VDD3V3

[14]

TDAT

N.C. N.C. N.C. TDAT[6] TDAT[4] TDAT[3]

[13]

TDAT

TDAT

N.C.

[12]

[10]

BOTTOM VIEW

TDAT

N.C. TDAT[7] N.C. VDD3V3

[11]

TDAT[8] N.C. N.C. VDD2V5 N.C. TDAT[2] TDAT[0]

AJUST_REQ

ADETECT

[0]

ADETECT

[1]

2625242322212019181716151413121110987654321

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 9

DATA SHEET

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

7 PIN DESCRIPTION

Table 1 – SBI Interface Signals (30)

Pin Name Type Pin

Function

No.

REFCLK Input AB3 The SBI reference clock signal (REFCLK)

provides reference timing for the SBI ADD
and DROP busses.

REFCLK is nominally a 50% duty cycle clock
of frequency 19.44 MHz ±50ppm.

FASTCLK Input Y1 The high-speed reference clock signal

(FASTCLK) is used by the FREEDM-84A672
to generate an internal clock for use when
processing DS-3 links.

FASTCLK is nominally a 50% duty cycle,
±50ppm clock having one of the following
frequencies: 51.84 MHz, 44.928 MHz or
66 MHz.

C1FP Input AE5 The C1 octet frame pulse signal (C1FP)

provides frame synchronisation for devices
connected via an SBI interface. C1FP must
be asserted for 1 REFCLK cycle every 500 µs
or multiples thereof (i.e. every 9720 n
REFCLK cycles, where n is a positive
integer). All devices interconnected via an
SBI interface must be synchronised to a
C1FP signal from a single source.

C1FP is sampled on the rising edge of
REFCLK.

Note – If the SBI bus is being operated in
synchronous mode [Ref. 3], C1FP must be
asserted for 1 REFCLK cycle every 6 ms or
multiples thereof.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 10

DATA SHEET

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

Pin Name Type Pin

Function

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

No.

C1FPOUT Output AA4 The C1 octet frame pulse output signal

(C1FPOUT) may be used to provide frame
synchronisation for devices interconnected
via an SBI interface. C1FPOUT is asserted
for 1 REFCLK cycle every 500 µs (i.e. every
9720 REFCLK cycles). If C1FPOUT is used
for synchronisation, it must be connected to
the C1FP inputs of all the devices connected
to the SBI interface.

C1FPOUT is updated on the rising edge of
REFCLK.

Note – The C1FPOUT pulse generated by
FREEDM-84A672 is not suitable for use in
systems in which the SBI bus is operated in
synchronous mode [Ref. 3].

DDATA[0]
DDATA[1]
DDATA[2]
DDATA[3]
DDATA[4]
DDATA[5]
DDATA[6]
DDATA[7]

Input AE6

AC8
AD8
AE8
AC10
AE9
AF9
AE10

The SBI DROP bus data signals
(DDATA[7:0]) contain the time division
multiplexed receive data from the up to 84
independently timed links. Data from each
link is transported as a tributary within the SBI
TDM bus structure. Multiple PHY devices
can drive the SBI DROP bus at uniquely
assigned tributary column positions.

DDATA[7:0] are sampled on the rising edge of
REFCLK.

DDP Input AC6 The SBI DROP bus parity signal (DDP)

carries the even or odd parity for the DROP
bus signals. The parity calculation
encompasses the DDATA[7:0], DPL and DV5
signals.

Multiple PHY devices can drive DDP at
uniquely assigned tributary column positions.
This parity signal is intended to detect
accidental PHY source clashes in the column
assignment.

DDP is sampled on the rising edge of
REFCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 11

DATA SHEET

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

Pin Name Type Pin

Function

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

No.

DPL Input AD1 The SBI DROP bus payload signal (DPL)

indicates valid data within the SBI TDM bus
structure. This signal is asserted during all
octets making up a tributary. This signal may
be asserted during the V3 or H3 octet within a
tributary to accommodate negative timing
adjustments between the tributary rate and
the fixed TDM bus structure. This signal may
be deasserted during the octet following the
V3 or H3 octet within a tributary to
accommodate positive timing adjustments
between the tributary rate and the fixed TDM
bus structure.

Multiple PHY devices can drive DPL at
uniquely assigned tributary column positions.

DPL is sampled on the rising edge of
REFCLK.

DV5 Input AE4 The SBI DROP bus payload indicator signal

(DV5) locates the position of the floating
payloads for each tributary within the SBI
TDM bus structure. Timing differences
between the port timing and the TDM bus
timing are indicated by adjustments of this
payload indicator relative to the fixed TDM
bus structure.

Multiple PHY devices can drive DV5 at
uniquely assigned tributary column positions.
All movements indicated by this signal must
be accompanied by appropriate adjustments
in the DPL signal.

DV5 is sampled on the rising edge of
REFCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 12

DATA SHEET

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

Pin Name Type Pin

Function

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

No.

ADATA[0]
ADATA[1]
ADATA[2]
ADATA[3]
ADATA[4]
ADATA[5]
ADATA[6]
ADATA[7]

Tristat
e
Output

AF5
AD7
AE7
AF7
AD9
AF8
AD10
AC11

The SBI ADD bus data signals (ADATA[7:0])
contain the time division multiplexed transmit
data from the up to 84 independently timed
links. Data from each link is transported as a
tributary within the SBI TDM bus structure.
Multiple link layer devices can drive the SBI
ADD bus at uniquely assigned tributary
column positions. ADATA[7:0] are tristated
when the FREEDM-84A672 is not outputting
data on a particular tributary column.

ADATA[7:0] are updated on the rising edge of
REFCLK.

ADP Tristat

e
Output

AD5 The SBI ADD bus parity signal (ADP) carries

the even or odd parity for the ADD bus
signals. The parity calculation encompasses
the ADATA[7:0], APL and AV5 signals.

Multiple link layer devices can drive this
signal at uniquely assigned tributary column
positions. ADP is tristated when the
FREEDM-84A672 is not outputting data on a
particular tributary column. This parity signal
is intended to detect accidental link layer
source clashes in the column assignment.

ADP is updated on the rising edge of
REFCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 13

DATA SHEET

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

Pin Name Type Pin

Function

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

No.

APL Tristat

e
Output

AC2 The SBI ADD bus payload signal (APL)

indicates valid data within the SBI TDM bus
structure. This signal is asserted during all
octets making up a tributary. This signal may
be asserted during the V3 or H3 octet within a
tributary to accommodate negative timing
adjustments between the tributary rate and
the fixed TDM bus structure. This signal may
be deasserted during the octet following the
V3 or H3 octet within a tributary to
accommodate positive timing adjustments
between the tributary rate and the fixed TDM
bus structure.

Multiple link layer devices can drive this
signal at uniquely assigned tributary column
positions. APL is tristated when the
FREEDM-84A672 is not outputting data on a
particular tributary column.

AV5 Tristat

e
output

APL is updated on the rising edge of
REFCLK.

AB4 The SBI ADD bus payload indicator signal

(AV5) locates the position of the floating
payloads for each tributary within the SBI
TDM bus structure. Timing differences
between the port timing and the TDM bus
timing are indicated by adjustments of this
payload indicator relative to the fixed TDM
bus structure.

Multiple link layer devices can drive this
signal at uniquely assigned tributary column
positions. AV5 is tristated when the
FREEDM-84A672 is not outputting data on a
particular tributary column.

AV5 is updated on the rising edge of
REFCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 14

DATA SHEET

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

Pin Name Type Pin

Function

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

No.

AJUST_REQ Input AC12 The SBI ADD bus justification request signal

(AJUST_REQ) is used to speed up or slow
down the output data rate of the FREEDM­84A672.

Negative timing adjustments are requested by
asserting AJUST_REQ during the V3 or H3
octet, depending on the tributary type. In
response to this the FREEDM-84A672 will
send an extra byte in the V3 or H3 octet of
the next frame along with a valid APL
indicating a negative justification.

Positive timing adjustments are requested by
asserting AJUST_REQ during the octet
following the V3 or H3 octet, depending on
the tributary type. FREEDM-84A672 will
respond to this by not sending an octet during
the octet following the V3 or H3 octet of the
next frame and deasserting APL to indicate a
positive justification.

AJUST_REQ is sampled on the rising edge of
REFCLK.

AACTIVE Output AF4 The SBI ADD bus active indicator signal

(AACTIVE) is asserted whenever FREEDM­84A672 is driving the SBI ADD bus signals,
ADATA[7:0], ADP, APL and AV5.

All other Link Layer devices driving the SBI
ADD bus should monitor this signal (to detect
multiple sources accidentaly driving the bus)
and should cease driving the bus whenever a
conflict is detected.

AACTIVE is updated on the rising edge of
REFCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 15

DATA SHEET

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

Pin Name Type Pin

Function

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

No.

ADETECT[0]
ADETECT[1]

Input AD12

AF12

The SBI ADD bus conflict detection signals
(ADETECT[1:0]) may be connected to the
AACTIVE outputs of other link layer devices
sharing the SBI ADD bus. FREEDM-84A672
will immediately tristate the SBI ADD bus
signals ADATA[7:0], ADP, APL and AV5 if
either of ADETECT[1] and ADETECT[0] is
asserted.

ADETECT[1:0] are asynchronous inputs.

Table 2 – Clock/Data Interface Signals (15)

Pin Name Type Pin

Function

No.

RCLK[0]
RCLK[1]
RCLK[2]

RD[0]
RD[1]
RD[2]

Input T1

R2
P3

Input R4

R3
R1

The receive line clock signals (RCLK[2:0])
contain the recovered line clock for the 3
independently timed links. RCLK[n] must be
externally gapped during the bits or time-slots
that are not part of the transmission format
payload (i.e. not part of the HDLC packet).
RCLK[2:0] is nominally a 50% duty cycle
clock between 0 and 51.84 MHz.

The RCLK[n] inputs are invalid and should be
tied low when their associated link is not
configured for operation (i.e. SPEn_EN input
is high).

The receive data signals (RD[2:0]) contain the
recovered line data for the 3 independently
timed links. RD[2:0] contain HDLC packet
data. For certain transmission formats,
RD[2:0] may contain place holder bits or time­slots. RCLK[n] must be externally gapped
during the place holder positions in the RD[n]
stream. The FREEDM-84A672 supports a
maximum data rate of 51.84 Mbit/s on each
link. RD[2:0] are sampled on the rising edge
of the corresponding RCLK[2:0].

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 16

DATA SHEET

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

Pin Name Type Pin

Function

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

No.

TCLK[0]
TCLK[1]
TCLK[2]

Input AB1

AA3
AC1

The transmit line clock signals (TCLK[2:0])
contain the transmit clocks for the 3
independently timed links. TCLK[n] must be
externally gapped during the bits or time-slots
that are not part of the transmission format
payload (i.e. not part of the HDLC packet).
TCLK[2:0] is nominally a 50% duty cycle
clock between 0 and 51.84 MHz.

The TCLK[n] inputs are invalid and should be
tied low when their associated link is not
configured for operation (i.e. SPEn_EN input
is high).

TD[0]
TD[1]
TD[2]

Output AA2

Y4
AB2

The transmit data signals (TD[2:0]) contain
the transmit data for the 3 independently
timed links. TD[2:0] contain HDLC packet
data. For certain transmission formats,
TD[2:0] may contain place holder bits or time­slots. TCLK[n] must be externally gapped
during the place holder positions in the TD[n]
stream. The FREEDM-84A672 supports a
maximum data rate of 51.84 Mbit/s on each
link.

TD[2:0] are updated on the falling edge of the
corresponding TCLK[2:0] clock.

SPE1_EN
SPE2_EN
SPE3_EN

Input Y2

AA1
W4

The Synchronous Payload Envelope Enable
signals (SPEn_EN) configure the operation of
the clock/data inputs and the SBI Interface.
When SPEn_EN is low, the corresponding
Synchronous Payload Envelope conveyed on
the SBI interface is unused and the
corresponding independently timed link
(signals RCLK[n-1], RD[n-1], TCLK[n-1] and
TD[n-1]) is enabled. When SPEn_EN is high,
the corresponding Synchronous Payload
Envelope conveyed on the SBI interface is
enabled and the corresponding independently
timed link is disabled.

SPEn_EN are asynchronous inputs.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 17

DATA SHEET

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

Table 3 – Any-PHY Packet Interface Signals (70)

Pin Name Type Pin

Function

No.

TXCLK Input H26 The transmit clock signal (TXCLK) provides

timing for the transmit Any-PHY packet
interface. TXCLK is a nominally 50% duty
cycle, 25 to 50 MHz clock.

TXADDR[0]
TXADDR[1]
TXADDR[2]
TXADDR[3]
TXADDR[4]
TXADDR[5]
TXADDR[6]
TXADDR[7]
TXADDR[8]
TXADDR[9]
TXADDR[10]
TXADDR[11]
TXADDR[12]

Input K23

J24
H25
G26
H24
G25
F26
H23
F25
E26
G23
F24
E25

The transmit address signals (TXADDR[12:0])
provide a channel address for polling a transmit
channel FIFO. The 10 least significant bits
provide the channel number (0 to 671) while the
3 most significant bits select one of seven
possible FREEDM-84A672 devices sharing a
single external controller. (One address is
reserved as a null address.) The Tx APPI of
each FREEDM-84A672 device is identified by
the base address in the TAPI672 Control
register.

The TXADDR[12:0] signals are sampled on the
rising edge of TXCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 18

DATA SHEET

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

Pin Name Type Pin

Function

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

No.

TPA1[0]
TPA1[1]
TPA1[2]
TPA2[0]
TPA2[1]
TPA2[2]

Tristate
Output

D26
F23
E24
D25
C26
B23

The transmit packet available signals (TPA1[2:0]
and TPA2[2:0]) reflects the status of a poll of
two transmit channel FIFOs. TPA1[2:0] returns
the polled results for channel address ‘n’
provided on TXADDR[12:0] and TPA2[2:0]
returns the polled results for channel address
‘n+1’. TPAn[2] reports packet underrun events
and TPAn[1:0] report the fill state of the transmit
channel FIFO. TPAn[2] is set high when one or
more packets has underrun on the channel and

a further data transfer has occurred since it was

last polled. When TPAn[2] is set low, no packet
has underrun on the channel since the last poll.
TPAn[1:0] are coded as follows:

TPAn[1:0] = “11” => Starving
TPAn[1:0] = “10” => (Reserved)
TPAn[1:0] = “01” => Space
TPAn[1:0] = “00” => Full

A “Starving” polled response indicates that the
polled transmit channel FIFO is at risk of
underflowing and should be supplied with data
as soon as possible. A “Space” polled response
indicates that the polled transmit channel FIFO
can accept XFER[3:0] plus one blocks (16 bytes
per block) of data. A “Full” polled response
indicates that the polled transmit channel FIFO
cannot accept XFER[3:0] plus one blocks of
data. (XFER[3:0] is a per-channel
programmable value – see description of
register 0x38C.)

It is the responsibility of the external controller to
prevent channel underflow conditions by
adequately polling each channel before data
transfer.

TPAn[2:0] are tristate during reset and when a
device address other than the FREEDM­84A672’s base address is provided on
TXADDR[12:10].

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 19

DATA SHEET

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

Pin Name Type Pin

Function

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

No.

TPAn[2:0] are updated on the rising edge of

TXCLK.

TRDY Tristate

Output

U26 The transmit ready signal (TRDY) indicates the

ability of the transmit Any-PHY packet interface
(APPI) to accept data. When TRDY is set low,
the transmit APPI is unable to accept further
data. When TRDY is set high, data provided on
the transmit APPI will be accepted by the
FREEDM-84A672 device.

TRDY is asserted one TXCLK cycle after TSX is
sampled high. TRDY is asserted by the
FREEDM-84A672 device which was selected by
the in-band channel address on TXDATA[15:0]
when TSX was sampled high. If TRDY is driven
low, the external controller must hold the data
on TXDATA[15:0] until TRDY is driven high.
TRDY may be driven low for 0 or more TXCLK
cycles before it is driven high. TRDY is always
driven tristate one TXCLK cycle after it is driven
high.

TRDY is tristate during reset.

TRDY is updated on the rising edge of TXCLK.

It is recommended that TRDY be connected
externally to a weak pull-up, e.g. 10 kW.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 20

DATA SHEET

PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

Pin Name Type Pin

Function

PM7385 FREEDM-84A672

WITH ANY-PHY PACKET INTERFACE

No.

TXDATA[0]
TXDATA[1]
TXDATA[2]
TXDATA[3]
TXDATA[4]
TXDATA[5]
TXDATA[6]
TXDATA[7]
TXDATA[8]
TXDATA[9]
TXDATA[10]
TXDATA[11]
TXDATA[12]
TXDATA[13]
TXDATA[14]
TXDATA[15]

Input R24

R25
R26
P24
P25
N24
N23
M26
L25
K26
L24
K25
L23
J26
K24
J25

The transmit data signals (TXDATA[15:0])
contain the transmit Any-PHY packet interface
(APPI) data provided by the external controller.
Data must be presented in big endian order, i.e.
the byte in TXDATA[15:8] is transmitted by the
FREEDM-84A672 before the byte in
TXDATA[7:0].

The first word of each data transfer contains an
address to identify the device and channel
associated with the data being transferred. This
prepended address must be qualified with the
TSX signal. The 10 least significant bits provide
the channel number (0 to 671) while the 3 most
significant bits select one of seven possible
FREEDM-84A672 devices sharing a single
external controller. (One address is reserved as
a null address.) The FREEDM-84A672 will not
respond to channel addresses outside the range
0 to 671, nor to device addresses other than the
base address stored in the TAPI672 Control
register.

The second and any subsequent words of each
data transfer contain packet data.

The TXDATA[15:0] signals are sampled on the
rising edge of TXCLK.

TXPRTY Input M23 The transmit parity signal (TXPRTY) reflects the

odd parity calculated over the TXDATA[15:0]
signals. TXPRTY is only valid when
TXDATA[15:0] are valid.

TXPRTY is sampled on the rising edge of
TXCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 21