PMC PM7384 Datasheet

PMC-Sierra,Inc.

Frame Engine and Data Link Manager

PM7384

FREEDM-84P672

FEATURES

• Single-chip multi-channel HDLC controller with a 66 MHz, 32 bit PCI 2.1 compatible bus for configuration, monitoring and transfer of packet data.

• On-chip DMA controller with scatter/ gather capabilities.

• Supports up to 672 bi-directiona l HDLC channels assigned to a maximum of 84 channelised or unchannelised links conveyed via a

19.44 MHz Scalable Bandwidth Interconnect (SBI™) interface.

• Data on the SBI interface is divided into three Synchronous Payload Envelopes (SPEs). Each SPE can be configured indepe nd entl y t o c arry da ta for either 28 T1/J1 li nks, 21 E1 link s, or one unchannelised DS-3 link.

• Supports three bi-directional HDLC channels each assigned to an unchannelised link with arbitrary rate link of up to 51.84 MHz when SYSCLK is running at 4 5 MHz. Ea ch link m ay be configured individually to replace one of the SPEs conveyed on the SBI interface.

• For each channel, the HDLC receiver supports programmable flag sequence detection, bit de-stuffing and fr ame check sequence validation. The receiver supports the valid ation of bo th CRC-CCITT and CRC-32 frame check sequences.

• For each channel, the HDLC transmitter supports program ma ble flag sequence generation, bit stuffing and frame check s equence generat ion. The transmitter supports the generation of both CRC-CCITT and CRC-32 frame check sequences. The transmitter also aborts packets under the direction of the host or automatically when the channel underflows.

• Provides 32 Kbytes of on-chip memory for partial packet buffering in both the transmit and receive directions. This memory may be configured to support a variety of different channel configurations from a single channel with 32 Kbytes of buffering to 672 channels, each with a minimu m of 48 bytes of buffering.

• Provides a standard five signal P1149.1 JTAG test port for boundary scan board test purposes.

• Supports 3.3 Volt I/O on non-PCI signals.

Supports 3.3 Volt PCI

signaling environment.

• 352 pin enhanced ball grid array (SBGA) package.

APPLICATIONS

• PPP interfaces for routers.

• Internet/Edge Routers.

• Frame Relay/Multiservice Switch es.

• Packet-based DSLAM equipment.

• Remote Access Concentrators.

• Multiservice Access Concentrators.

BLOCK DIAGRAM

RCLK[2:0]

RD[2:0]

DDATA[7:0]

DPL DV5

DDP

ADATA[7:0]

APL AV5

ADP

AJUST_REQ

AACTIVE

ADETECT[1:0]

TD [2:0]

TCLK[2:0]

SBI

Extract

SBI

Insert

Receive Channel

Assigner

(RCAS672)

Transmit Channel Assigner

(TCAS672)

FASTCLK

C1FP

C1FPOUT

HDLC Processor

Performance

HDLC Processor

SPE3_EN

REFCLK

Receive

(RHDL672)

Monitor

(PMON)

Transmit

(THDL672)

RSTB

SYSCLK

Receive

DMA

Controller

Transmit

DMA

Controller

JTAG

TCK

TMS

PMCTEST

AD[31:0] C/BEB[3:0] PAR FRAMEB TRDYB IRDYB STOPB

PCI

Controller

(GPIC672)

TD0

TD1

DEVSELB IDSEL LOCKB REQB GNTB PERRB SERRB PCIINTB PCICLK PCICLKO M66EN

SPE1_EN

SPE2_EN

(RMAC672)

(TMAC672)

TRSTB

Frame Engine and Data Link Manager

TYPICAL APPLICATION

PM7384 FREEDM-84P672

MULTISERVICE APPLICATION

PM5342

OC-3

SPECTRA-155

PM8316

TEMUX-84

SBI Bus

PM7384

FREEDM-

84P672

PM7341

S/UNI-IMA-84

PM73122

AAL1gator-32

PCI Bus

Any-PHY

(Cell)

AAL5 SAR

Frame Relay

Interworking

Packet

Memory

Micro-

processor

N X DS-3 CHANNELIZED INTERFACE

DS-3

LIU

DS-3

LIU

DS-3

LIU

PM8316

TEMUX-84

SBI Bus

Fractional DS-3

PM7384

FREEDM-

84P672

PCI Bus

Packet

Memory

Micro-

processor

Head Office: PMC-Sierra, Inc. 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200

To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn: Document Coordinator

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

All product documentation is available on our web site at: http://www.pmc-sierra.com For corpo rate info rmation, send email to: info@pmc-sierra.com

PMC-1991024 (r2)