Datasheet PM7382-PI Datasheet (PMC)

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PMC-2010333 ISSUE 3 FRAME ENGINE AND DATA LINK MANAGER 32P256

PM7382 FREEDM-32P256

PM7382

FREEDM™-32P256

FRAME ENGINE AND DATALINK

MANAGER 32P256

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ISSUE 3: AUGUST 2001

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PUBLIC REVISION HISTORY

Issue No. Issue Date Details of Change

Issue 1 April 11, 2001 Created Document.

Issue 2 August 13, 2001 Changed Status from Advance to Released

Issue 3 August 22, 2001 Added patent information to legal footer.

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1 FEATURES...............................................................................................1

2 APPLICATIONS........................................................................................4

3 REFERENCES .........................................................................................5

4 BLOCK DIAGRAM....................................................................................6

5 DESCRIPTION .........................................................................................7

6 PIN DIAGRAM ........................................................................................10

7 PIN DESCRIPTION ................................................................................ 11

8 FUNCTIONAL DESCRIPTION ...............................................................36

8.1 HIGH SPEED MULTI-VENDOR INTEGRATION PROTOCOL

(H-MVIP) ......................................................................................36

8.2 HIGH-LEVEL DATA LINK CONTROL (HDLC) PROTOCOL.........36

8.3 RECEIVE CHANNEL ASSIGNER ................................................37

8.3.1 LINE INTERFACE TRANSLATOR (LIT) ........................39

8.3.2 LINE INTERFACE..........................................................39

8.3.3 PRIORITY ENCODER...................................................40

8.3.4 CHANNEL ASSIGNER ..................................................40

8.3.5 LOOPBACK CONTROLLER .........................................41

8.4 RECEIVE HDLC PROCESSOR / PARTIAL PACKET BUFFER...41

8.4.1 HDLC PROCESSOR .....................................................42

8.4.2 PARTIAL PACKET BUFFER PROCESSOR..................42

8.5 RECEIVE DMA CONTROLLER ...................................................44

8.5.1 DATA STRUCTURES ....................................................44

8.5.2 DMA TRANSACTION CONTROLLER...........................54

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8.5.3 WRITE DATA PIPELINE/MUX.......................................54

8.5.4 DESCRIPTOR INFORMATION CACHE........................54

8.5.5 FREE QUEUE CACHE..................................................55

8.6 PCI CONTROLLER......................................................................55

8.6.1 MASTER MACHINE ......................................................56

8.6.2 MASTER LOCAL BUS INTERFACE..............................58

8.6.3 TARGET MACHINE.......................................................59

8.6.4 CBI BUS INTERFACE ...................................................61

8.6.5 ERROR / BUS CONTROL .............................................61

8.7 TRANSMIT DMA CONTROLLER.................................................61

8.7.1 DATA STRUCTURES ....................................................62

8.7.2 TASK PRIORITIES ........................................................74

8.7.3 DMA TRANSACTION CONTROLLER...........................74

8.7.4 READ DATA PIPELINE..................................................74

8.7.5 DESCRIPTOR INFORMATION CACHE........................74

8.7.6 FREE QUEUE CACHE..................................................75

8.8 TRANSMIT HDLC CONTROLLER / PARTIAL PACKET BUFFER75

8.8.1 TRANSMIT HDLC PROCESSOR..................................75

8.8.2 TRANSMIT PARTIAL PACKET BUFFER PROCESSOR76

8.9 TRANSMIT CHANNEL ASSIGNER .............................................78

8.9.1 LINE INTERFACE TRANSLATOR (LIT) ........................80

8.9.2 LINE INTERFACE..........................................................80

8.9.3 PRIORITY ENCODER...................................................81

8.9.4 CHANNEL ASSIGNER ..................................................81

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8.10 PERFORMANCE MONITOR .......................................................82

8.11 JTAG TEST ACCESS PORT INTERFACE...................................82

8.12 PCI HOST INTERFACE ...............................................................82

9 NORMAL MODE REGISTER DESCRIPTION........................................87

9.1 PCI HOST ACCESSIBLE REGISTERS .......................................87

10 PCI CONFIGURATION REGISTER DESCRIPTION ............................250

10.1 PCI CONFIGURATION REGISTERS.........................................250

11 TEST FEATURES DESCRIPTION .......................................................261

11.1 TEST MODE REGISTERS ........................................................261

11.2 JTAG TEST PORT .....................................................................262

11.2.1 IDENTIFICATION REGISTER .....................................263

11.2.2 BOUNDARY SCAN REGISTER ..................................263

12 OPERATIONS ......................................................................................280

12.1 TOCTL CONNECTIONS............................................................280

12.2 JTAG SUPPORT........................................................................280

13 FUNCTIONAL TIMING .........................................................................287

13.1 RECEIVE H-MVIP LINK TIMING ...............................................287

13.2 TRANSMIT H-MVIP LINK TIMING.............................................288

13.3 RECEIVE NON H-MVIP LINK TIMING ......................................289

13.4 TRANSMIT NON H-MVIP LINK TIMING....................................291

13.5 PCI INTERFACE........................................................................292

13.6 BERT INTERFACE ....................................................................301

14 ABSOLUTE MAXIMUM RATINGS........................................................303

15 D.C. CHARACTERISTICS....................................................................304

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16 FREEDM-32P256 TIMING CHARACTERISTICS.................................306

17 ORDERING AND THERMAL INFORMATION ......................................316

18 MECHANICAL INFORMATION.............................................................317

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LIST OF FIGURES

FIGURE 1 – H-MVIP PROTOCOL ....................................................................36

FIGURE 2 – HDLC FRAME...............................................................................37

FIGURE 3 – CRC GENERATOR.......................................................................37

FIGURE 4 – PARTIAL PACKET BUFFER STRUCTURE..................................43

FIGURE 5 – RECEIVE PACKET DESCRIPTOR...............................................45

FIGURE 6 – RECEIVE PACKET DESCRIPTOR TABLE...................................48

FIGURE 7 – RPDRF AND RPDRR QUEUES ...................................................50

FIGURE 8 – RPDRR QUEUE OPERATION......................................................52

FIGURE 9 – RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE.........53

FIGURE 10 – GPIC ADDRESS MAP ................................................................60

FIGURE 11 – TRANSMIT DESCRIPTOR..........................................................62

FIGURE 12 – TRANSMIT DESCRIPTOR TABLE .............................................66

FIGURE 13 – TDRR AND TDRF QUEUES .......................................................68

FIGURE 14 – TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE ....70

FIGURE 15 – TD LINKING................................................................................73

FIGURE 16 – PARTIAL PACKET BUFFER STRUCTURE................................77

FIGURE 17 – INPUT OBSERVATION CELL (IN_CELL) .................................277

FIGURE 18 – OUTPUT CELL (OUT_CELL) ...................................................278

FIGURE 19 – BI-DIRECTIONAL CELL (IO_CELL) .........................................278

FIGURE 20 – LAYOUT OF OUTPUT ENABLE AND BI-DIRECTIONAL CELLS

..............................................................................................................279

FIGURE 21 – BOUNDARY SCAN ARCHITECTURE ......................................281

FIGURE 22 – TAP CONTROLLER FINITE STATE MACHINE........................283

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FIGURE 23 – RECEIVE 8.192 MBPS H-MVIP LINK TIMING .........................287

FIGURE 24 – RECEIVE 2.048 MBPS H-MVIP LINK TIMING .........................288

FIGURE 25 – TRANSMIT 8.192 MBPS H-MVIP LINK TIMING.......................288

FIGURE 26 – TRANSMIT 2.048 MBPS H-MVIP LINK TIMING.......................289

FIGURE 27 – UNCHANNELISED RECEIVE LINK TIMING ............................290

FIGURE 28 – CHANNELISED T1/J1 RECEIVE LINK TIMING .......................290

FIGURE 29 – CHANNELISED E1 RECEIVE LINK TIMING............................291

FIGURE 30 – UNCHANNELISED TRANSMIT LINK TIMING..........................291

FIGURE 31 – CHANNELISED T1/J1 TRANSMIT LINK TIMING.....................292

FIGURE 32 – CHANNELISED E1 TRANSMIT LINK TIMING .........................292

FIGURE 33 – PCI READ CYCLE ....................................................................294

FIGURE 34 – PCI WRITE CYCLE ..................................................................295

FIGURE 35 – PCI TARGET DISCONNECT ....................................................296

FIGURE 36 – PCI TARGET ABORT................................................................297

FIGURE 37 – PCI BUS REQUEST CYCLE ....................................................297

FIGURE 38 – PCI INITIATOR ABORT TERMINATION ...................................298

FIGURE 39 – PCI EXCLUSIVE LOCK CYCLE ...............................................299

FIGURE 40 – PCI FAST BACK TO BACK.......................................................301

FIGURE 41 – RECEIVE BERT PORT TIMING ...............................................301

FIGURE 42 – TRANSMIT BERT PORT TIMING.............................................302

FIGURE 43 – RECEIVE DATA & FRAME PULSE TIMING (2.048 MBPS H-MVIP

MODE) ..................................................................................................308

FIGURE 44 – RECEIVE DATA & FRAME PULSE TIMING (8.192 MBPS H-MVIP

MODE) ..................................................................................................308

FIGURE 45 – RECEIVE DATA TIMING (NON H-MVIP MODE) ......................309

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FIGURE 46 – BERT INPUT TIMING ...............................................................309

FIGURE 47 – TRANSMIT DATA & FRAME PULSE TIMING (2.048 MBPS

H-MVIP MODE)..................................................................................... 311

FIGURE 48 – TRANSMIT DATA & FRAME PULSE TIMING (8.192 MBPS

H-MVIP MODE).....................................................................................312

FIGURE 49 – TRANSMIT DATA TIMING (NON H-MVIP MODE)....................312

FIGURE 50 – BERT OUTPUT TIMING ...........................................................313

FIGURE 51 – PCI INTERFACE TIMING .........................................................314

FIGURE 52 – JTAG PORT INTERFACE TIMING............................................315

FIGURE 53 – 329 PIN PLASTIC BALL GRID ARRAY (PBGA) .......................317

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LIST OF TABLES

TABLE 1 – LINE SIDE INTERFACE SIGNALS (154)........................................ 11

TABLE 2 – PCI HOST INTERFACE SIGNALS (52) ..........................................21

TABLE 3 – MISCELLANEOUS INTERFACE SIGNALS (58).............................30

TABLE 4 – PRODUCTION TEST INTERFACE SIGNALS (0 - MULTIPLEXED)31

TABLE 5 – POWER AND GROUND SIGNALS (65) .........................................33

TABLE 6 – RECEIVE PACKET DESCRIPTOR FIELDS....................................45

TABLE 7 – RPDRR QUEUE ELEMENT............................................................51

TABLE 8 – RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE FIELDS

................................................................................................................53

TABLE 9 – TRANSMIT DESCRIPTOR FIELDS................................................63

TABLE 10 – TRANSMIT DESCRIPTOR REFERENCE.....................................69

TABLE 11 – TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE

FIELDS ...................................................................................................71

TABLE 12 – NORMAL MODE PCI HOST ACCESSIBLE REGISTER MEMORY

MAP ........................................................................................................82

TABLE 13 – PCI CONFIGURATION REGISTER MEMORY MAP.....................86

TABLE 14 – BIG ENDIAN FORMAT................................................................ 117

TABLE 15 – LITTLE ENDIAN FORMAT .......................................................... 117

TABLE 16 - RECEIVE LINKS #0 TO #2 CONFIGURATION ...........................128

TABLE 17 - RECEIVE LINKS #3 TO #31 CONFIGURATION .........................130

TABLE 18 – CRC[1:0] SETTINGS...................................................................137

TABLE 19 – RPQ_RDYN[2:0] SETTINGS ......................................................148

TABLE 20 – RPQ_LFN[1:0] SETTINGS..........................................................149

TABLE 21 – RPQ_SFN[1:0] SETTINGS .........................................................149

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TABLE 22 – TDQ_RDYN[2:0] SETTINGS.......................................................183

TABLE 23 – TDQ_FRN[1:0] SETTINGS .........................................................183

TABLE 24 – CRC[1:0] SETTINGS................................................................... 211

TABLE 25 – FLAG[2:0] SETTINGS.................................................................217

TABLE 26 – LEVEL[3:0]/TRANS SETTINGS ..................................................219

TABLE 27 - TRANSMIT LINKS #0 TO #2 CONFIGURATION.........................237

TABLE 28 - TRANSMIT LINKS #3 TO #31 CONFIGURATION.......................239

TABLE 29 – TEST MODE REGISTER MEMORY MAP ..................................262

TABLE 30 – INSTRUCTION REGISTER ........................................................263

TABLE 31 – BOUNDARY SCAN CHAIN .........................................................263

TABLE 32 – FREEDM–TOCTL CONNECTIONS ............................................280

TABLE 33 – FREEDM-32P256 ABSOLUTE MAXIMUM RATINGS.................303

TABLE 34 – FREEDM-32P256 D.C. CHARACTERISTICS.............................304

TABLE 35 – FREEDM-32P256 LINK INPUT (FIGURE 43 TO FIGURE 46)....306

TABLE 36 – FREEDM-32P256 LINK OUTPUT (FIGURE 47 TO FIGURE 50)309

TABLE 37 – PCI INTERFACE (FIGURE 51) ...................................................313

TABLE 38 – JTAG PORT INTERFACE (FIGURE 52)......................................314

TABLE 39 – FREEDM-32P256 ORDERING INFORMATION..........................316

TABLE 40 – FREEDM-32P256 THERMAL INFORMATION ............................316

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1 FEATURES

· Single-chip multi-channel HDLC controller with a 66 MHz, 32 bit Peripheral Component Interconnect (PCI) Revision 2.1 bus for configuration, monitoring and transfer of packet data, with an on-chip DMA controller with scatter/ gather capabilities.

· Supports up to 256 bi-directional HDLC channels assigned to a maximum of 32 H-MVIP digital telephony buses at 2.048 Mbps per link. The links are grouped into 4 logical groups of 8 links. A common clock and a type 0 frame pulse is shared among links in each logical group. The number of time-slots assigned to an HDLC channel is programmable from 1 to 32.

· Supports up to 256 bi-directional HDLC channels assigned to a maximum of 8 H-MVIP digital telephony buses at 8.192 Mbps per link. The links share a common clock and a type 0 frame pulse. The number of time-slots assigned to an HDLC channel is programmable from 1 to 128.

· Supports up to 256 bi-directional HDLC channels assigned to a maximum of 32 channelised T1/J1 or E1 links. The number of time-slots assigned to an HDLC channel is programmable from 1 to 24 (for T1/J1) and from 1 to 31 (for E1).

· Supports up to 32 bi-directional HDLC channels each assigned to an unchannelised arbitrary rate link, subject to a maximum aggregate link clock rate of 64 MHz in each direction. Channels assigned to links 0 to 2 support a clock rate of up to 51.84 MHz. Channels assigned to links 3 to 31 support a clock rate of up to 10 MHz.

· Supports three bi-directional HDLC channels each assigned to an unchannelised arbitrary rate link of up to 51.84 MHz when SYSCLK is running at 45 MHz.

· Supports a mix of up to 32 channelised, unchannelised and H-MVIP links, subject to the constraint of a maximum of 256 channels and a maximum aggregate link clock rate of 64 MHz in each direction.

· Links configured for channelised T1/J1/E1 or unchannelised operation support the gapped-clock method for determining time-slots which is backwards compatible with the FREEDM-8 and FREEDM-32 devices.

· For each channel, the HDLC receiver supports programmable flag sequence detection, bit de-stuffing and frame check sequence validation. The receiver

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supports the validation of both CRC-CCITT and CRC-32 frame check sequences.

· For each channel, the receiver checks for packet abort sequences, octet aligned packet length and for minimum and maximum packet length. The receiver supports filtering of packets that are larger than a user specified maximum value.

· Alternatively, for each channel, the receiver supports a transparent mode where each octet is transferred transparently to host memory. For channelised links, the octets are aligned with the receive time-slots.

· For each channel, time-slots are selectable to be in 56 kbits/s format or 64 kbits/s clear channel format.

· For each channel, the HDLC transmitter supports programmable flag sequence generation, bit stuffing and frame check sequence generation. The transmitter supports the generation of both CRC-CCITT and CRC-32 frame check sequences. The transmitter also aborts packets under the direction of the host or automatically when the channel underflows.

· Supports two levels of non-preemptive packet priority on each transmit channel. Low priority packets will not begin transmission until all high priority packets are transmitted.

· Alternatively, for each channel, the transmitter supports a transparent mode where each octet is inserted transparently from host memory. For channelised links, the octets are aligned with the transmit time-slots.

· Provides 32 Kbytes of on-chip memory for partial packet buffering in both the transmit and receive directions. This memory may be configured to support a variety of different channel configurations from a single channel with 32 Kbytes of buffering to 256 channels, each with a minimum of 48 bytes of buffering.

· Supports PCI burst sizes of up to 256 bytes for transfers of packet data.

· Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board

test purposes.

· Supports 3.3 Volt PCI signaling environments.

· Supports 5 Volt tolerant I/O (except PCI).

· Low power 2.5 Volt 0.25 mm CMOS technology.

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· 329 pin plastic ball grid array (PBGA) package.

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2 APPLICATIONS

· IETF PPP interfaces for routers

· TDM switches

· Frame Relay interfaces for ATM or Frame Relay switches and multiplexors

· FUNI or Frame Relay service inter-working interfaces for ATM switches and

multiplexors.

· Internet/Intranet access equipment.

· Packet-based DSLAM equipment.

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3 REFERENCES

1. International Organization for Standardization, ISO Standard 3309-1993, "Information Technology - Telecommunications and information exchange between systems - High-level data link control (HDLC) procedures - Frame structure", December 1993.

2. RFC-1662 - "PPP in HDLC-like Framing" Internet Engineering Task Force, July 1994.

3. PCI Special Interest Group, PCI Local Bus Specification, June 1, 1995, Version 2.1.

4. GO-MVIP, “MVIP-90 Standard”, October 1994, release 1.1.

5. GO-MVIP, “H-MVIP Standard”, January 1997, release 1.1a.

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4 BLOCK DIAGRAM

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5 DESCRIPTION

The PM7382 FREEDM-32P256 Frame Engine and Datalink Manager device is a monolithic integrated circuit that implements HDLC processing, and PCI Bus memory management functions for a maximum of 256 bi-directional channels.

The FREEDM-32P256 may be configured to support H-MVIP, channelised T1/J1/E1 or unchannelised traffic across 32 physical links.

The FREEDM-32P256 may be configured to interface with H-MVIP digital telephony buses at 2.048 Mbps. For 2.048 Mbps H-MVIP links, the FREEDM32P256 allows up to 256 bi-directional HDLC channels to be assigned to individual time-slots within a maximum of 32 H-MVIP links. The channel assignment supports the concatenation of time-slots (N x DS0) up to a maximum of 32 concatenated time-slots for each 2.048 Mbps H-MVIP link. Time-slots assigned to any particular channel need not be contiguous within the H-MVIP link. When configured for 2.048 Mbps H-MVIP operation, the FREEDM-32P256 partitions the 32 physical links into 4 logical groups of 8 links. Links 0 through 7, 8 through 15, 16 through 23 and 24 through 31 make up the 4 logical groups. Links in each logical group share a common clock and a common type 0 frame pulse in each direction.

The FREEDM-32P256 may be configured to interface with H-MVIP digital telephony buses at 8.192 Mbps. For 8.192 Mbps H-MVIP links, the FREEDM32P256 allows up to 256 bi-directional HDLC channels to be assigned to individual time-slots within a maximum of 8 H-MVIP links. The channel assignment supports the concatenation of time-slots (N x DS0) up to a maximum of 128 concatenated time-slots for each 8.192 H-MVIP link. Time-slots assigned to any particular channel need not be contiguous within the H-MVIP link. When configured for 8.192 Mbps H-MVIP operation, the FREEDM-32P256 partitions the 32 physical links into 8 logical groups of 4 links. Only the first link, which

must be located at physical links numbered 4m (0£m£7), of each logical group can be configured for 8.192 Mbps operation. The remaining 3 physical links in the logical group (numbered 4m+1, 4m+2 and 4m+3) are unused. All links configured for 8.192 Mbps H-MVIP operation will share a common type 0 frame pulse, a common frame pulse clock and a common data clock.

For channelised T1/J1/E1 links, the FREEDM-32P256 allows up to 256 bidirectional HDLC channels to be assigned to individual time-slots within a maximum of 32 independently timed T1/J1 or E1 links. The gapped clock method to determine time-slot positions as per the FREEDM-8 and FREEDM-32 devices is retained. The channel assignment supports the concatenation of time-slots (N x DS0) up to a maximum of 24 concatenated time-slots for a T1/J1

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link and 31 concatenated time-slots for an E1 link. Time-slots assigned to any particular channel need not be contiguous within the T1/J1 or E1 link.

For unchannelised links, the FREEDM-32P256 processes up to 32 bi-directional HDLC channels within 32 independently timed links. The links can be of arbitrary frame format. When limited to three unchannelised links, each link can be rated at up to 51.84 MHz provided SYSCLK is running at 45 MHz. For lower rate unchannelised links, the FREEDM-32P256 processes up to 32 links each rated at up to 10 MHz. In this case, the aggregate clock rate of all the links is limited to 64 MHz.

The FREEDM-32P256 supports mixing of up to 32 channelised T1/J1/E1, unchannelised and H-MVIP links. The total number of channels in each direction is limited to 256. The aggregate instantaneous clock rate over all 32 possible links is limited to 64 MHz.

In the receive direction, the FREEDM-32P256 performs channel assignment and packet extraction and validation. For each provisioned HDLC channel, the FREEDM-32P256 delineates the packet boundaries using flag sequence detection, and performs bit de-stuffing. Sharing of opening and closing flags, as well as sharing of zeros between flags are supported. The resulting packet data is placed into the internal 32 Kbyte partial packet buffer RAM. The partial packet buffer acts as a logical FIFO for each of the assigned channels. Partial packets are DMA'd out of the RAM, across the PCI bus and into host packet memory. The FREEDM-32P256 validates the frame check sequence for each packet, and verifies that the packet is an integral number of octets in length and is within a programmable minimum and maximum length. The receive packet status is updated before linking the packet into a receive ready queue. The FREEDM32P256 alerts the PCI Host that there are packets in a receive ready queue by, optionally, asserting an interrupt on the PCI bus.

Alternatively, in the receive direction, the FREEDM-32P256 supports a transparent operating mode. For each provisioned transparent channel, the FREEDM-32P256 directly transfers the received octets into host memory verbatim. If the transparent channel is assigned to a channelised link, then the octets are aligned to the received time-slots.

In the transmit direction, the PCI Host provides packets to transmit using a transmit ready queue. For each provisioned HDLC channel, the FREEDM32P256 DMA's partial packets across the PCI bus and into the transmit partial packet buffer. The partial packets are read out of the packet buffer by the FREEDM-32P256 and a frame check sequence is optionally calculated and inserted at the end of each packet. Bit stuffing is performed before being assigned to a particular link. The flag sequence is automatically inserted when there is no packet data for a particular channel. Sequential packets are

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PM7382 FREEDM-32P256

optionally separated by two flags (an opening flag and a closing flag) or a single flag (combined opening and closing flag). Zeros between flags are not shared. PCI bus latency may cause one or more channels to underflow, in which case, the packets are aborted, and the host is notified. For normal traffic, an abort sequence is generated, followed by inter-frame time fill characters (flags or allones bytes) until a new packet is sourced from the PCI host. No attempt is made to automatically re-transmit an aborted packet.

Alternatively, in the transmit direction, the FREEDM-32P256 supports a transparent operating mode. For each provisioned transparent channel, the FREEDM-32P256 directly inserts the transmitted octets from host memory. If the transparent channel is assigned to a channelised link, then the octets are aligned to the transmitted time-slots. If a channel underflows due to excessive PCI bus latency, an abort sequence is generated, followed by inter-frame time fill characters (flags or all-ones bytes) to indicate idle channel. Data resumes immediately when the FREEDM-32P256 receives new data from the host.

The FREEDM-32P256 is configured, controlled and monitored using the PCI bus interface. The PCI bus supports 3.3 Volt signaling. The FREEDM-32P256 is

implemented in low power 2.5 Volt 0.25 mm CMOS technology. All non-PCI FREEDM-32P256 I/O pins are 5 volt tolerant. The FREEDM-32P256 is packaged in a 329 pin plastic ball grid array (PBGA) package.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 9

RELEASED

DATA SHEET

PMC-2010333 ISSUE 3 FRAME ENGINE AND DATA LINK MANAGER 32P256

PM7382 FREEDM-32P256

6 PIN DIAGRAM

The FREEDM-32P256 is manufactured in a 329 pin plastic ball grid array package.

2322212019181716151413121110987654321

RMVCK[2] RD[16] RCLK[17] RCLK[19] RD[21] RD[22] RD[23] RD[24] RCLK[25] RCLK[27] RCLK[29] VDD2V5 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.

RFPB[2] RCLK[16] RD[18] RD[20] VDD2V5 RCLK[22] RFPB[3] RCLK[24] RCLK[26] RD[28] RD[30] RCLK[31] N.C. N.C. N.C. N.C. N.C. N.C. VDD2V5 N.C. N.C. N.C. N.C.

RD[15] RSTB RCLK[15] RCLK[18] RCLK[20] RCLK[21] RMVCK[3] RD[25] RD[27] RCLK[28] RCLK[30] RD[31] N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.

RCLK[13] RD[13] RCLK[14] RD[17] RD[19] VDD3V3 RCLK[23] VSS RD[26] VDD3V3 RD[29] VSS N.C. VDD3V3 N.C. VSS N.C. VDD3V3 N.C. N.C. N.C. N.C. N.C.

RD[12] VDD2V5 RCLK[12] RD[14] N.C. N.C. VDD2V5 N.C.

RD[11] RCLK[10] RCLK[11] VSS VSS N.C. N.C. N.C.

RD[10] RD[9] RCLK[8] RCLK[9]

RD[8] RMVCK[1] RFPB[1] VDD3V3 VDD3V3 AD[31] REQB GNTB

RCLK[7] RCLK[6] RD[6] RD[7] AD[29] AD[27] AD[28] AD[30]

SYSCLK RCLK[5] RD[5] VSS VSS VSS VSS VSS VSS VSS AD[24] AD[25] AD[26]

RD[4] RD[3] RCLK[3] RCLK[4] VSS VSS VSS VSS VSS CBEB[3] AD[22] AD[23] IDSEL

VDD2V5 RCLK[2] RD[2] VDD3V3 VSS VSS VSS VSS VSS VDD3V3 AD[21] AD[20] VDD2V5

RCLK[0] RD[1] RCLK[1] RD[0] VSS VSS VSS VSS VSS AD[16] AD[18] AD[19] AD[17]

RMV8FPC RFPB[0] RMVCK[0] VSS VSS VSS VSS VSS VSS VSS CBEB[2] FRAMEB IRDYB

RBD RMV8DC RFP8B RBCLK STOPB TRDYB DEVSELB LOCKB

TCK TMS TRSTB VDD3V3 VDD3V3 PERRB SERRB PAR

TFP8B TDO TDI TMV8DC AD[14] CBEB[1] AD[15] AD[13]

TFPB[0] TMV8FPC TMVCK[0] VSS VSS AD[10] AD[12] AD[11]

TD[0] VDD2V5 TCLK[0] TD[2] AD[6] AD[8] VDD2V5 AD[9]

TCLK[1] TD[1] TCLK[2] TD[4] TMVCK[1] VDD3V3 TD[12] VSS TCLK[15] VDD3V3 TCLK[17] VSS TD[22] VDD3V3 TD[24] VSS TCLK[27] VDD3V3 TBD N.C. AD[5] CBEB[0] AD[7]

TCLK[3] TD[3] TCLK[6] TFPB[1] TD[9] TD[10] TD[13] TCLK[14] TMVCK[2] TD[17] TCLK[18] TD[20] TCLK[20] TCLK[22] TFPB[3] TD[25] TCLK[26] TCLK[29] TCLK[30] TBCLK AD[2] AD[4] AD[3]

TD[5] TCLK[4] TCLK[7] TCLK[8] VDD2V5 TD[11] TCLK[12] TD[14] TFPB[2] TCLK[16] TD[19] TCLK[19] TD[21] TD[23] TMVCK[3] TCLK[25] TD[27] TCLK[28] VDD2V5 TD[31] PMCTEST N.C. AD[1]

TCLK[5] TD[6] TD[7] TD[8] TCLK[9] TCLK[10] TCLK[11] TCLK[13] TD[15] TD[16] TD[18] VDD2V5 TCLK[21] TCLK[23] TCLK[24] TD[26] TD[28] TD[29] TD[30] TCLK[31] N.C. M66EN AD[0]

2322212019181716151413121110987654321

BOTTOM VIEW

PCICLKO PCICLK N.C. PCIINTB

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 10

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PMC-2010333 ISSUE 3 FRAME ENGINE AND DATA LINK MANAGER 32P256

PM7382 FREEDM-32P256

7 PIN DESCRIPTION

Table 1 – Line Side Interface Signals (154)

Pin Name Type Pin

Function

No.

RCLK[0] RCLK[1] RCLK[2] RCLK[3] RCLK[4] RCLK[5] RCLK[6] RCLK[7] RCLK[8] RCLK[9] RCLK[10] RCLK[11] RCLK[12] RCLK[13] RCLK[14] RCLK[15] RCLK[16] RCLK[17] RCLK[18] RCLK[19] RCLK[20] RCLK[21] RCLK[22] RCLK[23] RCLK[24] RCLK[25] RCLK[26] RCLK[27] RCLK[28] RCLK[29] RCLK[30] RCLK[31]

Input N23

N21 M22 L21 L20 K22 J22 J23 G21 G20 F22 F21 E21 D23 D21 C21 B22 A21 C20 A20 C19 C18 B18 D17 B16 A15 B15 A14 C14 A13 C13 B12

The receive line clock signals (RCLK[31:0]) contain the recovered line clock for the 32 independently timed links. Processing of the receive links are on a priority basis, in descending order from RCLK[0] to RCLK[31]. Therefore, the highest rate link should be connected to RCLK[0] and the lowest to RCLK[31].

For channelised T1/J1 or E1 links, RCLK[n] must be gapped during the framing bit (for T1/J1 interfaces) or during time-slot 0 (for E1 interfaces) of the RD[n] stream. The FREEDM32P256 uses the gapping information to determine the time-slot alignment in the receive stream. RCLK[31:0] is nominally a 50% duty cycle clock of frequency 1.544 MHz for T1/J1 links and 2.048 MHz for E1 links.

For unchannelised links, RCLK[n] must be externally gapped during the bits or time-slots that are not part of the transmission format payload (i.e. not part of the HDLC packet). RCLK[2:0] is nominally a 50% duty cycle clock between 0 and 51.84 MHz. RCLK[31:3] is nominally a 50% duty cycle clock between 0 and 10 MHz.

The RCLK[n] inputs are invalid and should be forced to a low state when their associated link is configured for operation in H-MVIP mode.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 11

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DATA SHEET

PMC-2010333 ISSUE 3 FRAME ENGINE AND DATA LINK MANAGER 32P256

Pin Name Type Pin

Function

PM7382 FREEDM-32P256

No.

RD[0] RD[1] RD[2] RD[3] RD[4] RD[5] RD[6] RD[7] RD[8] RD[9] RD[10] RD[11] RD[12] RD[13] RD[14] RD[15] RD[16] RD[17] RD[18] RD[19] RD[20] RD[21] RD[22] RD[23] RD[24] RD[25] RD[26] RD[27] RD[28] RD[29] RD[30] RD[31]

Input N20

N22 M21 L22 L23 K21 J21 J20 H23 G22 G23 F23 E23 D22 E20 C23 A22 D20 B21 D19 B20 A19 A18 A17 A16 C16 D15 C15 B14 D13 B13 C12

The receive data signals (RD[31:0]) contain the recovered line data for the 32 independently timed links in normal mode (PMCTEST set low). Processing of the receive links is on a priority basis, in descending order from RD[0] to RD[31]. Therefore, the highest rate link should be connected to RD[0] and the lowest to RD[31].

For H-MVIP links, RD[n] contains 32/128 timeslots, depending on the H-MVIP data rate configured (2.048 or 8.192 Mbps). When configured for 2.048 Mbps H-MVIP operation, RD[31:24], RD[23:16], RD[15:8] and RD[7:0] are sampled on every 2nd rising edge of RMVCK[3], RMVCK[2], RMVCK[1] and RMVCK[0] respectively (at the ¾ point of the bit interval). When configured for 8.192 Mbps H-MVIP

operation, RD[4m] (0£m£7) are sampled on every 2nd rising edge of RMV8DC (at the ¾ point of the bit interval).

For channelised links, RD[n] contains the 24 (T1/J1) or 31 (E1) time-slots that comprise the channelised link. RCLK[n] must be gapped during the T1/J1 framing bit position or the E1 frame alignment signal (time-slot 0). The FREEDM-32P256 uses the location of the gap to determine the channel alignment on RD[n]. RD[31:0] are sampled on the rising edge of the corresponding RCLK[31:0].

For unchannelised links, RD[n] contains the HDLC packet data. For certain transmission formats, RD[n] may contain place holder bits or time-slots. RCLK[n] must be externally gapped during the place holder positions in the RD[n] stream. The FREEDM-32P256 supports a maximum data rate of 10 Mbit/s on an individual RD[31:3] link and a maximum data rate of 51.84 Mbit/s on RD[2:0]. RD[31:0] are sampled on the rising edge of the corresponding RCLK[31:0].

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 12

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PMC-2010333 ISSUE 3 FRAME ENGINE AND DATA LINK MANAGER 32P256

Pin Name Type Pin

Function

PM7382 FREEDM-32P256

No.

RMVCK[0] RMVCK[1] RMVCK[2] RMVCK[3]

Input P21

H22 A23 C17

The receive MVIP data clock signals (RMVCK[3:0]) provide the receive data clock for the 32 links when configured to operate in 2.048 Mbps H-MVIP mode.

When configured for 2.048 Mbps H-MVIP operation, the 32 links are partitioned into 4 groups of 8, and each group of 8 links share a common data clock. RMVCK[0], RMVCK[1], RMVCK[2] and RMVCK[3] sample the data on links RD[7:0], RD[15:8], RD[23:16] and RD[31:24] respectively. Each RMVCK[n] is nominally a 50% duty cycle clock with a frequency of 4.096 MHz.

RMVCK[n] is ignored and should be tied low when no physical link within the associated logical group of 8 links is configured for operation in 2.048 Mbps H-MVIP mode.

RFPB[0] RFPB[1] RFPB[2] RFPB[3]

Input P22

H21 B23 B17

The receive frame pulse signals (RFPB[3:0]) reference the beginning of each frame for the 32 links when configured for operation in 2.048 Mbps H-MVIP mode.

When configured for 2.048 Mbps H-MVIP operation, the 32 links are partitioned into 4 groups of 8, and each group of 8 links share a common frame pulse. RFPB[0], RFPB[1], RFPB[2] and RFPB[3] reference the beginning of a frame on links RD[7:0], RD[15:8], RD[23:16] and RD[31:24] respectively.

When configured for operation in 2.048 Mbps HMVIP mode, RFPB[n] is sampled on the falling edge of RMVCK[n]. Otherwise, RFPB[n] is ignored and should be tied low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 13

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DATA SHEET

PMC-2010333 ISSUE 3 FRAME ENGINE AND DATA LINK MANAGER 32P256

Pin Name Type Pin

Function

PM7382 FREEDM-32P256

No.

RFP8B Input R21 The receive frame pulse for 8.192 Mbps H-MVIP

signal (RFP8B) references the beginning of each frame for links configured for operation in

8.192 Mbps H-MVIP mode.

RFP8B references the beginning of a frame for any link configured for 8.192 Mbps H-MVIP

operation. Only links 4m (0£m£7) may be configured for 8.192 Mbps H-MVIP operation.

When one or more links are configured for

8.192 Mbps H-MVIP operation, RFP8B is sampled on the falling edge of RMV8FPC. When no links are configured for 8.192 Mbps HMVIP operation, RFP8B is ignored and should be tied low.

RMV8FPC Input P23 The receive 8.192 Mbps H-MVIP frame pulse

clock signal (RMV8FPC) provides the receive frame pulse clock for links configured for operation in 8.192 Mbps H-MVIP mode.

RMV8FPC is used to sample RFP8B. RMV8FPC is nominally a 50% duty cycle, clock with a frequency of 4.096 MHz. The falling edge of RMV8FPC must be aligned with the falling edge of RMV8DC with no more than ±10 ns skew.

RMV8FPC is ignored and should be tied low when no physical links are configured for operation in 8.192 Mbps H-MVIP mode.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 14

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DATA SHEET

PMC-2010333 ISSUE 3 FRAME ENGINE AND DATA LINK MANAGER 32P256

Pin Name Type Pin

Function

PM7382 FREEDM-32P256

No.

RMV8DC Input R22 The receive 8.192 Mbps H-MVIP data clock

signal (RMV8DC) provides the receive data clock for links configured to operate in 8.192 Mbps H-MVIP mode.

RMV8DC is used to sample data on RD[4m] (0£m£7) when link 4m is configured for 8.192

Mbps H-MVIP operation. RMV8DC is nominally a 50% duty cycle clock with a frequency of

16.384 MHz.

RMV8DC is ignored and should be tied low when no physical links are configured for operation in 8.192 Mbps H-MVIP mode.

RBD Tristate

Output

R23 The receive BERT data signal (RBD) contains

the receive bit error rate test data. RBD reports the data on the selected one of the receive data signals (RD[31:0]) and is updated on the falling edge of RBCLK. RBD may be tristated by setting the RBEN bit in the FREEDM-32P256 Master BERT Control register low. BERT is not supported for H-MVIP links.

RBCLK Tristate

R20 The receive BERT clock signal (RBCLK)

Output

contains the receive bit error rate test clock. RBCLK is a buffered version of the selected one of the receive clock signals (RCLK[31:0]). RBCLK may be tristated by setting the RBEN bit in the FREEDM-32P256 Master BERT Control register low. BERT is not supported for H-MVIP links.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 15

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DATA SHEET

PMC-2010333 ISSUE 3 FRAME ENGINE AND DATA LINK MANAGER 32P256

Pin Name Type Pin

Function

PM7382 FREEDM-32P256

No.

TCLK[0] TCLK[1] TCLK[2] TCLK[3] TCLK[4] TCLK[5] TCLK[6] TCLK[7] TCLK[8] TCLK[9] TCLK[10] TCLK[11] TCLK[12] TCLK[13] TCLK[14] TCLK[15] TCLK[16] TCLK[17] TCLK[18] TCLK[19] TCLK[20] TCLK[21] TCLK[22] TCLK[23] TCLK[24] TCLK[25] TCLK[26] TCLK[27] TCLK[28] TCLK[29] TCLK[30] TCLK[31]

Input W21

Y23 Y21 AA23 AB22 AC23 AA21 AB21 AB20 AC19 AC18 AC17 AB17 AC16 AA16 Y15 AB14 Y13 AA13 AB12 AA11 AC11 AA10 AC10 AC9 AB8 AA7 Y7 AB6 AA6 AA5 AC4

The transmit line clock signals (TCLK[31:0]) contain the transmit clocks for the 32 independently timed links. Processing of the transmit links is on a priority basis, in descending order from TCLK[0] to TCLK[31]. Therefore, the highest rate link should be connected to TCLK[0] and the lowest to TCLK[31].

For channelised T1/J1 or E1 links, TCLK[n] must be gapped during the framing bit (for T1/J1 interfaces) or during time-slot 0 (for E1 interfaces) of the TD[n] stream. The FREEDM32P256 uses the gapping information to determine the time-slot alignment in the transmit stream.

For unchannelised links, TCLK[n] must be externally gapped during the bits or time-slots that are not part of the transmission format payload (i.e. not part of the HDLC packet).

TCLK[2:0] is nominally a 50% duty cycle clock between 0 and 51.84 MHz. TCLK[31:3] is nominally a 50% duty cycle clock between 0 and 10 MHz. Typical values for TCLK[31:0] include

1.544 MHz (for T1/J1 links) and 2.048 MHz (for E1 links).

The TCLK[n] inputs are invalid and should be tied low when their associated link is configured for operation in H-MVIP mode.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 16

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DATA SHEET

PMC-2010333 ISSUE 3 FRAME ENGINE AND DATA LINK MANAGER 32P256

Pin Name Type Pin

Function

PM7382 FREEDM-32P256

No.

TD[0] TD[1] TD[2] TD[3] TD[4] TD[5] TD[6] TD[7] TD[8] TD[9] TD[10] TD[11] TD[12] TD[13] TD[14] TD[15] TD[16] TD[17] TD[18] TD[19] TD[20] TD[21] TD[22] TD[23] TD[24] TD[25] TD[26] TD[27] TD[28] TD[29] TD[30] TD[31]

Output

W23 Y22 W20 AA22 Y20 AB23 AC22 AC21 AC20 AA19 AA18 AB18 Y17 AA17 AB16 AC15 AC14 AA14 AC13 AB13 AA12 AB11 Y11 AB10 Y9 AA8 AC8 AB7 AC7 AC6 AC5 AB4

The transmit data signals (TD[31:0]) contain the transmit data for the 32 independently timed links in normal mode (PMCTEST set low). Processing of the transmit links is on a priority basis, in descending order from TD[0] to TD[31]. Therefore, the highest rate link should be connected to TD[0] and the lowest to TD[31].

For H-MVIP links, TD[n] contain 32/128 timeslots, depending on the H-MVIP data rate configured (2.048 or 8.192 Mbps). When configured for 2.048 Mbps H-MVIP operation, TD[31:24], TD[23:16], TD[15:8] and TD[7:0] are updated on every 2nd falling edge of TMVCK[3], TMVCK[2], TMVCK[1] and TMVCK[0] respectively. When configured for 8.192 Mbps

H-MVIP operation, TD[4m] (0£m£7) are updated on every 2nd falling edge of TMV8DC.

For channelised links, TD[n] contains the 24 (T1/J1) or 31 (E1) time-slots that comprise the channelised link. TCLK[n] must be gapped during the T1/J1 framing bit position or during the E1 frame alignment signal (time-slot 0). The FREEDM-32P256 uses the location of the gap to determine the channel alignment on TD[n]. TD[31:0] are updated on the falling edge of the corresponding TCLK[31:0].

For unchannelised links, TD[n] contains the HDLC packet data. For certain transmission formats, TD[n] may contain place holder bits or time-slots. TCLK[n] must be externally gapped during the place holder positions in the TD[n] stream. The FREEDM-32P256 supports a maximum data rate of 10 Mbit/s on an individual TD[31:3] link and a maximum data rate of 51.84 Mbit/s on TD[2:0].

TD[31:0] are updated on the falling edge of the corresponding TCLK[31:0] clock.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 17

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DATA SHEET

PMC-2010333 ISSUE 3 FRAME ENGINE AND DATA LINK MANAGER 32P256

Pin Name Type Pin

Function

PM7382 FREEDM-32P256

No.

TMVCK[0] TMVCK[1] TMVCK[2] TMVCK[3]

Input V21

Y19 AA15 AB9

The transmit MVIP data clock signals (TMVCK[3:0]) provide the transmit data clocks for the 32 links when configured to operate in

2.048 Mbps H-MVIP mode.

When configured for 2.048 Mbps H-MVIP operation, the 32 links are partitioned into 4 groups of 8, and each group of 8 links share a common clock. TMVCK[0], TMVCK[1], TMVCK[2] and TMVCK[3] update the data on links TD[7:0], TD[15:8], TD[23:16] and TD[31:24] respectively. Each TMVCK[n] is nominally a 50% duty cycle clock with a frequency of 4.096 MHz.

TMVCK[n] is ignored and should be tied low when no physical link within the associated group of 8 logical links is configured for operation in 2.048 Mbps H-MVIP mode.

TFPB[0] TFPB[1] TFPB[2] TFPB[3]

Input V23

AA20 AB15 AA9

The transmit frame pulse signals (TFPB[3:0]) reference the beginning of each frame when configured for operation in 2.048 Mbps H-MVIP mode.

When configured for 2.048 Mbps H-MVIP operation, the 32 links are partitioned into 4 groups of 8, and each group of 8 links share a common frame pulse. TFPB[0], TFPB[1], TFPB[2] and TFPB[3] reference the beginning of a frame on links TD[7:0], TD[15:8], TD[23:16] and TD[31:24] respectively.

When configured for operation in 2.048 Mbps HMVIP mode, TFPB[n] is sampled on the falling edge of TMVCK[n]. Otherwise, TFPB[n] is ignored and should be tied low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 18

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DATA SHEET

PMC-2010333 ISSUE 3 FRAME ENGINE AND DATA LINK MANAGER 32P256

Pin Name Type Pin

Function

PM7382 FREEDM-32P256

No.

TFP8B Input U23 The transmit frame pulse for 8.192 Mbps H-

MVIP signal (TFP8B) references the beginning of each frame for links configured to operate in

8.192 Mbps H-MVIP mode.

TFP8B references the beginning of a frame for any link configured for 8.192 Mbps H-MVIP

operation. Only links 4m (0£m£7) may be configured for 8.192 Mbps H-MVIP operation.

When one or more links are configured for

8.192 Mbps H-MVIP operation, TFP8B is sampled on the falling edge of TMV8FPC. When no links are configured for 8.192 Mbps HMVIP operation, TFPB[n] is ignored and should be tied low.

TMV8FPC Input V22 The transmit 8.192 Mbps H-MVIP frame pulse

clock signal (TMV8FPC) provides the transmit frame pulse clock for links configured for operation in 8.192 Mbps H-MVIP mode.

TMV8FPC is used to sample TFP8B. TMV8FPC is nominally a 50% duty cycle, clock with a frequency of 4.096 MHz. The falling edge of TMV8FPC must be aligned with the falling edge of TMV8DC with no more than ±10 ns skew.

TMV8FPC[n] is ignored and should be tied low when no physical links are configured for operation in 8.192 Mbps H-MVIP mode.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 19

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DATA SHEET

PMC-2010333 ISSUE 3 FRAME ENGINE AND DATA LINK MANAGER 32P256

Pin Name Type Pin

Function

PM7382 FREEDM-32P256

No.

TMV8DC Input U20 The transmit 8.192 Mbps H-MVIP data clock

signal (TMV8DC) provides the transmit data clock for links configured to operate in 8.192 Mbps H-MVIP mode.

TMV8DC is used to update data on TD[4m] (0£m£7) when link 4m is configured for 8.192

Mbps H-MVIP operation. TMV8DC is nominally a 50% duty cycle clock with a frequency of

16.384 MHz.

TMV8DC is ignored and should be tied low when no physical links are configured for operation in 8.192 Mbps H-MVIP mode.

TBD Input Y5 The transmit BERT data signal (TBD) contains

the transmit bit error rate test data. When the TBERTEN bit in the BERT Control register is set high, the data on TBD is transmitted on the selected one of the transmit data signals (TD[31:0]). TBD is sampled on the rising edge of TBCLK. BERT is not supported for H-MVIP links.

TBCLK Tristate

AA4 The transmit BERT clock signal (TBCLK)

Output

contains the transmit bit error rate test clock. TBCLK is a buffered version of the selected one of the transmit clock signals (TCLK[31:0]). TBCLK may be tristated by setting the TBEN bit in the FREEDM-32P256 Master BERT Control register low. BERT is not supported for H-MVIP links.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 20

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DATA SHEET

PMC-2010333 ISSUE 3 FRAME ENGINE AND DATA LINK MANAGER 32P256

PM7382 FREEDM-32P256

Table 2 – PCI Host Interface Signals (52)

Pin Name Type Pin

Function

No.

PCICLK Input G3 The PCI clock signal (PCICLK) provides timing

for PCI bus accesses. PCICLK is a nominally 50% duty cycle, 25 to 66 MHz clock.

PCICLKO Output G4 The PCI clock output signal (PCICLKO) is a

buffered version of the PCICLK. PCICLKO may be used to derive the SYSCLK input.

C/BEB[0] C/BEB[1] C/BEB[2] C/BEB[3]

I/O Y2

U3 P3 L4

The PCI bus command and byte enable bus (C/BEB[3:0]) contains the bus command or the byte valid indications. During the first clock cycle of a transaction, C/BEB[3:0] contains the bus command code. For subsequent clock cycles, C/BEB[3:0] identifies which bytes on the AD[31:0] bus carry valid data. C/BEB[3] is associated with byte 3 (AD[31:24]) while C/BEB[0] is associated with byte 0 (AD[7:0]). When C/BEB[n] is set high, the associated byte is invalid. When C/BEB[n] is set low, the associated byte is valid.

When the FREEDM-32P256 is the initiator, C/BEB[3:0] is an output bus.

When the FREEDM-32P256 is the target, C/BEB[3:0] is an input bus.

When the FREEDM-32P256 is not involved in the current transaction, C/BEB[3:0] is tristated.

As an output bus, C/BEB[3:0] is updated on the rising edge of PCICLK. As an input bus, C/BEB[3:0] is sampled on the rising edge of PCICLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 21

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PMC-2010333 ISSUE 3 FRAME ENGINE AND DATA LINK MANAGER 32P256

Pin Name Type Pin

Function

PM7382 FREEDM-32P256

No.

AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[30] AD[31]

I/O AC1

AB1 AA3 AA1 AA2 Y3 W4 Y1 W3 W1 V3 V1 V2 U1 U4 U2 N4 N1 N3 N2 M2 M3 L3 L2 K3 K2 K1 J3 J2 J4 J1

The PCI address and data bus (AD[31:0]) carries the PCI bus multiplexed address and data. During the first clock cycle of a transaction, AD[31:0] contains a physical byte address. During subsequent clock cycles of a transaction, AD[31:0] contains data.

A transaction is defined as an address phase followed by one or more data phases. When Little-Endian byte formatting is selected, AD[31:24] contain the most significant byte of a DWORD while AD[7:0] contain the least significant byte. When Big-Endian byte formatting is selected. AD[7:0] contain the most significant byte of a DWORD while AD[31:24] contain the least significant byte. When the FREEDM-32P256 is the initiator, AD[31:0] is an output bus during the first (address) phase of a transaction. For write transactions, AD[31:0] remains an output bus for the data phases of the transaction. For read transactions, AD[31:0] is an input bus during the data phases.

When the FREEDM-32P256 is the target, AD[31:0] is an input bus during the first (address) phase of a transaction. For write transactions, AD[31:0] remains an input bus during the data phases of the transaction. For read transactions, AD[31:0] is an output bus during the data phases.

When the FREEDM-32P256 is not involved in the current transaction, AD[31:0] is tristated.

As an output bus, AD[31:0] is updated on the rising edge of PCICLK. As an input bus, AD[31:0] is sampled on the rising edge of PCICLK.

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PMC-2010333 ISSUE 3 FRAME ENGINE AND DATA LINK MANAGER 32P256

Pin Name Type Pin

Function

PM7382 FREEDM-32P256

No.

PAR I/O T1 The parity signal (PAR) indicates the parity of the

AD[31:0] and C/BEB[3:0] buses. Even parity is calculated over all 36 signals in the buses regardless of whether any or all the bytes on the AD[31:0] are valid. PAR always reports the parity of the previous PCICLK cycle. Parity errors detected by the FREEDM-32P256 are indicated on output PERRB and in the FREEDM-32P256 Interrupt Status register.

When the FREEDM-32P256 is the initiator, PAR is an output for writes and an input for reads.

When the FREEDM-32P256 is the target, PAR is an input for writes and an output for reads.

When the FREEDM-32P256 is not involved in the current transaction, PAR is tristated.

As an output signal, PAR is updated on the rising edge of PCICLK. As an input signal, PAR is sampled on the rising edge of PCICLK.

FRAMEB I/O P2 The active low cycle frame signal (FRAMEB)

identifies a transaction cycle. When FRAMEB transitions low, the start of a bus transaction is indicated. FRAMEB remains low to define the duration of the cycle. When FRAMEB transitions high, the last data phase of the current transaction is indicated.

When the FREEDM-32P256 is the initiator, FRAMEB is an output.

When the FREEDM-32P256 is the target, FRAMEB is an input.

When the FREEDM-32P256 is not involved in the current transaction, FRAMEB is tristated.

As an output signal, FRAMEB is updated on the rising edge of PCICLK. As an input signal, FRAMEB is sampled on the rising edge of PCICLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 23

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DATA SHEET

PMC-2010333 ISSUE 3 FRAME ENGINE AND DATA LINK MANAGER 32P256

Pin Name Type Pin

Function

PM7382 FREEDM-32P256

No.

TRDYB I/O R3 The active low target ready signal (TRDYB)

indicates when the target is ready to start or continue with a transaction. TRDYB works in conjunction with IRDYB to complete transaction data phases. During a transaction in progress, TRDYB is set high to indicate that the target cannot complete the current data phase and to force a wait state. TRDYB is set low to indicate that the target can complete the current data phase. The data phase is completed when TRDYB is set low and the initiator ready signal (IRDYB) is also set low.

When the FREEDM-32P256 is the initiator, TRDYB is an input.

When the FREEDM-32P256 is the target, TRDYB is an output. During accesses to FREEDM-32P256 registers, TRDYB is set high to extend data phases over multiple PCICLK cycles.

When the FREEDM-32P256 is not involved in the current transaction, TRDYB is tristated.

As an output signal, TRDYB is updated on the rising edge of PCICLK. As an input signal, TRDYB is sampled on the rising edge of PCICLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 24

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PMC-2010333 ISSUE 3 FRAME ENGINE AND DATA LINK MANAGER 32P256

Pin Name Type Pin

Function

PM7382 FREEDM-32P256

No.

IRDYB I/O P1 The active low initiator ready (IRDYB) signal is

used to indicate whether the initiator is ready to start or continue with a transaction. IRDYB works in conjunction with TRDYB to complete transaction data phases. When IRDYB is set high and a transaction is in progress, the initiator is indicating it cannot complete the current data phase and is forcing a wait state. When IRDYB is set low and a transaction is in progress, the initiator is indicating it has completed the current data phase. The data phase is completed when IRDYB is set low and the target ready signal (IRDYB) is also set low.

When the FREEDM-32P256 is the initiator, IRDYB is an output.

When the FREEDM-32P256 is the target, IRDYB is an input.

When the FREEDM-32P256 is not involved in the current transaction, IRDYB is tristated.

IRDYB is updated on the rising edge of PCICLK or sampled on the rising edge of PCICLK depending on whether it is an output or an input.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 25

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Pin Name Type Pin

Function

PM7382 FREEDM-32P256

No.

STOPB I/O R4 The active low stop signal (STOPB) requests the

initiator to stop the current bus transaction. When STOPB is set high by a target, the initiator continues with the transaction. When STOPB is set low, the initiator will stop the current transaction.

When the FREEDM-32P256 is the initiator, STOPB is an input. When STOPB is sampled low, the FREEDM-32P256 will terminate the current transaction in the next PCICLK cycle.

When the FREEDM-32P256 is the target, STOPB is an output. The FREEDM-32P256 only issues transaction stop requests when responding to reads and writes to configuration space (disconnecting after 1 DWORD transferred) or if an initiator introduces wait states during a transaction.

When the FREEDM-32P256 is not involved in the current transaction, STOPB is tristated.

STOPB is updated on the rising edge of PCICLK or sampled on the rising edge of PCICLK depending on whether it is an output or an input.

IDSEL Input L1 The initialization device select signal (IDSEL)

enables read and write access to the PCI configuration registers. When IDSEL is set high during the address phase of a transaction and the C/BEB[3:0] code indicates a register read or write, the FREEDM-32P256 performs a PCI configuration register transaction and asserts the DEVSELB signal in the next PCICLK period.

IDSEL is sampled on the rising edge of PCICLK.

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PMC-2010333 ISSUE 3 FRAME ENGINE AND DATA LINK MANAGER 32P256

Pin Name Type Pin

Function

PM7382 FREEDM-32P256

No.

DEVSELB I/O R2 The active low device select signal (DEVSELB)

indicates that a target claims the current bus transaction. During the address phase of a transaction, all targets decode the address on the AD[31:0] bus. When a target, recognizes the address as its own, it sets DEVSELB low to indicate to the initiator that the address is valid. If no target claims the address in six bus clock cycles, the initiator assumes that the target does not exist or cannot respond and aborts the transaction.

When the FREEDM-32P256 is the initiator, DEVSELB is an input. If no target responds to an address in six PCICLK cycles, the FREEDM32P256 will abort the current transaction and alerts the PCI Host via an interrupt.

When the FREEDM-32P256 is the target, DEVSELB is an output. DELSELB is set low when the address on AD[31:0] is recognised.

When the FREEDM-32P256 is not involved in the current transaction, DEVSELB is tristated.

FREEDM-32P256 is updated on the rising edge of PCICLK or sampled on the rising edge of PCICLK depending on whether it is an output or an input.

LOCKB Input R1 The active low bus lock signal (LOCKB) locks a

target device. When LOCKB and FRAME are set low, and the FREEDM-32P256 is the target, an initiator is locking the FREEDM-32P256 as an "owned" target. Under these circumstances, the FREEDM-32P256 will reject all transaction with other initiators. The FREEDM-32P256 will continue to reject other initiators until its owner releases the lock by forcing both FRAMEB and LOCKB high. As a initiator, the FREEDM32P256 will never lock a target.

LOCKB is sampled using the rising edge of PCICLK.

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Pin Name Type Pin

Function

PM7382 FREEDM-32P256

No.

REQB Tristate

Output

H2 The active low PCI bus request signal (REQB)

requests an external arbiter for control of the PCI bus. REQB is set low when the FREEDM32P256 desires access to the host memory. REQB is set high when access is not desired.

REQB is updated on the rising edge of PCICLK.

GNTB Input H1 The active low PCI bus grant signal (GNTB)

indicates the granting of control over the PCI in response to a bus request via the REQB output. When GNTB is set high, the FREEDM-32P256 does not have control over the PCI bus. When GNTB is set low, the external arbiter has granted the FREEDM-32P256 control over the PCI bus. However, the FREEDM-32P256 will not proceed until the FRAMEB signal is sampled high, indicating no current transactions are in progress.

PCIINTB OD

Output

GNTB is sampled on the rising edge of PCICLK.

G1 The active low PCI interrupt signal (PCIINTB) is

set low when a FREEDM-32P256 interrupt source is active, and that source is unmasked. The FREEDM-32P256 may be enabled to report many alarms or events via interrupts. PCIINTB returns high when the interrupt is acknowledged via an appropriate register access.

PCIINTB is an open drain output and is asynchronous to PCICLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 28

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Pin Name Type Pin

Function

PM7382 FREEDM-32P256

No.

PERRB I/O T3 The active low parity error signal (PERRB)

indicates a parity error over the AD[31:0] and C/BEB[3:0] buses. Parity error is signalled when even parity calculations do not match the PAR signal. PERRB is set low at the cycle immediately following an offending PAR cycle. PERRB is set high when no parity error is detected.

PERRB is enabled by setting the PERREN bit in the Control/Status register in the PCI Configuration registers space. Regardless of the setting of PERREN, parity errors are always reported by the PERR bit in the Control/Status register in the PCI Configuration registers space.

PERRB is updated on the rising edge of PCICLK.

SERRB OD

Output

T2 The active low system error signal (SERRB)

indicates an address parity error. Address parity errors are detected when the even parity calculations during the address phase do not match the PAR signal. When the FREEDM32P256 detects a system error, SERRB is set low for one PCICLK period.

SERRB is enabled by setting the SERREN bit in the Control/Status register in the PCI Configuration registers space. Regardless of the setting of SERREN, parity errors are always reported by the SERR bit in the Control/Status register in the PCI Configuration registers space.

SERRB is an open drain output and is updated on the rising edge of PCICLK.

M66EN Input AC2 The active high 66 MHz mode enable signal

(M66EN) reflects the speed of operation of the PCI bus. M66EN should be set high for 66 MHz operation on the PCI bus. M66EN should be set low for 33 MHz operation on the PCI bus.

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PM7382 FREEDM-32P256

Table 3 – Miscellaneous Interface Signals (58)

Pin Name Type Pin

Function

No.

SYSCLK Input K23 The system clock (SYSCLK) provides timing for

the core logic. SYSCLK is nominally a 50% duty cycle, 25 to 45 MHz clock.

RSTB Input C22 The active low reset signal (RSTB) signal

provides an asynchronous FREEDM-32P256 reset. RSTB is an asynchronous input. When RSTB is set low, all FREEDM-32P256 registers are forced to their default states. In addition, TD[31:0] are forced high and all PCI output pins are forced tristate and will remain high or tristated, respectively, until RSTB is set high.

PMCTEST Input AB3 The PMC production test enable signal

(PMCTEST) places the FREEDM-32P256 is test mode. When PMCTEST is set high, production test vectors can be executed to verify manufacturing via the test mode interface signals TA[11:0], TA[12]/TRS, TRDB, TWRB and TDAT[15:0]. PMCTEST must be tied low for normal operation.

TCK Input T23 The test clock signal (TCK) provides timing for

test operations that can be carried out using the IEEE P1149.1 test access port. TMS and TDI are sampled on the rising edge of TCK. TDO is updated on the falling edge of TCK.

TMS Input T22 The test mode select signal (TMS) controls the

test operations that can be carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull up resistor.

TDI Input U21 The test data input signal (TDI) carries test data

into the FREEDM-32P256 via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK.

TDI has an integral pull up resistor.

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Pin Name Type Pin

Function

PM7382 FREEDM-32P256

No.

TDO Tristate

Output

U22 The test data output signal (TDO) carries test

data out of the FREEDM-32P256 via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tristate output which is inactive except when scanning of data is in progress.

TRSTB Input T21 The active low test reset signal (TRSTB)

provides an asynchronous FREEDM-32P256 test access port reset via the IEEE P1149.1 test access port. TRSTB is an asynchronous input with an integral pull up resistor.

Note that when TRSTB is not being used, it must be connected to the RSTB input.

NC1-50 Open These pins must be left unconnected.

Table 4 – Production Test Interface Signals (0 - Multiplexed)

Pin Name Type Pin

Function

No.

TA[0] TA[1] TA[2] TA[3] TA[4] TA[5] TA[6] TA[7] TA[8] TA[9] TA[10] TA[11]

TA[12] /TRS

Input G23

F23 E23 D22 E20 C23 A22

The test mode address bus (TA[11:0]) selects specific registers during production test (PMCTEST set high) read and write accesses. TA[11:0] replace RD[21:10] when PMCTEST is set high.

D20 B21 D19 B20 A19

Input A16 The test register select signal (TA[12]/TRS)

selects between normal and test mode register accesses during production test (PMCTEST set high). TRS is set high to select test registers and is set low to select normal registers. TA[12]/TRS replaces RD[24] when PMCTEST is set high.

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Pin Name Type Pin

Function

PM7382 FREEDM-32P256

No.

TRDB Input A18 The test mode read enable signal (TRDB) is set

low during FREEDM-32P256 register read accesses during production test (PMCTEST set high). The FREEDM-32P256 drives the test data bus (TDAT[15:0]) with the contents of the addressed register while TRDB is low. TRDB replaces RD[22] when PMCTEST is set high.

TWRB Input A17 The test mode write enable signal (TWRB) is set

low during FREEDM-32P256 register write accesses during production test (PMCTEST set high). The contents of the test data bus (TDAT[15:0]) are clocked into the addressed register on the rising edge of TWRB. TWRB replaces RD[23] when PMCTEST is set high.

TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15]

I/O AC14

AA14 AC13 AB13 AA12

The bi-directional test mode data bus (TDAT[15:0]) carries data read from or written to FREEDM-32P256 registers during production test. TDAT[15:0] replace TD[31:16] when

PMCTEST is set high. AB11 Y11 AB10 Y9 AA8 AC8 AB7 AC7 AC6 AC5 AB4

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PM7382 FREEDM-32P256

Table 5 – Power and Ground Signals (65)

Pin Name Type Pin

Function

No.

VDD3V3[1] VDD3V3[2] VDD3V3[3] VDD3V3[4] VDD3V3[5] VDD3V3[6] VDD3V3[7] VDD3V3[8] VDD3V3[9] VDD3V3[10] VDD3V3[11] VDD3V3[12] VDD3V3[13] VDD3V3[14]

Power D6

D10 D14 D18 H4 H20 M4 M20 T4 T20 Y6 Y10 Y14 Y18

The VDD3V3[14:1] DC power pins should be connected to a well decoupled +3.3 V DC supply. These power pins provide DC current to the I/O pads.

VDD2V5[1] VDD2V5[2] VDD2V5[3] VDD2V5[4] VDD2V5[5] VDD2V5[6] VDD2V5[7] VDD2V5[8] VDD2V5[9] VDD2V5[10] VDD2V5[11] VDD2V5[12]

Power E2

M1 W2 AB5 AC12 AB19 W22 M23 E22 B19 A12 B5

The VDD2V5[12:1] DC power pins should be connected to a well decoupled +2.5 V DC supply. These power pins provide DC current to the digital core.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 33

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Pin Name Type Pin

Function

PM7382 FREEDM-32P256

No.

VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14]

Ground D8

D12 D16 F4 F20 K4 K20 P4 P20 V4 V20 Y8 Y12 Y16

The VSS[14:1] DC ground pins should be connected to ground. They provide a ground reference for the 3.3 V rail. They also provide a ground reference for the 2.5 V rail.

VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39]

K10

K11 K12

The VSS[39:15] DC ground pins should be connected to ground. They provide improved

thermal properties for the 329 PBGA package. K13 K14 L10 L11 L12 L13 L14 M10 M11 M12 M13 M14 N10 N11 N12 N13 N14 P10 P11 P12 P13 P14

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PM7382 FREEDM-32P256

Notes on Pin Description:

1. All FREEDM-32P256 non-PCI inputs and bi-directionals present minimum capacitive loading and are 5 Volt tolerant. PCI signals conform to the 3.3 Volt signaling environment.

2. All FREEDM-32P256 non-PCI outputs and bi-directionals have 4 mA drive capability, except the PCICLKO, RBCLK, TBCLK and RBD outputs which have 8 mA drive capability.

3. All FREEDM-32P256 outputs can be tristated under control of the IEEE P1149.1 test access port, even those which do not tristate under normal operation. All non-PCI outputs and bi-directionals are 5 V tolerant when tristated.

4. All non-PCI inputs are Schmitt triggered. Inputs TMS, TDI and TRSTB have internal pull-up resistors.

5. Power to the VDD3V3 pins should be applied before power to the VDD2V5 pins is applied. Similarly, power to the VDD2V5 pins should be removed before power to the VDD3V3 pins is removed.

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PM7382 FREEDM-32P256

8 FUNCTIONAL DESCRIPTION

8.1 High Speed Multi-Vendor Integration Protocol (H-MVIP)

H-MVIP defines a synchronous, time division multiplexed (TDM) bus of Nx64 Kbps constant bit rate (CBR) data streams. Each 64 Kbps data stream (timeslot) carries an 8-bit byte of HDLC traffic, as described in the following section, and is characterised by 8 KHz framing. H-MVIP supports higher bandwidth applications on existing telephony networks by fitting more time-slots into a 125

ms frame. The FREEDM-32P256 supports H-MVIP data rates of 2.048 Mbps and 8.192 Mbps with 32 or 128 time-slots per frame and associated clocking frequencies of 4.096 and 16.384 MHz respectively. Figure 1 shows a diagram of the H-MVIP protocol supported by the FREEDM-32P256 device.

Figure 1 – H-MVIP Protocol

Data Clock

(4, 16 MH z)

Fram e Pulse Cloc k

(4 MHz )

Frame Pulse

(8 KHz )

Serial D ata

TS 31/127

B8 B1 B2 B8

TS 0

8.2 High-Level Data Link Control (HDLC) Protocol

Figure 2 shows a diagram of the synchronous HDLC protocol supported by the FREEDM-32P256 device. The incoming stream is examined for flag bytes (01111110 b it pattern ) which de lineate the opening and closing of the HDLC packet. The packet is bit de-stuffed which discards a "0" bit which directly follows five contiguous "1" bits. The resulting HDLC packet size must be a multiple of an octet (8 bits) and within the expected minimum and maximum packet length limits. The minimum packet length is that of a packet containing two information bytes (address and control) and FCS bytes. For packets with CRC-CCITT as FCS, the minimum packet length is four bytes while those with CRC-32 as FCS, the minimum length is six bytes. An HDLC packet is aborted when seven contiguous "1" bits (with no inserted "0" bits) are received. At least

125 us

B2 B8B7

TS 1

TS 31/127

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PM7382 FREEDM-32P256

one flag byte must exist between HDLC packets for delineation. Contiguous flag bytes, or all ones bytes between packets are used as an "inter-frame time fill". Adjacent flag bytes may share zeros.

Figure 2 – HDLC Frame

Flag Information FCS Flag

Flag

HDLC Packet

The CRC algorithm for the frame checking sequence (FCS) field is either a CRC-CCITT or CRC-32 function. Figure 3 shows a CRC encoder block diagram

using the generating polynomial g(X) = 1 + g1X + g2X2 +…+ g

n-1

+ Xn. The CRC-CCITT FCS is two bytes in size and has a generating polynomial g(X) = 1 + X5 + X12 + X16. The CRC-32 FCS is four bytes in size and has a generating polynomial g(X) = 1 + X + X2 + X4 + X5 + X7 + X8 + X10 + X11 + X12 + X16 + X22 + X23 + X26 + X32. The first FCS bit received is the residue of the highest term.

Figure 3 – CRC Generator

LSB MSB

8.3 Receive Channel Assigner

The Receive Channel Assigner block (RCAS256) processes up to 32 serial links. Links may be configured to support 2.048 or 8.192 Mbps H-MVIP traffic, to support T1/J1/E1 channelised traffic or to support unchannelised traffic. When configured to support 2.048 Mbps H-MVIP traffic, each group of 8 links share a clock and frame pulse. All links configured for 8.192 Mbps H-MVIP traffic share a common clock and frame pulse. For T1/J1/E1 channelised traffic or for unchannelised traffic, each link is independent and has its own associated clock. For each link, the RCAS256 performs a serial to parallel conversion to form data bytes. The data bytes are multiplexed, in byte serial format, for delivery to the Receive HDLC Processor / Partial Packet Buffer block (RHDL256) at SYSCLK rate. In the event where multiple streams have accumulated a byte of data,

Parity Check Digits

n-1

Message

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multiplexing is performed on a fixed priority basis with link #0 having the highest priority and link #31 the lowest.

From the point of view of the RCAS256, links configured for H-MVIP traffic behave identically to links configured for T1/J1/E1 channelised or unchannelised traffic in the back end, only differing on the link side as described herein. First, the number of time-slots in each frame is programmable to be 32 or 128 and has an associated data clock frequency that is double the data rate. This provides more bandwidth per link for applications requiring higher data densities on a single link. Second, H-MVIP links reference the start of each frame with a frame pulse, thereby avoiding having to gap the link clock during the framing bits/bytes of each frame. The frame pulse is provided by an H-MVIP bus master and ensures that all agents sharing the H-MVIP bus remain synchronized. When configured for operation in 2.048 Mbps mode, the frame pulse is sampled using the same clock which samples the data. When configured for operation in 8.192 Mbps H-MVIP mode, the frame pulse is sampled using a separate frame pulse clock provided by an H-MVIP bus master. The frame pulse clock has a synchronous timing relationship to the data clock. Third, not all links are independent. When configured for operation in 2.048 Mbps H-MVIP mode, each group of 8 links share a clock and a frame pulse. Links 0 through 7, 8 through 15, 16 through 23 and 24 through 31 each share a clock and a frame pulse. Not all 8 links within each group need to be configured for operation in 2.048 Mbps H-MVIP mode. However, any link within each logical group of 8 which is configured for 2.048 Mbps H-MVIP operation will share the same clock and frame pulse. When configured for operation in 8.192 Mbps H-MVIP mode, links

4m (0£m£7) share a frame pulse, a data clock and a frame pulse clock. Again, not all eight 4m (0£m£7) links need to be configured for operation in 8.192 Mbps

H-MVIP mode, however, any link which is configured for 8.192 Mbps H-MVIP operation will share the same frame pulse, data clock and frame pulse clock. If link 4m is configured for 8.192 Mbps H-MVIP operation, then data transferred on that link is “spread” over links 4m, 4m+1, 4m+2 and 4m+3 from a channel assigner point of view. Accordingly, when link 4m is configured for operation in

8.192 Mbps H-MVIP mode, links 4m+1, 4m+2 and 4m+3 must also be configured for operation in 8.192 Mbps H-MVIP mode. In the back end, the RCAS256 extracts and processes the time-slots in the same way as channelised T1/J1/E1 traffic.

Links containing a T1/J1 or an E1 stream may be channelised. Data at each time-slot may be independently assigned to a different channel. The RCAS256 performs a table lookup to associate the link and time-slot identity with a channel. T1/J1 and E1 framing bits/bytes are identified by observing the gap in the link clock which is squelched during the framing bits/bytes. For unchannelised links, clock rates are limited to 51.84 MHz for links #0 to #2 and limited to 10 MHz for the remaining links. All data on each link belongs to one channel. For the case of a mixture of channelised, unchannelised and H-MVIP

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links, the total instantaneous link rate over all the links is limited to 64 MHz. The RCAS256 performs a table lookup using only the link number to determine the associated channel, as time-slots are non-existent in unchannelised links.

The RCAS256 provides diagnostic loopback that is selectable on a per channel basis. The RCAS256 does not support diagnostic loopback for links configured as H-MVIP. When a channel is in diagnostic loopback, stream data on the received links originally destined for that channel is ignored. Transmit data of that channel is substituted in its place.

8.3.1 Line Interface Translator (LIT)

The LIT block translates the information on the 32 physical links into a suitable format for interpretation by the Line Interface block. The LIT block performs three functions: data translation, clock translation and frame pulse generation.

When link 4m (0£m£7) is configured for operation in 8.192 Mbps H-MVIP mode, the LIT block translates the 128 time-slots on link 4m to the Line Interface block across links 4m, 4m+1, 4m+2 and 4m+3. The LIT block provides time-slots 0 through 31, 32 through 63, 64 through 95 and 96 through 127 to the Line Interface block on links 4m, 4m+1, 4m+2 and 4m+3 respectively. When link 4m is configured for operation in 8.192 Mbps H-MVIP mode, data cannot be received on inputs RD[4m+3:4m+1]. However, links 4m+1, 4m+2 and 4m+3 must be programmed in the RCAS256 Link Configuration register for 8.192 Mbps H-MVIP operation. When links are configured for operation in 2.048 Mbps HMVIP mode, channelised T1/J1/E1 mode or unchannelised mode, the LIT block does not perform any translation on the link data.

When a link is configured for operation in H-MVIP mode, the LIT block divides the appropriate clock (RMVCK[n] for 2.048 Mbps H-MVIP and RMV8DC for

8.192 Mbps H-MVIP) by two and provides this divided down clock to the Line Interface block. When a link is configured for operation in channelised T1/J1/E1 or unchannelised mode, the LIT block does not perform any translation on the link clock.

When a link is configured for operation in H-MVIP mode, the LIT block samples the appropriate frame pulse (RFPB[n] for 2.048 Mbps H-MVIP and RFP8B for

8.192 Mbps H-MVIP) and presents the sampled frame pulse to the Line Interface block. When a link is configured for operation in channelised T1/J1/E1 or unchannelised mode, the gapped clock is passed to the LIT block unmodified.

8.3.2 Line Interface

There are 32 identical line interface blocks in the RCAS256. Each line interface block contains 2 sub-blocks; one supporting channelised T1/J1/E1 streams and

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the other H-MVIP streams. Based on configuration, only one of the sub-blocks are active at one time; the other is held reset. Each sub-block contains a bit counter, an 8-bit shift register and a holding register. Each sub-block performs serial to parallel conversion. Whenever the holding register is updated, a request for service is sent to the priority encoder block. When acknowledged by the priority encoder, the line interface would respond with the data residing in the holding register in the active sub-block.

To support H-MVIP links, each line interface block contains a time-slot counter. The time-slot counter is incremented each time the holding register is updated. When a frame pulse occurs, the time-slot counter is initialised to indicate that the next bit is the most significant bit of the first time-slot.

To support non H-MVIP channelised links, each line interface block contains a time-slot counter and a clock activity monitor. The time-slot counter is incremented each time the holding register is updated. The clock activity monitor is a counter that increments at the system clock (SYSCLK) rate and is cleared by a rising edge of the receive clock (RCLK[n]). A framing bit (T1/J1) or a framing byte (E1) is detected when the counter reaches a programmable threshold, in which case, the bit and time-slot counters are initialised to indicate that the next bit is the most significant bit of the first time-slot. For unchannelised links, the time-slot counter and the clock activity monitor are held reset.

8.3.3 Priority Encoder

The priority encoder monitors the line interfaces for requests and synchronises them to the SYSCLK timing domain. Requests are serviced on a fixed priority scheme where highest to lowest priority is assigned from the line interface attached to RD[0] to that attached to RD[31]. Thus, simultaneous requests from RD[m] will be serviced ahead of RD[n], if m < n. When there are no pending requests, the priority encoder generates an idle cycle. In addition, once every fourth SYSCLK cycle, the priority encoder inserts a null cycle where no requests are serviced. This cycle is used by the channel assigner downstream for host microprocessor accesses to the provisioning RAMs.

8.3.4 Channel Assigner

The channel assigner block determines the channel number of the data byte currently being processed. The block contains a 1024 word channel provision RAM. The address of the RAM is constructed from concatenating the link number and the time-slot number of the current data byte. The fields of each RAM word include the channel number and a time-slot enable flag. The time-slot enable flag labels the current time-slot as belonging to the channel indicted by the channel number field.

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8.3.5 Loopback Controller

The loopback controller block implements the channel based diagnostic loopback function. Every valid data byte belonging to a channel with diagnostic loopback enabled from the Transmit HDLC Processor / Partial Packet Buffer block (THDL256) is written into a 64 word FIFO. The loopback controller monitors for an idle time-slot or a time-slot carrying a channel with diagnostic loopback enabled. If either conditions hold, the current data byte is replaced by data retrieved from the loopback data FIFO.

8.4 Receive HDLC Processor / Partial Packet Buffer

The Receive HDLC Processor / Partial Packet Buffer block (RHDL256) processes up to 256 synchronous transmission HDLC data streams. Each channel can be individually configured to perform flag sequence detection, bit de-stuffing and CRC-CCITT or CRC-32 verification. The packet data is written into the partial packet buffer. At the end of a frame, packet status including CRC error, octet alignment error and maximum length violation are also loaded into the partial packet buffer. Alternatively, a channel can be provisioned as transparent, in which case, the HDLC data stream is passed to the partial packet buffer processor verbatim.

There is a natural precedence in the alarms detectable on a receive packet. Once a packet exceeds the programmable maximum packet length, no further processing is performed on it. Thus, octet alignment detection, FCS verification and abort recognition are squelched on packets with a maximum length violation. An abort indication squelches octet alignment detection, minimum packet length violations, and FCS verification. In addition, FCS verification is only performed on packets that do not have octet alignment errors, in order to allow the RHDL256 to perform CRC calculations on a byte-basis.

The partial packet buffer is an 32 Kbyte RAM that is divided into 16-byte blocks. Each block has an associated pointer which points to another block. A logical FIFO is created for each provisioned channel by programming the block pointers to form a circular linked list. A channel FIFO can be assigned a minimum of 3 blocks (48 bytes) and a maximum of 2048 blocks (32 Kbytes). The depth of the channel FIFOs are monitored in a round-robin fashion. Requests are made to the Receive DMA Controller block (RMAC256) to transfer, to the PCI host memory, data in channel FIFOs with depths exceeding their associated threshold.

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8.4.1 HDLC Processor

The HDLC processor is a time-slice state machine which can process up to 256 independent channels. The state vector and provisioning information for each channel is stored in a RAM. Whenever new channel data arrives, the appropriate state vector is read from the RAM, processed and written back to the RAM. The HDLC state-machine can be configured to perform flag delineation, bit de-stuffing, CRC verification and length monitoring. The resulting HDLC data and status information is passed to the partial packet buffer processor to be stored in the appropriate channel FIFO buffer.

The configuration of the HDLC processor is accessed using indirect channel read and write operations. When an indirect operation is performed, the information is accessed from RAM during a null clock cycle generated by the upstream Receive Channel Assigner block (RCAS256). Writing new provisioning data to a channel resets the channel's entire state vector.

8.4.2 Partial Packet Buffer Processor

The partial packet buffer processor controls the 32 Kbyte partial packet RAM which is divided into 16 byte blocks. A block pointer RAM is used to chain the partial packet blocks into circular channel FIFO buffers. Thus, non-contiguous sections of the RAM can be allocated in the partial packet buffer RAM to create a channel FIFO. System software is responsible for the assignment of blocks to individual channel FIFOs. Figure 4 shows an example of three blocks (blocks 1, 3, and 200) linked together to form a 48 byte channel FIFO.

The partial packet buffer processor is divided into three sections: writer, reader and roamer. The writer is a time-sliced state machine which writes the HDLC data and status information from the HDLC processor into a channel FIFO in the packet buffer RAM. The reader transfers channel FIFO data from the packet buffer RAM to the downstream Receive DMA Controller block (RMAC256). The roamer is a time-sliced state machine which tracks channel FIFO buffer depths and signals the reader to service a particular channel. If a buffer over-run occurs, the writer ends the current packet from the HDLC processor in the channel FIFO with an over-run flag and ignores the rest of the packet.

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Figure 4 – Partial Packet Buffer Structure

Block 0

Block 1

Block 2

Block 3

Partial Packet

Buffer RAM

16 bytes

Block 0

Block 1

Block 2

Block 3

Block

Pointer RAM

0x03

0xC8

0x01

Block 2047

16 bytes

Block 200Block 200

Block 2047

The FIFO algorithm of the partial packet buffer processor is based on a programmable per-channel transfer size. Instead of tracking the number of full blocks in a channel FIFO, the processor tracks the number of transactions. Whenever the partial packet writer fills a transfer-sized number of blocks or writes an end-of-packet flag to the channel FIFO, a transaction is created. Whenever the partial packet reader transmits a transfer-size number of blocks or an end-of-packet flag to the RMAC256 block, a transaction is deleted. Thus, small packets less than the transfer size will be naturally transferred to the RMAC256 block without having to precisely track the number of full blocks in the channel FIFO.

The partial packet roamer performs the transaction accounting for all channel FIFOs. The roamer increments the transaction count when the writer signals a new transaction and sets a per-channel flag to indicate a non-zero transaction count. The roamer searches the flags in a round-robin fashion to decide for which channel FIFO to request transfer by the RMAC256 block. The roamer informs the partial packet reader of the channel to process. The reader transfers the data to the RMAC256 until the channel transfer size is reached or an end of

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packet is detected. The reader then informs the roamer that a transaction is consumed. The roamer updates its transaction count and clears the non-zero transaction count flag if required. The roamer then services the next channel with its transaction flag set high.

The writer and reader determine empty and full FIFO conditions using flags. Each block in the partial packet buffer has an associated flag. The writer sets the flag after the block is written and the reader clears the flag after the block is read. The flags are initialized (cleared) when the block pointers are written using indirect block writes. The writer declares a channel FIFO overrun whenever the writer tries to store data to a block with a set flag. In order to support optional removal of the FCS from the packet data, the writer does not declare a block as filled (set the block flag nor increment the transaction count) until the first double word of the next block in channel FIFO is filled. If the end of a packet resides in the first double word, the writer declares both blocks as full at the same time. When the reader finishes processing a transaction, it examines the first double word of the next block for the end-of-packet flag. If the first double word of the next block contains only FCS bytes, the reader would, optionally, process next transaction (end-of-packet) and consume the block, as it contains information not transferred to the RMAC256 block.

8.5 Receive DMA Controller

The Receive DMA Controller block (RMAC256) is a DMA controller which stores received packet data in host computer memory. The RMAC256 is not directly connected to the host memory PCI bus. Memory accesses are serviced by a downstream PCI controller block (GPIC). The RMAC256 and the host exchange information using receive packet descriptors (RPDs). The descriptor contains the size and location of buffers in host memory and the packet status information associated with the data in each buffer. RPDs are transferred from the RMAC256 to the host and vice versa using descriptor reference queues. The RMAC256 maintains all the pointers for the operation of the queues. The RMAC256 provides two receive packet descriptor reference (RPDR) free queues to support small and large buffers. The RMAC256 acquires free buffers by reading RPDRs from the free queues. After a packet is received, the RMAC256 places the associated RPDR onto a RPDR ready queue. To minimize host bus accesses, the RMAC256 maintains a descriptor reference table to store current DMA information. This table contains separate DMA information entries for up to 256 receive channels.

8.5.1 Data Structures

For packet data, the RMAC256 communicates with the host using Receive Packet Descriptors (RPD), Receive Packet Descriptor References (RPDR), the

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Receive Packet Descriptor Reference Ready (RPDRR) queue and the Receive Packet Descriptor Reference Small and Large Buffer Free (RPDRF) queues.

The RMAC256 copies packet data to data buffers in host memory. The RPD, RPDR, RPDRR queue, and Small and Large RPDRF queues are data structures which are used to transfer host memory data buffer information. All five data structures are manipulated by both the RMAC256 and the host computer. The RPD holds the data buffer size, data buffer address, and packet status information. The RPDR is a pointer which is used to index into a table of RPDs. The RPDRR queue and RPDRF queues allow the RMAC256 and the host to pass RPDRs back and forth. These data structures are described in more detail in the following sections.

Receive Packet Descriptor

The Receive Packet Descriptors (RPDs) pass buffer and packet information between the RMAC256 and the host. Both the RMAC256 and the host read and write information in the RPDs. The host writes RPD fields which describe the size and address of data buffers in host memory. The RMAC256 writes RPD fields which provide number of bytes used in each data buffer, RPD link information, and the status of the received packet. RPDs are stored in host memory in a Receive Packet Descriptor Table which is described in a later section. The Receive Packet Descriptor structure is shown in Figure 5.

Figure 5 – Receive Packet Descriptor

Data Buffer Start Address [31:0]

Status [5:0 ]

Reserved (6)

Bytes In Bu ffer [1 5:0]

RCC[9:0] Res (1)

Reserved (16)

Table 6 – Receive Packet Descriptor Fields

Field

Description

Data Buffer Start Address[31:0]

The Data Buffer Start Address[31:0] bits point to the data buffer in host memory. This field is expected to be configured by the Host during initialisation.

The Data Buffer Start Address field is valid in all RPDs.

Off set[1:0]

Receive Buffer Size [15:0]

Next RPD Pointer [14:0]

0 Bit 31

Reserved (7)

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Field Description

CE The Chain End (CE) bit indicates the end of a linked list of

RPDs. When CE is set to logic one, the current RPD is the last RPD of a linked list of RPDs. When CE is set to logic zero, the current RPD is not the last RPD of a linked list.

The CE bit is valid for all RPDs written by the RMAC256 to the Receive Ready Queue. When a packet requires only one RPD, the CE bit is set to logic one. The CE bit is ignored for all RPDs read by the RMAC256 from the Receive Free Queues, each of which is assumed to point to only one buffer, i.e. not a chain.

Offset[1:0] The Offset[1:0] bits indicate the byte offset of the data

packet from the start of the buffer. If this value is nonzero, there will be ‘dummy’ (i.e. undefined) bytes at the start of the data buffer prior to the packet data proper.

For a linked list of RPDs, only the first RPD's Offset field is valid. All other RPD Offset fields of the linked list are set to 0.

Status [5:0] The Status[5:0] bits indicate the status of the received

packet.

Status[0] Rx buffer overrun Status[1] Packet exceeds max. allowed size Status[2] CRC error Status[3] Packet Length not an exact no. of bytes Status[4] HDLC abort detected Status[5] Unused (set to 0)

For a linked list of RPDs, only the last RPD's Status field is valid. All other RPD Status fields of the linked list are invalid and should be ignored. When a packet requires only one RPD, the Status field is valid.

Bytes in Buffer [15:0]

The Bytes in Buffer[15:0] bits indicate the number of bytes actually used in the current RPD's data buffer to store packet data. The count excludes the 'dummy' bytes inserted as a result of a non-zero Offset field. A count greater than 32767 bytes indicates a packet that is shorter than the expected length of the FCS field.

The Bytes in Buffer field is invalid when Status[0] or Status[4] is asserted .

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Field Description

Next RPD Pointer [14:0]

The Next RPD Pointer[14:0] bits store a RPDR which enables the RMAC256 to support linked lists of RPDs. This field, which is only valid when CE is equal to logic zero, contains the RPDR to the next RPD in a linked list. The RMAC256 links RPDs when more than one buffer is needed to store a packet.

The Next RPD Pointer is not valid for the last RPD in a linked list (when CE=1). When a packet requires only one RPD, the Next RPD Pointer field is not valid.

RCC[9:0] The Receive Channel Code (RCC[9:0]) bits are used by

the RMAC256 to associate a RPD with a channel.

For a linked list of RPDs, all the RPDs’ RCC[9:0] fields are valid. i.e. all contain the same channel value.

Receive Buffer Size [15:0]

The Receive Buffer Size[15:0] bits indicate the size in bytes of the current RPD's data buffer. This field is expected to be configured by the Host during initialisation. The Receive Buffer Size must be a non-zero integer multiple of sixteen and less than or equal to 32752.

The Receive Buffer Size field is valid in all RPDs.

The Receive Buffer Size and Data Buffer Start Address fields are written only by the host. The RMAC256 reads these fields to determine where to store packet data. All other fields are written only by the RMAC256.

Receive Packet Descriptor Table

The Receive Packet Descriptor Table resides in host memory and stores all the RPDs. The RPD Table can contain a maximum of 32768 RPDs. The base of the RPD table is user programmable using the Rx Packet Descriptor Table Base (RPDTB) register. The table is indexed by a Receive Packet Descriptor Reference (RPDR) which is a 15-bit pointer defining the offset of a RPD from the table base. Thus, as shown in the following diagram, a RPD can be located by adding the RPDR to the Rx Packet Descriptor Table Base register.

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Figure 6 – Receive Packet Descriptor Table

RPDTB[31:4] = Rx Packet Descriptor Table Base register

RPDR[14:0] = Receive Packet Descriptor Reference

RPD_ADDR[31:0] = Receive Packet Descriptor Address

Bit 31 Bit 0

RPDTB[31:4]

0000

RPDR[14:0]

0000

RPD_ADDR[31:0]

RPDTB

Bit 0Bit 31

Dword 0

RPD 1

RPD_ADDR

Dword 1 Dword 2 Dword 3 Dword 0

RPD 2

Dword 3

Dword 0

RPD 32768

Dword 3

The Receive Packet Descriptor Table resides in host memory. The Rx Packet Descriptor Table Base register resides in the RMAC256; this register is initialised by the host. The RPDRs reside in host memory and are accessed using receive packet queues which are described in the next section.

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Receive Packet Queues

Receive Packet Queues are used to transfer RPDRs between the host and the RMAC256. There are three queues: a RPDR Large Buffer Free Queue (RPDRLFQ), a RPDR Small Buffer Free Queue (RPDRSFQ) and a RPDR Ready Queue (RPDRRQ). The free queues contain RPDRs referencing RPDs that define free buffers. The ready queue contains RPDRs referencing RPDs that define buffers ready for host processing. The RMAC256 pulls RPDRs from the free queues when it needs free data buffers. The RMAC256 places an RPDR onto the ready queue after it has filled the buffers with data from each complete packet. The host removes RPDRs from the ready queue to process the data buffers. The host places the RPDRs back onto the free queues after it finishes reading the data from the buffers.

When starting to process a packet, the RMAC256 uses a small buffer RPD to store the first buffer of packet data. If the packet data requires more than one buffer, the RMAC256 uses large buffer RPDs to store the remainder of the packet. The RMAC256 links together all the RPDs required to store the packet and returns the RPDR associated with the first RPD onto the ready queue.

All receive packet queues reside in host memory and are defined by the Rx Queue Base (RQB) register and index registers which reside in the RMAC256. The Rx Queue Base is the base address for the receive packet queues. Each packet queue has four index registers which define the start and end of the queue and the read and write locations of the queue. Each index register is 16 bits in length and defines an offset from the Rx Queue Base. Thus, as shown in the Figure 7, the host address of a RPDR is calculated by adding the index register to the Rx Queue Base register. The host initializes the Rx Queue Base register and all the index registers. When an entity (either the RMAC256 or the host) removes elements from a queue, the entity updates the read pointer for that queue. When an entity (either the RMAC256 or the host) places elements onto a queue, the entity updates the write pointer for that queue.

The read index for each queue points to the last valid RPDR read while the write index points to where the next RPDR can be written. The start index points to the first valid location within the queue; an RPDR can be written to this location. However, the end index points to a location that is beyond a queue; an RPDR can not be written to this location. Note however, the start index of one queue can be set to the end index of another queue. A queue is empty when the read index is one less than the write index; a queue is also empty if the read index is one less than the end index and the write index equals the start index. A queue is full when the read index is equal to the write index. Figure 7 shows the RPDR reference queues.

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Figure 7 – RPDRF and RPDRR Queues

Receive Packet Descriptor (RPD) Reference Queues

Base Address:

RQB [31:2] = Rx Q ueue B ase register

Index Registers:

Large Buffer Free Queue:

RPDRLFQS[15:0] = RPDR Large Free Queue Start register

RPDR LFQW [15:0 ] = RPDR Large Free Queu e Write register RPDRLFQR[15:0] = RPDR Large Free Queue Read register

RPDRLFQE[15:0] = RPD R Large Free Queue End register

Ready Queue:

RPDRRQS[15:0] = RPDR Ready Queue Start register RPDRRQW[15:0] = RPDR Ready Queue Write register RPDRRQR[15:0] = RPDR Ready Queue Read register RPDRRQE[15:0] = RPDR Ready Queue End register

Small Buffer Free Queue:

RPDRSFQS[15:0] = RPDR Small Free Queue Start register

RPDR SFQW [15:0] = RPD R Small Free Q ueue W rite register

RPDR SFQR [15:0] = R PDR Sm all Free Qu eue Read register RPDR SFQE [15:0] = RP DR Sm all Free Queue E nd register

Base Address

+ Index Register

------------------------Host Address

RQB[31:2]

Index[15 :0]

AD[31:0]

Rx Packet Descriptor Reference Queue Memory Map

RPDRRQS

RPDRRQ R

RPDRRQW

RPDRRQE

RPDRLFQS

RPDRLFQR

RPDRLFQW

RPDRLFQE

RPDRSFQS

RPDRSFQR

Bit 31

Status + RPDR

RPDR

Bit 0

RQB

Host Memory

RPD Reference Queues

256KB

RPDRSFQW

RPDRSFQE

RPDR

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Note that the maximum value to which an end pointer may be set is FFFF hex, resulting in a maximum offset from the queue base address of (4*(FFFF-1)) = 3FFF8 hex. An end pointer must not be set to 0 hex in an attempt to include offset 3FFFC hex in a queue.

As shown in Figure 7, the ready queue elements have a status field as well as an RPDR field. The RMAC256 fills in the status field to mark whether a packet was successfully received or not. The host reads the status field. The ready queue element is shown in Table 7 below along with the definition of the status bits.

If the RMAC256 requires a buffer of a particular size (i.e. small or large) and no RPDR is available in the corresponding free queue, a RPDR from the other free queue is substituted. The host may, therefore, force the RMAC256 to store received data in buffers of only one size by setting one of the free queues to zero length, i.e. by setting the start and end index registers of one of the queues to equal values. If the RMAC256 requires a buffer and neither free queue contains RPDRs, an RPQ_ERRI interrupt is generated.

Table 7 – RPDRR Queue Element

Bit 16 Bit 0

STATUS[1:0] RPDR[14:0]

Field Description

STATUS[1:0] The encoding for the status field is as follows:

00 – Successful reception of packet. 01 – Unsuccessful reception of packet. 10 – Unprovisioned partial packet. 11 – Partial packet returned due to RAWMAX

limit being reached.

RPDR[14:0] The RPDR[14:0] field defines the offset of the first

RPD in a linked chain of RPDs, each pointing to a buffer containing the received data.

As described previously, the RMAC256 links RPDs together if more than one buffer is needed for a packet. The RMAC256 links additional buffer RPDs to the end of the chain as required until the entire packet is copied to host memory (provided that the host has not disabled use of both the small and large free queues by setting one of them to length zero). After storing the packet data, the RMAC256 places the STATUS+RPDR for the first RPD onto the ready queue. Only the RPDR associated with the first RPD is placed onto the ready queue. All other required RPDs are linked to the first RPD as shown in Figure 8.

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Although a STATUS+RPDR only totals to 17 bits, each queue entry is a dword, i.e. 32 bits. When the RMAC256 block writes a STATUS+RPDR to the ready queue, it sets the remaining 7 bits in the third byte to zero and the fourth byte is unmodified.

Figure 8 – RPDRR Queue Operation

Rx Packet Descriptor Reference Ready Queue

RPDRRQ_START_ADDR

RPDRRQ_READ_ADDR

RPDRRQ_WRITE_ADDR

STATUS+RPDR

Bit 0 Bit 31

RPD - 16 bytes

buffer

-packet M

buffer

-packet N

RPD - 16 bytes

RPDRRQ_END_ADDR

buffer

-start of packet O

buffer

-middle of packet O

buffer

-end of packet O

Receive Channel Descriptor Reference Table

On a per-channel basis, the RMAC256 caches information such as the current DMA information in a Receive Channel Descriptor Reference (RCDR) Table. The RMAC256 can process 256 channels and stores three dwords of information per channel. This information is cached internally in order to

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decrease the number of host bus accesses required to process each data packet. The structure of the RCDR table is shown in Figure 9.

Figure 9 – Receive Channel Descriptor Reference Table

Bit 0 Bit 31

RCC 0

RCC 1

Buffer Size[14:0]

DMA Current Address[31:0]

Bytes Avail. in Buffer[14:0]

Buffer Size[14:0]

DMA Current Address[31:0]

RBC[1:0]

Res

RBC[1:0]

Res

RPD Pointer[14:0] Bytes Avail. in Buffer[14:0]

Start RPD Pointer[14:0]

RPD Pointer[14:0]

Start RPD Pointer[14:0]

RCC 671

Bytes Avail. in Buffer[14:0]

Buffer Size[14:0]

DMA Current Address[31:0]

RBC[1:0]

Res

RPD Pointer[14:0]

Start RPD Pointer[14:0]

Table 8 – Receive Channel Descriptor Reference Table Fields

Field Description

Bytes Available in Buffer[15:0]

This field is used to keep track of the number of bytes available in the current data buffer. The RMAC256 initialises the Bytes Available in Buffer to the Receive Buffer Size minus the offset at the head of the buffer. The field is decremented each time a byte is written into the buffer.

RBC[1:0] This field is used to keep track of the number of buffers

used when storing ‘raw’ (i.e. non packet delimited) data. The RMAC256 initialises the RBC field to the value of the RAWMAX[1:0] field in the RMAC Control Register. The field is decremented each time a buffer is filled with data. If the field reaches zero, the chain of RPDs is placed on the ready queue and a new chain started.

RPD Pointer[14:0] This field contains the pointer to the current RPD.

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Field Description

Buffer Size[14:0] This field contains the size in bytes of the buffer

currently being written to.

V This bit (Valid) indicates whether a packet is currently

being received on the DMA channel. When the V bit is set to 1, the other fields in the RCDR table entry for the DMA channel contain valid information.

Start RPD Pointer[14:0]

DMA Current Address[31:0]

This field contains the pointer to the first RPD for the packet being received.

The DMA Current Address [31:0] bits holds the host address of the next dword in the current buffer. The RMAC256 increments this field on each access to the buffer.

8.5.2 DMA Transaction Controller

The DMA Transaction Controller coordinates the reception of data packets from the Receive Packet Interface and their subsequent storage in host memory. A packet may be received over a number of separate transactions, interleaved with transactions belonging to other DMA channels. As well as sending the received data to host memory, the DMA Transaction Controller initiates data transactions of its own for the purposes of maintaining the data structures (queues, descriptors, etc.) in host memory.

8.5.3 Write Data Pipeline/Mux

The Write Data Pipeline/Mux performs two functions. First, it pipelines receive data between the RHDL256 block and the GPIC block, inserting enough delay to enable the DMA Transaction Controller to generate appropriate control signals at the GPIC interface. Second, it provides a multiplexor to the data out lines on the GPIC interface, allowing the DMA Transaction Controller to output data relating to the transactions the controller itself initiates.

8.5.4 Descriptor Information Cache

The Descriptor Information Cache provides the storage for the Receive Channel Descriptor Reference (RCDR) Table described above (Figure 9).

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8.5.5 Free Queue Cache

The Free Queue Cache block implements the 6 element RPDR Small Buffer Free Queue cache and the 6 element RPDR Large Buffer Free Queue cache. These caches are used to store free small buffer and large buffer RPDRs. Caching RPDRs reduces the number of host bus accesses that the RMAC256 makes.

Each cache is managed independently. The elements of the cache are consumed one at a time as they are needed by the RMAC256. The RPDR small buffer cache is reloaded when it is empty and the RMAC256 requires a new small buffer RPDR. The large buffer RPDR cache is reloaded when it is empty and the RMAC256 requires a new large buffer RPDR. When reloading either of the caches, the appropriate cache controller will read up to six new elements. The cache controller may read fewer than six elements if there are fewer than six new elements available, or the read pointer index is within six elements of the end of the free queue. If the read pointer is near the end of the free queue, the cache controller reads only to the end of the queue and does not start reading from the top of the queue until the next time a reload is required. To do so would require two host memory transactions and would be of no benefit.

8.6 PCI Controller

The General-Purpose Peripheral Component Interconnect Controller block (GPIC) provides a 32-bit Master and Target interface core which contains all the required control functions for full Peripheral Component Interconnect (PCI) Bus Revision 2.1 compliance. Communications between the PCI bus and other FREEDM-32P256 blocks can be made through either an internal asynchronous16-bit bus or through one of two synchronous FIFO interfaces. One of the FIFO interfaces is dedicated to servicing the Receive DMA Controller block (RMAC256) and the other to the Transmit DMA Controller block (TMAC256).

The GPIC supports a 32-bit PCI bus operating at up to 66 MHz and bridges between the timing domain of the DMA controllers (SYSCLK) and the timing domain of the PCI bus (PCICLK). The GPIC is backwards compatible and will operate at 33 MHz when connected to a 33 MHz PCI bus. By itself, the GPIC does not generate any PCI bus accesses. All transactions on the bus are initiated by another PCI bus master or by the core device. The GPIC transforms each access to and from the PCI bus to the intended target or initiator in the core device. Except for the configuration space registers and parity generating/checking, the GPIC performs no operations on the data.

The GPIC is made up of four sections: master state machine, a target state machine, internal microprocessor bus interface and error/bus controller. The

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target and master blocks operate independent of each other. The error/bus control block monitors the control signals from the target and master blocks to determine the state of the PCI I/O pads. This block also generates and/or checks parity for all data going to or coming from the PCI bus. The internal microprocessor bus interface block contains configuration and status registers together with the production test logic for the GPIC block.

8.6.1 Master Machine

The GPIC master machine translates requests from the RMAC256 and

TMAC256 block interfaces into PCI bus transactions. The GPIC initiates four types of PCI cycles: memory read (burst or single), memory read multiple, memory read line and memory write (burst or single). The number of data transfers in any cycle is controlled by the DMA controllers. The maximum burst size is determined by the particular data path. A read cycle to the RMAC256 is restricted to a maximum burst size of 8 dwords and a write cycle is limited to a maximum of 64. The TMAC256 interface has a limit of 64 dwords on a read cycle and 8 on a write cycle.

In response to a DMA controller requesting a cycle, the GPIC must arbitrate for control of the PCI bus. In the event that the RMAC256 and TMAC256 request service simultaneously, the GPIC66 processes the RMAC256 DMA operation first.

When an external PCI bus arbitrator issues a Grant in response to the Request from the GPIC, the master state machine monitors the PCI bus to insure that the previous master has completed its transaction and has released the bus before beginning the cycle. Once the GPIC has control of the bus, it will assert the FRAME signal and drive the bus with the address and command. The value for the address is provided by the selected DMA controller. After the initial data transfer, the GPIC tracks the address for all remaining transfers in the burst internally in case the GPIC is disconnected by the target and must retry the transaction.

The target of the GPIC master burst cycle has the option of stopping or disconnecting the burst at any point. In the event of a target disconnect the GPIC will terminate the present cycle and release the PCI bus. If the GPIC is asserting the REQUEST line at the time of the disconnect, it will remove the REQUEST for two PCI clock cycles then reassert it. When the PCI bus arbitrator returns the GRANT, the GPIC will restart the burst access at the next address and continue until the burst is completed or repeat the sequence if the target disconnects again.

During burst reads, the GPIC accepts the data without inserting any wait states. Data is written directly into the read FIFO where the RMAC256 or TMAC256 can

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remove it at its own rate. During burst writes, the GPIC will output the data without inserting any wait states, but may terminate the transaction early if the local master fails to fill the write FIFO with data before the GPIC requires it. (If a write transaction is terminated early due to data starvation, the GPIC will automatically initiate a further transaction to write the remaining data when it becomes available.)

Normally, the GPIC will begin requesting the PCI bus for a write transaction shortly after data starts to be loaded into the write FIFO by the RMAC256 or TMAC256. The RMAC256, however, is not required to supply a transaction length when writing packet data and in addition, may insert pauses during the transfer. In the case of packet data writes by the RMAC256, the GPIC will hold off requesting the PCI bus until the write FIFO has filled up with a number of dwords equal to a programmable threshold. If the FIFO empties without reaching the end of the transition, the GPIC will terminate the current transaction and restart a new transaction to transfer any remaining data when the RMAC256 signals an end of transaction. Beginning the PCI transaction before all the data is in the write FIFO allows the GPIC to reduce the impact of the bus latency on the core device.

Each master PCI cycle generated by the GPIC can be terminated in three ways: Completion, Timeout or Master Abort. The normal mode of operation of the GPIC is to terminate after transferring all the data from the master FIFO selected. As noted above this may involve multiple PCI accesses because of the inability of the target to accept the full burst or data starvation during writes. After the completion of the burst transfer the GPIC will release the bus unless another FIFO is requesting service, in which case if the GRANT is asserted the GPIC will insert one idle cycle on the bus and then start a new transfer.

The maximum duration of the a master burst cycle is controlled by the value set in the LATENCY TIMER register in the GPIC Configuration Register block. This value is set by the host on boot and is loaded into a counter in the GPIC master state at the start of each access. If the counter reaches zero and the GRANT signal has been removed the GPIC will release the bus regardless of whether it has completed the present burst cycle. This type of termination is referred to as a Master Time-out. In the case of a Master Time-out the GPIC will remove the REQUEST signal for two PCI clocks and then reassert it to complete the burst cycle.

If no target responds to the address placed on the bus by the GPIC after 4 PCI clocks the GPIC will terminate the cycle and flag the cycle in the PCI Command/ Status Configuration Register as a Master Abort. If the Stop on Error enable (SOE_E) bit is set in the GPIC Command Register, the GPIC will not process any more requests until the error condition is cleared. If the SOE_E is not set, the GPIC will discard the REQUEST and indicate to the local master that the cycle is

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complete. This action will result in any write data being lost and any read data being erroneous.

8.6.2 Master Local Bus Interface

The master local bus is a 32 bit data bus which connects the local master device to the GPIC. The GPIC contains two local master interface blocks, with one supporting the RMAC256 and the other the TMAC256. Each local master interface has been optimised to support the traffic pattern generated by the RMAC256 or the TMAC256 and are not interchangeable.

The data path between the GPIC and local master device provides a mechanism to segregate the system timing domain of the core from the PCI bus. Transfers on each of the RMAC256 and TMAC256 interfaces are timed to its own system clock. The DMA controllers isolated from all aspects of the PCI bus protocol, and instead “sees” a simple synchronous protocol. Read or write cycles on the local master bus will initiate a request for service to the GPIC which will then transfer the data via the PCI bus.

The GPIC maximises data throughput between the PCI bus and the local device by paralleling local bus data transfers with PCI access latency. The GPIC allows either DMA controller to write data independent of each other and independent of PCI bus control. The GPIC temporarily buffers the data from each DMA controller while it is arbitrating for control of the PCI bus. After completion of a write transfer, the DMA controller is then released to perform other tasks. The GPIC can buffer only a single transaction from each DMA controller.

Read accesses on the local bus are optimised by allowing the DMA controllers access to the data from the PCI bus as soon as the first data becomes available. After the initial synchronisation and PCI bus latency data is transferred at the slower of PCI bus rate or the core logic SYSCLK rate. Once a read transaction is started, the DMA controller is held waiting for the ready signal while the GPIC is arbitrating for the PCI bus.

All data is passed between the GPIC and the DMA controllers in little Endian format and, in the default mode of operation, the GPIC expects all data on the PCI bus to also be in little Endian format. The GPIC provides a selection bit in the internal Control register which allows the Endian format of the PCI bus data to be changed. If enabled, the GPIC will swizzle all packet data on the PCI bus (but not descriptor references and the contents of descriptors). The swizzling is performed according to the “byte address invariance” rule, i.e. the only change to the data is the mirror-imaging of byte lanes.

The interface for the RMAC256 provides for byte addressability of write transactions whereas the interface for the TMAC256 provides for byte

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addressability of read transactions. Other transactions must be dword aligned. For byte-addressable transactions, the data transferred between the local device and the GPIC need not be dword aligned with the data as it is presented on the PCI bus. The GPIC will perform any byte-realignment required. In order to complete a transfer involving byte re-alignment, the GPIC may need to add an extra burst cycle to the PCI transaction.

8.6.3 Target Machine

The GPIC target machine performs all the required functions of a stand alone PCI target device. The target block performs three main functions. The first is the target state machine which controls the protocol of PCI target accesses to the GPIC. The second function is to provide all PCI Configuration registers. Last, the target block provides a Target Interface to the CBI registers in the other FREEDM-32P256 blocks.

The GPIC tracks the PCI bus and decodes all addresses and commands placed on the bus to determine whether to respond to the access. The GPIC responds to the following types of PCI bus commands only: Configuration read and write, memory read and write, memory-read-multiple and memory-read-line which are aliased to memory read and memory-write-and-invalidate which is aliased to memory write. The GPIC will ignore any access that falls within the address range but has any other command type.

After accepting a target access as a medium speed device, the FREEDM32P256 inserts one wait state for a configuration read/write and five wait states for other command types before completing the transaction by asserting TRDYB.

Burst accesses to the GPIC are accepted provided they are of linear type. If a master makes a memory access to the GPIC with the lower two address bits set to any value but "00" (linear burst type) the GPIC ignores the cycle. Burst accesses of any length are accepted, but the FREEDM-32P256 will disconnect if the master inserts any wait states during the transaction. The FREEDM-32P256 will also disconnect on every read and write access to configuration space after transferring one Dword of data.

Figure 10 illustrates the GPIC address space.

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Figure 10 – GPIC Address Map

PCI ADDRESS MAP

CBI Registers Base Address

CBI Registers

4GB

8KB

The GPIC responds with medium timing to master accesses. (i.e. DEVSELB is asserted 2 PCICLK cycles after FRAMEB asserted). The GPIC inserts five wait states on reads to the internal CBI register space (six wait states for the 2nd and subsequent dwords of a burst read). The target machine will only terminate an access with a Retry if the target is locked and another master tries to access the GPIC. The GPIC will terminate any access to a non-burst area with a Disconnect and always with data transferred. The target does not support delayed transactions. The GPIC will perform a Target-Abort termination only in the case of an address parity error in an address that the GPIC claims.

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8.6.4 CBI Bus Interface

The CBI bus interface provides access to the CBI address space of the FREEDM-32P256 blocks. The CBI address space is set by the associated BAR in the PCI Configuration registers.

Write transfers to the CBI space always write all 32 bits provided that at least one byte enable is asserted. A write command with all byte enables negated will be ignored. Read transfers always return the 32 bits regardless of the status of the byte enables, as long as at least one byte enable is asserted. A read command with all byte enables negated will be ignored.

8.6.5 Error / Bus Control

The Error/Bus Control block monitors signals from both the Target block and Master Block to determine the direction of the PCI bus pads and to generate or check parity. After reset, the GPIC sets all bi-directional PCI bus pads to inputs and monitors the bus for accesses. The Error/Bus control unit remains in this state unless either the Master requests the PCI bus or the Target responds to a PCI Master Access. The Error/Bus control unit decodes the state of each state machine to determine the direction of each PCI bus signal.

All PCI bus devices are required to check and generate even parity across AD[31:0] and C/BEB[3:0] signals. The GPIC generates parity on Master address and write data phases; the target generates parity on read data phases. The GPIC is required to check parity on all PCI bus phases even if it is not participating in the cycle. But, the GPIC will report parity errors only if the GPIC is involved in the PCI cycle or if the GPIC detects an address parity error or data parity is detected in a PCI special cycle. The GPIC updates the PCI Configuration Status register for all detected error conditions.

8.7 Transmit DMA Controller

The Transmit DMA Controller block (TMAC256) is a DMA controller which retrieves packet data from host computer memory for transmission. The minimum packet data length is two bytes. The TMAC256 communicates with the host computer bus through the master interface connected to PCI Controller block (GPIC) which translates host bus specific signals from the host to the master interface format. The TMAC256 uses the master interface whenever it wishes to initiate a host bus read or write; in this case, the TMAC256 is the initiator and the host memory is the target.

The TMAC256 and the host exchange information using transmit descriptors (TDs). The descriptor contains the size and location of buffers in host memory

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and the packet status information associated with the data in each buffer. TDs are transferred from the TMAC256 to the host and vice versa using descriptor reference queues. The TMAC256 maintains all the pointers for the operation of the queues. The TMAC256 acquires buffers with data ready for transmission by reading TDRs from a TDR ready queue. After a packet has been transmitted, the TMAC256 places the associated TDR onto a TDR free queue.

To minimise host bus accesses, the TMAC256 maintains a descriptor reference table to store current DMA information. This table contains separate DMA information entries for up to 256 transmit channels. The TMAC256 also performs per-channel sorting of packets received in the TDR ready queue to eliminate head-of-line blocking.

8.7.1 Data Structures

The TMAC256 communicates with the host using Transmit Descriptors (TD), Transmit Descriptor References (TDR), the Transmit Data Reference Ready (TDRR) queue and the Transmit Data Reference Free (TDRF) queue.

The TMAC256 reads packet data from data buffers in host memory. The TD, TDR, TDRR queue, and TDRF queue are data structures which are used to transfer host memory data buffer information. All four data structures are manipulated by both the TMAC256 and the host computer. The TD holds the data buffer size, data buffer address, and other packet information. The TDR is a pointer which is used to index into a table of TDs. The TDRR queue and TDRF queue allow the TMAC256 and the host to pass TDRs back and forth. These data structures are described in more detail in the following sections.

Transmit Descriptor

The Transmit Descriptors (TDs) pass buffer and packet information between the TMAC256 and the host. Both the TMAC256 and the host read and write information in the TDs. TDs are stored in host memory in a Transmit Descriptor Table. The Transmit Descriptor structure is shown in Figure 11.

Figure 11 – Transmit Descriptor

Bit 31 0

Data Bu ffer S tart Addres s [31:0 ]

IOCABT

Bytes In B uffer [1 5:0]

Res (2)

TCC[9:0]

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Host Next TD P ointer[14 :0]

Transmit Buffer Size[15:0]

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Table 9 – Transmit Descriptor Fields

Field Description

Data Buffer Start Address [31:0]

The Data Buffer Start Address[31:0] bits point to the data buffer in host memory.

The Data Buffer Start Address field is valid in all TDs

Bytes In Buffer [15:0] The Bytes In Buffer[15:0] field is used by the host to

indicate the total number of bytes to be transmitted in the current TD. Zero length buffers are illegal.

P The Priority bit is set by the host to indicate the

priority of the associated packet in a two level quality of service scheme. Packets with its P bit set high are queued in the high priority queue in the TMAC256. Packets with the P bit set low are queued in the low priority queue. Packets in the low priority queue will not begin transmission until the high priority queue is empty.

ABT The Abort (ABT) bit is used by the host to abort the

transmission of a packet. When ABT is set to logic 1, the packet will be aborted after all the data in the buffer has been transmitted. If ABT is set to logic 1 in the current TD, the M bit must be set low and the CE bit must be set to high.

IOC The Interrupt On Complete (IOC) bit is used by the

host to instruct the TMAC256 to interrupt the host when the current TD's data buffer has been read. When IOC is logic 1, the TMAC256 asserts the IOCI interrupt when the data buffer has been read. Additionally, the Free Queue FIFO will be flushed. If IOC is logic zero, the TMAC256 will not generate an interrupt and the Free Queue FIFO will operate normally.

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Field Description

CE The Chain End (CE) bit is used by the host to indicate

the end of a linked list of TDs presented to the TMAC256. The linked list can contain one or more packets as delineated by the M bit (see above). When CE is set to logic 1, the current TD is the last TD of a linked list of TDs. When CE is set to logic 0, the current TD is not the last TD of a linked list. When the current TD is not the last of the linked list, the Host Next TD Pointer[14:0] field is valid, otherwise the field is not valid.

Note: When CE is set to logic 1, the only valid value for M is logic 0.

Note: When presenting raw (i.e. unpacketised) data for transmission, the host should code the M and CE bits as for a single packet chain, i.e. M=1, CE=0 for all TDs except the last in the chain and M=0, CE=1 for the last TD in the chain.

TCC[9:0] The Transmit Channel Code (TCC[9:0]) bits are used

by the host to associate a channel with a TD pointed to by a TDR.

All TCC[9:0] fields in a linked list of TDs must be set to the same value.

V The V bit is used to indicate that the TMAC Next TD

Pointer field is valid. When set to logic 1, the TMAC Next TD Pointer[14:0] field is valid. When V is set to logic 0, the TMAC Next TD Pointer[14:0] field is invalid. The V bit is used by the host to reclaim data buffers in the event that data presented to the TMAC256 is returned to the host due to a channel becoming unprovisioned. The V bit is expected to be initialised to logic 0 by the host.

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Field Description

TMAC Next TD Pointer [14:0]

The TMAC Next TD Pointer[14:0] bits are used to store TDRs which permits the TMAC256 to create linked lists of TDs passed to it via the TDRR queue. The TDs are linked with other TDs belonging to the same channel and same priority level. In the case that data presented to the TMAC256 is returned to the host due to a channel becoming unprovisioned, a TDR pointing to the start of the per-channel linked list of TDs is placed on the TDRF queue. It is the responsibility of the host to follow the TMAC256 and host links in order to recover all the buffers.

M The More (M) bit is used by the host to support

packets that require multiple TDs. If M is set to logic 1, the current TD is just one of several TDs for the current packet. If M is set to logic 0, this TD either describes the entire packet (in the single TD packet case) or describes the end of a packet (in the multiple TD packet case).

Note: When M is set to logic 1, the only valid value for CE is logic 0.

Host Next TD Pointer [14:0]

The Host Next TD Pointer[14:0] bits are used to store TDRs which permits the host to support linked lists of TDs. As described above, linked lists of TDs are terminated by setting the CE bit to logic 1. Linked lists of TDs are used by the host to pass multiple TD packets or multiple packets associated with the same channel and priority level to the TMAC256.

Transmit Buffer Size [15:0]

The Transmit Buffer Size[15:0] field is used to indicate the size in bytes of the current TD's data buffer. (N.B. The TMAC256 does not make use of this field.)

Transmit Descriptor Table

The Transmit Descriptor Table, which resides in host memory, contains all of the Transmit Descriptors referenced by the TMAC256. To access a TD, the TMAC256 takes a TDR from a TDRR queue or from the TCDR table and adds 16 times its value (because each TD is 16 bytes in size) to the Transmit Descriptor Table Base (TDTB) pointer to form the actual address of the TD in host memory. Each TD must reside in the Transmit Descriptor Table. The

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Transmit Descriptor Table can contain a maximum of 32768 TDs. The base of the Transmit Descriptor Table is user programmable using the TMAC Tx Descriptor Table Base register. Thus, as shown below, each TD can be located using a Transmit Descriptor Reference (TDR) combined with the TMAC Tx Descriptor Table Base register.

Figure 12 – Transmit Descriptor Table

TDTB[31:4] = Tx Descriptor Table Base register

TDR[14:0] = Transmit Descriptor Reference

TD_ADDR[31:0] = Transmit Descriptor Address

Bit 31 Bit 0

TDTB[31:4]

0000

TDR[14:0]

0000

TDTB

TD_ADDR

TD1

TD2

TD 32768

TD_ADDR[31:0]

Bit 0Bit 31

Dword 0 Dword 1 Dword 2 Dword 3 Dword 0

Dword 3

Dword 0

Dword 3

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Transmit Queues

Pointers to the transmit descriptors (TDs) containing packet(s) ready for transmission are passed from the host to the TMAC256 using the Transmit Descriptor Reference Ready (TDRR) queue, which resides in host memory. Pointers to transmit descriptor structures whose buffers have been read by the TMAC256 are passed from the TMAC256 to the host using the Transmit Descriptor Reference Free (TDRF) queue, which also resides in host memory. The TMAC256 contains a Free Queue cache which can store up to six TDRs. If caching is enabled, free TDRs are written into the TDRF queue six at a time, to reduce the number of host memory accesses. The Free Queue cache is flushed to the TDRF queue if the Interrupt On Completion (IOC) bit is set in the TD, which sends the corresponding TDR directly to the TDRF queue. The Free Queue cache is also flushed to the TDRF queue if the FQFLUSH register bit is set high. The FQFLUSH register bit is self clearing.

The queues, shown in Figure 13 are defined by a common base pointer residing in the Transmit Queue Base register and eight offset pointers, four per queue. For each queue, two pointers define the start and the end of the queue, and two pointers keep track of the current read and write locations within the queue. The read pointer for each queue points to the offset of the last valid TDR read, and the write pointer points to the offset where next TDR can be written. The end of a queue is not a valid location for a TDR to be read or written. A queue is empty when the read pointer is one less than the write pointer or if the read pointer is one less than the end pointer and the write pointer equals the start pointer. A queue is full when the read pointer is equal to the write pointer. Each queue element is 32 bits in size, but only the least significant 18 bits are valid. The 18 least significant bits consist of a 15-bit TDR and three status bits for the TD pointed at by this TDR. The status bits are used by the TMAC256 to inform the host of the success or failure of transmission (see Table 10). When the TMAC256 writes TDRs to the TDRF queue, it sets bits [23:18] of the queue element to 0 and leaves bits [31:24] unaltered. Once a TDR is placed on the TDRF queue, the FREEDM-32P256 will make no further accesses to the TD nor the associated buffer.

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Figure 13 – TDRR and TDRF Queues

Transmit Descriptor Referance Queues

Base Address:

TQB[31:2] = Tx Queue Base register

Index Registers:

Ready:

TDRRQS[15:0] = TDR Ready Queue Start registe TDRRQW[15:0] = TDR Ready Queue Write registe TDRRQR[15:0] = TDR Ready Queue Read register TDRRQE[15:0] = TDR Ready Queue End registe

Free:

TDRFQS[15:0] = TDR Free Queue Start register TDRFQW[15:0] = TDR Free Queue Write register TDRFQR[15:0] = TDR Free Queue Read register TDRFQE[15:0] = TDR Free Queue End register

Base Address

+ Index Register

------------------------PCI Address

TQB[31:2]

Index[15:0]

D[31:0]

Tx Descriptor Reference Queue Mem ory Map

TDR FQS

TDR FQR

TDR FQW

TDR FQE

TDRRQS

TDRRQR

TDRRQW

TDRRQE

Status + TDR

TDR

Bit 0Bit 31

PCI Host Memory

TQB

TDR Reference Queues

Valid TDR

256KB

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Table 10 – Transmit Descriptor Reference

Bit 17 Bit 0

STATUS[2:0] TDR[14:0]

Field Description

Status[2:0] The TMAC256 fills in the Status field to indicate to the

host the results of processing the TD. The encoding is:

Status[1:0] Description

00 Last or only buffer of packet, buffer read. 01 Buffer of partial packet, buffer read. 10 Unprovisioned channel, buffer not read. 11 Malformed packet (e.g. Bytes In Buffer field

set to 0), buffer not read.

Status[2] Description

0 No underflow detected. 1 Underflow detected.

TDR[14:0] The TDR[14:0] field contains the offset of the TD

returned.

If a TDR is returned to the host with the status field set to “10” (unprovisioned channel), the TDR may point to a binary tree of TDs and buffers (as indicated by the CE and V bits in the TDs). It is the responsibility of the host to traverse the tree to reclaim all the buffers. If a TDR is returned to the host with the status field set to any other value, the TDR will only point to one TD and buffer regardless of the values of V and CE in that TD.

The underflow status bit (Status[2]) is normally attached to the TDR belonging to a packet experiencing underflow. For long packets spanning multiple buffers, underflow is reported only once at the first available TDR of that channel. All subsequent TDRs of that packet will be returned normally without the underflow status. In rare cases, due to internal buffering by the FREEDM-32P256, a packet may experience underflow at the very end of a packet, just as the TDR is being returned to the TDR free queue. The underflow status will then be reported in the first TDR of the immediate next packet of that channel. Because of the uncertainty with the reporting of underflows between the current verse the subsequent packet, the underflow status should only be used to gather performance statistics on channels and not for initiating packet specific responses such as retransmission.

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Transmit Channel Descriptor Reference Table

The TMAC256 maintains a Transmit Channel Descriptor Reference (TCDR) table in which is stored certain information relating to DMA activity on each channel together with TD pointers which are used by the TMAC256 to sort packet chains supplied by the host into per-channel linked lists (see below). The caching of DMA-related information reduces the number of host bus accesses required to process each data packet, while the sorting into per-channel linked lists eliminates head of line blocking. Each channel is provided with two entries in the TCDR table, one for high priority packets (Pri 1) and one for low priority packets (Pri 0). The structure of the TCDR table is shown in Figure 14 below.

Figure 14 – Transmit Channel Descriptor Reference Table

Bit 0

TCC 0, Pri 0

TCC 1, Pri 0

Bit 33

Res

Reserved (12)

PiP

Last TD Pointer [14:0]

Reserved (12)

PiP

Last TD Pointer [14:0]

IOCAbrt

Bytes to Tx [15:0]

DMA Current Address[31:0]

IOCAbrt

Bytes to Tx [15:0]

DMA Current Address[31:0]

DAMCE

Current TD Pointer [14:0]

Res

Host TD Pointer [14:0]

Next TD Pointer [14:0]

DAMCE

Current TD Pointer [14:0]

Host TD Pointer [14:0]

Next TD Pointer [14:0]

IOCAbrt

TCC 671, Pri 1

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Reserved (12)

Res

PiP

Res

Bytes to Tx [15:0]

Last TD Pointer [14:0]

DMA Current Address[31:0]

DAMCE

Current TD Pointer [14:0]

Res

Host TD Pointer [14:0]

Next TD Pointer [14:0]

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Table 11 – Transmit Channel Descriptor Reference Table Fields

Field Description

NA Indicates that a ‘null abort’ is to be sent to the

downstream block when it next requests data on this channel. The NA bit is set if a mal-formed TD is encountered while searching down a host chain.

ABRT A copy of the ABRT bit in the TD currently being read.

IOC A copy of the IOC bit in the TD currently being read.

M A copy of the M bit in the TD currently being read.

CE A copy of the CE bit in the TD currently being read.

A Indicates if this channel is active (i.e. provisioned). If

the channel is active, the A bit is set to logic 1. If the channel is inactive, the A bit is set to logic 0.

D Indicates whether the linked list of packets for this

channel is empty or not. If the D bit is set to logic 1, the list is not empty and the current TD pointer field is valid (i.e., it points to a valid TD). If the D bit is set to logic 0, the list is empty and the current TD pointer field is invalid.

Current TD Pointer

Offset to the TD currently being read. (See Figure 15)

[14:0]

Bytes To Tx[15:0] The Bytes to Tx[15:0] bits are used to indicate the total

number of bytes that remain to be read in the current buffer. Each access to the data buffer decrements this value. A value of zero in this field indicates the buffer has been completely read.

Host TD Pointer [14:0] A copy of the Host Next TD Pointer field of the TD

currently being read, i.e. a pointer to the next TD in the chain currently being read. (See Figure 15)

DMA Current Address[31:0]

The DMA Current Address [31:0] bits hold the address of the next dword in the current buffer. This field is incremented on each access to the buffer.

U Indicates that an underflow has occurred on this

channel. This bit is set in response to an underflow indication for the downstream THDL256 block and is cleared when a TDR is written to the TDR Free Queue (or to the free queue cache).

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Field Description

PiP The Packet Transfer in Progress bit indicates that a

packet is currently being transmitted on this channel at this priority level.

Last TD Pointer [14:0] Offset to the head of the last host-linked chain of TDs

to be read. (See Figure 15)

V Indicates if the linked list of packets for this channel

contains more than one host-linked chain (See Figure

15). If the V bit is set to logic 1, the list contains more than one chain and the next and last TD pointer fields are valid. If the V bit is set to logic 0, the list is either empty or contains only one host-linked chain and the next and last TD pointer fields are invalid.

Next TD Pointer [14:0] Offset to the head of the next host-linked chain of TDs

to be read. (See Figure 15)

Transmit Descriptor Linking

As described above, the TCDR table contains pointers which the TMAC256 uses to construct linked lists of data packets to be transmitted. After the host places a new TDR in the TDR Ready queue, the TMAC256 retrieves the TDR and links it to the TD pointed at by the Last TD Pointer field. The TMAC256 may create up to 1,344 linked lists, viz. a high-priority list and a low-priority list for each DMA channel. Whenever a new data packet is requested by the downstream block, the TMAC256 picks a packet from the high-priority linked list unless it is empty, in which case, a packet from the low-priority linked list is used.

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Figure 15 – TD Linking

TD TD

V=1

M=1

CE=0

TMAC Link

Data

Host Li nk

M=0

CE=1

Data

V=0

M=0

CE=1

Curr.

TDR

Last

TCDR Table

Host TDR

Host Link

V=1 M=1

CE=0

M=1

CE=0

TMAC Link

Data

Host Link

M=0

CE=0

Data

Host Link

M=0

CE=1

Data

The host links the TDs vertically while the TMAC256 links TDs horizontally. Figure 15 shows the TDs for packets P1 and P2 linked by the host before the TDR is placed on the TDRR queue, as are the TDs for packet P3 and P4. Packet P3 is linked to packet P1 by the TMAC256, as is packet P4 linked to

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packet P3. The TMAC256 indicates valid horizontal links by setting the V bit to logic 1.

8.7.2 Task Priorities

The TMAC256 must perform a number of tasks concurrently in order to maintain a steady flow of data through the system. The main tasks of the TMAC256 are managing the Ready Queue (i.e. removing chains of data packets from the queue and attaching them to the appropriate per-channel linked list) and servicing requests for data from the Transmit Packet Interface. The priority of service for each of the tasks is fixed by the TMAC256 as follows:

· Top priority is given to servicing ‘expedited’ read requests from the Transmit HDLC Processor / Partial Packet Buffer block (THDL256).

· Second priority is given to removing chains of data packets from the TDRR queue and attaching them to the appropriate per-channel linked list.

· Third priority is given to servicing non-expedited read requests from the THDL256.

8.7.3 DMA Transaction Controller

The DMA Transaction Controller coordinates the processing of requests from the THDL256 with the reading of data stored in host memory. The reading of a data packet may require a number of separate host memory transactions, interleaved with transactions of other DMA channels. As well as reading data from the Host Master Interface, the DMA Transaction Controller initiates read and write transactions to the PCI Controller block (GPIC) for the purposes of maintaining the data structures (queues, descriptors, etc.) in host memory.

8.7.4 Read Data Pipeline

The Read Data Pipeline inserts delay in the data stream between the GPIC interface and the THDL256 interface to enable the DMA Transaction Controller to generate appropriate control signals at the Transmit Packet Interface.

8.7.5 Descriptor Information Cache

The Descriptor Information Cache provides the storage for the Transmit Channel Descriptor Reference (TCDR) Table.

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8.7.6 Free Queue Cache

The Free Queue Cache block implements the 6 element TDR Free Queue cache. Caching TDRs reduces the number of host bus accesses that the TMAC256 makes.

TDRs are written to the cache one at a time as they are released by the TMAC256. The cache is then flushed to host memory when it becomes full, when a TD with the IOC bit set high is released, when the FQFLUSH register bit is set high or when a TD is released as the result of unprovisioning a channel. The cache controller may also flush the cache when it contains fewer than six elements or if the pointer index is within six elements of the end of the free queue. When the write pointer is near the end of the free queue, the cache controller writes only to the end of the queue and does not start writing from the top of the queue until the next time a flush is required. To do so would require two host memory transactions and would be of no benefit.

8.8 Transmit HDLC Controller / Partial Packet Buffer

The Transmit HDLC Controller / Partial Packet Buffer block (THDL256) contains a partial packet buffer for PCI latency control and a transmit HDLC controller. Packet data retrieved from the PCI host memory by the Transmit DMA Controller block (TMAC256) is stored in channel specific FIFOs residing in the partial packet buffer. When the amount of data in a FIFO reaches a programmable threshold, the HDLC controller is enabled to initiate transmission. The HDLC controller performs flag generation, bit stuffing and, optionally, frame check sequence (FCS) insertion. The FCS is software selectable to be CRC-CCITT or CRC-32. The minimum packet size, excluding FCS, is two bytes. A single byte payload is illegal. The HDLC controller delivers data to the Transmit Channel Assigner block (TCAS256) on demand. A packet in progress is aborted if an under-run occurs. The THDL256 is programmable to operate in transparent mode where packet data retrieved from the PCI host is transmitted verbatim.

8.8.1 Transmit HDLC Processor

The HDLC processor is a time-slice state machine which can process up to 256 independent channels. The state vector and provisioning information for each channel is stored in a RAM. Whenever the TCAS256 requests data, the appropriate state vector is read from the RAM, processed and finally written back to the RAM. The HDLC state-machine can be configured to perform flag insertion, bit stuffing and CRC generation. The HDLC processor requests data from the partial packet processor whenever a request for channel data arrives. However, the HDLC processor does not start transmitting a packet until the entire packet is stored in the channel FIFO or until the FIFO free space is less than the

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software programmable limit. If a channel FIFO under-runs, the HDLC processor aborts the packet.

The configuration of the HDLC processor is accessed using indirect channel read and write operations. When an indirect operation is performed, the information is accessed from RAM during a null clock cycle inserted by the TCAS256 block. Writing new provisioning data to a channel resets the channel’s entire state vector.

8.8.2 Transmit Partial Packet Buffer Processor

The partial packet buffer processor controls the 32 Kbyte partial packet RAM which is divided into 16 byte blocks. A block pointer RAM is used to chain the partial packet blocks into circular channel FIFO buffers. Thus, non-contiguous sections of RAM can be allocated in the partial packet buffer RAM to create a channel FIFO. Figure 16 shows an example of three blocks (blocks 1, 3, and

200) linked together to form a 48 byte channel FIFO. The three pointer values

would be written sequentially using indirect block write accesses. When a channel is provisioned with this FIFO, the state machine can be initialised to point to any one of the three blocks.

The partial packet buffer processor is divided into three sections: reader, writer and roamer. The roamer is a time-sliced state machine which tracks each channel's FIFO buffer free space and signals the writer to service a particular channel. The writer requests data from the TMAC256 block and transfers packet data from the TMAC256 to the associated channel FIFO. The reader is a timesliced state machine which transfers the HDLC information from a channel FIFO to the HDLC processor when the HDLC processor requests it. If a buffer underrun occurs for a channel, the reader informs the HDLC processor and purges the rest of the packet.

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Figure 16 – Partial Packet Buffer Structure

Block 0

Block 1

Block 2

Block 3

Partial Packet

Buffer RAM

16 bytes

Block 0

Block 1

Block 2

Block 3

Block

Pointer RAM

0x03

0xC8

0x01

Block 2047

16 bytes

Block 200Block 200

Block 2047

The FIFO algorithm of the partial packet buffer processor is based on perchannel software programmable transfer size and free space trigger level. Instead of tracking the number of full blocks in a channel FIFO, the processor tracks the number of empty blocks, called free space, as well as the number of end of packets stored in the FIFO. Recording the number of empty blocks instead of the number of full blocks reduces the amount of information the roamer must store in its state RAM.

The partial packet roamer records the FIFO free space and end-of-packet count for all channel FIFOs. When the reader signals that a block has been read, the roamer increments the FIFO free space and sets a per-channel request flag if

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the free space is greater than the limit set by XFER[3:0]. The roamer also decrements the end-of-packet count when the reader signals that it has passed an end of a packet to the HDLC processor. If the HDLC is transmitting a packet and the FIFO free space is greater than the starving trigger level and there are no complete packets within the FIFO (end-of-packet count equal to zero), a perchannel starving flag is set. The roamer searches the starving flags in a roundrobin fashion to decide which channel FIFO should make expedited data requests to the TMAC256 block. If no starving flags are set, the roamer searches the request flags in a round-robin fashion to decide which channel FIFO should make regular data requests to the TMAC256 block. The roamer informs the partial packet writer of the channel FIFO to process, the FIFO free space and the type of request it should make. The writer sends a request for data to the TMAC256 block, writes the response data to the channel FIFO, and sets the block full flags. The writer reports back to the roamer the number of blocks and end-of-packets transferred. The maximum amount of data transferred during one request is limited by a software programmable limit (XFER[3:0]).

The configuration of the HDLC processor is accessed using indirect channel read and write operations as well as indirect block read and write operations. When an indirect operation is performed, the information is accessed from RAM during a null clock cycle identified by the TCAS256 block. Writing new provisioning data to a channel resets the entire state vector.

8.9 Transmit Channel Assigner

The Transmit Channel Assigner block (TCAS256) processes up to 256 channels. Data for all channels is sourced from a single byte-serial stream from the Transmit HDLC Controller / Partial Packet Buffer block (THDL256). The TCAS256 demultiplexes the data and assigns each byte to any one of 32 links. Each link may be configured to support 2.048 or 8.192 H-MVIP traffic, to support T1/J1/E1 channelised traffic or to support unchannelised traffic. When configured to support H-MVIP traffic, each group of 8 links share a clock and frame pulse, otherwise each link is independent and has its own associated clock. For each high-speed link (TD[2:0]), the TCAS provides a six byte FIFO. For the remaining links (TD[31:3]), the TCAS provides a single byte holding register. The TCAS256 also performs parallel to serial conversion to form a bitserial stream. In the event where multiple links are in need of data, TCAS256 requests data from upstream blocks on a fixed priority basis with link TD[0] having the highest priority and link TD[31] the lowest.

From the point of view of the TCAS256, links configured for H-MVIP traffic behave identically to links configured for T1/J1/E1 channelised or unchannelised traffic in the back end, only differing on the link side as described herein. First, the number of time-slots in each frame is programmable to be 32 or 128 and has

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an associated data clock frequency that is double the data rate. This provides more bandwidth per link for applications requiring higher data densities on a single link. Data at each time-slot may be independently assigned to be sourced from a different channel. Second, H-MVIP links reference the start of each frame with a frame pulse, thereby avoiding having to gap the link clock during the framing bits/bytes of each frame. The frame pulse is provided by an H-MVIP bus master and ensures that all agents sharing the H-MVIP bus remain synchronized. When configured for operation in 2.048 Mbps H-MVIP mode, the frame pulse is sampled using the same clock which samples the data. When configured for operation in 8.192 Mbps H-MVIP mode, the frame pulse is sampled using a separate frame pulse clock provided by an H-MVIP bus master. The frame pulse clock has a synchronous timing relationship to the data clock. Third, not all links are independent. When configured for operation in 2.048 Mbps H-MVIP mode, each group of 8 links share a clock and a frame pulse. Links 0 through 7, 8 through 15, 16 through 23 and 24 through 31 each share a clock and a frame pulse. Not all 8 links within each group need to be configured for operation in 2.048 Mbps H-MVIP mode. However, any link within each logical group of 8 which is configured for 2.048 Mbps H-MVIP operation will share the same clock and frame pulse. When configured for operation in 8.192 Mbps H-

MVIP mode, links 4m (0£m£7) share a frame pulse, a data clock and a frame pulse clock. Again, not all eight 4m (0£m£7) links need to be configured for

operation in 8.192 Mbps H-MVIP mode, however, any link which is configured for

8.192 Mbps H-MVIP operation will share the same frame pulse, data clock and

frame pulse clock. If link 4m is configured for 8.192 Mbps H-MVIP operation, then data transferred on that link is “spread” over links 4m, 4m+1 4m+2 and 4m+3 from a channel assigner point of view. Accordingly, when link 4m is configured for operation in 8.192 Mbps H-MVIP mode, links 4m+1, 4m+2 and 4m+3 must also be configured for operation in 8.192 Mbps H-MVIP mode. In the back end, the TCAS256 extracts and processes the time-slots identically to channelised T1/J1/E1 traffic.

Links containing a T1/J1 or an E1 stream may be channelised. Data at each time-slot may be independently assigned to be sourced from a different channel. The link clock is only active during time-slots 1 to 24 of a T1/J1 stream and is inactive during the frame bit. Similarly, the clock is only active during time-slots 1 to 31 of an E1 stream and is inactive during the FAS and NFAS framing bytes. The most significant bit of time-slot 1 of a channelised link is identified by noting the absence of the clock and its re-activation. With knowledge of the transmit link and time-slot identity, the TCAS256 performs a table look-up to identify the channel from which a data byte is to be sourced.

Links may also be unchannelised. Then, all data bytes on that link belong to one channel. The TCAS256 performs a table look-up to identify the channel to which a data byte belongs using only the outgoing link identity, as no time-slots are associated with unchannelised links. Link clocks are no longer limited to T1/J1

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or E1 rates and may range up to a maximum clock rate of 51.84 MHz for TCLK[2:0] and 10 MHz for TCLK[31:3]. The link clock is only active during bit times containing data to be transmitted and inactive during bits that are to be ignored by the downstream devices, such as framing and overhead bits. For the case of two unchannelised links, the maximum link rate is 51.84 MHz. For the case of more numerous unchannelised links or a mixture of channelised, unchannelised and H-MVIP links, the total instantaneous link rate over all the links is limited to 64 MHz.

8.9.1 Line Interface Translator (LIT)

The LIT block translates the information between the 32 physical links and the Line Interface block. The LIT block performs three functions: data translation, clock translation and frame pulse generation.

When link 4m (0£m£7) is configured for operation in 8.192 Mbps H-MVIP mode, the LIT block translates the data arriving from the Line Interface block on links 4m, 4m+1, 4m+2 and 4m+3 onto the 128 time-slot link 4m. The LIT block translates data arriving from the Line Interface block on link 4m, 4m+1, 4m+2 and 4m+3 onto time-slots 0 through 31, 32 through 63, 64 through 95 and 96 through 127 respectively. When link 4m is configured for operation in 8.192 Mbps H-MVIP mode, outputs TD[4m+3:4m+1] are driven with constant ones. However, links 4m+1, 4m+2 and 4m+3 must be programmed in the TCAS256 Link Configuration register for 8.192 Mbps H-MVIP operation. When links are configured for operation in 2.048 Mbps H-MVIP mode, channelised T1/J1/E1 mode or unchannelised mode, the LIT block does not perform any translation on the link data.

When a link is configured for operation in H-MVIP mode, the LIT block divides the appropriate clock (TMVCK[n] for 2.048 Mbps H-MVIP and TMV8DC for 8.192 Mbps H-MVIP) by two and provides this divided down clock to the Line Interface block. When a link is configured for operation in channelised T1/J1/E1 or unchannelised mode, the LIT block does not perform any translation on the link clock.

When a link is configured for operation in H-MVIP mode, the LIT block samples the appropriate frame pulse (TFPB[n] for 2.048 Mbps H-MVIP and TFP8B for

8.192 Mbps H-MVIP) and presents the sampled frame pulse to the Line Interface

block. When a link is configured for operation in channelised T1/J1/E1 or unchannelised mode, the gapped clock is passed to the LIT block unmodified.

8.9.2 Line Interface

There are 32 identical line interface blocks in the TCAS256. Each line interface block contains 2 sub-blocks; one supporting channelised T1/J1/E1 streams and

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the other H-MVIP streams. Based on configuration, only one of the sub-blocks are active at one time; the other is held reset. Each sub-block contains a bit counter, an 8-bit shift register and a holding register. Each sub-block performs parallel to serial conversion. Whenever the shift register is updated, a request for service is sent to the priority encoder block. When acknowledged by the priority encoder, the line interface would respond by writing the data into the holding register in the active sub-block.

To support H-MVIP links, each line interface block contains a time-slot counter. The time-slot counter is incremented each time the holding register is updated. When a frame pulse occurs, the time-slot counter is cleared to indicate that the next byte belongs to the first time-slot.

To support non H-MVIP channelised links, each line interface block contains a time-slot counter and a clock activity monitor. The time-slot counter is incremented each time the shift register is updated. The clock activity monitor is a counter that increments at the system clock (SYSCLK) rate and is cleared by a rising edge of the transmit clock (TCLK[n]). A framing bit (T1/J1) or a framing byte (E1) is detected when the counter reaches a programmable threshold, at which point, the bit and time-slot counters are initialised to indicate that the next bit sampled is the most significant bit of the first time-slot. For unchannelised links, the time-slot counter and the clock activity monitor are held reset.

8.9.3 Priority Encoder

The priority encoder monitors the line interfaces for requests and synchronises them to the SYSCLK timing domain. Requests are serviced on a fixed priority scheme where highest to lowest priority is assigned from line interface TD[0] to line interface TD[31]. Thus, simultaneous requests from line interface TD[m] will be serviced ahead of line interface TD[n], if m < n. The priority encoder selects the request from the link with the highest priority for service. When there are no pending requests, the priority encoder generates an idle cycle. In addition, once every fourth SYSCLK cycle, the priority encoder inserts a null cycle where no requests are serviced. This cycle is used by the channel assigner downstream for CBI accesses to the channel provision RAM.

8.9.4 Channel Assigner

The channel assigner block determines the channel number of the request currently being processed. The block contains a 1024 word channel provision RAM. The address of the RAM is constructed from concatenating the link number and the time-slot number of the highest priority requester. The fields of each RAM word include the channel number and a time-slot enable flag. The time-slot enable flag labels the current time-slot as belonging to the channel indicted by the channel number field. For time-slots that are enabled, the

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channel assigner issues a request to the THDL256 block which responds with packet data within one byte period of the transmit stream.

8.10 Performance Monitor

The Performance Monitor block (PMON) contains four counters. The first two accumulate receive partial packet buffer FIFO overrun events and transmit partial packet buffer FIFO underflow events, respectively. The remaining two counters are software programmable to accumulate a variety of events, such as receive packet count, FCS error counts, etc. All counters saturate upon reaching maximum value. The accumulation logic consists of a counter and holding register pair. The counter is incremented when the associated event is detected. Writing to the FREEDM-32P256 Master Clock / BERT Activity Monitor and Accumulation Trigger register transfer the count to the corresponding holding register and clear the counter. The contents of the holding register is accessible via the PCI interface.

8.11 JTAG Test Access Port Interface

The JTAG Test Access Port block provides JTAG support for boundary scan.

The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The FREEDM-32P256 identification code is 073820CD hexadecimal.

8.12 PCI Host Interface

The FREEDM-32P256 supports two different normal mode register types as defined below:

1. PCI Host Accessible registers (PA) - these registers can be accessed through the PCI Host interface.

2. PCI Configuration registers (PC) - these register can only be accessed through the PCI Host interface during a PCI configuration cycle.

The PCI registers are addressable on dword boundaries only. The PCI offset shown in the table below must be combined with a base address to form the PCI Interface address. The base address can be found in the FREEDM-32P256 Memory Base Address register in the PCI Configuration memory space.

Table 12 – Normal Mode PCI Host Accessible Register Memory Map

PCI Offset Register

0x000 FREEDM-32P256 Master Reset

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PCI Offset Register

0x004 FREEDM-32P256 Master Interrupt Enable

0x008 FREEDM-32P256 Master Interrupt Status

0x00C FREEDM-32P256 Master Clock / Frame Pulse / BERT Activity

Monitor and Accumulation Trigger

0x010 FREEDM-32P256 Master Link Activity Monitor

0x014 FREEDM-32P256 Master Line Loopback #1

0x018 FREEDM-32P256 Master Line Loopback #2

0x01C FREEDM-32P256 Reserved

0x020 FREEDM-32P256 Master BERT Control

0x024 FREEDM-32P256 Master Performance Monitor Control

0x028 - 0x07C Reserved

0x080 GPIC Control

0x084 - 0x0FC GPIC Reserved

0x100 RCAS Indirect Channel and Time-slot Select

0x104 RCAS Indirect Channel Data

0x108 RCAS Framing Bit Threshold

0x10C RCAS Channel Disable

0x110 - 0x17C RCAS Reserved

0x180 – 0x1FC RCAS Link #0 through #31 Configuration

0x200 RHDL Indirect Channel Select

0x204 RHDL Indirect Channel Data Register #1

0x208 RHDL Indirect Channel Data Register #2

0x20C RHDL Reserved

0x210 RHDL Indirect Block Select

0x214 RHDL Indirect Block Data Register

0x218 - 0x21C RHDL Reserved

0x220 RHDL Configuration

0x224 RHDL Maximum Packet Length

0x228 - 0x23C RHDL Reserved

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PCI Offset Register

0x240 - 0x27C Reserved

0x280 RMAC Control

0x284 RMAC Indirect Channel Provisioning

0x288 RMAC Packet Descriptor Table Base LSW

0x28C RMAC Packet Descriptor Table Base MSW

0x290 RMAC Queue Base LSW

0x294 RMAC Queue Base MSW

0x298 RMAC Packet Descriptor Reference Large Buffer Free Queue

Start

0x29C RMAC Packet Descriptor Reference Large Buffer Free Queue

Write

0x2A0 RMAC Packet Descriptor Reference Large Buffer Free Queue

Read

0x2A4 RMAC Packet Descriptor Reference Large Buffer Free Queue

End

0x2A8 RMAC Packet Descriptor Reference Small Buffer Free Queue

Start

0x2AC RMAC Packet Descriptor Reference Small Buffer Free Queue

Write

0x2B0 RMAC Packet Descriptor Reference Small Buffer Free Queue

Read

0x2B4 RMAC Packet Descriptor Reference Small Buffer Free Queue

End

0x2B8 RMAC Packet Descriptor Reference Ready Queue Start

0x2BC RMAC Packet Descriptor Reference Ready Queue Write

0x2C0 RMAC Packet Descriptor Reference Ready Queue Read

0x2C4 RMAC Packet Descriptor Reference Ready Queue End

0x2C8 - 0x2FC RMAC Reserved

0x300 TMAC Control

0x304 TMAC Indirect Channel Provisioning

0x308 TMAC Descriptor Table Base LSW

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PCI Offset Register

0x30C TMAC Descriptor Table Base MSW

0x310 TMAC Queue Base LSW

0x314 TMAC Queue Base MSW

0x318 TMAC Descriptor Reference Free Queue Start

0x31C TMAC Descriptor Reference Free Queue Write

0x320 TMAC Descriptor Reference Free Queue Read

0x324 TMAC Descriptor Reference Free Queue End

0x328 TMAC Descriptor Reference Ready Queue Start

0x32C TMAC Descriptor Reference Ready Queue Write

0x330 TMAC Descriptor Reference Ready Queue Read

0x334 TMAC Descriptor Reference Ready Queue End

0x338 - 0x37C TMAC Reserved

0x380 THDL Indirect Channel Select

0x384 THDL Indirect Channel Data #1

0x388 THDL Indirect Channel Data #2

0x38C THDL Indirect Channel Data #3

0x390 - 0x39C THDL Reserved

0x3A0 THDL Indirect Block Select

0x3A4 THDL Indirect Block Data

0x3A8 - 0x3AC THDL Reserved

0x3B0 THDL Configuration

0x3B4 - 0x3BC THDL Reserved

0x3C0 - 0x3FC Reserved

0x400 TCAS Indirect Channel and Time-slot Select

0x404 TCAS Indirect Channel Data

0x408 TCAS Framing Bit Threshold

0x40C TCAS Idle Time-slot Fill Data

0x410 TCAS Channel Disable

0x414 - 0x47C TCAS Reserved

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PCI Offset Register

0x480 - 0x4FC TCAS Link #0 through #31 Configuration

0x500 PMON Status

0x504 PMON Receive FIFO Overflow Count

0x508 PMON Transmit FIFO Underflow Count

0x50C PMON Configurable Count #1

0x510 PMON Configurable Count #2

0x514 - 0x51C PMON Reserved

0x520 - 0x7FC Reserved

The following PCI configuration registers are implemented by the PCI Interface. These registers can only be accessed when the PCI Interface is a target and a configuration cycle is in progress as indicated using the IDSEL input.

Table 13 – PCI Configuration Register Memory Map

PCI Offset Register

0x00 Vendor Identification/Device Identification

0x04 Command/Status

0x08 Revision Identifier/Class Code

0x0C Cache Line Size/Latency Timer/Header Type/BIST

0x10 CBI Memory Base Address Register

0x14 - 0x24 Unused Base Address Register

0x28 - 0x38 Reserved

0x3C Interrupt Line/Interrupt Pin/MIN_GNT/MAX_LAT

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9 NORMAL MODE REGISTER DESCRIPTION

Normal mode registers are used to configure and monitor the operation of the FREEDM-32P256.

Notes on Normal Mode Register Bits:

1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read.

2. Except where noted, all configuration bits that can be written into can also be read back. This allows the processor controlling the FREEDM-32P256 to determine the programming state of the block.

3. Writable normal mode register bits are cleared to logic zero upon reset unless otherwise noted.

4. Writing into read-only normal mode register bit locations does not affect FREEDM-32P256 operation unless otherwise noted.

5. Certain register bits are reserved. These bits are associated with megacell functions that are unused in this application. To ensure that the FREEDM32P256 operates as intended, reserved register bits must only be written with their default values. Similarly, writing to reserved registers should be avoided.

9.1 PCI Host Accessible Registers

PCI host accessible registers can be accessed by the PCI host. For each register description below, the hexadecimal register number indicates the PCI offset from the base address in the FREEDM-32P256 CBI Register Base Address Register when accesses are made using the PCI Host Port.

Note

These registers are not byte addressable. Writing to any one of these registers modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to the register.

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Bit Type Function Default

Bit 31

Unused XXXXH

Bit 16

Bit 15 R/W Reset 0

Bit 14

Unused XXXXH

Bit 0

This register provides software reset capability.

Note

This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.

RESET:

The RESET bit allows the FREEDM-32P256 to be reset under software control. If the RESET bit is a logic one, the entire FREEDM-32P256 except the PCI Interface is held in reset. This bit is not self-clearing. Therefore, a logic zero must be written to bring the FREEDM-32P256 out of reset. Holding the FREEDM-32P256 in a reset state places it into a low power, stand-by mode. A hardware reset clears the RESET bit, thus negating the software reset.

Note

Unlike the hardware reset input (RSTB), RESET does not force the FREEDM32P256's PCI pins tristate. Transmit link data pins (TD[31:0]) are forced high. In addition, all registers except the GPIC PCI Configuration registers, are reset to their default values.

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Bit Type Function Default

Bit 31

Unused XXXXH

Bit 16

Bit 15 R/W TFUDRE 0

Bit 14 R/W IOCE 0

Bit 13 R/W TDFQEE 0

Bit 12 R/W TDQRDYE 0

Bit 11 R/W TDQFE 0

Bit 10 R/W RPDRQEE 0

Bit 9 R/W RPDFQEE 0

Bit 8 R/W RPQRDYE 0

Bit 7 R/W RPQLFE 0

Bit 6 R/W RPQSFE 0

Bit 5 R/W RFOVRE 0

Bit 4 R/W RPFEE 0

Bit 3 R/W RABRTE 0

Bit 2 R/W RFCSEE 0

Bit 1 R/W PERRE 0

Bit 0 R/W SERRE 0

This register provides interrupt enables for various events detected or initiated by the FREEDM-32P256.

Note

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Datasheet PM7382-PI Datasheet (PMC)

Specifications and Main Features

Frequently Asked Questions

User Manual

CONTENTS

LIST OF FIGURES

LIST OF TABLES

9 NORMAL MODE REGISTER DESCRIPTION