PMC PM7381 Datasheet

PMC-Sierra,Inc.

Frame Engine and Data Link Manager

PM7381

FREEDM-32A672

FEATURES

The FREEDM-32A672 chip offers
the following features:

• Single-chip multi-channel HDLC
controller with a 50 MHz, 16-bit
Any-PHY Packet Interface (APPI)
for transfer of packet data using an
external controller. Each APPI bus
can support up to seven
FREEDM-32A672 devices to
enable high-density and
low-latency applications.

• Supports up to 672 bi-directional
HDLC channels assigned to a
maximum of 32 H-MVIP digital
telephony buses at 2.048 Mbit/s
per link, or 8 H-MVIP buses at

8.192 Mbit/s per link.

• Supports up to 672 bi-directional
HDLC channels assigned to a
maximum of 32 channelized T1/

J1/E1 links. You can program the
number of time-slots assigned to
an HDLC channel from 1 to 24 (for
T1/J1) and from 1 to 31 (for E1).

• Supports up to 32 bi-directional
HDLC channels, each assigned to
an unchannelized arbitrary- r ate
link, subject to a maximum
aggregate link clock-rate of 64
MHz in each direction.

• Channels assigned to links 0 to 2
support clock rates up to 52 MHz.
Channels assigned to links 3 to 31
support clock rates up to 10 MHz.
In the special case, where no
more than 3 high-speed links are
used, the maximum aggregate link
clock-rate is 156 MHz.

• Links configured for channelized
T1/J1/E1 or unchannelized
operation support the

gapped-clock method for
determining time-slots, which is
backwards compatible with the
FREEDM-8 and FREEDM-32
devices.

• For each channel, the HDLC
receiver supports programmable
flag-sequence detection, bit
de-stuffing and frame-check
sequence validation. The receiver
supports the validation of both
CRC-CCITT and CRC-32
frame-check sequences.

• For each channel, the HDLC
transmitter supports
programmable flag-sequence
generation, bit stuffing and
frame-check sequence
generation. The transmitter
supports the generation of both
CRC-CCITT and CRC-32
frame-check sequences. The

BLOCK DIAGRAM

RD[31:0]

RCLK[31:0]

RFPB[3:0]

RMVCK[3:0]

RMV8DC

RMV8FPC

RFP8B

TD[31:0]

TCLK[31:0]

TFPB[3:0]

TMVCK[3:0]

TMV8DC

TMV8FPC

TFP8B

RBD

RBCLK

Receive
Channel

Assigner

(RCAS672)

Transmit
Channel
Assigner

(TCAS672)

Receive

HDLC

Processor

(RHDL672)

Transmit

HDLC

Processor

(THDL672)

Microprocessor

Interface

RSTB

SYSCLK

32 k Receive

Partial
Packet
Buffer

Performance

Monitor

(PMON)

32 k Transmit

Partial
Packet
Buffer

JTAG

PMCTEST

Receive

Any-PHY

Packet

Interface

(RAPI672)

Transmit
Any-PHY

Packet

Interface

(TAPI672)

RXCLK
RXADDR[2:0]
RPA
RENB
RXDATA[15:0]
RXPRTY
RSX
REOP
RMOD
RERR
RVAL

TXCLK
TXADDR[12:0]
TPA1[2:0]
TPA2[2:0]
TRDY
TXDATA[15:0]
TXPRTY
TSX
TEOP
TMOD
TERR

D[15:0]

A[11:2]

ALE

CSB

RDB

INTB

WRB

TRSTB

TBD

TBCLK

PMC-1980428 (r2) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE © 2001 PMC-Sierra, Inc.

TMS

TD0

TD1

TCK

Frame Engine and Data Link Manager

PM7381 FREEDM-32A672

transmitter also aborts packets
under the direction of the host or
automatically when the channel
underflows.

• Provides 32 kbytes of on-chip
memory for partial packet bufferi ng
in both the transmit and receive
directions. You can configure this
memory to support a variety of
different channel configurations:
from a single channel with 32

kbytes of buffering to 672
channels, each with a minimum of
48 bytes of buffering.

• Provides a standard five signal
P1149.1 JTAG test-port for
boundary scan board-test
purposes.

• Supports 5 Volt tolerant I/Os for
non-APPI signals. Supports a 3.3
Volt APPI signaling environment.

• 329-pin plastic ball grid-array
(PBGA) packag e.

TYPICAL APPLICATIONS

EIGHT LINK T1/E1 PORT ADAPTER FOR PPP PROCESSING

SBI

8

8

32xT1/E1/J1

8

PM4318
OCTLIU

PM4318
OCTLIU

PM4318
OCTLIU

PM4332

TE-32

APPLICATIONS

Use the FREEDM-32A672 chip in
the following applications:

• Remote Access Concentrat or s.

• Frame Relay/Multiservice

Switches.

• Multiservice Access
Concentrators.

• Internet/Edge Routers.

• Packet Based DSLAM Equipment.

Any-PHY

(Packet)

Packet

PM7380

FREEDM-

32A672

Mamory

Processor

8

PM4318
OCTLIU

N*DS3 FRAME RELAY TO ATM INTERWORKING

PM7381

FREEDM-

32A672

PM7381

FREEDM-

32A672

Head Office:
PMC-Sierra, Inc.
8555 Baxter Place
Burnaby, B.C. V5A 4V7
Canada
Tel: [phone]
Fax: [phone]

DS3

DS3

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

PM8316

TEMUX-84

PM8316

TEMUX-84

To order documentation,
send email to:
[e-mail]
or contact the head office,
Attn: Document Coordinator

Any-PHY

(Packet)

APPI

Interface

All product documentation is available
on our web site at:
http://www.pmc-sierra.com
For corpo rate information,
send email to:
[e-mail]

Frame Relay

to ATM

Interworking

Packet

Memory

AAL-5 SAR

UTOPIA/
Any-PHY

(Cell)

PMC-1980428 (r2)

© 2001PMC-Sierra, Inc. Aug.2001.
FREEDM-32A672, Any-PHY,
FREEDM-8, FREEDM-32, OCTLIU,
TE-32, TEMUX, SBI and PMC-Sierra
are trademarks of PMC-Sierra, Inc.