PMC PM7380-PI Datasheet

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PMC-1990262 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 32P672

PM7380 FREEDM-32P672

PM7380

FREEDM™-32P672

FRAME ENGINE AND DATALINK

MANAGER 32P672

DATA SHEET

PROPRIETARY AND CONFIDENTIAL

ISSUE 5: AUGUST 2001

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PM7380 FREEDM-32P672

PUBLIC REVISION HISTORY

Issue No. Issue

Details of Change

Date

Issue 1 February,

Created Document.

18, 1999

Issue 2 May 30,

Added pinout.

1999

Issue 3 Jan, 2000 Minor Corrections.

Issue 4 July 2000 Minor Corrections to some DC and AC timing

parameters

Issue 5 August

Added patent information to legal footer.

2001

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PM7380 FREEDM-32P672

CONTENTS

1 FEATURES...............................................................................................1

2 APPLICATIONS........................................................................................4

3 REFERENCES .........................................................................................5

4 APPLICATION EXAMPLES......................................................................6

5 BLOCK DIAGRAM....................................................................................8

6 DESCRIPTION .........................................................................................9

7 PIN DIAGRAM ........................................................................................12

8 PIN DESCRIPTION ................................................................................13

9 FUNCTIONAL DESCRIPTION ...............................................................38

9.1 HIGH SPEED MULTI-VENDOR INTEGRATION PROTOCOL

(H-MVIP) ......................................................................................38

9.2 HIGH-LEVEL DATA LINK CONTROL (HDLC) PROTOCOL.........38

9.3 RECEIVE CHANNEL ASSIGNER ................................................39

9.3.1 LINE INTERFACE TRANSLATOR (LIT) ........................41

9.3.2 LINE INTERFACE..........................................................42

9.3.3 PRIORITY ENCODER...................................................42

9.3.4 CHANNEL ASSIGNER ..................................................42

9.3.5 LOOPBACK CONTROLLER .........................................43

9.4 RECEIVE HDLC PROCESSOR / PARTIAL PACKET BUFFER...43

9.4.1 HDLC PROCESSOR .....................................................44

9.4.2 PARTIAL PACKET BUFFER PROCESSOR..................44

9.5 RECEIVE DMA CONTROLLER ...................................................46

9.5.1 DATA STRUCTURES ....................................................46

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9.5.2 DMA TRANSACTION CONTROLLER...........................56

9.5.3 WRITE DATA PIPELINE/MUX.......................................56

9.5.4 DESCRIPTOR INFORMATION CACHE........................56

9.5.5 FREE QUEUE CACHE..................................................57

9.6 PCI CONTROLLER......................................................................57

9.6.1 MASTER MACHINE ......................................................58

9.6.2 MASTER LOCAL BUS INTERFACE..............................60

9.6.3 TARGET MACHINE.......................................................61

9.6.4 CBI BUS INTERFACE ...................................................63

9.6.5 ERROR / BUS CONTROL .............................................63

9.7 TRANSMIT DMA CONTROLLER.................................................63

9.7.1 DATA STRUCTURES ....................................................64

9.7.2 TASK PRIORITIES ........................................................76

9.7.3 DMA TRANSACTION CONTROLLER...........................76

9.7.4 READ DATA PIPELINE..................................................76

9.7.5 DESCRIPTOR INFORMATION CACHE........................76

9.7.6 FREE QUEUE CACHE..................................................77

9.8 TRANSMIT HDLC CONTROLLER / PARTIAL PACKET BUFFER77

9.8.1 TRANSMIT HDLC PROCESSOR..................................77

9.8.2 TRANSMIT PARTIAL PACKET BUFFER PROCESSOR78

9.9 TRANSMIT CHANNEL ASSIGNER .............................................80

9.9.1 LINE INTERFACE TRANSLATOR (LIT) ........................82

9.9.2 LINE INTERFACE..........................................................82

9.9.3 PRIORITY ENCODER...................................................83

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9.9.4 CHANNEL ASSIGNER ..................................................83

9.10 PERFORMANCE MONITOR .......................................................84

9.11 JTAG TEST ACCESS PORT INTERFACE...................................84

9.12 PCI HOST INTERFACE...............................................................84

10 NORMAL MODE REGISTER DESCRIPTION........................................89

10.1 PCI HOST ACCESSIBLE REGISTERS .......................................89

11 PCI CONFIGURATION REGISTER DESCRIPTION ............................252

11.1 PCI CONFIGURATION REGISTERS.........................................252

12 TEST FEATURES DESCRIPTION .......................................................263

12.1 TEST MODE REGISTERS ........................................................263

12.2 JTAG TEST PORT.....................................................................264

12.2.1 IDENTIFICATION REGISTER .....................................265

12.2.2 BOUNDARY SCAN REGISTER ..................................265

13 OPERATIONS ......................................................................................282

13.1 TOCTL CONNECTIONS............................................................282

13.2 JTAG SUPPORT........................................................................282

14 FUNCTIONAL TIMING .........................................................................289

14.1 RECEIVE H-MVIP LINK TIMING ...............................................289

14.2 TRANSMIT H-MVIP LINK TIMING.............................................290

14.3 RECEIVE NON H-MVIP LINK TIMING ......................................291

14.4 TRANSMIT NON H-MVIP LINK TIMING....................................293

14.5 PCI INTERFACE........................................................................294

14.6 BERT INTERFACE ....................................................................303

15 ABSOLUTE MAXIMUM RATINGS........................................................305

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16 D.C. CHARACTERISTICS....................................................................306

17 FREEDM-32P672 TIMING CHARACTERISTICS.................................308

18 ORDERING AND THERMAL INFORMATION ......................................318

19 MECHANICAL INFORMATION.............................................................319

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PM7380 FREEDM-32P672

LIST OF FIGURES

FIGURE 1 – H-MVIP PROTOCOL ....................................................................38

FIGURE 2 – HDLC FRAME...............................................................................39

FIGURE 3 – CRC GENERATOR.......................................................................39

FIGURE 4 – PARTIAL PACKET BUFFER STRUCTURE..................................45

FIGURE 5 – RECEIVE PACKET DESCRIPTOR...............................................47

FIGURE 6 – RECEIVE PACKET DESCRIPTOR TABLE...................................50

FIGURE 7 – RPDRF AND RPDRR QUEUES ...................................................52

FIGURE 8 – RPDRR QUEUE OPERATION......................................................54

FIGURE 9 – RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE.........55

FIGURE 10 – GPIC ADDRESS MAP ................................................................62

FIGURE 11 – TRANSMIT DESCRIPTOR..........................................................64

FIGURE 12 – TRANSMIT DESCRIPTOR TABLE .............................................68

FIGURE 13 – TDRR AND TDRF QUEUES .......................................................70

FIGURE 14 – TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE ....72

FIGURE 15 – TD LINKING................................................................................75

FIGURE 16 – PARTIAL PACKET BUFFER STRUCTURE................................79

FIGURE 17 – INPUT OBSERVATION CELL (IN_CELL) .................................279

FIGURE 18 – OUTPUT CELL (OUT_CELL) ...................................................280

FIGURE 19 – BI-DIRECTIONAL CELL (IO_CELL) .........................................280

FIGURE 20 – LAYOUT OF OUTPUT ENABLE AND BI-DIRECTIONAL CELLS

..............................................................................................................281

FIGURE 21 – BOUNDARY SCAN ARCHITECTURE ......................................283

FIGURE 22 – TAP CONTROLLER FINITE STATE MACHINE........................285

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FIGURE 23 – RECEIVE 8.192 MBPS H-MVIP LINK TIMING .........................289

FIGURE 24 – RECEIVE 2.048 MBPS H-MVIP LINK TIMING .........................290

FIGURE 25 – TRANSMIT 8.192 MBPS H-MVIP LINK TIMING.......................290

FIGURE 26 – TRANSMIT 2.048 MBPS H-MVIP LINK TIMING.......................291

FIGURE 27 – UNCHANNELISED RECEIVE LINK TIMING ............................292

FIGURE 28 – CHANNELISED T1/J1 RECEIVE LINK TIMING .......................292

FIGURE 29 – CHANNELISED E1 RECEIVE LINK TIMING............................293

FIGURE 30 – UNCHANNELISED TRANSMIT LINK TIMING..........................293

FIGURE 31 – CHANNELISED T1/J1 TRANSMIT LINK TIMING.....................294

FIGURE 32 – CHANNELISED E1 TRANSMIT LINK TIMING .........................294

FIGURE 33 – PCI READ CYCLE ....................................................................296

FIGURE 34 – PCI WRITE CYCLE ..................................................................297

FIGURE 35 – PCI TARGET DISCONNECT ....................................................298

FIGURE 36 – PCI TARGET ABORT................................................................299

FIGURE 37 – PCI BUS REQUEST CYCLE ....................................................299

FIGURE 38 – PCI INITIATOR ABORT TERMINATION ...................................300

FIGURE 39 – PCI EXCLUSIVE LOCK CYCLE ...............................................301

FIGURE 40 – PCI FAST BACK TO BACK.......................................................303

FIGURE 41 – RECEIVE BERT PORT TIMING ...............................................303

FIGURE 42 – TRANSMIT BERT PORT TIMING.............................................304

FIGURE 43 – RECEIVE DATA & FRAME PULSE TIMING (2.048 MBPS H-MVIP

MODE) ..................................................................................................310

FIGURE 44 – RECEIVE DATA & FRAME PULSE TIMING (8.192 MBPS H-MVIP

MODE) ..................................................................................................310

FIGURE 45 – RECEIVE DATA TIMING (NON H-MVIP MODE) ...................... 311

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FIGURE 46 – BERT INPUT TIMING ............................................................... 311

FIGURE 47 – TRANSMIT DATA & FRAME PULSE TIMING (2.048 MBPS

H-MVIP MODE).....................................................................................313

FIGURE 48 – TRANSMIT DATA & FRAME PULSE TIMING (8.192 MBPS

H-MVIP MODE).....................................................................................314

FIGURE 49 – TRANSMIT DATA TIMING (NON H-MVIP MODE)....................314

FIGURE 50 – BERT OUTPUT TIMING ...........................................................315

FIGURE 51 – PCI INTERFACE TIMING .........................................................316

FIGURE 52 – JTAG PORT INTERFACE TIMING............................................317

FIGURE 53 – 329 PIN PLASTIC BALL GRID ARRAY (PBGA) .......................319

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LIST OF TABLES

TABLE 1 – LINE SIDE INTERFACE SIGNALS (154)........................................13

TABLE 2 – PCI HOST INTERFACE SIGNALS (52) ..........................................23

TABLE 3 – MISCELLANEOUS INTERFACE SIGNALS (58).............................32

TABLE 4 – PRODUCTION TEST INTERFACE SIGNALS (0 - MULTIPLEXED)33

TABLE 5 – POWER AND GROUND SIGNALS (65) .........................................35

TABLE 6 – RECEIVE PACKET DESCRIPTOR FIELDS....................................47

TABLE 7 – RPDRR QUEUE ELEMENT............................................................53

TABLE 8 – RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE FIELDS

................................................................................................................55

TABLE 9 – TRANSMIT DESCRIPTOR FIELDS................................................65

TABLE 10 – TRANSMIT DESCRIPTOR REFERENCE.....................................71

TABLE 11 – TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE

FIELDS ...................................................................................................73

TABLE 12 – NORMAL MODE PCI HOST ACCESSIBLE REGISTER MEMORY

MAP ........................................................................................................84

TABLE 13 – PCI CONFIGURATION REGISTER MEMORY MAP.....................88

TABLE 14 – BIG ENDIAN FORMAT................................................................ 119

TABLE 15 – LITTLE ENDIAN FORMAT .......................................................... 119

TABLE 16 - RECEIVE LINKS #0 TO #2 CONFIGURATION ...........................130

TABLE 17 - RECEIVE LINKS #3 TO #31 CONFIGURATION .........................132

TABLE 18 – CRC[1:0] SETTINGS...................................................................139

TABLE 19 – RPQ_RDYN[2:0] SETTINGS ......................................................150

TABLE 20 – RPQ_LFN[1:0] SETTINGS..........................................................151

TABLE 21 – RPQ_SFN[1:0] SETTINGS .........................................................151

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TABLE 22 – TDQ_RDYN[2:0] SETTINGS.......................................................185

TABLE 23 – TDQ_FRN[1:0] SETTINGS .........................................................185

TABLE 24 – CRC[1:0] SETTINGS...................................................................213

TABLE 25 – FLAG[2:0] SETTINGS.................................................................219

TABLE 26 – LEVEL[3:0]/TRANS SETTINGS ..................................................221

TABLE 27 - TRANSMIT LINKS #0 TO #2 CONFIGURATION.........................239

TABLE 28 - TRANSMIT LINKS #3 TO #31 CONFIGURATION.......................241

TABLE 29 – TEST MODE REGISTER MEMORY MAP ..................................264

TABLE 30 – INSTRUCTION REGISTER ........................................................265

TABLE 31 – BOUNDARY SCAN CHAIN .........................................................265

TABLE 32 – FREEDM–TOCTL CONNECTIONS ............................................282

TABLE 33 – FREEDM-32P672 ABSOLUTE MAXIMUM RATINGS.................305

TABLE 34 – FREEDM-32P672 D.C. CHARACTERISTICS.............................306

TABLE 35 – FREEDM-32P672 LINK INPUT (FIGURE 43 TO FIGURE 46)....308

TABLE 36 – FREEDM-32P672 LINK OUTPUT (FIGURE 47 TO FIGURE 50) 311

TABLE 37 – PCI INTERFACE (FIGURE 51) ...................................................315

TABLE 38 – JTAG PORT INTERFACE (FIGURE 52)......................................316

TABLE 39 – FREEDM-32P672 ORDERING INFORMATION..........................318

TABLE 40 – FREEDM-32P672 THERMAL INFORMATION ............................318

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1 FEATURES

· Single-chip multi-channel HDLC controller with a 66 MHz, 32 bit Peripheral
Component Interconnect (PCI) Revision 2.1 bus for configuration, monitoring
and transfer of packet data, with an on-chip DMA controller with scatter/
gather capabilities.

· Supports up to 672 bi-directional HDLC channels assigned to a maximum of
32 H-MVIP digital telephony buses at 2.048 Mbps per link. The links are
grouped into 4 logical groups of 8 links. A common clock and a type 0 frame
pulse is shared among links in each logical group. The number of time-slots
assigned to an HDLC channel is programmable from 1 to 32.

· Supports up to 672 bi-directional HDLC channels assigned to a maximum of
8 H-MVIP digital telephony buses at 8.192 Mbps per link. The links share a
common clock and a type 0 frame pulse. The number of time-slots assigned
to an HDLC channel is programmable from 1 to 128.

· Supports up to 672 bi-directional HDLC channels assigned to a maximum of
32 channelised T1/J1 or E1 links. The number of time-slots assigned to an
HDLC channel is programmable from 1 to 24 (for T1/J1) and from 1 to 31 (for
E1).

· Supports up to 32 bi-directional HDLC channels each assigned to an
unchannelised arbitrary rate link, subject to a maximum aggregate link clock
rate of 64 MHz in each direction. Channels assigned to links 0 to 2 support a
clock rate of up to 51.84 MHz. Channels assigned to links 3 to 31 support a
clock rate of up to 10 MHz.

· Supports three bi-directional HDLC channels each assigned to an
unchannelised arbitrary rate link of up to 51.84 MHz when SYSCLK is running
at 45 MHz.

· Supports a mix of up to 32 channelised, unchannelised and H-MVIP links,
subject to the constraint of a maximum of 672 channels and a maximum
aggregate link clock rate of 64 MHz in each direction.

· Links configured for channelised T1/J1/E1 or unchannelised operation
support the gapped-clock method for determining time-slots which is
backwards compatible with the FREEDM-8 and FREEDM-32 devices.

· For each channel, the HDLC receiver supports programmable flag sequence
detection, bit de-stuffing and frame check sequence validation. The receiver

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supports the validation of both CRC-CCITT and CRC-32 frame check
sequences.

· For each channel, the receiver checks for packet abort sequences, octet
aligned packet length and for minimum and maximum packet length. The
receiver supports filtering of packets that are larger than a user specified
maximum value.

· Alternatively, for each channel, the receiver supports a transparent mode
where each octet is transferred transparently to host memory. For
channelised links, the octets are aligned with the receive time-slots.

· For each channel, time-slots are selectable to be in 56 kbits/s format or 64
kbits/s clear channel format.

· For each channel, the HDLC transmitter supports programmable flag
sequence generation, bit stuffing and frame check sequence generation. The
transmitter supports the generation of both CRC-CCITT and CRC-32 frame
check sequences. The transmitter also aborts packets under the direction of
the host or automatically when the channel underflows.

· Supports two levels of non-preemptive packet priority on each transmit
channel. Low priority packets will not begin transmission until all high priority
packets are transmitted.

· Alternatively, for each channel, the transmitter supports a transparent mode
where each octet is inserted transparently from host memory. For
channelised links, the octets are aligned with the transmit time-slots.

· Provides 32 Kbytes of on-chip memory for partial packet buffering in both the
transmit and receive directions. This memory may be configured to support a
variety of different channel configurations from a single channel with 32
Kbytes of buffering to 672 channels, each with a minimum of 48 bytes of
buffering.

· Supports PCI burst sizes of up to 256 bytes for transfers of packet data.

· Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board

test purposes.

· Supports 3.3 Volt PCI signaling environments.

· Supports 5 Volt tolerant I/O (except PCI).

· Low power 2.5 Volt 0.25 mm CMOS technology.

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· 329 pin plastic ball grid array (PBGA) package.

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2 APPLICATIONS

· IETF PPP interfaces for routers

· TDM switches

· Frame Relay interfaces for ATM or Frame Relay switches and multiplexors

· FUNI or Frame Relay service inter-working interfaces for ATM switches and

multiplexors.

· Internet/Intranet access equipment.

· Packet-based DSLAM equipment.

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3 REFERENCES

1. International Organization for Standardization, ISO Standard 3309-1993,
"Information Technology - Telecommunications and information exchange
between systems - High-level data link control (HDLC) procedures - Frame
structure", December 1993.

2. RFC-1662 - "PPP in HDLC-like Framing" Internet Engineering Task Force,
July 1994.

3. PCI Special Interest Group, PCI Local Bus Specification, June 1, 1995,
Version 2.1.

4. GO-MVIP, “MVIP-90 Standard”, October 1994, release 1.1.

5. GO-MVIP, “H-MVIP Standard”, January 1997, release 1.1a.

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4 APPLICATION EXAMPLES

H-MVIP Bus

PM4354

COMET-QUAD

PM4354

T1/E1/J1

COMET-QUAD

TDM

Switch

PM4354

Fabric

COMET-QUAD

PM4354

COMET-QUAD

H-MVIP Bus

PCI Bus

Packet

Memory

PM7380

FREEDM-

32P672

PCI

Controller

Bus Arbite

DS3

LIU

PM8315

TEMUX

PCI Bus

Packet

Memory

PM7380

...

FREEDM-

32P672

PCI

Controlle

Bus Arbite

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5 BLOCK DIAGRAM

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6 DESCRIPTION

The PM7380 FREEDM-32P672 Frame Engine and Datalink Manager device is a
monolithic integrated circuit that implements HDLC processing, and PCI Bus
memory management functions for a maximum of 672 bi-directional channels.

The FREEDM-32P672 may be configured to support H-MVIP, channelised
T1/J1/E1 or unchannelised traffic across 32 physical links.

The FREEDM-32P672 may be configured to interface with H-MVIP digital
telephony buses at 2.048 Mbps. For 2.048 Mbps H-MVIP links, the FREEDM­32P672 allows up to 672 bi-directional HDLC channels to be assigned to
individual time-slots within a maximum of 32 H-MVIP links. The channel
assignment supports the concatenation of time-slots (N x DS0) up to a maximum
of 32 concatenated time-slots for each 2.048 Mbps H-MVIP link. Time-slots
assigned to any particular channel need not be contiguous within the H-MVIP
link. When configured for 2.048 Mbps H-MVIP operation, the FREEDM-32P672
partitions the 32 physical links into 4 logical groups of 8 links. Links 0 through 7,
8 through 15, 16 through 23 and 24 through 31 make up the 4 logical groups.
Links in each logical group share a common clock and a common type 0 frame
pulse in each direction.

The FREEDM-32P672 may be configured to interface with H-MVIP digital
telephony buses at 8.192 Mbps. For 8.192 Mbps H-MVIP links, the FREEDM­32P672 allows up to 672 bi-directional HDLC channels to be assigned to
individual time-slots within a maximum of 8 H-MVIP links. The channel
assignment supports the concatenation of time-slots (N x DS0) up to a maximum
of 128 concatenated time-slots for each 8.192 H-MVIP link. Time-slots assigned
to any particular channel need not be contiguous within the H-MVIP link. When
configured for 8.192 Mbps H-MVIP operation, the FREEDM-32P672 partitions
the 32 physical links into 8 logical groups of 4 links. Only the first link, which

must be located at physical links numbered 4m (0£m£7), of each logical group
can be configured for 8.192 Mbps operation. The remaining 3 physical links in
the logical group (numbered 4m+1, 4m+2 and 4m+3) are unused. All links
configured for 8.192 Mbps H-MVIP operation will share a common type 0 frame
pulse, a common frame pulse clock and a common data clock.

For channelised T1/J1/E1 links, the FREEDM-32P672 allows up to 672 bi­directional HDLC channels to be assigned to individual time-slots within a
maximum of 32 independently timed T1/J1 or E1 links. The gapped clock
method to determine time-slot positions as per the FREEDM-8 and FREEDM-32
devices is retained. The channel assignment supports the concatenation of
time-slots (N x DS0) up to a maximum of 24 concatenated time-slots for a T1/J1

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 9

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PMC-1990262 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 32P672

PM7380 FREEDM-32P672

link and 31 concatenated time-slots for an E1 link. Time-slots assigned to any
particular channel need not be contiguous within the T1/J1 or E1 link.

For unchannelised links, the FREEDM-32P672 processes up to 32 bi-directional
HDLC channels within 32 independently timed links. The links can be of
arbitrary frame format. When limited to three unchannelised links, each link can
be rated at up to 51.84 MHz provided SYSCLK is running at 45 MHz. For lower
rate unchannelised links, the FREEDM-32P672 processes up to 32 links each
rated at up to 10 MHz. In this case, the aggregate clock rate of all the links is
limited to 64 MHz.

The FREEDM-32P672 supports mixing of up to 32 channelised T1/J1/E1,
unchannelised and H-MVIP links. The total number of channels in each direction
is limited to 672. The aggregate instantaneous clock rate over all 32 possible
links is limited to 64 MHz.

In the receive direction, the FREEDM-32P672 performs channel assignment and
packet extraction and validation. For each provisioned HDLC channel, the
FREEDM-32P672 delineates the packet boundaries using flag sequence
detection, and performs bit de-stuffing. Sharing of opening and closing flags, as
well as sharing of zeros between flags are supported. The resulting packet data
is placed into the internal 32 Kbyte partial packet buffer RAM. The partial packet
buffer acts as a logical FIFO for each of the assigned channels. Partial packets
are DMA'd out of the RAM, across the PCI bus and into host packet memory.
The FREEDM-32P672 validates the frame check sequence for each packet, and
verifies that the packet is an integral number of octets in length and is within a
programmable minimum and maximum length. The receive packet status is
updated before linking the packet into a receive ready queue. The FREEDM­32P672 alerts the PCI Host that there are packets in a receive ready queue by,
optionally, asserting an interrupt on the PCI bus.

Alternatively, in the receive direction, the FREEDM-32P672 supports a
transparent operating mode. For each provisioned transparent channel, the
FREEDM-32P672 directly transfers the received octets into host memory
verbatim. If the transparent channel is assigned to a channelised link, then the
octets are aligned to the received time-slots.

In the transmit direction, the PCI Host provides packets to transmit using a
transmit ready queue. For each provisioned HDLC channel, the FREEDM­32P672 DMA's partial packets across the PCI bus and into the transmit partial
packet buffer. The partial packets are read out of the packet buffer by the
FREEDM-32P672 and a frame check sequence is optionally calculated and
inserted at the end of each packet. Bit stuffing is performed before being
assigned to a particular link. The flag sequence is automatically inserted when
there is no packet data for a particular channel. Sequential packets are

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 10

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PMC-1990262 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 32P672

PM7380 FREEDM-32P672

optionally separated by two flags (an opening flag and a closing flag) or a single
flag (combined opening and closing flag). Zeros between flags are not shared.
PCI bus latency may cause one or more channels to underflow, in which case,
the packets are aborted, and the host is notified. For normal traffic, an abort
sequence is generated, followed by inter-frame time fill characters (flags or all­ones bytes) until a new packet is sourced from the PCI host. No attempt is made
to automatically re-transmit an aborted packet.

Alternatively, in the transmit direction, the FREEDM-32P672 supports a
transparent operating mode. For each provisioned transparent channel, the
FREEDM-32P672 directly inserts the transmitted octets from host memory. If the
transparent channel is assigned to a channelised link, then the octets are aligned
to the transmitted time-slots. If a channel underflows due to excessive PCI bus
latency, an abort sequence is generated, followed by inter-frame time fill
characters (flags or all-ones bytes) to indicate idle channel. Data resumes
immediately when the FREEDM-32P672 receives new data from the host.

The FREEDM-32P672 is configured, controlled and monitored using the PCI bus
interface. The PCI bus supports 3.3 Volt signaling. The FREEDM-32P672 is

implemented in low power 2.5 Volt 0.25 mm CMOS technology. All non-PCI
FREEDM-32P672 I/O pins are 5 volt tolerant. The FREEDM-32P672 is
packaged in a 329 pin plastic ball grid array (PBGA) package.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 11

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DATA SHEET

PMC-1990262 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 32P672

PM7380 FREEDM-32P672

7 PIN DIAGRAM

The FREEDM-32P672 is manufactured in a 329 pin plastic ball grid array
package.

2322212019181716151413121110987654321

RMVCK[2] RD[16] RCLK[17] RCLK[19] RD[21] RD[22] RD[23] RD[24] RCLK[25] RCLK[27] RCLK[29] VDD2V5 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.

A

RFPB[2] RCLK[16] RD[18] RD[20] VDD2V5 RCLK[22] RFPB[3] RCLK[24] RCLK[26] RD[28] RD[30] RCLK[31] N.C. N.C. N.C. N.C. N.C. N.C. VDD2V5 N.C. N.C. N.C. N.C.

B

RD[15] RSTB RCLK[15] RCLK[18] RCLK[20] RCLK[21] RMVCK[3] RD[25] RD[27] RCLK[28] RCLK[30] RD[31] N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.

C

RCLK[13] RD[13] RCLK[14] RD[17] RD[19] VDD3V3 RCLK[23] VSS RD[26] VDD3V3 RD[29] VSS N.C. VDD3V3 N.C. VSS N.C. VDD3V3 N.C. N.C. N.C. N.C. N.C.

D

RD[12] VDD2V5 RCLK[12] RD[14] N.C. N.C. VDD2V5 N.C.

E

RD[11] RCLK[10] RCLK[11] VSS VSS N.C. N.C. N.C.

F

RD[10] RD[9] RCLK[8] RCLK[9]

G

RD[8] RMVCK[1] RFPB[1] VDD3V3 VDD3V3 AD[31] REQB GNTB

H

RCLK[7] RCLK[6] RD[6] RD[7] AD[29] AD[27] AD[28] AD[30]

J

SYSCLK RCLK[5] RD[5] VSS VSS VSS VSS VSS VSS VSS AD[24] AD[25] AD[26]

K

RD[4] RD[3] RCLK[3] RCLK[4] VSS VSS VSS VSS VSS CBEB[3] AD[22] AD[23] IDSEL

L

VDD2V5 RCLK[2] RD[2] VDD3V3 VSS VSS VSS VSS VSS VDD3V3 AD[21] AD[20] VDD2V5

M

RCLK[0] RD[1] RCLK[1] RD[0] VSS VSS VSS VSS VSS AD[16] AD[18] AD[19] AD[17]

N

RMV8FPC RFPB[0] RMVCK[0] VSS VSS VSS VSS VSS VSS VSS CBEB[2] FRAMEB IRDYB

P

RBD RMV8DC RFP8B RBCLK STOPB TRDYB DEVSELB LOCKB

R

TCK TMS TRSTB VDD3V3 VDD3V3 PERRB SERRB PAR

T

TFP8B TDO TDI TMV8DC AD[14] CBEB[1] AD[15] AD[13]

U

TFPB[0] TMV8FPC TMVCK[0] VSS VSS AD[10] AD[12] AD[11]

V

TD[0] VDD2V5 TCLK[0] TD[2] AD[6] AD[8] VDD2V5 AD[9]

W

TCLK[1] TD[1] TCLK[2] TD[4] TMVCK[1] VDD3V3 TD[12] VSS TCLK[15] VDD3V3 TCLK[17] VSS TD[22] VDD3V3 TD[24] VSS TCLK[27] VDD3V3 TBD N.C. AD[5] CBEB[0] AD[7]

Y

TCLK[3] TD[3] TCLK[6] TFPB[1] TD[9] TD[10] TD[13] TCLK[14] TMVCK[2] TD[17] TCLK[18] TD[20] TCLK[20] TCLK[22] TFPB[3] TD[25] TCLK[26] TCLK[29] TCLK[30] TBCLK AD[2] AD[4] AD[3]

AA

TD[5] TCLK[4] TCLK[7] TCLK[8] VDD2V5 TD[11] TCLK[12] TD[14] TFPB[2] TCLK[16] TD[19] TCLK[19] TD[21] TD[23] TMVCK[3] TCLK[25] TD[27] TCLK[28] VDD2V5 TD[31] PMCTEST N.C. AD[1]

AB

TCLK[5] TD[6] TD[7] TD[8] TCLK[9] TCLK[10] TCLK[11] TCLK[13] TD[15] TD[16] TD[18] VDD2V5 TCLK[21] TCLK[23] TCLK[24] TD[26] TD[28] TD[29] TD[30] TCLK[31] N.C. M66EN AD[0]

AC

2322212019181716151413121110987654321

BOTTOM VIEW

PCICLKO PCICLK N.C. PCIINTB

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 12

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DATA SHEET

PMC-1990262 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 32P672

PM7380 FREEDM-32P672

8 PIN DESCRIPTION

Table 1 – Line Side Interface Signals (154)

Pin Name Type Pin

Function

No.

RCLK[0]
RCLK[1]
RCLK[2]
RCLK[3]
RCLK[4]
RCLK[5]
RCLK[6]
RCLK[7]
RCLK[8]
RCLK[9]
RCLK[10]
RCLK[11]
RCLK[12]
RCLK[13]
RCLK[14]
RCLK[15]
RCLK[16]
RCLK[17]
RCLK[18]
RCLK[19]
RCLK[20]
RCLK[21]
RCLK[22]
RCLK[23]
RCLK[24]
RCLK[25]
RCLK[26]
RCLK[27]
RCLK[28]
RCLK[29]
RCLK[30]
RCLK[31]

Input N23

N21
M22
L21
L20
K22
J22
J23
G21
G20
F22
F21
E21
D23
D21
C21
B22
A21
C20
A20
C19
C18
B18
D17
B16
A15
B15
A14
C14
A13
C13
B12

The receive line clock signals (RCLK[31:0])
contain the recovered line clock for the 32
independently timed links. Processing of
the receive links are on a priority basis, in
descending order from RCLK[0] to
RCLK[31]. Therefore, the highest rate link
should be connected to RCLK[0] and the
lowest to RCLK[31].

For channelised T1/J1 or E1 links, RCLK[n]
must be gapped during the framing bit (for
T1/J1 interfaces) or during time-slot 0 (for
E1 interfaces) of the RD[n] stream. The
FREEDM-32P672 uses the gapping
information to determine the time-slot
alignment in the receive stream.
RCLK[31:0] is nominally a 50% duty cycle
clock of frequency 1.544 MHz for T1/J1 links
and 2.048 MHz for E1 links.

For unchannelised links, RCLK[n] must be
externally gapped during the bits or time­slots that are not part of the transmission
format payload (i.e. not part of the HDLC
packet). RCLK[2:0] is nominally a 50% duty
cycle clock between 0 and 51.84 MHz.
RCLK[31:3] is nominally a 50% duty cycle
clock between 0 and 10 MHz.

The RCLK[n] inputs are invalid and should
be forced to a low state when their
associated link is configured for operation in
H-MVIP mode.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 13

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PMC-1990262 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 32P672

Pin Name Type Pin

Function

PM7380 FREEDM-32P672

No.

RD[0]
RD[1]
RD[2]
RD[3]
RD[4]
RD[5]
RD[6]
RD[7]
RD[8]
RD[9]
RD[10]
RD[11]
RD[12]
RD[13]
RD[14]
RD[15]
RD[16]
RD[17]
RD[18]
RD[19]
RD[20]
RD[21]
RD[22]
RD[23]
RD[24]
RD[25]
RD[26]
RD[27]
RD[28]
RD[29]
RD[30]
RD[31]

Input N20

N22
M21
L22
L23
K21
J21
J20
H23
G22
G23
F23
E23
D22
E20
C23
A22
D20
B21
D19
B20
A19
A18
A17
A16
C16
D15
C15
B14
D13
B13
C12

The receive data signals (RD[31:0]) contain
the recovered line data for the 32
independently timed links in normal mode
(PMCTEST set low). Processing of the
receive links is on a priority basis, in
descending order from RD[0] to RD[31].
Therefore, the highest rate link should be
connected to RD[0] and the lowest to
RD[31].

For H-MVIP links, RD[n] contains 32/128
time-slots, depending on the H-MVIP data
rate configured (2.048 or 8.192 Mbps).
When configured for 2.048 Mbps H-MVIP
operation, RD[31:24], RD[23:16], RD[15:8]
and RD[7:0] are sampled on every 2nd rising
edge of RMVCK[3], RMVCK[2], RMVCK[1]
and RMVCK[0] respectively (at the ¾ point
of the bit interval). When configured for

8.192 Mbps H-MVIP operation, RD[4m]
(0£m£7) are sampled on every 2nd rising

edge of RMV8DC (at the ¾ point of the bit
interval).

For channelised links, RD[n] contains the 24
(T1/J1) or 31 (E1) time-slots that comprise
the channelised link. RCLK[n] must be
gapped during the T1/J1 framing bit position
or the E1 frame alignment signal (time-slot

0). The FREEDM-32P672 uses the location
of the gap to determine the channel
alignment on RD[n]. RD[31:0] are sampled
on the rising edge of the corresponding
RCLK[31:0].

For unchannelised links, RD[n] contains the
HDLC packet data. For certain transmission
formats, RD[n] may contain place holder bits
or time-slots. RCLK[n] must be externally
gapped during the place holder positions in
the RD[n] stream. The FREEDM-32P672
supports a maximum data rate of 10 Mbit/s

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 14

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DATA SHEET

PMC-1990262 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 32P672

Pin Name Type Pin

Function

PM7380 FREEDM-32P672

No.

on an individual RD[31:3] link and a

maximum data rate of 51.84 Mbit/s on
RD[2:0]. RD[31:0] are sampled on the
rising edge of the corresponding
RCLK[31:0].

RMVCK[0]
RMVCK[1]
RMVCK[2]
RMVCK[3]

Input P21

H22
A23
C17

The receive MVIP data clock signals
(RMVCK[3:0]) provide the receive data
clock for the 32 links when configured to
operate in 2.048 Mbps H-MVIP mode.

When configured for 2.048 Mbps H-MVIP
operation, the 32 links are partitioned into 4
groups of 8, and each group of 8 links share
a common data clock. RMVCK[0],
RMVCK[1], RMVCK[2] and RMVCK[3]
sample the data on links RD[7:0], RD[15:8],
RD[23:16] and RD[31:24] respectively.
Each RMVCK[n] is nominally a 50% duty
cycle clock with a frequency of 4.096 MHz.

RFPB[0]
RFPB[1]
RFPB[2]
RFPB[3]

Input P22

H21
B23
B17

RMVCK[n] is ignored and should be tied low
when no physical link within the associated
logical group of 8 links is configured for
operation in 2.048 Mbps H-MVIP mode.

The receive frame pulse signals
(RFPB[3:0]) reference the beginning of each
frame for the 32 links when configured for
operation in 2.048 Mbps H-MVIP mode.

When configured for 2.048 Mbps H-MVIP
operation, the 32 links are partitioned into 4
groups of 8, and each group of 8 links share
a common frame pulse. RFPB[0], RFPB[1],
RFPB[2] and RFPB[3] reference the
beginning of a frame on links RD[7:0],
RD[15:8], RD[23:16] and RD[31:24]
respectively.

When configured for operation in 2.048
Mbps H-MVIP mode, RFPB[n] is sampled
on the falling edge of RMVCK[n].
Otherwise, RFPB[n] is ignored and should
be tied low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 15

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PMC-1990262 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 32P672

Pin Name Type Pin

Function

PM7380 FREEDM-32P672

No.

RFP8B Input R21 The receive frame pulse for 8.192 Mbps H-

MVIP signal (RFP8B) references the
beginning of each frame for links configured
for operation in 8.192 Mbps H-MVIP mode.

RFP8B references the beginning of a frame
for any link configured for 8.192 Mbps H-

MVIP operation. Only links 4m (0£m£7)
may be configured for 8.192 Mbps H-MVIP
operation.

When one or more links are configured for

8.192 Mbps H-MVIP operation, RFP8B is
sampled on the falling edge of RMV8FPC.
When no links are configured for 8.192
Mbps H-MVIP operation, RFP8B is ignored
and should be tied low.

RMV8FPC Input P23 The receive 8.192 Mbps H-MVIP frame

pulse clock signal (RMV8FPC) provides the
receive frame pulse clock for links
configured for operation in 8.192 Mbps H­MVIP mode.

RMV8FPC is used to sample RFP8B.
RMV8FPC is nominally a 50% duty cycle,
clock with a frequency of 4.096 MHz. The
falling edge of RMV8FPC must be aligned
with the falling edge of RMV8DC with no
more than ±10 ns skew.

RMV8FPC is ignored and should be tied low
when no physical links are configured for
operation in 8.192 Mbps H-MVIP mode.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 16

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DATA SHEET

PMC-1990262 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 32P672

Pin Name Type Pin

Function

PM7380 FREEDM-32P672

No.

RMV8DC Input R22 The receive 8.192 Mbps H-MVIP data clock

signal (RMV8DC) provides the receive data
clock for links configured to operate in 8.192
Mbps H-MVIP mode.

RMV8DC is used to sample data on RD[4m]
(0£m£7) when link 4m is configured for

8.192 Mbps H-MVIP operation. RMV8DC is
nominally a 50% duty cycle clock with a
frequency of 16.384 MHz.

RMV8DC is ignored and should be tied low
when no physical links are configured for
operation in 8.192 Mbps H-MVIP mode.

RBD Tristate

Output

R23 The receive BERT data signal (RBD)

contains the receive bit error rate test data.
RBD reports the data on the selected one of
the receive data signals (RD[31:0]) and is
updated on the falling edge of RBCLK.
RBD may be tristated by setting the RBEN
bit in the FREEDM-32P672 Master BERT
Control register low. BERT is not supported
for H-MVIP links.

RBCLK Tristate

R20 The receive BERT clock signal (RBCLK)

Output

contains the receive bit error rate test clock.
RBCLK is a buffered version of the selected
one of the receive clock signals
(RCLK[31:0]). RBCLK may be tristated by
setting the RBEN bit in the FREEDM­32P672 Master BERT Control register low.
BERT is not supported for H-MVIP links.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 17

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DATA SHEET

PMC-1990262 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 32P672

Pin Name Type Pin

Function

PM7380 FREEDM-32P672

No.

TCLK[0]
TCLK[1]
TCLK[2]
TCLK[3]
TCLK[4]
TCLK[5]
TCLK[6]
TCLK[7]
TCLK[8]
TCLK[9]
TCLK[10]
TCLK[11]
TCLK[12]
TCLK[13]
TCLK[14]
TCLK[15]
TCLK[16]
TCLK[17]
TCLK[18]
TCLK[19]
TCLK[20]
TCLK[21]
TCLK[22]
TCLK[23]
TCLK[24]
TCLK[25]
TCLK[26]
TCLK[27]
TCLK[28]
TCLK[29]
TCLK[30]
TCLK[31]

Input W21

Y23
Y21
AA23
AB22
AC23
AA21
AB21
AB20
AC19
AC18
AC17
AB17
AC16
AA16
Y15
AB14
Y13
AA13
AB12
AA11
AC11
AA10
AC10
AC9
AB8
AA7
Y7
AB6
AA6
AA5
AC4

The transmit line clock signals (TCLK[31:0])
contain the transmit clocks for the 32
independently timed links. Processing of
the transmit links is on a priority basis, in
descending order from TCLK[0] to
TCLK[31]. Therefore, the highest rate link
should be connected to TCLK[0] and the
lowest to TCLK[31].

For channelised T1/J1 or E1 links, TCLK[n]
must be gapped during the framing bit (for
T1/J1 interfaces) or during time-slot 0 (for
E1 interfaces) of the TD[n] stream. The
FREEDM-32P672 uses the gapping
information to determine the time-slot
alignment in the transmit stream.

For unchannelised links, TCLK[n] must be
externally gapped during the bits or time­slots that are not part of the transmission
format payload (i.e. not part of the HDLC
packet).

TCLK[2:0] is nominally a 50% duty cycle
clock between 0 and 51.84 MHz.
TCLK[31:3] is nominally a 50% duty cycle
clock between 0 and 10 MHz. Typical
values for TCLK[31:0] include 1.544 MHz
(for T1/J1 links) and 2.048 MHz (for E1
links).

The TCLK[n] inputs are invalid and should
be tied low when their associated link is
configured for operation in H-MVIP mode.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 18

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DATA SHEET

PMC-1990262 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 32P672

Pin Name Type Pin

Function

PM7380 FREEDM-32P672

No.

TD[0]
TD[1]
TD[2]
TD[3]
TD[4]
TD[5]
TD[6]
TD[7]
TD[8]
TD[9]
TD[10]
TD[11]
TD[12]
TD[13]
TD[14]
TD[15]
TD[16]
TD[17]
TD[18]
TD[19]
TD[20]
TD[21]
TD[22]
TD[23]
TD[24]
TD[25]
TD[26]
TD[27]
TD[28]
TD[29]
TD[30]
TD[31]

Output

W23
Y22
W20
AA22
Y20
AB23
AC22
AC21
AC20
AA19
AA18
AB18
Y17
AA17
AB16
AC15
AC14
AA14
AC13
AB13
AA12
AB11
Y11
AB10
Y9
AA8
AC8
AB7
AC7
AC6
AC5
AB4

The transmit data signals (TD[31:0]) contain
the transmit data for the 32 independently
timed links in normal mode (PMCTEST set
low). Processing of the transmit links is on
a priority basis, in descending order from
TD[0] to TD[31]. Therefore, the highest rate
link should be connected to TD[0] and the
lowest to TD[31].

For H-MVIP links, TD[n] contain 32/128
time-slots, depending on the H-MVIP data
rate configured (2.048 or 8.192 Mbps).
When configured for 2.048 Mbps H-MVIP
operation, TD[31:24], TD[23:16], TD[15:8]
and TD[7:0] are updated on every 2nd falling
edge of TMVCK[3], TMVCK[2], TMVCK[1]
and TMVCK[0] respectively. When
configured for 8.192 Mbps H-MVIP

operation, TD[4m] (0£m£7) are updated on
every 2nd falling edge of TMV8DC.

For channelised links, TD[n] contains the 24
(T1/J1) or 31 (E1) time-slots that comprise
the channelised link. TCLK[n] must be
gapped during the T1/J1 framing bit position
or during the E1 frame alignment signal
(time-slot 0). The FREEDM-32P672 uses
the location of the gap to determine the
channel alignment on TD[n]. TD[31:0] are
updated on the falling edge of the
corresponding TCLK[31:0].

For unchannelised links, TD[n] contains the
HDLC packet data. For certain transmission
formats, TD[n] may contain place holder bits
or time-slots. TCLK[n] must be externally
gapped during the place holder positions in
the TD[n] stream. The FREEDM-32P672
supports a maximum data rate of 10 Mbit/s
on an individual TD[31:3] link and a
maximum data rate of 51.84 Mbit/s on
TD[2:0].

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 19