PMC PM7367-PI Datasheet

DATA SHEET

PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER

PM7367 FREEDM-32P32

PM7367

FREEDM™-32P32

FRAME ENGINE AND DATALINK

MANAGER

DATA SHEET

ISSUE 2: AUGUST 2001

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

DATA SHEET

PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER

PM7367 FREEDM-32P32

PUBLIC REVISION HISTORY

Issue No. Issue Date Details of Change

Issue 2 August 2001 Added patent information to legal footer. Issue 1 Nov, 1999 Data sheet created.

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DATA SHEET

PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER

PM7367 FREEDM-32P32

LIST OF REGISTERS

REGISTER 0X000 : FREEDM-32P32 MASTER RESET ..................................79

REGISTER 0X004 : FREEDM-32P32 MASTER INTERRUPT ENABLE...........81

REGISTER 0X008 : FREEDM-32P32 MASTER INTERRUPT STATUS ...........86

REGISTER 0X00C : FREEDM-32P32 MASTER CLOCK / BERT ACTIVITY

MONITOR AND ACCUMULATION TRIGGER ........................................90

REGISTER 0X010 : FREEDM-32P32 MASTER LINK ACTIVITY MONITOR ...92

REGISTER 0X014 : FREEDM-32P32 MASTER LINE LOOPBACK #1 ............96

REGISTER 0X018 : FREEDM-32P32 MASTER LINE LOOPBACK #2 ............98

REGISTER 0X020 : FREEDM-32P32 MASTER BERT CONTROL ................100

REGISTER 0X024 : FREEDM-32P32 MASTER PERFORMANCE MONITOR

CONTROL ............................................................................................102

REGISTER 0X040 : GPIC CONTROL ............................................................106

REGISTER 0X100 : RCAS INDIRECT LINK AND TIME-SLOT SELECT........109

REGISTER 0X104 : RCAS INDIRECT CHANNEL DATA................................ 111

REGISTER 0X108 : RCAS FRAMING BIT THRESHOLD............................... 113

REGISTER 0X10C : RCAS CHANNEL DISABLE ........................................... 115

REGISTER 0X180 : RCAS LINK #0 CONFIGURATION ................................. 117

REGISTER 0X184 - 0X188 : RCAS LINK #1 TO #2 CONFIGURATION......... 119

REGISTER 0X18C : RCAS LINK #3 CONFIGURATION ................................121

REGISTER 0X190-0X1FC : RCAS LINK #4 TO LINK #31 CONFIGURATION123

REGISTER 0X200 : RHDL INDIRECT CHANNEL SELECT ...........................125

REGISTER 0X204 : RHDL INDIRECT CHANNEL DATA REGISTER #1 ........127

REGISTER 0X208 : RHDL INDIRECT CHANNEL DATA REGISTER #2 ........130

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PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER

PM7367 FREEDM-32P32

REGISTER 0X210 : RHDL INDIRECT BLOCK SELECT ................................133

REGISTER 0X214 : RHDL INDIRECT BLOCK DATA .....................................135

REGISTER 0X220 : RHDL CONFIGURATION ...............................................137

REGISTER 0X224 : RHDL MAXIMUM PACKET LENGTH .............................139

REGISTER 0X280 : RMAC CONTROL...........................................................141

REGISTER 0X284 : RMAC INDIRECT CHANNEL PROVISIONING ..............144

REGISTER 0X288 : RMAC PACKET DESCRIPTOR TABLE BASE LSW ......146

REGISTER 0X28C : RMAC PACKET DESCRIPTOR TABLE BASE MSW.....147

REGISTER 0X290 : RMAC QUEUE BASE LSW ............................................149

REGISTER 0X294 : RMAC QUEUE BASE MSW ...........................................150

REGISTER 0X298 : RMAC PACKET DESCRIPTOR REFERENCE LARGE

BUFFER FREE QUEUE START...........................................................152

REGISTER 0X29C : RMAC PACKET DESCRIPTOR REFERENCE LARGE

BUFFER FREE QUEUE WRITE ..........................................................154

REGISTER 0X2A0 : RMAC PACKET DESCRIPTOR REFERENCE LARGE

BUFFER FREE QUEUE READ ............................................................156

REGISTER 0X2A4 : RMAC PACKET DESCRIPTOR REFERENCE LARGE

BUFFER FREE QUEUE END...............................................................158

REGISTER 0X2A8 : RMAC PACKET DESCRIPTOR REFERENCE SMALL

BUFFER FREE QUEUE START...........................................................160

REGISTER 0X2AC : RMAC PACKET DESCRIPTOR REFERENCE SMALL

BUFFER FREE QUEUE WRITE ..........................................................162

REGISTER 0X2B0 : RMAC PACKET DESCRIPTOR REFERENCE SMALL

BUFFER FREE QUEUE READ ............................................................164

REGISTER 0X2B4 : RMAC PACKET DESCRIPTOR REFERENCE SMALL

BUFFER FREE QUEUE END...............................................................166

REGISTER 0X2B8 : RMAC PACKET DESCRIPTOR REFERENCE READY

QUEUE START ....................................................................................168

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PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER

PM7367 FREEDM-32P32

REGISTER 0X2BC : RMAC PACKET DESCRIPTOR REFERENCE READY

QUEUE WRITE ....................................................................................170

REGISTER 0X2C0 : RMAC PACKET DESCRIPTOR REFERENCE READY

QUEUE READ ......................................................................................172

REGISTER 0X2C4 : RMAC PACKET DESCRIPTOR REFERENCE READY

QUEUE END ........................................................................................174

REGISTER 0X300 : TMAC CONTROL ...........................................................176

REGISTER 0X304 : TMAC INDIRECT CHANNEL PROVISIONING...............179

REGISTER 0X308 : TMAC DESCRIPTOR TABLE BASE LSW......................181

REGISTER 0X30C : TMAC DESCRIPTOR TABLE BASE MSW ....................182

REGISTER 0X310 : TMAC QUEUE BASE LSW ............................................184

REGISTER 0X314 : TMAC QUEUE BASE MSW ...........................................185

REGISTER 0X318 : TMAC DESCRIPTOR REFERENCE FREE QUEUE START

..............................................................................................................187

REGISTER 0X31C TMAC DESCRIPTOR REFERENCE FREE QUEUE WRITE

..............................................................................................................189

REGISTER 0X320 : TMAC DESCRIPTOR REFERENCE FREE QUEUE READ

..............................................................................................................191

REGISTER 0X324 : TMAC DESCRIPTOR REFERENCE FREE QUEUE END

..............................................................................................................193

REGISTER 0X328 :TMAC DESCRIPTOR REFERENCE READY QUEUE

START ..................................................................................................195

REGISTER 0X32C : TMAC DESCRIPTOR REFERENCE READY QUEUE

WRITE ..................................................................................................197

REGISTER 0X330 : TMAC DESCRIPTOR REFERENCE READY QUEUE READ199

REGISTER 0X334 : TMAC DESCRIPTOR REFERENCE READY QUEUE END

..............................................................................................................201

REGISTER 0X380 : THDL INDIRECT CHANNEL SELECT............................203

REGISTER 0X384 : THDL INDIRECT CHANNEL DATA #1............................205

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PM7367 FREEDM-32P32

REGISTER 0X388 : THDL INDIRECT CHANNEL DATA #2............................208

REGISTER 0X38C : THDL INDIRECT CHANNEL DATA #3 ...........................211

REGISTER 0X3A0 : THDL INDIRECT BLOCK SELECT ................................216

REGISTER 0X3A4 : THDL INDIRECT BLOCK DATA .....................................218

REGISTER 0X3B0 : THDL CONFIGURATION ...............................................220

REGISTER 0X400 : TCAS INDIRECT LINK AND TIME-SLOT SELECT ........222

REGISTER 0X404 : TCAS INDIRECT CHANNEL DATA ................................224

REGISTER 0X408 : TCAS FRAMING BIT THRESHOLD ...............................226

REGISTER 0X40C : TCAS IDLE TIME-SLOT FILL DATA...............................228

REGISTER 0X410 : TCAS CHANNEL DISABLE ............................................230

REGISTER 0X480 : TCAS LINK #0 CONFIGURATION .................................232

REGISTER 0X484-0X488 : TCAS LINK #1 TO LINK #2 CONFIGURATION ..234

REGISTER 0X48C : TCAS LINK #3 CONFIGURATION.................................236

REGISTER 0X490-0X4FC : TCAS LINK #4 TO LINK #31 CONFIGURATION238

REGISTER 0X500 : PMON STATUS ..............................................................240

REGISTER 0X504 : PMON RECEIVE FIFO OVERFLOW COUNT................242

REGISTER 0X508 : PMON RECEIVE FIFO UNDERFLOW COUNT .............244

REGISTER 0X50C : PMON CONFIGURABLE COUNT #1.............................246

REGISTER 0X510 : PMON CONFIGURABLE COUNT #2 .............................248

REGISTER 0X00 : VENDOR IDENTIFICATION/DEVICE IDENTIFICATION..251

REGISTER 0X04 : COMMAND/STATUS ........................................................252

REGISTER 0X08 : REVISION IDENTIFIER/CLASS CODE............................256

REGISTER 0X0C : CACHE LINE SIZE/LATENCY TIMER/HEADER TYPE ...257

REGISTER 0X10 : CBI MEMORY BASE ADDRESS REGISTER...................258

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PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER

PM7367 FREEDM-32P32

REGISTER 0X3C : INTERRUPT LINE / INTERRUPT PIN / MIN_GNT /

MAX_LAT..............................................................................................260

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DATA SHEET

PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER

PM7367 FREEDM-32P32

LIST OF FIGURES

FIGURE 1 – HDLC FRAME...............................................................................30

FIGURE 2 – CRC GENERATOR.......................................................................31

FIGURE 3 – PARTIAL PACKET BUFFER STRUCTURE..................................35

FIGURE 4 – RECEIVE PACKET DESCRIPTOR...............................................37

FIGURE 5 – RECEIVE PACKET DESCRIPTOR TABLE...................................40

FIGURE 6 – RPDRF AND RPDRR QUEUES ...................................................42

FIGURE 7 – RPDRR QUEUE OPERATION......................................................44

FIGURE 8 – RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE.........45

FIGURE 9 – GPIC ADDRESS MAP ..................................................................52

FIGURE 10 – TRANSMIT DESCRIPTOR .........................................................54

FIGURE 11 – TRANSMIT DESCRIPTOR TABLE .............................................58

FIGURE 12 – TDRR AND TDRF QUEUES .......................................................60

FIGURE 13 – TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE ....62

FIGURE 14 – TD LINKING................................................................................65

FIGURE 15 – PARTIAL PACKET BUFFER STRUCTURE................................69

FIGURE 16 – INPUT OBSERVATION CELL (IN_CELL) .................................274

FIGURE 17 – OUTPUT CELL (OUT_CELL) ...................................................275

FIGURE 18 – BI-DIRECTIONAL CELL (IO_CELL) .........................................275

FIGURE 19 – LAYOUT OF OUTPUT ENABLE AND BI-DIRECTIONAL CELLS

..............................................................................................................276

FIGURE 20 – BOUNDARY SCAN ARCHITECTURE ......................................278

FIGURE 21 – TAP CONTROLLER FINITE STATE MACHINE........................280

FIGURE 22 – UNCHANNELISED RECEIVE LINK TIMING ............................284

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PM7367 FREEDM-32P32

FIGURE 23 – CHANNELISED T1 RECEIVE LINK TIMING ............................285

FIGURE 24 – CHANNELISED E1 RECEIVE LINK TIMING............................285

FIGURE 25 – UNCHANNELISED TRANSMIT LINK TIMING..........................286

FIGURE 26 – CHANNELISED T1 TRANSMIT LINK TIMING..........................286

FIGURE 27 – CHANNELISED E1 TRANSMIT LINK TIMING .........................287

FIGURE 28 – PCI READ CYCLE ....................................................................288

FIGURE 29 – PCI WRITE CYCLE ..................................................................290

FIGURE 30 – PCI TARGET DISCONNECT ....................................................291

FIGURE 31 – PCI TARGET ABORT................................................................291

FIGURE 32 – PCI BUS REQUEST CYCLE ....................................................292

FIGURE 33 – PCI INITIATOR ABORT TERMINATION ...................................293

FIGURE 34 – PCI EXCLUSIVE LOCK CYCLE ...............................................294

FIGURE 35 – PCI FAST BACK TO BACK.......................................................296

FIGURE 36 – RECEIVE BERT PORT TIMING ...............................................296

FIGURE 37 – TRANSMIT BERT PORT TIMING.............................................297

FIGURE 38 – RECEIVE LINK INPUT TIMING ................................................302

FIGURE 39 – BERT INPUT TIMING ...............................................................302

FIGURE 40 – TRANSMIT LINK OUTPUT TIMING..........................................304

FIGURE 41 – BERT OUTPUT TIMING ...........................................................304

FIGURE 42 – PCI INTERFACE TIMING .........................................................305

FIGURE 43 – JTAG PORT INTERFACE TIMING............................................306

FIGURE 44 – 272 PIN PLASTIC BALL GRID ARRAY (PBGA) .......................308

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DATA SHEET

PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER

PM7367 FREEDM-32P32

LIST OF TABLES

TABLE 1 – LINE SIDE INTERFACE SIGNALS (132)..........................................9

TABLE 2 – PCI HOST INTERFACE SIGNALS (51) ..........................................14

TABLE 3 – MISCELLANEOUS INTERFACE SIGNALS (41).............................23

TABLE 4 – PRODUCTION TEST INTERFACE SIGNALS (0 - MULTIPLEXED)26

TABLE 5 – POWER AND GROUND SIGNALS (60) .........................................27

TABLE 6 – RECEIVE PACKET DESCRIPTOR FIELDS....................................37

TABLE 7 – RPDRR QUEUE ELEMENT............................................................43

TABLE 8 – RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE FIELDS

................................................................................................................45

TABLE 9 – TRANSMIT DESCRIPTOR FIELDS................................................55

TABLE 10 – TRANSMIT DESCRIPTOR REFERENCE.....................................61

TABLE 11 – TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE

FIELDS ...................................................................................................63

TABLE 12 – NORMAL MODE PCI HOST ACCESSIBLE REGISTER MEMORY

MAP ........................................................................................................73

TABLE 13 – PCI CONFIGURATION REGISTER MEMORY MAP.....................77

TABLE 14 – BIG ENDIAN FORMAT................................................................107

TABLE 15 – LITTLE ENDIAN FORMAT ..........................................................107

TABLE 16 – CRC[1:0] SETTINGS...................................................................129

TABLE 17 – RPQ_RDYN[2:0] SETTINGS ......................................................142

TABLE 18 – RPQ_LFN[1:0] SETTINGS..........................................................143

TABLE 19 – RPQ_SFN[1:0] SETTINGS .........................................................143

TABLE 20 – TDQ_RDYN[2:0] SETTINGS.......................................................177

TABLE 21 – TDQ_FRN[1:0] SETTINGS .........................................................177

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PM7367 FREEDM-32P32

TABLE 22 – CRC[1:0] SETTINGS...................................................................206

TABLE 23 – FLAG[2:0] SETTINGS.................................................................212

TABLE 24 – LEVEL[3:0]/TRANS SETTINGS ..................................................214

TABLE 25 – TEST MODE REGISTER MEMORY MAP ..................................262

TABLE 26 – INSTRUCTION REGISTER ........................................................263

TABLE 27 – BOUNDARY SCAN CHAIN .........................................................264

TABLE 28 – FREEDM–EQUAD CONNECTIONS ...........................................277

TABLE 29 – FREEDM–TOCTAL CONNECTIONS ..........................................277

TABLE 30 – FREEDM-32P32 ABSOLUTE MAXIMUM RATINGS...................298

TABLE 31 – FREEDM-32P32 D.C. CHARACTERISTICS...............................299

TABLE 32 – FREEDM-32P32 LINK INPUT (FIGURE 38, FIGURE 39)...........301

TABLE 33 – FREEDM-32P32 LINK OUTPUT (FIGURE 40, FIGURE 41).......303

TABLE 34 – PCI INTERFACE (FIGURE 42) ...................................................304

TABLE 35 – JTAG PORT INTERFACE (FIGURE 43)......................................305

TABLE 36 – FREEDM-32P32 ORDERING INFORMATION............................307

TABLE 37 – FREEDM-32P32 THERMAL INFORMATION..............................307

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PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER

PM7367 FREEDM-32P32

1 FEATURES

· Single-chip Peripheral Component Interconnect (PCI) Bus multi-channel HDLC controller.

· Supports up to 32 bi-directional HDLC channels assigned to a maximum of 32 channelised T1 or E1 links. The number of time-slots assigned to an HDLC channel is programmable from 1 to 24 (for T1) and from 1 to 31 (for E1).

· Supports up to 32 bi-directional HDLC channels each assigned to an unchannelised arbitrary rate link; subject to a maximum aggregate link clock rate of 64 MHz in each direction. Channels assigned to links 0 to 2 can have a clock rate of up to 45 MHz when SYSCLK is at or above 25 MHz and up to 52 MHz when SYSCLK is at 33 MHz. Channels assigned to links 3 to 31 can have a clock rate of up to 10 MHz.

· Supports up to two bi-directional HDLC channels each assigned to an unchannelised arbitrary rate link of up to 45 MHz when SYSCLK is at or above 25 MHz and up to 52 MHz when SYSCLK is at 33 MHz.

· Supports a mix of up to 32 channelised and unchannelised links; subject to the constraint of a maximum of 32 channels and a maximum aggregate link clock rate of 64 MHz in each direction.

· For each channel, the HDLC receiver performs flag sequence detection, bit de-stuffing, and frame check sequence validation. The receiver supports the validation of both CRC-CCITT and CRC-32 frame check sequences. The receiver also checks for packet abort sequences, octet aligned packet length and for minimum and maximum packet length.

· Alternatively, for each channel, the receiver supports a transparent mode where each octet is transferred transparently to host memory. For channelised links, the octets are aligned with the receive time-slots.

· For each channel, time-slots are selectable to be in 56 kbits/s format or 64 kbits/s clear channel format.

· For each channel, the HDLC transmitter performs flag sequence generation, bit stuffing, and, optionally, frame check sequence generation. The transmitter supports the generation of both CRC-CCITT and CRC-32 frame check sequences. The transmitter also aborts packets under the direction of the host or automatically when the channel underflows.

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PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER

PM7367 FREEDM-32P32

· Supports two levels of non-preemptive packet priority on each transmit channel. Low priority packets will not begin transmission until all high priority packets are transmitted.

· Alternatively, for each channel, the transmitter supports a transparent mode where each octet is inserted transparently from host memory. For channelised links, the octets are aligned with the transmit time-slots.

· Directly supports a 32-bit, 33 MHz PCI 2.1 interface for configuration, monitoring and transfer of packet data, with an on-chip DMA controller with scatter/gather capabilities.

· Provides 8 kbytes of on-chip memory for partial packet buffering in each direction. This memory can be configured to support a variety of different channel configurations from a single channel with 8 kbytes of buffering to 32 channels, each with a minimum of 48 bytes of buffering.

· Supports PCI burst sizes of up to 128 bytes for transfers of packet data.

· Pin compatible with PM7366-PI (FREEDM-8 PBGA) device.

· Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board

test purposes.

· Supports 3.3 and 5 Volt PCI signaling environments.

· Low power CMOS technology.

· 272 pin Plastic ball grid array (PBGA) package (27 mm X 27 mm).

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PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER

PM7367 FREEDM-32P32

2 APPLICATIONS

· DCC Processing in SONET/SDH interfaces

· Packet-based DSLAM equipment.

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PM7367 FREEDM-32P32

3 REFERENCES

1. International Organization for Standardization, ISO Standard 3309-1993, "Information Technology - Telecommunications and information exchange between systems - High-level data link control (HDLC) procedures - Frame structure", December 1993.

2. RFC-1662 - "PPP in HDLC-like Framing" Internet Engineering Task Force, July 1994.

3. PCI Special Interest Group, PCI Local Bus Specification, June 1, 1995, Version 2.1.

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A

/

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PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER

PM7367 FREEDM-32P32

4 BLOCK DIAGRAM

.

AD[31:0]

C/BEB[3:0]

PAR

TRDYB

IRDYB

STOPB

DEVSELB

IDSEL

LOCKB

GNTB

PERRB

SERRB

PCIINTB

PCICLK

PCICLKO

SYSCLK

PMCTEST

TDO TDI

TCK TMS

JTAG Port

TRSTB

RSTB

FRAMEB

PCI

Controller

REQB

(GPIC)

RBCLK

RBD

DM

Receive

Controller

(RHDL)

Partial Packet Buffer

(RMAC)

(PMON)

Performance Monitor

Receive HDLC Processor

Transmit

Transmit HDLC Processor

DM

Partial Packet Buffer

(TMAC)

Controller

(THDL)

TBCLK

ssigner

Channel

(RCAS)

Receive

Transmit

Channel

ssigner

(TCAS)

TBD

RD[31:0]

RCLK[31:0]

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TD[31:0]

TCLK[31:0]

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PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER

PM7367 FREEDM-32P32

5 DESCRIPTION

The PM7367 FREEDM-32P32 Frame Engine and Datalink Manager device is a monolithic integrated circuit that implements HDLC processing, and PCI Bus memory management functions for a maximum of 32 bi-directional channels.

For channelised links, the FREEDM-32P32 allows up to 32 bi-directional HDLC channels to be assigned to individual time-slots within a maximum of 32 independently timed T1 or E1 links. The channel assignment supports the concatenation of time-slots (N x DS0) up to a maximum of 24 concatenated timeslots for a T1 link and 31 concatenated time-slots for an E1 link. Time-slots assigned to any particular channel need not be contiguous within the T1 or E1 link.

For unchannelised links, the FREEDM-32P32 processes up to 32 bi-directional HDLC channels within 32 independently timed links. The links can be of arbitrary frame format. When limited to two unchannelised links, each link can be rated at up to 45 MHz when SYSCLK is at 25 MHz and at up to 52 MHz when SYSCLK is at 33 MHz. For lower rate unchannelised links, the FREEDM-32P32 processes up to 32 links, where the aggregate clock rate of all the links is limited to 64 MHz, links 0 to 2 can have a clock rate of up to 45 MHz when SYSCLK is at or above 25 MHz and up to 52 MHz when SYSCLK is at 33 MHz and links 3 to 31 can have a clock rate of up to 10 MHz.

The FREEDM-32P32 supports mixing of up to 32 channelised and unchannelised links. The total number of channels in each direction is limited to

32. The aggregate clock rate over all 32 possible links is limited to 64 MHz.

In the receive direction, the FREEDM-32P32 performs channel assignment and packet extraction and validation. For each provisioned HDLC channel, the FREEDM-32P32 delineates the packet boundaries using flag sequence detection, and performs bit de-stuffing. Sharing of opening and closing flags, as well as, sharing of zeros between flags are supported. The resulting packet data is placed into the internal 8 kbyte partial packet buffer RAM. The partial packet buffer acts as a logical FIFO for each of the assigned channels. Partial packets are DMA'd out of the RAM, across the PCI bus and into host packet memory. The FREEDM-32P32 validates the frame check sequence for each packet, and verifies that the packet is an integral number of octets in length and is within a programmable minimum and maximum length. The receive packet status is updated before linking the packet into a receive ready queue. The FREEDM32P32 alerts the PCI Host that there are packets in a receive ready queue by, optionally, asserting an interrupt on the PCI bus.

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PM7367 FREEDM-32P32

Alternatively, in the receive direction, the FREEDM-32P32 supports a transparent operating mode. For each provisioned transparent channel, the FREEDM32P32 directly transfers the received octets into host memory verbatim. If the transparent channel is assigned to a channelised link, then the octets are aligned to the received time-slots.

In the transmit direction, the PCI Host provides packets to transmit using a transmit ready queue. For each provisioned HDLC channel, the FREEDM32P32 DMA's partial packets across the PCI bus and into the transmit partial packet buffer. The partial packets are read out of the packet buffer by the FREEDM-32P32 and frame check sequence is optionally calculated and inserted at the end of each packet. Bit stuffing is performed before being assigned to a particular link. The flag sequence is automatically inserted when there is no packet data for a particular channel. Sequential packets are optionally separated by two flags (an opening flag and a closing flag) or a single flag (combined opening and closing flag). Zeros between flags are not shared. PCI bus latency may cause one or more channels to underflow, in which case, the packets are aborted, and the host is notified. For normal traffic, an abort sequence is generated, followed by inter-frame time fill characters (flags or all-ones bytes) until a new packet is sourced from the PCI host. No attempt is made to automatically re-transmit an aborted packet.

Alternatively, in the transmit direction, the FREEDM-32P32 supports a transparent operating mode. For each provisioned transparent channel, the FREEDM-32P32 directly inserts the transmitted octets from host memory. If the transparent channel is assigned to a channelised link, then the octets are aligned to the transmitted time-slots. If a channel underflows due to excessive PCI bus latency, an abort sequence is generated, followed by inter-frame time fill characters (flags or all-ones bytes) to indicate idle channel. Data resumes immediately when the FREEDM-32P32 receives new data from the host.

The FREEDM-32P32 is configured, controlled and monitored using the PCI bus interface. The FREEDM-32P32 is implemented in low power CMOS technology. It has TTL compatible inputs and outputs and is packaged in a 272 pin plastic ball grid array (PBGA) package.

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PM7367 FREEDM-32P32

6 PIN DIAGRAM

The FREEDM-32P32 is manufactured in a 272 pin Plastic ball grid array package. The center 16 balls are not used as signal I/Os and are thermal balls.

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PM7367 FREEDM-32P32

7 PIN DESCRIPTION

Table 1 – Line Side Interface Signals (132)

Pin Name Type Pin

Function

No.

RCLK[0] RCLK[1] RCLK[2] RCLK[3] RCLK[4] RCLK[5] RCLK[6] RCLK[7] RCLK[8] RCLK[9] RCLK[10] RCLK[11] RCLK[12] RCLK[13] RCLK[14] RCLK[15] RCLK[16] RCLK[17] RCLK[18] RCLK[19] RCLK[20] RCLK[21] RCLK[22] RCLK[23] RCLK[24] RCLK[25] RCLK[26] RCLK[27] RCLK[28] RCLK[29] RCLK[30] RCLK[31]

Input G1

G3 F2 F3 E2 D1 D2 B4 A4 C6 A5 C7 B7 C8 A8 C9 A9 C10 A10 C11 A12 C12 A13 C13 B14 A15 D14 A16 C16 D16 W17 Y17

The receive line clock signals (RCLK[31:0]) contain the recovered line clock for the 32 independently timed links. Processing of the receive links is on a priority basis, in descending order from RCLK[0] to RCLK[31]. Therefore, the highest rate link should be connected to RCLK[0] and the lowest to RCLK[31]. RD[31:0] is sampled on the rising edge of the corresponding RCLK[31:0] clock.

For channelised T1 or E1 links, RCLK[n] must be gapped during the framing bit (for T1 interfaces) or during time-slot 0 (for E1 interfaces) of the RD[n] stream. The FREEDM-32P32 uses the gapping information to determine the time-slot alignment in the receive stream. RCLK[31:0] is nominally a 50% duty cycle clock of 1.544 MHz for T1 links and 2.048 MHz for E1 links.

For unchannelised links, RCLK[n] must be externally gapped during the bits or timeslots that are not part of the transmission format payload (i.e. not part of the HDLC packet). RCLK[2:0] is nominally a 50% duty cycle clock between 0 and 52 MHz. RCLK[31:3] is nominally a 50% duty cycle clock between 0 and 10 MHz.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 9

DATA SHEET

PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER

Pin Name Type Pin

Function

PM7367 FREEDM-32P32

No.

RD[0] RD[1] RD[2] RD[3] RD[4] RD[5] RD[6] RD[7] RD[8] RD[9] RD[10] RD[11] RD[12] RD[13] RD[14] RD[15] RD[16] RD[17] RD[18] RD[19] RD[20] RD[21] RD[22] RD[23] RD[24] RD[25] RD[26] RD[27] RD[28] RD[29] RD[30] RD[31]

Input H3

G2 F1 G4 E1 E3 E4 D5 C5 B5 D7 B6 A6 A7 B8 D9 B9 D10 B10 A11 B11 B12 D12 B13 A14 C14 B15 C15 B16 A17 U16 V16

The receive data signals (RD[31:0]) contain the recovered line data for the 32 independently timed links in normal mode (PMCTEST set low). Processing of the receive links is on a priority basis, in descending order form RD[0] to RD[31]. Therefore, the highest rate link should be connected to RD[0] and the lowest to RD[31].

For channelised links, RD[n] contains the 24 (T1) or 31 (E1) time-slots that comprise the channelised link. RCLK[n] must be gapped during the T1 framing bit position or the E1 frame alignment signal (time-slot 0). The FREEDM-32P32 uses the location of the gap to determine the channel alignment on RD[n].

For unchannelised links, RD[n] contains the HDLC packet data. For certain transmission formats, RD[n] may contain place holder bits or time-slots. RCLK[n] must be externally gapped during the place holder positions in the RD[n] stream. The FREEDM-32P32 supports a maximum data rate of 10 Mbit/s on an individual RD[31:3] link and a maximum data rate of 52 Mbit/s on RD[2:0].

RD[31:0] is sampled on the rising edge of the corresponding RCLK[31:0] clock.

RBD Tristate

Output

H1 The receive BERT data signal (RBD)

contains the receive bit error rate test data. RBD reports the data on the selected one of the receive data signals (RD[31:0]) and is updated on the falling edge of RBCLK. RBD may be tri-stated by setting the RBEN bit in the FREEDM-32P32 Master BERT Control register low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 10

DATA SHEET

PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER

Pin Name Type Pin

Function

PM7367 FREEDM-32P32

No.

RBCLK Tristate

Output

H2 The receive BERT clock signal (RBCLK)

contains the receive bit error rate test clock. RBCLK is a buffered version of the selected one of the receive clock signals (RCLK[31:0]). RBCLK may be tri-stated by setting the RBEN bit in the FREEDM-32P32 Master BERT Control register low.

TCLK[0] TCLK[1] TCLK[2] TCLK[3] TCLK[4] TCLK[5] TCLK[6] TCLK[7] TCLK[8] TCLK[9] TCLK[10] TCLK[11] TCLK[12] TCLK[13] TCLK[14] TCLK[15] TCLK[16] TCLK[17] TCLK[18] TCLK[19] TCLK[20] TCLK[21] TCLK[22] TCLK[23] TCLK[24] TCLK[25] TCLK[26] TCLK[27] TCLK[28] TCLK[29] TCLK[30] TCLK[31]

Input L2

L4 M2 M4 N2 P1 R1 R2 P4 T2 T3 T4 W4 U5 V5 Y5 U7 Y6 W7 V8 Y8 V9 Y9 V10 Y11 V11 Y12 V12 Y13 V13 W14 V14

The transmit line clock signals (TCLK[31:0]) contain the transmit clocks for the 32 independently timed links. Processing of the transmit links is on a priority basis, in descending order from TCLK[0] to TCLK[31]. Therefore, the highest rate link should be connected to TCLK[0] and the lowest to TCLK[31]. TD[31:0] is updated on the falling edge of the corresponding TCLK[31:0] clock.

For channelised T1 or E1 links, TCLK[n] must be gapped during the framing bit (for T1 interfaces) or during time-slot 0 (for E1 interfaces) of the TD[n] stream. The FREEDM-32P32 uses the gapping information to determine the time-slot alignment in the transmit stream.

For unchannelised links, TCLK[n] must be externally gapped during the bits or timeslots that are not part of the transmission format payload (i.e. not part of the HDLC packet).

TCLK[31:3] is nominally a 50% duty cycle clock between 0 and 10 MHz. TCLK[2:0] is nominally a 50% duty cycle clock between 0 and 52 MHz. Typical values for TCLK[31:0] include 1.544 MHz (for T1 links) and 2.048 MHz (for E1 links).

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 11

DATA SHEET

PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER

Pin Name Type Pin

Function

PM7367 FREEDM-32P32

No.

TD[0] TD[1] TD[2] TD[3] TD[4] TD[5] TD[6] TD[7] TD[8] TD[9] TD[10] TD[11] TD[12] TD[13] TD[14] TD[15] TD[16] TD[17] TD[18] TD[19] TD[20] TD[21] TD[22] TD[23] TD[24] TD[25] TD[26] TD[27] TD[28] TD[29] TD[30] TD[31]

Output L1

L3 M1 M3 N1 N3 P2 P3 T1 R3 U1 U2 U3 V4 Y4 W5 V6 W6 V7 Y7 W8 U9 W9 W10 Y10 W11 U11 W12 U12 W13 Y14 Y15

The transmit data signals (TD[31:0]) contains the transmit data for the 32 independently timed links in normal mode (PMCTEST set low). Processing of the transmit links is on a priority basis, in descending order from TD[0] to TD[31]. Therefore, the highest rate link should be connected to TD[0] and the lowest to TD[31].

For channelised links, TD[n] contains the 24 (T1) or 31 (E1) time-slots that comprise the channelised link. TCLK[n] must be gapped during the T1 framing bit position or the E1 frame alignment signal (time-slot 0). The FREEDM-32P32 uses the location of the gap to determine the channel alignment on TD[n].

For unchannelised links, TD[n] contains the HDLC packet data. For certain transmission formats, TD[n] may contain place holder bits or time-slots. TCLK[n] must be externally gapped during the place holder positions in the TD[n] stream. The FREEDM-32P32 supports a maximum data rate of 10 Mbit/s on an individual TD[31:3] link and a maximum data rate of 52 Mbit/s on TD[2:0]

TD[31:0] is updated on the falling edge of the corresponding TCLK[31:0] clock.

TBD Input W15 The transmit BERT data signal (TBD)

contains the transmit bit error rate test data. When the TBERTEN bit in the BERT Control register is set high, the data on TBD is transmitted on the selected one of the transmit data signals (TD[31:0]). TBD is sampled on the rising edge of TBCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 12

DATA SHEET

PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER

Pin Name Type Pin

Function

PM7367 FREEDM-32P32

No.

TBCLK Tristate

Output

Y16 The transmit BERT clock signal (TBCLK)

contains the transmit bit error rate test clock. TBCLK is a buffered version of the selected one of the transmit clock signals (TCLK[31:0]). TBCLK may be tri-stated by setting the TBEN bit in the FREEDM-32P32 Master BERT Control register low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 13

DATA SHEET

PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER

PM7367 FREEDM-32P32

Table 2 – PCI Host Interface Signals (51)

Pin Name Type Pin

Function

No.

PCICLK Input B17 The PCI clock signal (PCICLK) provides timing

for PCI bus accesses. PCICLK is a nominally 50% duty cycle, 0 to 33 MHz clock.

PCICLKO Output C17 The PCI clock output signal (PCICLKO) is a

buffered version of the PCICLK. PCICLKO may be used to drive the SYSCLK input.

AD[0]

AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[30]

I/O U19

U18 T17 U20 T18 T19 T20 R18 R20 P18 P19 P20 N18 N19 N20 M17 J19 J18 J17 H20 H19 H18 G20 G19 F19 E20 G17 F18 E19 D20 E18

The PCI address and data bus (AD[31:0]) carries the PCI bus multiplexed address and data. During the first clock cycle of a transaction, AD[31:0] contains a physical byte address. During subsequent clock cycles of a transaction, AD[31:0] contains data.

A transaction is defined as an address phase followed by one or more data phases. When Little-Endian byte formatting is selected, AD[31:24] contain the most significant byte of a DWORD while AD[7:0] contain the least significant byte. When Big-Endian byte formatting is selected. AD[7:0] contain the most significant byte of a DWORD while AD[31:24] contain the least significant byte. When the FREEDM-32P32 is the initiator, AD[31:0] is an output bus during the first (address) phase of a transaction. For write transactions, AD[31:0] remains an output bus for the data phases of the transaction. For read transactions, AD[31:0] is an input bus during the data phases.

When the FREEDM-32P32 is the target, AD[31:0] is an input bus during the first (address) phase of a transaction. For write transactions, AD[31:0] remains an input bus during the data phases of the transaction. For read transactions, AD[31:0] is an output bus during the data phases.

When the FREEDM-32P32 is not involved in the current transaction, AD[31:0] is tri-stated.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 14

DATA SHEET

PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER

Pin Name Type Pin

Function

PM7367 FREEDM-32P32

No.

AD[31] I/O D19 As an output bus, AD[31:0] is updated on the

rising edge of PCICLK. As an input bus, AD[31:0] is sampled on the rising edge of PCICLK.

C/BEB[0]

C/BEB[1] C/BEB[2] C/BEB[3]

I/O R19

M18 J20 G18

The PCI bus command and byte enable bus (C/BEB[3:0]) contains the bus command or the byte valid indications. During the first clock cycle of a transaction, C/BEB[3:0] contains the bus command code. For subsequent clock cycles, C/BEB[3:0] identifies which bytes on the AD[31:0] bus carry valid data. C/BEB[3] is associated with byte 3 (AD[31:24]) while C/BEB[0] is associated with byte 0 (AD[7:0]). When C/BEB[n] is set high, the associated byte is invalid. When C/BEB[n] is set low, the associated byte is valid.

When the FREEDM-32P32 is the initiator, C/BEB[3:0] is an output bus.

When the FREEDM-32P32 is the target, C/BEB[3:0] is an input bus.

When the FREEDM-32P32 is not involved in the current transaction, C/BEB[3:0] is tri-stated.

As an output bus, C/BEB[3:0] is updated on the rising edge of PCICLK. As an input bus, C/BEB[3:0] is sampled on the rising edge of PCICLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 15

DATA SHEET

PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER

Pin Name Type Pin

Function

PM7367 FREEDM-32P32

No.

PAR I/O M19 The parity signal (PAR) indicates the parity of

the AD[31:0] and C/BEB[3:0] buses. Even parity is calculated over all 36 signals in the buses regardless of whether any or all the bytes on the AD[31:0] are valid. PAR always reports the parity of the previous PCICLK cycle. Parity errors detected by the FREEDM-32P32 are indicated on output PERRB and in the FREEDM-32P32 Interrupt Status register.

When the FREEDM-32P32 is the initiator, PAR is an output for writes and an input for reads.

When the FREEDM-32P32 is the target, PAR is an input for writes and an output for reads.

When the FREEDM-32P32 is not involved in the current transaction, PAR is tri-stated.

As an output signal, PAR is updated on the rising edge of PCICLK. As an input signal, PAR is sampled on the rising edge of PCICLK.

FRAMEB I/O K17 The active low cycle frame signal (FRAMEB)

identifies a transaction cycle. When FRAMEB transitions low, the start of a bus transaction is indicated. FRAMEB remains low to define the duration of the cycle. When FRAMEB transitions high, the last data phase of the current transaction is indicated.

When the FREEDM-32P32 is the initiator, FRAMEB is an output.

When the FREEDM-32P32 is the target, FRAMEB is an input.

When the FREEDM-32P32 is not involved in the current transaction, FRAMEB is tri-stated.

As an output signal, FRAMEB is updated on the rising edge of PCICLK. As an input signal, FRAMEB is sampled on the rising edge of PCICLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 16

PMC PM7367-PI Datasheet

CONTENTS

LIST OF REGISTERS

LIST OF FIGURES

LIST OF TABLES