PMC PM7366-BI, PM7366-PI Datasheet

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PMC-1970930 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER

PM7366 FREEDM-8

PM7366

FREEDM™-8

EIGHT CHANNEL FRAME ENGINE AND

DATALINK MANAGER

PROPRIETARY AND CONFIDENTIAL

ISSUE 4: AUGUST 2001

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REVISION HISTORY

Issue No. Issue Date Details of Change

Issue 4 August 2001 Added patent information to legal footer, last page. Change

bars pertain to issue 3.

Issue 3 August 1999 Updated to include PBGA package option

· Addition of new pinout, pin description, and mechanical diagram.

Incorporated Documentation Errata from PMC-980452, “PM7366 FREEDM-8 Revision D Device Errata Sheet” Issue 4.

Issue 2 May 1998 Updated for Freedm-8 Release to Production

Issue 1 Sept. 1997 Document created for Prototype release

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1 FEATURES ....................................................................................................................... 1

2 APPLICATIONS ................................................................................................................ 3

3 REFERENCES.................................................................................................................. 4

4 APPLICATION EXAMPLES .............................................................................................. 5

5 BLOCK DIAGRAM ............................................................................................................ 6

6 DESCRIPTION.................................................................................................................. 7

7 PIN DIAGRAM...................................................................................................................9

8 PIN DESCRIPTION..........................................................................................................11

9 FUNCTIONAL DESCRIPTION........................................................................................ 33

9.1 HIGH-LEVEL DATA LINK CONTROL PROTOCOL ........................................... 33

9.2 RECEIVE CHANNEL ASSIGNER ...................................................................... 34

9.2.1 LINE INTERFACE............................................................................. 34

9.2.2 PRIORITY ENCODER...................................................................... 34

9.2.3 CHANNEL ASSIGNER ..................................................................... 35

9.2.4 LOOPBACK CONTROLLER ............................................................ 35

9.3 RECEIVE HDLC PROCESSOR / PARTIAL PACKET BUFFER ........................ 35

9.3.1 HDLC PROCESSOR ........................................................................ 36

9.3.2 PARTIAL PACKET BUFFER PROCESSOR..................................... 36

9.4 RECEIVE DMA CONTROLLER ......................................................................... 38

9.4.1 DATA STRUCTURES ....................................................................... 38

9.4.2 DMA TRANSACTION CONTROLLER ............................................. 48

9.4.3 WRITE DATA PIPELINE/MUX .......................................................... 48

9.4.4 DESCRIPTOR INFORMATION CACHE........................................... 48

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9.4.5 FREE QUEUE CACHE..................................................................... 48

9.5 PCI CONTROLLER............................................................................................ 49

9.5.1 MASTER MACHINE ......................................................................... 49

9.5.2 MASTER LOCAL BUS INTERFACE................................................. 51

9.5.3 TARGET MACHINE .......................................................................... 52

9.5.4 CBI BUS INTERFACE ...................................................................... 54

9.5.5 ERROR / BUS CONTROL................................................................ 54

9.6 TRANSMIT DMA CONTROLLER ...................................................................... 54

9.6.1 DATA STRUCTURES ....................................................................... 55

9.6.2 TASK PRIORITIES ........................................................................... 66

9.6.3 DMA TRANSACTION CONTROLLER ............................................. 66

9.6.4 READ DATA PIPELINE ..................................................................... 66

9.6.5 DESCRIPTOR INFORMATION CACHE........................................... 66

9.6.6 FREE QUEUE CACHE..................................................................... 66

9.7 TRANSMIT HDLC CONTROLLER / PARTIAL PACKET BUFFER .................... 67

9.7.1 TRANSMIT HDLC PROCESSOR..................................................... 67

9.7.2 TRANSMIT PARTIAL PACKET BUFFER PROCESSOR ................. 67

9.8 TRANSMIT CHANNEL ASSIGNER ................................................................... 69

9.8.1 LINE INTERFACE............................................................................. 70

9.8.2 PRIORITY ENCODER...................................................................... 70

9.8.3 CHANNEL ASSIGNER ..................................................................... 71

9.9 PERFORMANCE MONITOR ............................................................................. 71

9.10 JTAG TEST ACCESS PORT INTERFACE ........................................................ 71

9.11 PCI HOST INTERFACE..................................................................................... 71

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10 NORMAL MODE REGISTER DESCRIPTION ................................................................ 76

10.1 PCI HOST ACCESSIBLE REGISTERS ............................................................. 76

11 PCI CONFIGURATION REGISTER DESCRIPTION .................................................... 216

11.1 PCI CONFIGURATION REGISTERS .............................................................. 216

12 TEST FEATURES DESCRIPTION ............................................................................... 226

12.1 TEST MODE REGISTERS .............................................................................. 226

12.2 JTAG TEST PORT ........................................................................................... 227

12.2.1 IDENTIFICATION REGISTER ........................................................ 228

12.2.2 BOUNDARY SCAN REGISTER ..................................................... 228

13 OPERATIONS ............................................................................................................... 241

13.1 EQUAD CONNECTIONS................................................................................. 241

13.2 TOCTL CONNECTIONS .................................................................................. 241

13.3 JTAG SUPPORT.............................................................................................. 242

14 FUNCTIONAL TIMING.................................................................................................. 248

14.1 RECEIVE LINK INPUT TIMING ....................................................................... 248

14.2 TRANSMIT LINK OUTPUT TIMING ................................................................ 249

14.3 PCI INTERFACE .............................................................................................. 250

14.4 BERT INTERFACE .......................................................................................... 258

15 ABSOLUTE MAXIMUM RATINGS................................................................................ 260

16 D.C. CHARACTERISTICS ............................................................................................ 261

17 FREEDM-8 TIMING CHARACTERISTICS ................................................................... 263

18 ORDERING AND THERMAL INFORMATION .............................................................. 269

19 MECHANICAL INFORMATION..................................................................................... 270

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LIST OF REGISTERS

ACCUMULATION TRIGGER .......................................................................................... 87

REGISTER 0X040 : GPIC CONTROL ......................................................................................... 98

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QUEUE START............................................................................................................. 142

QUEUE WRITE............................................................................................................. 143

QUEUE READ............................................................................................................... 144

QUEUE END ................................................................................................................. 145

QUEUE START............................................................................................................. 146

QUEUE WRITE............................................................................................................. 147

QUEUE READ............................................................................................................... 148

QUEUE END ................................................................................................................. 149

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REGISTER 0X500 : PMON STATUS......................................................................................... 206

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LIST OF FIGURES

FIGURE 1 – HDLC FRAME ......................................................................................................... 33

FIGURE 2 – CRC GENERATOR ................................................................................................. 33

FIGURE 3 – PARTIAL PACKET BUFFER STRUCTURE ............................................................ 37

FIGURE 4 – RECEIVE PACKET DESCRIPTOR ......................................................................... 39

FIGURE 5 – RECEIVE PACKET DESCRIPTOR TABLE............................................................. 42

FIGURE 6 – RPDRF AND RPDRR QUEUES.............................................................................. 44

FIGURE 7 – RPDRR QUEUE OPERATION................................................................................ 46

FIGURE 8 – RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE................................... 47

FIGURE 9 – GPIC ADDRESS MAP............................................................................................. 53

FIGURE 10 – TRANSMIT DESCRIPTOR.................................................................................... 55

FIGURE 11 – TRANSMIT DESCRIPTOR TABLE........................................................................ 58

FIGURE 12 – TDRR AND TDRF QUEUES ................................................................................. 60

FIGURE 13 – TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE .............................. 62

FIGURE 14 – TD LINKING .......................................................................................................... 65

FIGURE 15 – PARTIAL PACKET BUFFER STRUCTURE .......................................................... 68

FIGURE 16 – INPUT OBSERVATION CELL (IN_CELL) ........................................................... 238

FIGURE 17 – OUTPUT CELL (OUT_CELL).............................................................................. 239

FIGURE 18 – BI-DIRECTIONAL CELL (IO_CELL).................................................................... 239

FIGURE 19 – LAYOUT OF OUTPUT ENABLE AND BI-DIRECTIONAL CELLS....................... 240

FIGURE 20 – BOUNDARY SCAN ARCHITECTURE ................................................................ 242

FIGURE 21 – TAP CONTROLLER FINITE STATE MACHINE .................................................. 244

FIGURE 22 – UNCHANNELISED RECEIVE LINK TIMING ...................................................... 248

FIGURE 23 – CHANNELISED T1 RECEIVE LINK TIMING ...................................................... 248

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FIGURE 24 – CHANNELISED E1 RECEIVE LINK TIMING ...................................................... 249

FIGURE 25 – UNCHANNELISED TRANSMIT LINK TIMING.................................................... 249

FIGURE 26 – CHANNELISED T1 TRANSMIT LINK TIMING.................................................... 250

FIGURE 27 – CHANNELISED E1 TRANSMIT LINK TIMING.................................................... 250

FIGURE 28 – PCI READ CYCLE............................................................................................... 252

FIGURE 29 – PCI WRITE CYCLE............................................................................................. 253

FIGURE 30 – PCI TARGET DISCONNECT .............................................................................. 254

FIGURE 31 – PCI TARGET ABORT .......................................................................................... 254

FIGURE 32 – PCI BUS REQUEST CYCLE............................................................................... 255

FIGURE 33 – PCI INITIATOR ABORT TERMINATION ............................................................. 255

FIGURE 34 – PCI EXCLUSIVE LOCK CYCLE.......................................................................... 256

FIGURE 35 – PCI FAST BACK TO BACK ................................................................................. 258

FIGURE 36 – RECEIVE BERT PORT TIMING.......................................................................... 258

FIGURE 37 – TRANSMIT BERT PORT TIMING ....................................................................... 259

FIGURE 38 – RECEIVE LINK INPUT TIMING .......................................................................... 264

FIGURE 39 – BERT INPUT TIMING.......................................................................................... 264

FIGURE 40 – TRANSMIT LINK OUTPUT TIMING.................................................................... 265

FIGURE 41 – BERT OUTPUT TIMING...................................................................................... 266

FIGURE 42 – PCI INTERFACE TIMING.................................................................................... 267

FIGURE 43 – JTAG PORT INTERFACE TIMING...................................................................... 268

FIGURE 44 – 256 PIN ENHANCED BALL GRID ARRAY (SBGA)............................................. 270

FIGURE 45 – 272 PIN PLASTIC BALL GRID ARRAY (PBGA).................................................. 271

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LIST OF TABLES

TABLE 1 – LINE SIDE INTERFACE SIGNALS (36)......................................................................11

TABLE 2 – PCI HOST INTERFACE SIGNALS (51)..................................................................... 15

TABLE 3 – MISCELLANEOUS INTERFACE SIGNALS (12) ....................................................... 24

TABLE 4 – PRODUCTION TEST INTERFACE SIGNALS (30) ................................................... 25

TABLE 5 – DON’T CARE SIGNALS (58) ..................................................................................... 27

TABLE 6 – NO-CONNECT SIGNALS (9)..................................................................................... 29

TABLE 7 – POWER AND GROUND SIGNALS (60).................................................................... 30

TABLE 8 – RECEIVE PACKET DESCRIPTOR FIELDS .............................................................. 39

TABLE 9 – RPDRR QUEUE ELEMENT....................................................................................... 45

TABLE 10 – RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE FIELDS...................... 47

TABLE 11 – TRANSMIT DESCRIPTOR FIELDS......................................................................... 55

TABLE 12 – TRANSMIT DESCRIPTOR REFERENCE ............................................................... 61

TABLE 13 – TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE FIELDS ................... 62

TABLE 14 – NORMAL MODE PCI HOST ACCESSIBLE REGISTER MEMORY MAP ............... 72

TABLE 15 – PCI CONFIGURATION REGISTER MEMORY MAP............................................... 75

TABLE 16 – BIG ENDIAN FORMAT ............................................................................................ 99

TABLE 17 – LITTLE ENDIAN FORMAT....................................................................................... 99

TABLE 18 – CRC[1:0] SETTINGS ............................................................................................. 120

TABLE 19 – RPQ_RDYN[2:0] SETTINGS ................................................................................. 132

TABLE 20 – RPQ_LFN[1:0] SETTINGS .................................................................................... 133

TABLE 21 – RPQ_SFN[1:0] SETTINGS .................................................................................... 133

TABLE 22 – TDQ_RDYN[2:0] SETTINGS ................................................................................. 155

TABLE 23 – TDQ_FRN[1:0] SETTINGS .................................................................................... 155

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TABLE 24 – CRC[1:0] SETTINGS ............................................................................................. 175

TABLE 25 – FLAG[2:0] SETTINGS............................................................................................ 180

TABLE 26 – LEVEL[3:0]/TRANS SETTINGS............................................................................. 181

TABLE 27 – TEST MODE REGISTER MEMORY MAP............................................................. 227

TABLE 28 – INSTRUCTION REGISTER ................................................................................... 228

TABLE 29 – BOUNDARY SCAN CHAIN.................................................................................... 228

TABLE 30 – FREEDM–EQUAD CONNECTIONS ..................................................................... 241

TABLE 31 – FREEDM–TOCTL CONNECTIONS ...................................................................... 241

TABLE 32 – FREEDM-8 ABSOLUTE MAXIMUM RATINGS ..................................................... 260

TABLE 33 – FREEDM-8 D.C. CHARACTERISTICS ................................................................. 261

TABLE 34 – FREEDM-8 LINK INPUT (FIGURE 38, FIGURE 39) ............................................. 263

TABLE 35 – FREEDM-8 LINK OUTPUT (FIGURE 40, FIGURE 41) ......................................... 264

TABLE 36 – PCI INTERFACE (FIGURE 42).............................................................................. 266

TABLE 37 – JTAG PORT INTERFACE (FIGURE 43)................................................................ 267

TABLE 38 – FREEDM-8 ORDERING INFORMATION .............................................................. 269

TABLE 39 – FREEDM-8 THERMAL INFORMATION................................................................. 269

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1 FEATURES

· Single-chip Peripheral Component Interconnect (PCI) Bus multi-channel HDLC controller.

· Supports up to 128 bi-directional HDLC channels assigned to a maximum of 8 channelised T1

or E1 links. The number of time-slots assigned to an HDLC channel is programmable from 1 to 24 (for T1) and from 1 to 31 (for E1).

· Supports up to 8 bi-directional HDLC channels each assigned to an unchannelised arbitrary rate link; subject to a maximum aggregate link clock rate of 64 MHz in each direction. Channels assigned to links 0 to 2 can have a clock rate of up 52 MHz when SYSCLK is at 33 MHz. Channels assigned to links 3 to 7 can have a clock rate of up to 10 MHz.

· Supports up to two bi-directional HDLC Channels each assigned to an unchannelised arbitrary rate link of up to 52 MHz when SYSCLK is at 33 MHz.

· Supports a mix of up to 8 channelised and unchannelised links; subject to the constraint of a maximum of 128 channels and a maximum aggregate link clock rate of 64 MHz in each direction.

· For each channel, the HDLC receiver performs flag sequence detection, bit de-stuffing, and frame check sequence validation. The receiver supports the validation of both CRC-CCITT and CRC-32 frame check sequences. The receiver also checks for packet abort sequences, octet aligned packet length and for minimum and maximum packet length.

· Alternatively, for each channel, the receiver supports a transparent mode where each octet is transferred transparently to host memory. For channelised links, the octets are aligned with the receive time-slots.

· For each channel, time-slots are selectable to be in 56 kbits/s format or 64 kbits/s clear channel format.

· For each channel, the HDLC transmitter performs flag sequence generation, bit stuffing, and, optionally, frame check sequence generation. The transmitter supports the generation of both CRC-CCITT and CRC-32 frame check sequences. The transmitter also aborts packets under the direction of the host or automatically when the channel underflows.

· Supports two levels of non-preemptive packet priority on each transmit channel. Low priority packets will not begin transmission until all high priority packets are transmitted.

· Alternatively, for each channel, the transmitter supports a transparent mode where each octet is inserted transparently from host memory. For channelised links, the octets are aligned with the transmit time-slots.

· Directly supports a 32-bit, 33 MHz PCI 2.1 interface for configuration, monitoring and transfer of packet data, with an on-chip DMA controller with scatter/gather capabilities.

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· Provides 8 kbytes of on-chip memory for partial packet buffering in each direction. This memory can be configured to support a variety of different channel configurations from a single channel with 8 kbytes of buffering to 128 channels, each with a minimum of 48 bytes of buffering.

· Supports PCI burst sizes of up to 128 bytes for transfers of packet data.

· Pin compatible with PM7364 (FREEDM-32) device.

· Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.

· Supports 3.3 and 5 Volt PCI signaling environments.

· Low power CMOS technology.

· 256 pin enhanced ball grid array (SBGA) or 272 pin plastic ball grid array (PBGA) packages

(27 mm X 27 mm).

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2 APPLICATIONS

· IETF PPP interfaces for routers

· Frame Relay interfaces for ATM or Frame Relay switches and multiplexors

· FUNI or Frame Relay service inter-working interfaces for ATM switches and multiplexors.

· D-channel processing in ISDN terminals and switches.

· Internet/Intranet access equipment.

· Packet-based DSLAM equipment.

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3 REFERENCES

1. International Organization for Standardization, ISO Standard 3309-1993, "Information Technology - Telecommunications and information exchange between systems - High-level data link control (HDLC) procedures - Frame structure", December 1993.

2. RFC-1662 - "PPP in HDLC-like Framing" Internet Engineering Task Force, July 1994.

3. PCI Special Interest Group, PCI Local Bus Specification, June 1, 1995, Version 2.1.

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4 APPLICATION EXAMPLES

ACCESS SIDE

PM8313

DS3

D3MX

M13 Access Module

PM4314

QDSX

T1 Access Modu le

PM4314

QDSX

PM4388

TOCTL

PM4388

TOCTL

PM6344

EQUAD

PM7366 FREEDM

FREEDM-8

PCI Bus

Packet

Memory

Processor Module

Micro-

processor

HDLC BASED UPLINK SIDE

HSSI

Module

DS3/E3

Framer

LIU

HDLC Based

Uplink Module

HSSI

DS3/E3/J2

xDSL

E1 Access Module

ACCESS SIDE

XDSL

PHY

xDSL Access Module

PM7366

FREEDM-8

Packet

Memory

PM7322

RCMP

PCI Bus

SAR

Micro-

processor

ATM CELL BASED UPLINK SIDE

PM7345

S/UNI-PDH

DS-3/E3 ATM

PM5346

S/UNI-LITE

PM5348

S/UNI-DUAL

STS-3c ATM UNI

PM5347

S/UNI-PLUS

STS-3c ATM NNI

PM5355

S/UNI-622

T3/E3

OC-3

OC-12

Processor Module

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STS-12c ATM UNI/NNI

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5 BLOCK DIAGRAM

AD[31:0]

C/BEB[3:0]

PAR

TRDYB

IRDYB

STOPB

DEVSELB

IDSEL

LOCKB

GNTB

PERRB

SERRB

PCIINTB

PCICLK

PCICLKO

SYSCLK

PMCTEST

TDO

RSTB

FRAMEB

PCI

Controller

REQB

(GPIC)

TDI TCK TMS

JTAG Port

TRSTB

RBCLK

RBD

Receive

Controller

(RHDL)

Partial Packet Buffer

(RMAC)

(PMON)

Performance Monitor

Receive HDLC Processor

Transmit

Transmit HDLC Processor

Partial Packet Buffer

(TMAC)

Controller

(THDL)

TBCLK

ssigner

Channel

(RCAS)

Receive

Transmit

Channel

ssigner

(TCAS)

TBD

RD[7:0]

RCLK[7:0]

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TD[7:0]

TCLK[7:0]

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6 DESCRIPTION

The PM7366 FREEDM-8 Frame Engine and Datalink Manager device is a monolithic integrated circuit that implements HDLC processing, and PCI Bus memory management functions for a maximum of 128 bi-directional channels.

For channelised links, the FREEDM-8 allows up to 128 bi-directional HDLC channels to be assigned to individual time-slots within a maximum of 8 independently timed T1 or E1 links. The channel assignment supports the concatenation of time-slots (N x DS0) up to a maximum of 24 concatenated time-slots for a T1 link and 31 concatenated time-slots for an E1 link. Time-slots assigned to any particular channel need not be contiguous within the T1 or E1 link.

For unchannelised links, the FREEDM-8 processes up to 8 bi-directional HDLC channels within 8 independently timed links. The links can be of arbitrary frame format. When limited to two unchannelised links, each link can be rated at up to 52 MHz when SYSCLK is at 33 MHz. For lower rate unchannelised links, the FREEDM-8 processes up to 8 links, where the aggregate clock rate of all the links is limited to 64 MHz, links 0 to 2 can have a clock rate of up to 52 MHz when SYSCLK is at 33 MHz and links 3 to 7 can have a clock rate of up to 10 MHz. The FREEDM-8 also supports mixing of up to 8 channelised and unchannelised links. The total number of channels in each direction is limited to 128. The aggregate clock rate over all 8 possible links is limited to 64 MHz.

In the receive direction, the FREEDM-8 performs channel assignment and packet extraction and validation. For each provisioned HDLC channel, the FREEDM-8 delineates the packet boundaries using flag sequence detection, and performs bit de-stuffing. Sharing of opening and closing flags, as well as, sharing of zeros between flags are supported. The resulting packet data is placed into the internal 8 kbyte partial packet buffer RAM. The partial packet buffer acts as a logical FIFO for each of the assigned channels. Partial packets are DMA'd out of the RAM, across the PCI bus and into host packet memory. The FREEDM-8 validates the frame check sequence for each packet, and verifies that the packet is an integral number of octets in length and is within a programmable minimum and maximum length. The receive packet status is updated before linking the packet into a receive ready queue. The FREEDM-8 alerts the PCI Host that there are packets in a receive ready queue by, optionally, asserting an interrupt on the PCI bus.

Alternatively, in the receive direction, the FREEDM-8 supports a transparent operating mode. For each provisioned transparent channel, the FREEDM-8 directly transfers the received octets into host memory verbatim. If the transparent channel is assigned to a channelised link, then the octets are aligned to the received time-slots.

In the transmit direction, the PCI Host provides packets to transmit using a transmit ready queue. For each provisioned HDLC channel, the FREEDM-8 DMA's partial packets across the PCI bus and into the transmit partial packet buffer. The partial packets are read out of the packet buffer by the FREEDM-8 and frame check sequence is optionally calculated and inserted at the end of each packet. Bit stuffing is performed before being assigned to a particular link. The flag sequence is automatically inserted when there is no packet data for a particular channel. Sequential packets are optionally separated by two flags (an opening flag and a closing flag) or a single flag

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(combined opening and closing flag). Zeros between flags are not shared. PCI bus latency may cause one or more channels to underflow, in which case, the packets are aborted, and the host is notified. For normal traffic, an abort sequence is generated, followed by inter-frame time fill characters (flags or all-ones bytes) until a new packet is sourced from the PCI host. No attempt is made to automatically re-transmit an aborted packet.

Alternatively, in the transmit direction, the FREEDM-8 supports a transparent operating mode. For each provisioned transparent channel, the FREEDM-8 directly inserts the transmitted octets from host memory. If the transparent channel is assigned to a channelised link, then the octets are aligned to the transmitted time-slots. If a channel underflows due to excessive PCI bus latency, an abort sequence is generated, followed by inter-frame time fill characters (flags or all-ones bytes) to indicate idle channel. Data resumes immediately when the FREEDM-8 receives new data from the host.

The FREEDM-8 is configured, controlled and monitored using the PCI bus interface. The FREEDM-8 is implemented in low power CMOS technology, with TTL compatible inputs and outputs. The FREEDM-8 is available in two package options; a 256 pin enhanced ball grid array (SBGA) package, or a 272 pin plastic ball grid array (PBGA) package.

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7 PIN DIAGRAM

The PM7366-BI FREEDM-8 is manufactured in a 256 pin enhanced ball grid array (SBGA) package.

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

A VSS VSS VSS X X TA[2] TA[4] VSS TA[7] TA[9] VSS VSS X X X X X VSS VSS VSS A

B VSS VDD VDD X TA[0] X X X X X TA[ 10] X X X X X X VDD VDD VSS B

C VSS VDD VDD RD[7] X TA[1] X X TA[6] TA[8] X

D RD[5] RCLK[5] RCLK[6] EN5V RCLK[7] X VDD TA[3] TA[5] X VDD TRDB X VDD X PCICLKO VBIAS[2] GNTB AD[31] AD[30] D

E RD[3] RCLK[3] RCLK[4] RD[6] REQB AD[29] AD[27] AD[26] E

F RCLK[1] RD[2] RCLK [2] RD[4] AD[28] AD[25] AD[24] CBEB[3] F

G RBCLK RD[0] RD[1] VDD VDD IDSEL AD[22] AD[21] G

TA[11]/

TWRB X X X PCICLK VDD VDD VSS C

TRS

H VBIAS[1] SYSCLK RBD RCLK[0] AD[23] AD[20] AD[18] VSS H

J VSS TCK TMS TRSTB AD[19] AD[17] AD[16] CBEB[2] J

K VSS TDI TDO VDD FRAMEB IRDYB TRDYB DEVSELB K

BOTTOM VIEW

L TD[0] TCLK[0] TD[1] TCLK[1] VDD STOPB LOCKB VSS L

M TD[2] TCLK[2] TD[3] TD[4] CBEB[1] SERRB PERRB VSS M

N VSS TCLK[3] TCLK[4] TD[6] AD[11] AD[14] AD[15] PAR N

P TD[5] TCLK[5] TCLK[6] VDD VDD AD[10] AD[12] AD[13] P

R TD[7] TCLK[7] NC X AD[5] CBEB[0] AD[8] AD[9] R

T X NC NC X AD[1] AD[4] AD[6] AD[7] T

U X NC NC NC NC NC VDD X TDAT[5] VDD X TDAT[12] TDAT [14] VDD PMCTEST X VBIAS[3] AD[0] AD[2] AD[3] U

V VSS VDD VDD X X X TDAT[2] TDAT[4] TDAT[6] X TDAT[9] TDAT[11] X X TB D PCIINTB X VDD VDD VSS V

W VSS VDD VDD X X TDAT[1] TDAT[3] X X TDAT[7] X X X X X RSTB X VDD VDD VSS W

Y VSS VSS VSS NC TDAT[0] X X X VS S VSS TDAT[8] TDAT[10] VSS TDAT[13] TDAT[15] TBCLK X VSS VSS VSS Y

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 9

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PM7366 FREEDM-8

The PM7366-PI FREEDM-8 is manufactured in a 272 pin plastic ball grid array (PBGA) package.

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

A VSS NC NC X X X X X X TA[9] X X X TA[3] TA[2] X X NC NC VSS A

B NC VBIAS [2] NC PCICLK X X X TWRB

CNCNCVDDPCICLKOXXXXXXXXXXXXENV5VDDNCNCC

D AD[29] AD[31] GNTB VSS X VDD X VSS TRDB VDD TA[7] TA[5] VSS TA[0] VDD RD[7] VSS NC RCLK[6] RCLK[5] D

E AD[25] AD[28] AD[30] REQB RD[6] RD[5] RCLK[4] RD[4] E

F IDSEL AD[24] AD[27] VDD VDD RCLK[3] RCLK[2] RD[2] F

TA[11]/

TA[10] TA[8] TA[6] TA[4] X TA[1] X RCLK [7] NC NC NC B

TRS

BOTTOM VIEW

G AD[22] AD[23] CBEB[3] AD[26] RD[3] RCL K[1] RD[1] RCLK[0] G

H AD[19] AD[20] AD[21] VSS VSS RD[0] RBCLK R BD H

J CBEB[2] AD[1 6] AD[17] AD[18] VSS VSS VSS VSS SYSCLK TRSTB VBIA S[1] TMS J

K DEVSELB TRDYB IRDYB FRAMEB VSS VSS VS S VSS VDD TDI TCK T DO K

L STOPB PERRB LOCKB VDD VS S VSS VS S VSS TCLK[1] TD[1] TCLK[0] TD [0] L

M SERRB PAR CBEB[1] AD[15] VSS VSS VSS VSS TCLK[3] TD[3] TCLK[2] TD [2] M

N AD[14] AD[13] AD[12] VSS VSS TD[5] TCLK[4] TD[4] N

P AD[11] AD[10] AD[9] NC X TD[7] TD[6] TCLK[5] P

R AD[8] CBEB[0] AD[7] VDD VDD NC TCLK[7] TCLK[6] R

T AD[6] AD[5] AD[4] A D[2] XXXNCT

U AD[3] AD[0] AD[1] VSS X VDD RSTB VSS TDAT[12 ] TDAT[10] VDD TDAT[5] VSS X VDD X VSS NC NC NC U

V NC NC VDD NC X PMCTEST X X X X X X X TDAT[2] TDAT[0] X NC VDD NC NC V

W NC VBIAS[3] NC X PCINTB TBD X TDAT[13] TDAT[11] TDAT[9] TDAT[7] TDAT[6] TDAT[4] X TDAT[1] NC X NC NC NC W

Y VSS NC NC X TBCLK TD AT[15] TDAT[14] X X X TDAT[8] X X TDAT[3] X X NC NC NC VSS Y

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 10

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DATA SHEET

PMC-1970930 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER

PM7366 FREEDM-8

8 PIN DESCRIPTION

Table 1 – Line Side Interface Signals (36)

Pin Name Type

Pin No.

Function

-PI -BI

RCLK[0] RCLK[1] RCLK[2] RCLK[3] RCLK[4] RCLK[5] RCLK[6] RCLK[7]

Input G1

G3 F2 F3 E2 D1 D2 B4

H17 F20 F18 E19 E18 D19 D18 D16

The receive line clock signals (RCLK[7:0]) contain the recovered line clock for the 8 independently timed links. Processing of the receive links is on a priority basis, in descending order from RCLK[0] to RCLK[7]. Therefore, the highest rate link should be connected to RCLK[0] and the lowest to RCLK[7]. RD[7:0] is sampled on the rising edge of the corresponding RCLK[7:0] clock.

For channelised T1 or E1 links, RCLK[n] must be gapped during the framing bit (for T1 interfaces) or during time-slot 0 (for E1 interfaces) of the RD[n] stream. The FREEDM-8 uses the gapping information to determine the time-slot alignment in the receive stream. RCLK[7:0] is nominally a 50% duty cycle clock of 1.544 MHz for T1 links and 2.048 MHz for E1 links.

For unchannelised links, RCLK[n] must be externally gapped during the bits or time-slots that are not part of the transmission format payload (i.e. not part of the HDLC packet). RCLK[2:0] is nominally a 50% duty cycle clock between 0 and 52 MHz. RCLK[7:3] is nominally a 50% duty cycle clock between 0 and 10 MHz.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 11

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Pin No. Pin Name Type

Function

PM7366 FREEDM-8

-PI -BI

RD[0] RD[1] RD[2] RD[3] RD[4] RD[5] RD[6] RD[7]

Input H3

G2 F1 G4 E1 E3 E4 D5

G19 G18 F19 E20 F17 D20 E17 C17

The receive data signals (RD[7:0]) contain the recovered line data for the 8 independently timed links. Processing of the receive links is on a priority basis, in descending order form RD[0] to RD[7]. Therefore, the highest rate link should be connected to RD[0] and the lowest to RD[7].

For channelised links, RD[n] contains the 24 (T1) or 31 (E1) time-slots that comprise the channelised link. RCLK[n] must be gapped during the T1 framing bit position or the E1 frame alignment signal (time-slot

0). The FREEDM-8 uses the location of the gap to determine the channel alignment on RD[n].

For unchannelised links, RD[n] contains the HDLC packet data. For certain transmission formats, RD[n] may contain place holder bits or time-slots. RCLK[n] must be externally gapped during the place holder positions in the RD[n] stream. The FREEDM-8 supports a maximum data rate of 10 Mbit/s on an individual RD[7:3] link and a maximum data rate of 52 Mbit/s on RD[2:0].

RBD Tristate

H1 H18 The receive BERT data signal (RBD) contains the

Output

RBCLK Tristate

H2 G20 The receive BERT clock signal (RBCLK) contains the

Output

RD[7:0] is sampled on the rising edge of the corresponding RCLK[7:0] clock.

receive bit error rate test data. RBD reports the data on the selected one of the receive data signals (RD[7:0]) and is updated on the falling edge of RBCLK. RBD may be tri-stated by setting the RBEN bit in the FREEDM-8 Master BERT Control register low.

receive bit error rate test clock. RBCLK is a buffered version of the selected one of the receive clock signals (RCLK[7:0]). RBCLK may be tri-stated by setting the RBEN bit in the FREEDM-8 Master BERT Control register low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 12

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PMC-1970930 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER

Pin No. Pin Name Type

Function

PM7366 FREEDM-8

-PI -BI

TCLK[0] TCLK[1] TCLK[2] TCLK[3] TCLK[4] TCLK[5] TCLK[6] TCLK[7]

Input L2

L4 M2 M4 N2 P1 R1 R2

L19 L17 M19 N19 N18 P19 P18 R19

The transmit line clock signals (TCLK[7:0]) contain the transmit clocks for the 8 independently timed links. Processing of the transmit links is on a priority basis, in descending order from TCLK[0] to TCLK[7]. Therefore, the highest rate link should be connected to TCLK[0] and the lowest to TCLK[7]. TD[7:0] is updated on the falling edge of the corresponding TCLK[7:0] clock.

For channelised T1 or E1 links, TCLK[n] must be gapped during the framing bit (for T1 interfaces) or during time-slot 0 (for E1 interfaces) of the TD[n] stream. The FREEDM-8 uses the gapping information to determine the time-slot alignment in the transmit stream.

For unchannelised links, TCLK[n] must be externally gapped during the bits or time-slots that are not part of the transmission format payload (i.e. not part of the HDLC packet).

TCLK[7:3] is nominally a 50% duty cycle clock between 0 and 10 MHz. TCLK[2:0] is nominally a 50% duty cycle clock between 0 and 52 MHz. Typical values for TCLK[7:0] include 1.544 MHz (for T1 links) and 2.048 MHz (for E1 links).

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 13

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PMC-1970930 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER

Pin No. Pin Name Type

Function

PM7366 FREEDM-8

-PI -BI

TD[0] TD[1] TD[2] TD[3] TD[4] TD[5] TD[6] TD[7]

Output L1

L3 M1 M3 N1 N3 P2 P3

L20 L18 M20 M18 M17 P20 N17 R20

The transmit data signals (TD[7:0]) contains the transmit data for the 8 independently timed links. Processing of the transmit links is on a priority basis, in descending order from TD[0] to TD[7]. Therefore, the highest rate link should be connected to TD[0] and the lowest to TD[7].

For channelised links, TD[n] contains the 24 (T1) or 31 (E1) time-slots that comprise the channelised link. TCLK[n] must be gapped during the T1 framing bit position or the E1 frame alignment signal (time-slot

0). The FREEDM-8 uses the location of the gap to determine the channel alignment on TD[n].

For unchannelised links, TD[n] contains the HDLC packet data. For certain transmission formats, TD[n] may contain place holder bits or time-slots. TCLK[n] must be externally gapped during the place holder positions in the TD[n] stream. The FREEDM-8 supports a maximum data rate of 10 Mbit/s on an individual TD[7:3] link and a maximum data rate of 52 Mbit/s on TD[2:0]

TD[7:0] is updated on the falling edge of the corresponding TCLK[7:0] clock.

TBD Input W15 V6 The transmit BERT data signal (TBD) contains the

transmit bit error rate test data. When the TBERTEN bit in the BERT Control register is set high, the data on TBD is transmitted on the selected one of the transmit data signals (TD[7:0]). TBD is sampled on the rising edge of TBCLK.

TBCLK Tristate

Output

Y16 Y5 The transmit BERT clock signal (TBCLK) contains the

transmit bit error rate test clock. TBCLK is a buffered version of the selected one of the transmit clock signals (TCLK[7:0]). TBCLK may be tri-stated by setting the TBEN bit in the FREEDM-8 Master BERT Control register low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 14

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PMC-1970930 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER

PM7366 FREEDM-8

Table 2 – PCI Host Interface Signals (51)

Pin Name Type

Pin No.

Function

-PI -BI

PCICLK Input B17 C4 The PCI clock signal (PCICLK) provides timing for

PCI bus accesses. PCICLK is a nominally 50% duty cycle, 0 to 33 MHz clock.

PCICLKO Output C17 D5 The PCI clock output signal (PCICLKO) is a buffered

version of the PCICLK. PCICLKO may be used to drive the SYSCLK input.

AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[30]

I/O

U19 U18 T17 U20 T18 T19 T20 R18 R20 P18 P19 P20 N18 N19 N20 M17 J19 J18 J17 H20 H19 H18 G20 G19 F19 E20 G17 F18 E19 D20 E18

U3 T4 U2 U1 T3 R4 T2 T1 R2 R1 P3 N4 P2 P1 N3 N2 J2 J3 H2 J4 H3 G1 G2 H4 F2 F3 E1 E2 F4 E3 D1

The PCI address and data bus (AD[31:0]) carries the PCI bus multiplexed address and data. During the first clock cycle of a transaction, AD[31:0] contains a physical byte address. During subsequent clock cycles of a transaction, AD[31:0] contains data.

A transaction is defined as an address phase followed by one or more data phases. When Little-Endian byte formatting is selected, AD[31:24] contain the most significant byte of a DWORD while AD[7:0] contain the least significant byte. When Big-Endian byte formatting is selected. AD[7:0] contain the most significant byte of a DWORD while AD[31:24] contain the least significant byte. When the FREEDM-8 is the initiator, AD[31:0] is an output bus during the first (address) phase of a transaction. For write transactions, AD[31:0] remains an output bus for the data phases of the transaction. For read transactions, AD[31:0] is an input bus during the data phases.

When the FREEDM-8 is the target, AD[31:0] is an input bus during the first (address) phase of a transaction. For write transactions, AD[31:0] remains an input bus during the data phases of the transaction. For read transactions, AD[31:0] is an output bus during the data phases.

When the FREEDM-8 is not involved in the current transaction, AD[31:0] is tri-stated.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 15

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Pin No. Pin Name Type

Function

PM7366 FREEDM-8

-PI -BI

AD[31] I/O D19 D2 As an output bus, AD[31:0] is updated on the rising

edge of PCICLK. As an input bus, AD[31:0] is sampled on the rising edge of PCICLK.

C/BEB[0] C/BEB[1] C/BEB[2] C/BEB[3]

I/O R19

M18 J20 G18

R3 M4 J1 F1

The PCI bus command and byte enable bus (C/BEB[3:0]) contains the bus command or the byte valid indications. During the first clock cycle of a transaction, C/BEB[3:0] contains the bus command code. For subsequent clock cycles, C/BEB[3:0] identifies which bytes on the AD[31:0] bus carry valid data. C/BEB[3] is associated with byte 3 (AD[31:24]) while C/BEB[0] is associated with byte 0 (AD[7:0]). When C/BEB[n] is set high, the associated byte is invalid. When C/BEB[n] is set low, the associated byte is valid.

When the FREEDM-8 is the initiator, C/BEB[3:0] is an output bus.

When the FREEDM-8 is the target, C/BEB[3:0] is an input bus.

When the FREEDM-8 is not involved in the current transaction, C/BEB[3:0] is tri-stated.

As an output bus, C/BEB[3:0] is updated on the rising edge of PCICLK. As an input bus, C/BEB[3:0] is sampled on the rising edge of PCICLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 16

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Pin No. Pin Name Type

Function

PM7366 FREEDM-8

-PI -BI

PAR I/O M19 N1 The parity signal (PAR) indicates the parity of the

AD[31:0] and C/BEB[3:0] buses. Even parity is calculated over all 36 signals in the buses regardless of whether any or all the bytes on the AD[31:0] are valid. PAR always reports the parity of the previous PCICLK cycle. Parity errors detected by the FREEDM-8 are indicated on output PERRB and in the FREEDM-8 Interrupt Status register.

When the FREEDM-8 is the initiator, PAR is an output for writes and an input for reads.

When the FREEDM-8 is the target, PAR is an input for writes and an output for reads.

When the FREEDM-8 is not involved in the current transaction, PAR is tri-stated.

As an output signal, PAR is updated on the rising edge of PCICLK. As an input signal, PAR is sampled on the rising edge of PCICLK.

FRAMEB I/O K17 K4 The active low cycle frame signal (FRAMEB)

identifies a transaction cycle. When FRAMEB transitions low, the start of a bus transaction is indicated. FRAMEB remains low to define the duration of the cycle. When FRAMEB transitions high, the last data phase of the current transaction is indicated.

When the FREEDM-8 is the initiator, FRAMEB is an output.

When the FREEDM-8 is the target, FRAMEB is an input.

When the FREEDM-8 is not involved in the current transaction, FRAMEB is tri-stated.

As an output signal, FRAMEB is updated on the rising edge of PCICLK. As an input signal, FRAMEB is sampled on the rising edge of PCICLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 17

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PMC-1970930 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER

Pin No. Pin Name Type

Function

PM7366 FREEDM-8

-PI -BI

TRDYB I/O K19 K2 The active low target ready signal (TRDYB) indicates

when the target is ready to start or continue with a transaction. TRDYB works in conjunction with IRDYB to complete transaction data phases. During a transaction in progress, TRDYB is set high to indicate that the target cannot complete the current data phase and to force a wait state. TRDYB is set low to indicate that the target can complete the current data phase. The data phase is completed when TRDYB is set low and the initiator ready signal (IRDYB) is also set low.

When the FREEDM-8 is the initiator, TRDYB is an input.

When the FREEDM-8 is the target, TRDYB is an output. During accesses to FREEDM-8 registers, TRDYB is set high to extend data phases over multiple PCICLK cycles.

When the FREEDM-8 is not involved in the current transaction, TRDYB is tri-stated.

As an output signal, TRDYB is updated on the rising edge of PCICLK. As an input signal, TRDYB is sampled on the rising edge of PCICLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 18

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PMC-1970930 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER

Pin No. Pin Name Type

Function

PM7366 FREEDM-8

-PI -BI

IRDYB I/O K18 K3 The active low initiator ready (IRDYB) signal is used

to indicate whether the initiator is ready to start or continue with a transaction. IRDYB works in conjunction with TRDYB to complete transaction data phases. When IRDYB is set high and a transaction is in progress, the initiator is indicating it cannot complete the current data phase and is forcing a wait state. When IRDYB is set low and a transaction is in progress, the initiator is indicating it has completed the current data phase. The data phase is completed when IRDYB is set low and the target ready signal (IRDYB) is also set low.

When the FREEDM-8 is the initiator, IRDYB is an output.

When the FREEDM-8 is the target, IRDYB is an input.

When the FREEDM-8 is not involved in the current transaction, IRDYB is tri-stated.

IRDYB is updated on the rising edge of PCICLK or sampled on the rising edge of PCICLK depending on whether it is an output or an input.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 19

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PMC-1970930 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER

Pin No. Pin Name Type

Function

PM7366 FREEDM-8

-PI -BI

STOPB I/O L20 L3 The active low stop signal (STOPB) requests the

initiator to stop the current bus transaction. W hen STOPB is set high by a target, the initiator continues with the transaction. When STOPB is set low, the initiator will stop the current transaction.

When the FREEDM-8 is the initiator, STOPB is an input. When STOPB is sampled low, the FREEDM-8 will terminate the current transaction in the next PCICLK cycle.

When the FREEDM-8 is the target, STOPB is an output. The FREEDM-8 only issues transaction stop requests when responding to reads and writes to configuration space (disconnecting after 1 DW ORD transferred) or if an initiator introduces wait states during a transaction.

When the FREEDM-8 is not involved in the current transaction, STOPB is tri-stated.

STOPB is updated on the rising edge of PCICLK or sampled on the rising edge of PCICLK depending on whether it is an output or an input.

IDSEL Input F20 G3 The initialization device select signal (IDSEL) enables

read and write access to the PCI configuration registers. When IDSEL is set high during the address phase of a transaction and the C/BEB[3:0] code indicates a register read or write, the FREEDM-8 performs a PCI configuration register transaction and asserts the DEVSELB signal in the next PCICLK period.

IDSEL is sampled on the rising edge of PCICLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 20

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PMC-1970930 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER

Pin No. Pin Name Type

Function

PM7366 FREEDM-8

-PI -BI

DEVSELB I/O K20 K1 The active low device select signal (DEVSELB)

indicates that a target claims the current bus transaction. During the address phase of a transaction, all targets decode the address on the AD[31:0] bus. When a target, recognizes the address as its own, it sets DEVSELB low to indicate to the initiator that the address is valid. If no target claims the address in six bus clock cycles, the initiator assumes that the target does not exist or cannot respond and aborts the transaction.

When the FREEDM-8 is the initiator, DEVSELB is an input. If no target responds to an address in six PCICLK cycles, the FREEDM-8 will abort the current transaction and alerts the PCI Host via an interrupt.

When the FREEDM-8 is the target, DEVSELB is an output. DELSELB is set low when the address on AD[31:0] is recognised.

When the FREEDM-8 is not involved in the current transaction, DEVSELB is tri-stated.

FREEDM-8 is updated on the rising edge of PCICLK or sampled on the rising edge of PCICLK depending on whether it is an output or an input.

LOCKB Input L18 L2 The active low bus lock signal (LOCKB) locks a target

device. When LOCKB and FRAME are set low, and the FREEDM-8 is the target, an initiator is locking the FREEDM-8 as an "owned" target. Under these circumstances, the FREEDM-8 will reject all transaction with other initiators. The FREEDM-8 will continue to reject other initiators until its owner releases the lock by forcing both FRAMEB and LOCKB high. As a initiator, the FREEDM-8 will never lock a target.

LOCKB is sampled using the rising edge of PCICLK.

REQB Output E17 E4 The active low PCI bus request signal (REQB)

requests an external arbiter for control of the PCI bus. REQB is set low when the FREEDM-8 desires access to the host memory. REQB is set high when access is not desired.

REQB is updated on the rising edge of PCICLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 21

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DATA SHEET

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Pin No. Pin Name Type

Function

PM7366 FREEDM-8

-PI -BI

GNTB Input D18 D3 The active low PCI bus grant signal (GNTB) indicates

the granting of control over the PCI in response to a bus request via the REQB output. When GNTB is set high, the FREEDM-8 does not have control over the PCI bus. When GNTB is set low, the external arbiter has granted the FREEDM-8 control over the PCI bus. However, the FREEDM-8 will not proceed until the FRAMEB signal is sampled high, indicating no current transactions are in progress.

GNTB is sampled on the rising edge of PCICLK.

PCIINTB OD

Output

W16 V5 The active low PCI interrupt signal (PCIINTB) is set

low when a FREEDM-8 interrupt source is active, and that source is unmasked. The FREEDM-8 may be enabled to report many alarms or events via interrupts. PCIINTB returns high when the interrupt is acknowledged via an appropriate register access.

PCIINTB is an open drain output and is updated on the rising edge of PCICLK.

PERRB I/O L19 M2 The active low parity error signal (PERRB) indicates a

parity error over the AD[31:0] and C/BEB[3:0] buses. Parity error is signalled when even parity calculations do not match the PAR signal. PERRB is set low at the cycle immediately following an offending PAR cycle. PERRB is set high when no parity error is detected.

PERRB is enabled by setting the PERREN bit in the Control/Status register in the PCI Configuration registers space. Regardless of the setting of PERREN, parity errors are always reported by the PERR bit in the Control/Status register in the PCI Configuration registers space.

PERRB is updated on the rising edge of PCICLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 22

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PMC-1970930 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER

Pin No. Pin Name Type

Function

PM7366 FREEDM-8

-PI -BI

SERRB OD

Output

M20 M3 The active low system error signal (SERRB) indicates

an address parity error. Address parity errors are detected when the even parity calculations during the address phase do not match the PAR signal. When the FREEDM-8 detects a system error, SERRB is set low for one PCICLK period.

SERRB is enabled by setting the SERREN bit in the Control/Status register in the PCI Configuration registers space. Regardless of the setting of SERREN, parity errors are always reported by the SERR bit in the Control/Status register in the PCI Configuration registers space.

SERRB is an open drain output and is updated on the rising edge of PCICLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 23

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DATA SHEET

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PM7366 FREEDM-8

Table 3 – Miscellaneous Interface Signals (12)

Pin Name Type

Pin No.

Function

-PI -BI

SYSCLK Input J4 H19 The system clock (SYSCLK) provides timing for the

core logic. SYSCLK is nominally a 50% duty cycle 25 MHz to 33 MHz clock.

RSTB Input U14 W5 The active low reset signal (RSTB) signal provides an

asynchronous FREEDM-8 reset. RSTB is an asynchronous input. When RSTB is set low, all FREEDM-8 registers are forced to their default states. In addition, TD[7:0] are forced high and all PCI output pins are forced tri-state and will remain high or tri-stated, respectively, until RSTB is set high.

PMCTEST Input V15 U6 The PMC production test enable signal (PMCTEST)

places the FREEDM-8 is test mode. When PMCTEST is set high, production test vectors can be executed to verify manufacturing via the test mode interface signals TA[10:0], TA[11]/TRS, TRDB, TWRB and TDAT[15:0]. PMCTEST must be tied low in normal operation.

TCK Input K2 J19 The test clock signal (TCK) provides timing for test

operations that can be carried out using the IEEE P1149.1 test access port. TMS and TDI are sampled on the rising edge of TCK. TDO is updated on the falling edge of TCK.

TMS Input J1 J18 The test mode select signal (TMS) controls the test

operations that can be carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull up resistor.

TDI Input K3 K19 The test data input signal (TDI) carries test data into

the FREEDM-8 via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK.

TDI has an integral pull up resistor.

TDO Tristate

Output

K1 K18 The test data output signal (TDO) carries test data

out of the FREEDM-8 via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tri-state output which is inactive except when scanning of data is in progress.

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Function

PM7366 FREEDM-8

-PI -BI

TRSTB Input J3 J17 The active low test reset signal (TRSTB) provides an

asynchronous FREEDM-8 test access port reset via the IEEE P1149.1 test access port. TRSTB is an asynchronous input with an integral pull up resistor.

Note that when TRSTB is not being used, it must be connected to the RSTB input.

VBIAS[3:1] Input J2

B19 W19

U4 D4 H20

The bias signals (VBIAS[3:1]) provide 5 Volt bias to input and I/O pads to allow the FREEDM-8 to tolerate connections to 5 Volt devices. To avoid damage to the device, the VBIAS[3:1] signals must be connected together externally and must at all times be kept at a voltage that is equal to or higher than the VDD[28:1] power supplies. In a 3.3V operating environment, VBIAS[3:1] and VDD[28:1] may be connected together. In a 5V operating environment, VBIAS[3:1] should be powered up to 5V before VDD[28:1] are powered up to 3.3V.

EN5V Input C4 D17 The 5 Volt PCI signalling enable signal (EN5V)

causes the PCI Host Interface Signals to operate in the 5V PCI signalling environment when set high and the 3.3V PCI signalling environment when set low. EN5V is an asynchronous input with an integral pull up resistor.

Table 4 – Production Test Interface Signals (30)

Pin Name Type

Pin No.

Function

-PI -BI

TA[0] TA[1] TA[2] TA[3] TA[4] TA[5] TA[6] TA[7] TA[8] TA[9] TA[10]

Input D7

B6 A6 A7 B8 D9 B9 D10 B10 A11 B11

B16 C15 A15 D13 A14 D12 C12 A12 C11 A11 B10

The test mode address bus (TA[10:0]) selects specific registers during production test (PMCTEST set high) read and write accesses.

In normal operation (PMCTEST set low), TA[10:0] should be tied high.

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Function

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-PI -BI

TA[11]/TRS Input B12 C9 The test register select signal (TA[11]/TRS) selects

between normal and test mode register accesses during production test (PMCTEST set high). TRS is set high to select test registers and is set low to select normal registers.

In normal operation (PMCTEST set low), TA[11]/ TRS should be tied high.

TRDB Input D12 D9 The test mode read enable signal (TRDB) is set low

during FREEDM-8 register read accesses during production test (PMCTEST set high). The FREEDM8 drives the test data bus (TDAT[15:0]) with the contents of the addressed register while TRDB is low.

In normal operation (PMCTEST set low), TRDB should be tied high.

TWRB Input B13 C8 The test mode write enable signal (TWRB) is set low

during FREEDM-8 register write accesses during production test (PMCTEST set high). The contents of the test data bus (TDAT[15:0]) are clocked into the addressed register on the rising edge of TWRB.

In normal operation (PMCTEST set low), TWRB should be tied high.

TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15]

I/O

V6 W6 V7 Y7 W8 U9 W9 W10 Y10 W11 U11 W12 U12 W13 Y14 Y15

Y16 W15 V14 W14 V13 U12 V12 W11 Y10 V10 Y9 V9 U9 Y7 U8 Y6

The bi-directional test mode data bus (TDAT[15:0]) carries data read from or written to FREEDM-8 registers during production test.

In normal operation (PMCTEST set low), TDAT[15:0] should be left unconnected.

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Table 5 – Don’t Care Signals (58)

Pin Name Type

Pin No.

Function

-PI -BI

X Input A4

A5 A8 A9 A10 A12 A13 A14 A15 A16 A17 B5 B7 B14 B15 B16 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D14 D16 P4 T2 T3 T4 U5 U7 U16 V5

B17 C16 B7 C7 B6 A5 D6 A4 V4 W4 T20 R17 U20 T17 V17 W17 V16 W16 V15 Y15 U13 Y14 W13 Y13 W12 V11 W10 U10 W9 W8 V8 W7 V7 W6 A17 D15 A16 B15

The Don't Care pins X may be connected to logic high or logic low arbitrarily. Optionally, they may be left floating.

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Function

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-PI -BI

X Input V8

V9 V10 V11 V12 V13 V14 V16 W4 W7 W14 W17 Y5 Y6 Y8 Y9 Y11 Y12 Y13 Y17

C14 B14 C13 B13 B12 D11 B11 C10 B9 A8 B8 A7 D8 A6 C6 B5 C5 B4 U5 Y4

The Don't Care pins X may be connected to logic high or logic low arbitrarily. Optionally, they may be left floating.

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Table 6 – No-Connect Signals (9)

Pin Name Type

Pin No.

Function

-PI -BI

NC Open A2

A3 A18 A19 B1 B2 B3 B18 B20

U17 R18 T19 T18 U19 U18 U16 Y17 U15

The No-Connect pins NC must be left unconnected.

C1 C2 C19 C20 D3 P17 R3 T1 U1 U2 U3 V1 V2 V4 V17 V19 V20 W1 W2 W3 W5 W18 W20 Y2 Y3 Y4 Y18 Y19

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Table 7 – Power and Ground Signals (60)

Pin Name Type

Pin No.

Function

-PI -BI

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28

Power

C3 C18 D6 D11 D15 F4 F17 K4 L17 R4 R17 U6 U10 U15 V3 V18

B2 B3 B18 B19 C2 C3 C18 C19 D7 D10 D14 G4 G17 K17 L4 P4 P17 U7 U11 U14 V2 V3 V18 V19 W2 W3 W18 W19

The DC power pins should be connected to a well decoupled +3.3 V DC supply.

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Pin No. Pin Name Type

Function

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-PI -BI

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32

Ground

A1 A20 D4 D8 D13 D17 H4 H17 J9 J10 J11 J12 K9 K10 K11 K12 L9 L10 L11 L12 M9 M10 M11 M12 N4 N17 U4 U8 U13 U17 Y1 Y20

A1 A2 A3 A9 A10 A13 A18 A19 A20 B1 B20 C1 C20 H1 J20 K20 L1 M1 N20 V1 V20 W1 W20 Y1 Y2 Y3 Y8 Y11 Y12 Y18 Y19 Y20

The DC ground pins should be connected to ground.

Notes on Pin Description:

1. All FREEDM-8 inputs and bi-directionals present minimum capacitive loading and operate at TTL compatible logic levels. PCI signals conform to the 3.3 or 5 Volt signaling environment depending on the setting of the EN5V input.

2. Most FREEDM-8 non-PCI digital outputs and bi-directionals have 4 mA drive capability, except the PCICLKO, RBCLK, TBCLK, RBD and PCIINTB outputs which have 6 mA drive capability and the TD[0], TD[1], and TD[2] outputs which have 8 mA drive capability.

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3. All FREEDM-8 non-PCI digital outputs and bi-directionals are 5 V tolerant when tristated except those with 8 mA drive capability, i.e. TD[2:0]. (TD[2:0] are never tristated in normal operation – only under JTAG boundary scan control.)

4. Inputs TMS, TDI, TRSTB and EN5V are Schmitt triggered and have internal pull-up resistors.

5. Inputs RD[7:0], RCLK[7:0], TCLK[7:0], SYSCLK, PCICLK, TBD, RSTB, GNTB, IDSEL, LOCKB, TCK and PMCTEST are Schmitt triggered.

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9 FUNCTIONAL DESCRIPTION

9.1 High-Level Data Link Control Protocol

Figure 1 shows a diagram of the synchronous HDLC protocol supported by the FREEDM-8. The incoming stream is examined for flag bytes (01111110 b i t patte r n ) w h i c h d e l i neate the opening and closing of the HDLC packet. The packet is bit de-stuffed which discards a "0" bit which directly follows five contiguous "1" bits. The resulting HDLC packet size must be a multiple of an octet (8 bits) and within the expected minimum and maximum packet length limits. The minimum packet length is that of a packet containing two information bytes (address and control) and FCS bytes. For packets with CRC-CCITT as FCS, the minimum packet length is four bytes while those with CRC-32 as FCS, the minimum length is six bytes. An HDLC packet is aborted when seven contiguous "1" bits (with no inserted "0" bits) are received. At least one flag byte must exist between HDLC packets for delineation. Contiguous flag bytes, or all ones bytes between packets are used as an "inter-frame time fill". Adjacent flag bytes may share zeros.

Figure 1 – HDLC Frame

Flag Information FCS Flag

HDLC Packet

Flag

The CRC algorithm for the frame checking sequence (FCS) field is either a CRC-CCITT or CRC32 function. Figure 2 shows a CRC encoder block diagram using the generating polynomial g(X)

= 1 + g1X + g2X2 +…+ g

n-1

+ Xn. The CRC-CCITT FCS is two bytes in size and has a

generating polynomial g(X) = 1 + X5 + X12 + X16. The CRC-32 FCS is four bytes in size and has a generating polynomial g(X) = 1 + X + X2 + X4 + X5 + X7 + X8 + X10 + X11 + X12 + X16 + X22 + X23 + X26 + X32. The first FCS bit received is the residue of the highest term.

Figure 2 – CRC Generator

n-1

Message

LSB MSB

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9.2 Receive Channel Assigner

The Receive Channel Assigner block (RCAS) processes up to 8 serial links. Each link is independent and has its own associated clock. For each link, the RCAS performs a serial to parallel conversion to form data bytes. The data bytes are multiplexed, in byte serial format, for delivery to the Receive HDLC Processor / Partial Packet Buffer block (RHDL) at SYSCLK rate. In the event where multiple streams have accumulated a byte of data, multiplexing is performed on a fixed priority basis with link #0 having the highest priority and link #7 the lowest.

Links containing a T1 or an E1 stream may be channelised. Data at each time-slot may be independently assigned to a different channel. The RCAS performs a table lookup to associate the link and time-slot identity with a channel. T1 and E1 framing bits/bytes are identified by observing the gap in the link clock which is squelched during the framing bits/bytes. For unchannelised links, clock rates are limited to 52 MHz on link #0 to #2 and limited to 10 MHz for the remaining links. All data on each link belongs to one channel. For the case of two unchannelised links, the maximum link rate is 52 MHz for SYSCLK at 33 MHz. For the case of more numerous unchannelised links or a mixture of channelise with unchannelised links, the total instantaneous link rate over all the links is limited to 64 MHz. The RCAS performs a table lookup using only the link number to determine the associated channel, as time-slots are non-existent in unchannelised links.

The RCAS provides diagnostic loopback that is selectable on a per channel basis. When a channel is in diagnostic loopback, stream data on the received links originally destined for that channel is ignored. Transmit data of that channel is substituted in its place.

9.2.1 Line Interface

There are 8 identical line interface blocks in the RCAS. Each line interface contains a bit counter, an 8-bit shift register and a holding register, that, together, perform serial to parallel conversion. Whenever the holding register is updated, a request for service is sent to the priority encoder block. When acknowledged by the priority encoder, the line interface would respond with the data residing in the holding register.

To support channelised links, each line interface block contains a time-slot counter and a clock activity monitor. The time-slot counter is incremented each time the holding register is updated. The clock activity monitor is a counter that increments at the system clock (SYSCLK) rate and is cleared by a rising edge of the receive clock (RCLK[n]). A framing bit (T1) or framing byte (E1) is detected when the counter reaches a programmable threshold. In which case, the bit and timeslot counters are initialised to indicate that the next bit is the most significant bit of the first timeslot. For unchannelised links, the time-slot counter and the clock activity monitor are held reset.

9.2.2 Priority Encoder

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Thus, simultaneous requests from RD[m] will be serviced ahead of RD[n], if m < n. When there are no pending requests, the priority encoder generates an idle cycle. In addition, once every fourth SYSCLK cycle, the priority encoder inserts a null cycle where no requests are serviced. This cycle is used by the channel assigner downstream for host microprocessor accesses to the provisioning RAMs.

9.2.3 Channel Assigner

The channel assigner block determines the channel number of the data byte currently being processed. The block contains a 256 word channel provision RAM. The address of the RAM is constructed from concatenating the link number and the time-slot number of the current data byte. The fields of each RAM word include the channel number and a time-slot enable flag. The timeslot enable flag labels the current time-slot as belonging to the channel indicted by the channel number field.

9.2.4 Loopback Controller

The loopback controller block implements the channel based diagnostic loopback function. Every valid data byte belonging to a channel with diagnostic loopback enabled from the Transmit HDLC Processor / Partial Packet Buffer block (THDL) is written into a 64 word FIFO. The loopback controller monitors for an idle time-slot or a time-slot carrying a channel with diagnostic loopback enabled. If either conditions hold, the current data byte is replaced by data retrieved from the loopback data FIFO.

9.3 Receive HDLC Processor / Partial Packet Buffer

The Receive HDLC Processor / Partial Packet Buffer block (RHDL) processes up to 128 synchronous transmission HDLC data streams. Each channel can be individually configured to perform flag sequence detection, bit de-stuffing and CRC-CCITT or CRC-32 verification. The packet data is written into the partial packet buffer. At the end of a frame, packet status including CRC error, octet alignment error and maximum length violation are also loaded into the partial packet buffer. Alternatively, a channel can be provisioned as transparent, in which case, the HDLC data stream is passed to the partial packet buffer processor verbatim.

There is a natural precedence in the alarms detectable on a receive packet. Once a packet exceeds the programmable maximum packet length, no further processing is performed on it. Thus, octet alignment detection, FCS verification and abort recognition are squelched on packets with a maximum length violation. An abort indication squelches octet alignment detection, minimum packet length violations, and FCS verification. In addition, FCS verification is only performed on packets that do not have octet alignment errors, in order to allow the RHDL to perform CRC calculations on a byte-basis.

The partial packet buffer is an 8 Kbyte RAM that is divided into 16-byte blocks. Each block has an associated pointer which points to another block. A logical FIFO is created for each provisioned channel by programming the block pointers to form a circular linked list. A channel FIFO can be assigned a minimum of 3 blocks (48 bytes) and a maximum of 512 blocks (8 Kbytes). The depth

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of the channel FIFOs are monitored in a round-robin fashion. Requests are made to the Receive DMA Controller block (RMAC) to transfer, to the PCI host memory, data in channel FIFOs with depths exceeding their associated threshold.

9.3.1 HDLC Processor

The HDLC processor is a time-slice state machine which can process up to 128 independent channels. The state vector and provisioning information for each channel is stored in a RAM. Whenever new channel data arrives, the appropriate state vector is read from the RAM, processed and written back to the RAM. The HDLC state-machine can be configured to perform flag delineation, bit de-stuffing, CRC verification and length monitoring. The resulting HDLC data and status information is passed to the partial packet buffer processor to be stored in the appropriate channel FIFO buffer.

The configuration of the HDLC processor is accessed using indirect channel read and write operations. When an indirect operation is performed, the information is accessed from RAM during a null clock cycle generated by the upstream Receive Channel Assigner block (RCAS). Writing new provisioning data to a channel resets the channel's entire state vector.

9.3.2 Partial Packet Buffer Processor

The partial packet buffer processor controls the 8 Kbyte partial packet RAM which is divided into 16 byte blocks. A block pointer RAM is used to chain the partial packet blocks into circular channel FIFO buffers. Thus, non-contiguous sections of the RAM can be allocated in the partial packet buffer RAM to create a channel FIFO. System software is responsible for the assignment of blocks to individual channel FIFOs. Figure 3 shows an example of three blocks (blocks 1, 3, and 200) linked together to form a 48 byte channel FIFO.

The partial packet buffer processor is divided into three sections: writer, reader and roamer. The writer is a time-sliced state machine which writes the HDLC data and status information from the HDLC processor into a channel FIFO in the packet buffer RAM. The reader transfers channel FIFO data from the packet buffer RAM to the downstream Receive DMA Controller block (RMAC). The roamer is a time-sliced state machine which tracks channel FIFO buffer depths and signals the reader to service a particular channel. If a buffer over-run occurs, the writer ends the current packet from the HDLC processor in the channel FIFO with an over-run flag and ignores the rest of the packet.

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Figure 3 – Partial Packet Buffer Structure

Block 0

Block 1

Block 2

Block 3

Partial Packet

Buffer RAM

16 bytes

Block 0

Block 1

Block 2

Block 3

Block

Pointer RAM

0x03

0xC8

Block 511

16 bytes

Block 200Block 200

Block 511

0x01

The FIFO algorithm of the partial packet buffer processor is based on a programmable perchannel transfer size. Instead of tracking the number of full blocks in a channel FIFO, the processor tracks the number of transactions. Whenever the partial packet writer fills a transfersized number of blocks or writes an end-of-packet flag to the channel FIFO, a transaction is created. Whenever the partial packet reader transmits a transfer-size number of blocks or an end-of-packet flag to the RMAC block, a transaction is deleted. Thus, small packets less than the transfer size will be naturally transferred to the RMAC block without having to precisely track the number of full blocks in the channel FIFO.

The partial packet roamer performs the transaction accounting for all channel FIFOs. The roamer increments the transaction count when the writer signals a new transaction and sets a perchannel flag to indicate a non-zero transaction count. The roamer searches the flags in a roundrobin fashion to decide for which channel FIFO to request transfer by the RMAC block. The roamer informs the partial packet reader of the channel to process. The reader transfers the data to the RMAC until the channel transfer size is reached or an end of packet is detected. The reader then informs the roamer that a transaction is consumed. The roamer updates its transaction count and clears the non-zero transaction count flag if required. The roamer then services the next channel with its transaction flag set high.

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The writer and reader determine empty and full FIFO conditions using flags. Each block in the partial packet buffer has an associated flag. The writer sets the flag after the block is written and the reader clears the flag after the block is read. The flags are initialized (cleared) when the block pointers are written using indirect block writes. The writer declares a channel FIFO overrun whenever the writer tries to store data to a block with a set flag. In order to support optional removal of the FCS from the packet data, the writer does not declare a block as filled (set the block flag nor increment the transaction count) until the first double word of the next block in channel FIFO is filled. If the end of a packet resides in the first double word, the writer declares both blocks as full at the same time. When the reader finishes processing a transaction, it examines the first double word of the next block for the end-of-packet flag. If the first double word of the next block contains only FCS bytes, the reader would, optionally, process next transaction (end-of-packet) and consume the block, as it contains information not transferred to the RMAC block.

9.4 Receive DMA Controller

The Receive DMA Controller block (RMAC) is a DMA controller which stores received packet data in host computer memory. The RMAC is not directly connected to the host memory PCI bus. Memory accesses are serviced by a downstream PCI controller block (GPIC). The RMAC and the host exchange information using receive packet descriptors (RPDs). The descriptor contains the size and location of buffers in host memory and the packet status information associated with the data in each buffer. RPDs are transferred from the RMAC to the host and vice versa using descriptor reference queues. The RMAC maintains all the pointers for the operation of the queues. The RMAC provides two receive packet descriptor reference (RPDR) free queues to support small and large buffers. The RMAC acquires free buffers by reading RPDRs from the free queues. After a packet is received, the RMAC places the associated RPDR onto a RPDR ready queue. To minimise host bus accesses, the RMAC maintains a descriptor reference table to store current DMA information. This table contains separate DMA information entries for up to 128 receive channels.

9.4.1 Data Structures

For packet data, the RMAC communicates with the host using Receive Packet Descriptors (RPD), Receive Packet Descriptor References (RPDR), the Receive Packet Descriptor Reference Ready (RPDRR) queue and the Receive Packet Descriptor Reference Small and Large Buffer Free (RPDRF) queues.

The RMAC copies packet data to data buffers in host memory. The RPD, RPDR, RPDRR queue, and Small and Large RPDRF queues are data structures which are used to transfer host memory data buffer information. All five data structures are manipulated by both the RMAC and the host computer. The RPD holds the data buffer size, data buffer address, and packet status information. The RPDR is a pointer which is used to index into a table of RPDs. The RPDRR queue and RPDRF queues allow the RMAC and the host to pass RPDRs back and forth. These data structures are described in more detail in the following sections.

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Receive Packet Descriptor

The Receive Packet Descriptors (RPDs) pass buffer and packet information between the RMAC and the host. Both the RMAC and the host read and write information in the RPDs. The host writes RPD fields which describe the size and address of data buffers in host memory. The RMAC writes RPD fields which provide number of bytes used in each data buffer, RPD link information, and the status of the received packet. RPDs are stored in host memory in a Receive Packet Descriptor Table which is described in a later section. The Receive Packet Descriptor structure is shown in Figure 4.

Figure 4 – Receive Packet Descriptor

0 Bit 31

Data Bu ffer St art Address [31: 0]

Bytes In Buffer [15: 0]

Reserved (18)

Status [5:0 ] RCC [6:0 ]

Offset[1:0]

Next RPD Pointer [13:0]

Reserved (16)

Receive Buffer Size [15:0]

Table 8 – Receive Packet Descriptor Fields

Field Description

Data Buffer Start Address[31:0]

The Data Buffer Start Address[31:0] bits point to the data buffer in host memory. This field is expected to be configured by the Host during initialisation.

The Data Buffer Start Address field is valid in all RPDs.

RCC[6:0] The Receive Channel Code (RCC[6:0]) bits are used by the RMAC to

indicate which channel an RPD is associated with.

For a linked list of RPDs, all the RPDs’ RCC fields are valid, i.e. all contain the same channel value.

CE The Chain End (CE) bit indicates the end of a linked list of RPDs.

When CE is set to logic one, the current RPD is the last RPD of a linked list of RPDs. When CE is set to logic zero, the current RPD is not the last RPD of a linked list.

The CE bit is valid for all RPDs written by the RMAC to the Receive Ready Queue. When a packet requires only one RPD, the CE bit is set to logic one. The CE bit is ignored for all RPDs read by the RMAC from the Receive Free Queues, each of which is assumed to point to only one buffer, i.e. not a chain.

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Field Description

Offset[1:0] The Offset[1:0] bits indicate the byte offset of the data packet from the

start of the buffer. If this value is non-zero, there will be ‘dummy’ (i.e. undefined) bytes at the start of the data buffer prior to the packet data proper.

For a linked list of RPDs, only the first RPD's Offset field is valid. All other RPD Offset fields of the linked list are set to 0.

Status [5:0] The Status[5:0] bits indicate the status of the received packet.

Status[0] Rx buffer overrun Status[1] Packet exceeds max. allowed size Status[2] CRC error Status[3] Packet Length not an exact no. of bytes Status[4] HDLC abort detected Status[5] Unused (set to 0)

For a linked list of RPDs, only the last RPD's Status field is valid. All other RPD Status fields of the linked list are invalid and should be ignored. When a packet requires only one RPD, the Status field is valid.

Bytes in Buffer [15:0] The Bytes in Buffer[15:0] bits indicate the number of bytes actually

used in the current RPD's data buffer to store packet data. The count excludes the 'dummy' bytes inserted as a result of a non-zero Offset field. A count greater than 32767 bytes indicates a packet that is shorter than the expected length of the FCS field.

The Bytes in Buffer field is invalid when Status[0] or Status[4] is asserted .

Next RPD Pointer [13:0]

The Next RPD Pointer[13:0] bits store a RPDR which enables the RMAC to support linked lists of RPDs. This field, which is only valid when CE is equal to logic zero, contains the RPDR to the next RPD in a linked list. The RMAC links RPDs when more than one buffer is needed to store a packet.

The Next RPD Pointer is not valid for the last RPD in a linked list (when CE=1). When a packet requires only one RPD, the Next RPD Pointer field is not valid.

Receive Buffer Size [15:0]

The Receive Buffer Size[15:0] bits indicate the size in bytes of the current RPD's data buffer. This field is expected to be configured by the Host during initialisation. The Receive Buffer Size must be a nonzero integer multiple of 16 and less than or equal to 32752.

The Receive Buffer Size field is valid in all RPDs.

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The Receive Buffer Size and Data Buffer Start Address fields are written only by the host. The RMAC reads these fields to determine where to store packet data. All other fields are written only by the RMAC.

Receive Packet Descriptor Table

The Receive Packet Descriptor Table resides in host memory and stores all the RPDs. The RPD Table can contain a maximum of 16384 RPDs. The base of the RPD table is user programmable using the Rx Packet Descriptor Table Base (RPDTB) register. The table is indexed by a Receive Packet Descriptor Reference (RPDR) which is a 14-bit pointer defining the offset of a RPD from the table base. Thus, as shown in the following diagram, a RPD can be located by adding the RPDR to the Rx Packet Descriptor Table Base register.

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Figure 5 – Receive Packet Descriptor Table

RPDTB[31:4] = Rx Packet Descriptor Table Base register

RPDR[13:0] = Receive Packet Desriptor Reference

RPD_ADDR[31:0] = Receive Packet Descriptor Address

Bit 31 Bit 0

RPDTB[31:4]

0000

RPDR[13:0]

0000

RPD_ADDR[31:0]

RPDTB

Bit 0Bit 31

Dword 0

RPD 1

RPD_ADDR

Dword 1 Dword 2 Dword 3 Dword 0

RPD 2

Dword 3

Dword 0

RPD 16384

Dword 3

The Receive Packet Descriptor Table resides in host memory. The Rx Packet Descriptor Table Base register resides in the RMAC; this register is initialised by the host. The RPDRs reside in host memory and are accessed using receive packet queues which are described in the next section.

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Receive Packet Queues

Receive Packet Queues are used to transfer RPDRs between the host and the RMAC. There are three queues: a RPDR Large Buffer Free Queue (RPDRLFQ), a RPDR Small Buffer Free Queue (RPDRSFQ) and a RPDR Ready Queue (RPDRRQ). The free queues contain RPDRs referencing RPDs that define free buffers. The ready queue contains RPDRs referencing RPDs that define buffers ready for host processing. The RMAC pulls RPDRs from the free queues when it needs free data buffers. The RMAC places an RPDR onto the ready queue after it has filled the buffers with data from each complete packet. The host removes RPDRs from the ready queue to process the data buffers. The host places the RPDRs back onto the free queues after it finishes reading the data from the buffers.

When starting to process a packet, the RMAC uses a small buffer RPD to store the packet data. If the packet requires more than one buffer, the RMAC uses large buffer RPDs to store the remainder of the packet. The RMAC links together all the RPDs required to store the packet and returns the RPDR associated with the first RPD onto the ready queue.

All receive packet queues reside in host memory and are defined by the Rx Queue Base (RQB) register and index registers which reside in the RMAC. The Rx Queue Base is the base address for the receive packet queues. Each packet queue has four index registers which define the start and end of the queue and the read and write locations of the queue. Each index register is 16 bits in length and defines an offset from the Rx Queue Base. Thus, as shown in the Figure 6, the host address of a RPDR is calculated by adding the index register to the Rx Queue Base register. The host initialises the Rx Queue Base and all the index registers. When an entity (either the RMAC or the host) removes elements from a queue, the entity updates the read pointer for that queue. When an entity (either the RMAC or the host) places elements onto a queue, the entity updates the write pointer for that queue.

The read index for each queue points to the last valid RPDR read while the write index points to where the next RPDR can be written. The start index points to the first valid location within the queue; an RPDR can be written to this location. However, the end index points to a location that is beyond a queue; an RPDR can not be written to this location. Note however, the start index of one queue can be set to the end index of another queue. A queue is empty when the read index is one less than the write index; a queue is also empty if the read index is one less than the end index and the write index equals the start index. A queue is full when the read index is equal to the write index. Figure 6 shows the RPDR reference queues.

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Figure 6 – RPDRF and RPDRR Queues

Receive Packet Descriptor (RPD) Reference Queues

Base Address:

RQB[31:2] = R x Queue Ba se registe r

Index Registers:

Large Buffer Free Queue:

RPDRLFQS[1 5:0] = R PDR Large Free Queue Start regist er RPDRLFQW[15 :0] = RPDR Large Free Queue Write register RPDRLFQR[15: 0] = RPDR Large F ree Queue R ead regist er RPDRLFQE[1 5:0] = RPDR Large Free Queue End register

Ready Queue:

RPDRRQS[15:0] = RPDR Ready Queue Star t register RPDRRQW[1 5:0] = RPDR Rea dy Queue Write r egister RPDRRQR[ 15:0] = RPDR Ready Queue Read register RPDRRQE[15:0] = RPDR Ready Queue End r egister

Rx Packet Descriptor Reference Queue Memory

Small Buf fer Free Que ue:

RPDRSFQS[15:0] = RPDR Small Free Queue Start register RPDRSFQW[15:0] = RPDR Small Free Q ueue Writ e register RPDRSFQR[15:0] = RPDR Small Free Queue Read register RPDRSFQE[15:0] = RPDR Small Free Queue End register

Base Address

+ Index Register

------------------------Host Address

RQB[31: 2]

Index[15:0]

AD[31:0]

RPDRRQS

RPDRRQR

RPDRRQW

RPDRRQE

RPDRLFQS

RPDRLFQR

RPDRLFQW

RPDRLFQE

RPDRSFQS

RPDRSFQR

RPDRSFQW

RPDRSFQE

Bit 31

Status + R PDR

Status + RPDR

Status + R PDR

Status + RPDR

RPDR

Bit 0

RQB

Host Memory

RPD Referen ce Queues

Valid RPDR

256KB

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Note that the maximum value to which an end pointer may be set is FFFF hex, resulting in a maximum offset from the queue base address of (4*(FFFF-1)) = 3FFF8 hex. An end pointer must not be set to 0 hex in an attempt to include offset 3FFFC hex in a queue.

As shown in Figure 6, the ready queue elements have a status field as well as an RPDR field. The RMAC fills in the status field to mark whether a packet was successfully received or not. The host reads the status field. The ready queue element is shown in Table 9 below along with the definition of the status bits.

If the RMAC requires a buffer of a particular size (i.e. small or large) and no RPDR is available in the corresponding free queue, a RPDR from the other free queue is substituted. The host may, therefore, force the RMAC to store received data in buffers of only one size by setting one of the free queues to zero length, i.e. by setting the start and end index registers of one of the queues to equal values. If the RMAC requires a buffer and neither free queue contains RPDRs, an RPQ_ERRI interrupt is generated.

Table 9 – RPDRR Queue Element

Bit 15 Bit 0

STATUS[1:0] RPDR[13:0]

Field Description

STATUS[1:0] The encoding for the status field is as follows:

00 - Successful reception of packet.

01 - Unsuccessful reception of packet.

10 - Unprovisioned partial packet.

11 - Reserved.

RPDR[13:0] The RPDR[13:0] field defines the offset of the first RPD in a

linked chain of RPDs, each pointing to a buffer containing the received data.

As described previously, the RMAC links a large buffer RPD to a small buffer RPD if more than one buffer is needed for a packet. The RMAC links additional large buffer RPDs to the end of the chain as required until the entire packet is copied to host memory (provided that the host has not disabled use of both free queues by setting one of them to length zero). After storing the packet data, the RMAC places the STATUS+RPDR for the first RPD onto the ready queue. Only the RPDR associated with the first RPD is placed onto the ready queue. All other required RPDs are linked to the first RPD as shown in Figure 7.

Although a STATUS+RPDR only totals to 16 bits, each queue entry is a dword, i.e. 32 bits. When the RMAC block writes a STATUS+RPDR to the ready queue, it sets the third byte to 0 and the fourth (most significant) byte is unmodified.

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Figure 7 – RPDRR Queue Operation

Rx Packet Descriptor Reference Ready Queue

RPDRRQ_START_ADDR

RPDRRQ_READ_ADDR

RPDRRQ_WRITE_ADDR

STATUS + RPDR

Bit 0Bit 31

buffer

-packet M

RPD - 16 bytes

buffer

RPD - 16 bytes

-packet N

buffer

-start of packet O

RPD - 16 bytes

buffer

-middle of packet O

RPD - 16 bytes

buffer

-end of packet O

RPDRRQ_END_ADDR

Receive Channel Descriptor Reference Table

On a per-channel basis, the RMAC caches information such as the current DMA information in a Receive Channel Descriptor Reference (RCDR) Table. The RMAC can process 128 channels and stores three dwords of information per channel. This information is cached internally in order to decrease the number of host bus accesses required to process each data packet. The structure of the RCDR table is shown in Figure 8.

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Figure 8 – Receive Channel Descriptor Reference Table

PM7366 FREEDM-8

Bit 0Bit 31

RCC 0

Buffer Size[15:0]

RBC[1:0]

Res

RPD Pointer[13:0]Bytes Available in Buffer[15:0]

Start RPD Pointer[13:0]

DMA Current Address[31:0]

RCC 1

Buffer Size[15:0]

RBC[1:0]

Res

RPD Pointer[13:0]Bytes Available in Buffer[15:0]

Start RPD Pointer[13:0]

DMA Current Address[31:0]

RCC 127

Buffer Size[15:0]

DMA Current Address[31:0]

Table 10 – Receive Channel Descriptor Reference Table Fields

Field Description

Bytes Available in Buffer[15:0]

RBC[1:0] This field is used to keep track of the number of buffers used when

RPD Pointer[13:0] This field contains the pointer to the current RPD.

This field is used to keep track of the number of bytes available in the current data buffer. The RMAC initialises the Bytes Available in Buffer to the Receive Buffer Size minus the offset at the head of the buffer. The field is decremented each time a byte is written into the buffer.

storing ‘raw’ (i.e. non packet delimited) data. The RMAC initialises the RBC field to the value of the RAWMAX[1:0] field in the RMAC Control Register. The field is decremented each time a buffer is filled with data. If the field reaches zero, the chain of RPDs is placed on the ready queue and a new chain started.

RBC[1:0]

Res

RPD Pointer[13:0]Bytes Available in Buffer[15:0]

Start RPD Pointer[13:0]

Buffer Size[15:0] This field contains the size in bytes of the buffer currently being

written to.

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Field Description

V This bit (Valid) indicates whether a packet is currently being

received on the DMA channel. When the V bit is set to 1, the other fields in the RCDR table entry for the DMA channel contain valid information.

Start RPD Pointer[13:0] This field contains the pointer to the first RPD for the packet being

received.

DMA Current Address[31:0]

The DMA Current Address [31:0] bits holds the host address of the next dword in the current buffer. The RMAC increments this field on each access to the buffer.

9.4.2 DMA Transaction Controller

The DMA Transaction Controller coordinates the reception of data packets from the Receive Packet Interface and their subsequent storage in host memory. A packet may be received over a number of separate transactions, interleaved with transactions belonging to other DMA channels. As well as sending the received data to host memory, the DMA Transaction Controller initiates data transactions of its own for the purposes of maintaining the data structures (queues, descriptors, etc.) in host memory.

9.4.3 Write Data Pipeline/Mux

The Write Data Pipeline/Mux performs two functions. First, it pipelines receive data between the RHDL block and the GPIC block, inserting enough delay to enable the DMA Transaction Controller to generate appropriate control signals at the GPIC interface. Second, it provides a multiplexor to the data out lines on the GPIC interface, allowing the DMA Transaction Controller to output data relating to the transactions the controller itself initiates.

9.4.4 Descriptor Information Cache

The Descriptor Information Cache provides the storage for the Receive Channel Descriptor Reference (RCDR) Table described above (Figure 8).

9.4.5 Free Queue Cache

The Free Queue Cache block implements the 6 element RPDR Small Buffer Free Queue cache and the 6 element RPDR Large Buffer Free Queue cache. These caches are used to store free small buffer and large buffer RPDRs. Caching RPDRs reduces the number of host bus accesses that the RMAC makes.

Each cache is managed independently. The elements of the cache are consumed one at a time as they are needed by the RMAC. The RPDR small buffer cache is reloaded when it is empty and the RMAC requires a new small buffer RPDR. The large buffer RPDR cache is reloaded when it

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is empty and the RMAC requires a new large buffer RPDR. When reloading either of the caches, the appropriate cache controller will read up to six new elements. The cache controller may read fewer than six elements if there are fewer than six new elements available, or the read pointer index is within six elements of the end of the free queue. If the read pointer is near the end of the free queue, the cache controller reads only to the end of the queue and does not start reading from the top of the queue until the next time a reload is required. To do so would require two host memory transactions and would be of no benefit.

9.5 PCI Controller

The General-Purpose Peripheral Component Interconnect Controller block (GPIC) provides a 32bit Master and Target interface core which contains all the required control functions for Peripheral Component Interconnect (PCI) Bus Revision 2.1 interfacing. Communications between the PCI bus and other FREEDM-8 blocks can be made through either an internal asynchronous16-bit bus or through one of two synchronous FIFO interfaces. One of the FIFO interfaces is dedicated to servicing the Receive DMA Controller block (RMAC) and the other to the Transmit DMA Controller block (TMAC).

The GPIC supports a 32-bit PCI bus operating at up to 33 MHz and bridges between the timing domain of the DMA controllers (SYSCLK) and the timing domain of the PCI bus (PCICLK). By itself, the GPIC does not generate any PCI bus accesses. All transactions on the bus are initiated by another PCI bus master or by the core device. The GPIC transforms each access to and from the PCI bus to the intended target or initiator in the core device. Except for the configuration space registers and parity generating/checking, the GPIC performs no operations on the data.

The GPIC is made up of four sections: master state machine, a target state machine, internal microprocessor bus interface and error/bus controller. The target and master blocks operate independent of each other. The error/bus control block monitors the control signals from the target and master blocks to determine the state of the PCI I/O pads. This block also generates and/or checks parity for all data going to or coming from the PCI bus. The internal microprocessor bus interface block contains configuration and status registers together with the production test logic for the GPIC block.

9.5.1 Master Machine

The GPIC master machine translates requests from the RMAC and TMAC block interfaces into

PCI bus transactions. The GPIC initiates four types of PCI cycles: memory read (burst or single), memory read multiple, memory read line and memory write (burst or single). The number of data transfers in any cycle is controlled by the DMA controllers. The maximum burst size is determined by the particular data path. A read cycle to the RMAC is restricted to a maximum burst size of 8 dwords and a write cycle is limited to a maximum of 32. The TMAC interface has a limit of 32 dwords on a read cycle and 8 on a write cycle.

In response to a DMA controller requesting a cycle, the GPIC must arbitrate for control of the PCI bus. Before asserting the PCI Request line, the GPIC first does an internal arbitration to determine the priority of service in the event that both the RMAC and TMAC are requesting

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service. The GMAC arbitrates between the RMAC and TMAC on a “first-request-first-serve” basis. If the RMAC and TMAC request service simultaneously, the RMAC will receive priority. When the RMAC finishes the transaction, the bus will be arbitrated to the TMAC. It is possible for all four FIFOs (RMAC read, TMAC read, RMAC write, TMAC write) to request service simultaneously.

When an external PCI bus arbitrator issues a Grant in response to the Request from the GPIC, the master state machine monitors the PCI bus to insure that the previous master has completed its transaction and has released the bus before beginning the cycle. Once the GPIC has control of the bus, it will assert the FRAME signal and drive the bus with the address and command. The value for the address is provided by the selected DMA controller. After the initial data transfer, the GPIC tracks the address for all remaining transfers in the burst internally in case the GPIC is disconnected by the target and must retry the transaction.

The target of the GPIC master burst cycle has the option of stopping or disconnecting the burst at any point. In the event of a target disconnect the GPIC will terminate the present cycle and release the PCI bus. If the GPIC is asserting the REQUEST line at the time of the disconnect, it will remove the REQUEST for two PCI clock cycles then reassert it. When the PCI bus arbitrator returns the GRANT, the GPIC will restart the burst access at the next address and continue until the burst is completed or repeat the sequence if the target disconnects again.

During burst reads, the GPIC accepts the data without inserting any wait states. Data is written directly into the read FIFO where the RMAC or TMAC can remove it at its own rate. During burst writes, the GPIC will output the data without inserting any wait states, but may terminate the transaction early if the local master fails to fill the write FIFO with data before the GPIC requires it. (If a write transaction is terminated early due to data starvation, the GPIC will automatically initiate a further transaction to write the remaining data when it becomes available.)

Normally, the GPIC will begin requesting the PCI bus for a write transaction shortly after data starts to be loaded into the write FIFO by the RMAC or TMAC. The RMAC, however, is not required to supply a transaction length when writing packet data and in addition, may insert pauses during the transfer. In the case of packet data writes by the RMAC, the GPIC will hold off requesting the PCI bus until the write FIFO has filled up with a number of dwords equal to a programmable threshold. If the FIFO empties without reaching the end of the transition, the GPIC will terminate the current transaction and restart a new transaction to transfer any remaining data when the RMAC signals an end of transaction. Beginning the PCI transaction before all the data is in the write FIFO allows the GPIC to reduce the impact of the bus latency on the core device.

Each master PCI cycle generated by the GPIC can be terminated in three ways: Completion, Timeout or Master Abort. The normal mode of operation of the GPIC is to terminate after transferring all the data from the master FIFO selected. As noted above this may involve multiple PCI accesses because of the inability of the target to accept the full burst or data starvation during writes. After the completion of the burst transfer the GPIC will release the bus unless another FIFO is requesting service, in which case if the GRANT is asserted the GPIC will insert one idle cycle on the bus and then start a new transfer.

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The maximum duration of the a master burst cycle is controlled by the value set in the LATENCY TIMER register in the GPIC Configuration Register block. This value is set by the host on boot and is loaded into a counter in the GPIC master state at the start of each access. If the counter reaches zero and the GRANT signal has been removed the GPIC will release the bus regardless of whether it has completed the present burst cycle. This type of termination is referred to as a Master Time-out. In the case of a Master Time-out the GPIC will remove the REQUEST signal for two PCI clocks and then reassert it to complete the burst cycle.

If no target responds to the address placed on the bus by the GPIC after 4 PCI clocks the GPIC will terminate the cycle and flag the cycle in the PCI Command/ Status Configuration Register as a Master Abort. If the Stop on Error enable (SOE_E) bit is set in the GPIC Command Register, the GPIC will not process any more requests until the error condition is cleared. If the SOE_E is not set, the GPIC will discard the REQUEST and indicate to the local master that the cycle is complete. This action will result in any write data being lost and any read data being erroneous.

9.5.2 Master Local Bus Interface

The master local bus is a 32 bit data bus which connects the local master device to the GPIC. The GPIC contains two local master interface blocks, with one supporting the RMAC and the other the TMAC. Each local master interface has been optimised to support the traffic pattern generated by the RMAC or the TMAC and are not interchangeable.

The data path between the GPIC and local master device provides a mechanism to segregate the system timing domain of the core from the PCI bus. Transfers on each of the RMAC and TMAC interfaces are timed to its own system clock. The DMA controllers isolated from all aspects of the PCI bus protocol, and instead “sees” a simple synchronous protocol. Read or write cycles on the local master bus will initiate a request for service to the GPIC which will then transfer the data via the PCI bus.

The GPIC maximises data throughput between the PCI bus and the local device by paralleling local bus data transfers with PCI access latency. The GPIC allows either DMA controller to write data independent of each other and independent of PCI bus control. The GPIC temporarily buffers the data from each DMA controller while it is arbitrating for control of the PCI bus. After completion of a write transfer, the DMA controller is then released to perform other tasks. The GPIC can buffer only a single transaction from each DMA controller.

Read accesses on the local bus are optimised by allowing the DMA controllers access to the data from the PCI bus as soon as the first data becomes available. After the initial synchronisation and PCI bus latency data is transferred at the slower of PCI bus rate or the core logic SYSCLK rate. Once a read transaction is started, the DMA controller is held waiting for the ready signal while the GPIC is arbitrating for the PCI bus.

All data is passed between the GPIC and the DMA controllers in little Endian format and, in the default mode of operation, the GPIC expects all data on the PCI bus to also be in little Endian format. The GPIC provides a selection bit in the internal Control register which allows the Endian format of the PCI bus data to be changed. If enabled, the GPIC will swizzle all packet data on the PCI bus (but not descriptor references and the contents of descriptors). The swizzling is

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performed according to the “byte address invariance” rule, i.e. the only change to the data is the mirror-imaging of byte lanes.

The interface for the RMAC provides for byte addressability of write transactions whereas the interface for the TMAC provides for byte addressability of read transactions. Other transactions must be dword aligned. For byte-addressable transactions, the data transferred between the local device and the GPIC need not be dword aligned with the data as it is presented on the PCI bus. The GPIC will perform any byte-realignment required. In order to complete a transfer involving byte re-alignment, the GPIC may need to add an extra burst cycle to the PCI transaction.

9.5.3 Target Machine

The GPIC target machine performs all the required functions of a stand alone PCI target device. The target block performs three main functions. The first is the target state machine which controls the protocol of PCI target accesses to the GPIC. The second function is to provide all PCI Configuration registers. Last, the target block provides a Target Interface to the CBI registers in the other FREEDM-8 blocks.

The GPIC tracks the PCI bus and decodes all addresses and commands placed on the bus to determine whether to respond to the access. The GPIC responds to the following types of PCI bus commands only: Configuration read and write, memory read and write, memory-read-multiple and memory-read-line which are aliased to memory read and memory-write-and-invalidate which is aliased to memory write. The GPIC will ignore any access that falls within the address range but has any other command type.

After accepting a target access as a medium speed device, the FREEDM inserts one wait state for a configuration read/write and five wait states for other command types before completing the transaction by asserting TRDYB.

Burst accesses to the GPIC are accepted provided they are of linear type. If a master makes a memory access to the GPIC with the lower two address bits set to any value but "00" (linear burst type) the GPIC ignores the cycle. Burst accesses of any length are accepted, but the FREEDM will disconnect if the master inserts any wait states during the transaction. The FREEDM will also disconnect on every read and write access to configuration space after transferring one Dword of data.

Figure 9 illustrates the GPIC address space.

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Figure 9 – GPIC Address Map

PCI ADDRESS MAP

CBI Registers Base Address

CBI Registers

4GB

4KB

The GPIC responds with medium timing to master accesses. (I.e. DEVSELB is asserted 2 PCICLK cycles after FRAMEB asserted) It inserts five wait states on reads to the internal CBI register space (six wait states for the 2nd and subsequent dwords of a burst read). The target machine will only terminate an access with a Retry if the target is locked and another master tries to access the GPIC. The GPIC will terminate any access to a non-burst area with a Disconnect and always with data transferred. The target does not support delayed transactions. The GPIC will perform a Target-Abort termination only in the case of an address parity error in an address that the GPIC claims.

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9.5.4 CBI Bus Interface

The CBI bus interface provides access to the CBI address space of the FREEDM-8 blocks. The CBI address space is set by the associated BAR in the PCI Configuration registers.

Write transfers to the CBI space always write all 32 bits provided that at least one byte enable is asserted. A write command with all byte enables negated will be ignored. Read transfers always return the 32 bits regardless of the status of the byte enables, as long as at least one byte enable is asserted. A read command with all byte enables negated will be ignored.

9.5.5 Error / Bus Control

The Error/Bus Control block monitors signals from both the Target block and Master Block to determine the direction of the PCI bus pads and to generate or check parity. After reset, the GPIC sets all bi-directional PCI bus pads to inputs and monitors the bus for accesses. The Error/Bus control unit remains in this state unless either the Master requests the PCI bus or the Target responds to a PCI Master Access. The Error/Bus control unit decodes the state of each state machine to determine the direction of each PCI bus signal.

All PCI bus devices are required to check and generate even parity across AD[31:0] and C/BEB[3:0] signals. The GPIC generates parity on Master address and write data phases; the target generates parity on read data phases. The GPIC is required to check parity on all PCI bus phases even if it is not participating in the cycle. But, the GPIC will report parity errors only if the GPIC is involved in the PCI cycle or if the GPIC detects an address parity error or data parity is detected in a PCI special cycle. The GPIC updates the PCI Configuration Status register for all detected error conditions.

9.6 Transmit DMA Controller

The Transmit DMA Controller block (TMAC) is a DMA controller which retrieves packet data from host computer memory for transmission. The minimum packet data length is two bytes. The TMAC communicates with the host computer bus through the master interface connected to PCI Controller block (GPIC) which translates host bus specific signals from the host to the master interface format. The TMAC uses the master interface whenever it wishes to initiate a host bus read or write; in this case, the TMAC is the initiator and the host memory is the target.

The TMAC and the host exchange information using transmit descriptors (TDs). The descriptor contains the size and location of buffers in host memory and the packet status information associated with the data in each buffer. TDs are transferred from the TMAC to the host and vice versa using descriptor reference queues. The TMAC maintains all the pointers for the operation of the queues. The TMAC acquires buffers with data ready for transmission by reading TDRs from a TDR ready queue. After a packet has been transmitted, the TMAC places the associated TDR onto a TDR free queue.

To minimise host bus accesses, the TMAC maintains a descriptor reference table to store current DMA information. This table contains separate DMA information entries for up to 128 transmit

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channels. The TMAC also performs per-channel sorting of packets received in the TDR ready queue to eliminate head-of-line blocking.

9.6.1 Data Structures

The TMAC communicates with the host using Transmit Descriptors (TD), Transmit Descriptor References (TDR), the Transmit Data Reference Ready (TDRR) queue and the Transmit Data Reference Free (TDRF) queue.

The TMAC reads packet data from data buffers in host memory. The TD, TDR, TDRR queue, and TDRF queue are data structures which are used to transfer host memory data buffer information. All four data structures are manipulated by both the TMAC and the host computer. The TD holds the data buffer size, data buffer address, and other packet information. The TDR is a pointer which is used to index into a table of TDs. The TDRR queue and TDRF queue allow the TMAC and the host to pass TDRs back and forth. These data structures are described in more detail in the following sections.

Transmit Descriptor

The Transmit Descriptors (TDs) pass buffer and packet information between the TMAC and the host. Both the TMAC and the host read and write information in the TDs. TDs are stored in host memory in a Transmit Descriptor Table. The Transmit Descriptor structure is shown in Figure 10.

Figure 10 – Transmit Descriptor

Bit 31

Res(2)

Reserved (16)

Data Buffer Start Address [31:0]

IOCABT

MVReserved (5) TCC[6:0]Bytes In Buffer [15:0]

Transmit Buffer Size [15:0]

Host Next TD Pointer [13:0]TMAC Next TD Pointer [13:0]

Bit 0

Table 11 – Transmit Descriptor Fields

Field Description

Data Buffer Start Address [31:0]

The Data Buffer Start Address[31:0] bits point to the data buffer in host memory.

The Data Buffer Start Address field is valid in all TDs

Bytes In Buffer [15:0] The Bytes In Buffer[15:0] field is used by the host to indicate the

total number of bytes to be transmitted in the current TD. Zero length buffers are illegal.

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Field Description

P The Priority bit is set by the host to indicate the priority of the

associated packet in a two level quality of service scheme. Packets with its P bit set high are queued in the high priority queue in the TMAC. Packets with the P bit set low are queued in the low priority queue. Packets in the low priority queue will not begin transmission until the high priority queue is empty.

V The V bit is used to indicate that the TMAC Next TD Pointer field

is valid. When set to logic 1, the TMAC Next TD Pointer[13:0] field is valid. When V is set to logic 0, the TMAC Next TD Pointer[13:0] field is invalid. The V bit is used by the host to reclaim data buffers in the event that data presented to the TMAC is returned to the host due to a channel becoming unprovisioned. The V bit is expected to be initialised to logic 0 by the host.

M The More (M) bit is used by the host to support packets that

require multiple TDs. If M is set to logic 1, the current TD is just one of several TDs for the current packet. If M is set to logic 0, this TD either describes the entire packet (in the single TD packet case) or describes the end of a packet (in the multiple TD packet case).

Note: When M is set to logic 1, the only valid value for CE is logic 0.

CE The Chain End (CE) bit is used by the host to indicate the end of

a linked list of TDs presented to the TMAC. The linked list can contain one or more packets as delineated by the M bit (see above). When CE is set to logic 1, the current TD is the last TD of a linked list of TDs. When CE is set to logic 0, the current TD is not the last TD of a linked list. W hen the current TD is not the last of the linked list, the Host Next TD Pointer[13:0] field is valid, otherwise the field is not valid.

Note: When CE is set to logic 1, the only valid value for M is logic 0.

Note: When presenting raw (i.e. unpacketised) data for transmission, the host should code the M and CE bits as for a single packet chain, i.e. M=1, CE=0 for all TDs except the last in the chain and M=0, CE=1 for the last TD in the chain.

TCC[6:0] The Transmit Channel Code (TCC[6:0]) field is used by the host

to indicate with which channel a TD is associated. All TD in a chain must be associated with the same channel, i.e. have this field set to the same value.

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Field Description

TMAC Next TD Pointer [13:0]

The TMAC Next TD Pointer[13:0] bits are used to store TDRs which permits the TMAC to create linked lists of TDs passed to it via the TDRR queue. The TDs are linked with other TDs belonging to the same channel and same priority level. In the case that data presented to the TMAC is returned to the host due to a channel becoming unprovisioned, a TDR pointing to the start of the per-channel linked list of TDs is placed on the TDRF queue. It is the responsibility of the host to follow the TMAC and host links in order to recover all the buffers.

ABT The Abort (ABT) bit is used by the host to abort the transmission

of a packet. When ABT is set to logic 1, the packet will be aborted after all the data in the buffer has been transmitted. If ABT is set to logic 1 in the current TD, the M bit must be set low and the CE bit must be set to high..

IOC The Interrupt On Complete (IOC) bit is used by the host to

instruct the TMAC to interrupt the host when the current TD's data buffer has been read. When IOC is logic 1, the TMAC asserts the IOCI interrupt when the data buffer has been read. Additionally, the Free Queue FIFO will be flushed. If IOC is logic zero, the TMAC will not generate an interrupt and the Free Queue FIFO will operate normally.

Host Next TD Pointer [13:0] The Host Next TD Pointer[13:0] bits are used to store TDRs

which permits the host to support linked lists of TDs. As described above, linked lists of TDs are terminated by setting the CE bit to logic 1. Linked lists of TDs are used by the host to pass multiple TD packets or multiple packets associated with the same channel and priority level to the TMAC.

Transmit Buffer Size [15:0] The Transmit Buffer Size[15:0] field is used to indicate the size in

bytes of the current TD's data buffer. (N.B. The TMAC does not make use of this field.)

Transmit Descriptor Table

The Transmit Descriptor Table, which resides in host memory, contains all of the Transmit Descriptors referenced by the TMAC. To access a TD, the TMAC takes a TDR from a TDRR queue or from the TCDR table and adds 16 times its value (because each TD is 16 bytes in size) to the Transmit Descriptor Table Base (TDTB) pointer to form the actual address of the TD in host memory. Each TD must reside in the Transmit Descriptor Table. The Transmit Descriptor Table can contain a maximum of 16384 TDs. The base of the Transmit Descriptor Table is user programmable using the TMAC Tx Descriptor Table Base register. Thus, as shown below, each TD can be located using a Transmit Descriptor Reference (TDR) combined with the TMAC Tx Descriptor Table Base register.

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Figure 11 – Transmit Descriptor Table

TDTB[31:4] = Tx Descriptor Table Base register

TDR[13:0] = Transmit Descriptor Reference

TD_ADDR[31:0] = Transmit Descriptor Address

Bit 31 Bit 0

TDTB[31:4]

0000

TDR[13:0]

0000

TD_ADDR[31:0]

TDTB

TD1

TD_ADDR

TD2

Bit 0Bit 31

Dword 0 Dword 1 Dword 2 Dword 3 Dword 0

Dword 3

Dword 0

TD 16384

Dword 3

Transmit Queues

Pointers to the transmit descriptors (TDs) containing packet(s) ready for transmission are passed from the host to the TMAC using the Transmit Descriptor Reference Ready (TDRR) queue, which resides in host memory. Pointers to transmit descriptor structures whose buffers have been read by the TMAC are passed from the TMAC to the host using the Transmit Descriptor Reference Free (TDRF) queue, which also resides in host memory. The TMAC contains a Free Queue cache which can store up to six TDRs. If caching is enabled, free TDRs are written into the TDRF queue six at a time, to reduce the number of host memory accesses. The Free Queue cache is

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also flushed to the TDRF queue if the Interrupt On Completion (IOC) bit is set in the TD, which sends the corresponding TDR directly to the TDRF queue.

The queues, shown in Figure 12 are defined by a common base pointer residing in the Transmit Queue Base register and eight offset pointers, four per queue. For each queue, two pointers define the start and the end of the queue, and two pointers keep track of the current read and write locations within the queue. The read pointer for each queue points to the offset of the last valid TDR read, and the write pointer points to the offset where next TDR can be written. The end of a queue is not a valid location for a TDR to be read or written. A queue is empty when the read pointer is one less than the write pointer or if the read pointer is one less than the end pointer and the write pointer equals the start pointer. A queue is full when the read pointer is equal to the write pointer. Each queue element is 32 bits in size, but only the 17 least significant bits are valid. The 17 least significant bits consist of a 14-bit TDR and three status bits. The status bits are used by the TMAC to inform the host of the success or failure of transmission (see Table 12). When the TMAC writes TDRs to the TDRF queue, it sets bits [23:17] of the queue element to 0. Once a TDR is placed on the TDRF queue, the FREEDM-8 will make no further accesses to the TD nor the associated buffer.

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Figure 12 – TDRR and TDRF Queues

Transmit Descriptor Referance Queues

Base Address:

TQB[31:2] = Tx Queue Base register

Index Registers:

Ready:

TDRRQS[15:0] = TDR Ready Queue Start register TDRRQW[15:0] = TDR Ready Queue Write register TDRRQR[15:0] = TDR Ready Queue Read register TDRRQE[15:0] = TDR Ready Queue End register

Free:

TDRFQS[15:0] = TDR Free Queue Start register TDRFQW[15:0] = TDR Free Queue Write register TDRFQR[15:0] = TDR Free Queue Read register TDRFQE[15:0] = TDR Free Queue End register

Tx Descriptor Reference Queue Memory Map

Base Address

+ Index Register

------------------------PCI Address

TQB[31:2]

Index[15:0]

D[31:0]

TDRFQS

TDRFQR

TDRFQW

TDRFQE

TDRRQS

TDRRQR

TDRRQW

TDRRQE

Status + TDR

TDR

Bit 0Bit 31

PCI Host Memory

TQB

TDR Reference Queues

Valid TDR. Only least significant 17 bits are valid.

256KB

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Table 12 – Transmit Descriptor Reference

Bit 16 Bit 0

STATUS[2:0] TDR[13:0]

Field Description

Status[2:0] The TMAC fills in the Status field to indicate to the host the results of

processing the TD. The encoding is:

Status[1:0] Description

00 Last or only buffer of packet, buffer read.

01 Buffer of partial packet, buffer read.

10 Unprovisioned channel, buffer not read.

11 Malformed packet (e.g. Bytes In Buffer field set to 0),

buffer not read.

Status[2] Description

0 No underflow detected.

1 Underflow detected.

TDR[13:0] The TDR[13:0] field contains the offset of the TD returned.

If a TDR is returned to the host with the status field set to “10” (unprovisioned channel), the TDR may point to a binary tree of TDs and buffers (as indicated by the CE and V bits in the TDs). It is the responsibility of the host to traverse the tree to reclaim all the buffers. If a TDR is returned to the host with the status field set to any other value, the TDR will only point to one TD and buffer regardless of the values of V and CE in that TD.

The underflow status bit (Status[2]) is normally attached to the TDR belonging to a packet experiencing underflow. For long packets spanning multiple buffers, underflow is reported only once at the first available TDR of that channel. All subsequent TDRs of that packet will be returned normally without the underflow status. In rare cases, due to internal buffering by the FREEDM-8, a packet may experience underflow at the very end of a packet, just as the TDR is being returned to the TDR free queue. The underflow status will then be reported in the first TDR of the immediate next packet of that channel. Because of the uncertainty with the reporting of underflows between the current verse the subsequent packet, the underflow status should only be used to gather performance statistics on channels and not for initiating packet specific responses such as retransmission.

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Transmit Channel Descriptor Reference Table

The TMAC maintains a Transmit Channel Descriptor Reference (TCDR) table in which is stored certain information relating to DMA activity on each channel together with TD pointers which are used by the TMAC to sort packet chains supplied by the host into per-channel linked lists (see below). The caching of DMA-related information reduces the number of host bus accesses required to process each data packet, while the sorting into per-channel linked lists eliminates head of line blocking. Each channel is provided with two entries in the TCDR table, one for high priority packets (Pri 1) and one for low priority packets (Pri 0). The structure of the TCDR table is shown in Figure 13 below.

Figure 13 – Transmit Channel Descriptor Reference Table

Bit 31 Bit 0

TCC 0, Pri 0

M CE Last TD Pointer [13:0] A D Current TD Pointer [13:0]

Bytes to Tx [15:0] Abrt IOC Host TD Pointer [13:0]

DMA Current Address [31:0]

Last

UNA

TCC 1, Pri 0

Reserved

PiP

M CE Last TD Pointer [13:0] A D Current TD Pointer [13:0]

Bytes to Tx [15:0] Abrt IOC Host TD Pointer [13:0]

DMA Current Address [31:0]

Reserved Next TD Pointer [13:0]

PiP

Last

UNA

: : :

TCC 127, Pri 1

M CE Last TD Pointer [13:0] A D Current TD Pointer [13:0]

Bytes to Tx [15:0] Abrt IOC Host TD Pointer [13:0]

DMA Current Address [31:0]

Reserved Next TD Pointer [13:0]

PiP

Last

UNA

Table 13 – Transmit Channel Descriptor Reference Table Fields

Field Description

Next TD Pointer [13:0]

M A copy of the M bit in the TD currently being read.

CE A copy of the CE bit in the TD currently being read.

Last TD Pointer [13:0] Offset to the head of the last host-linked chain of TDs to be read.

(See Figure 14)

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Field Description

A Indicates if this channel is active (i.e. provisioned). If the channel

is active, the A bit is set to logic 1. If the channel is inactive, the A bit is set to logic 0.

D Indicates whether the linked list of packets for this channel is

empty or not. If the D bit is set to logic 1, the list is not empty and the current TD pointer field is valid (i.e., it points to a valid TD). If the D bit is set to logic 0, the list is empty and the current TD pointer field is invalid.

Current TD Pointer [13:0] Offset to the TD currently being read.

Bytes To Tx[15:0] The Bytes to Tx[15:0] bits are used to indicate the total number of

bytes that remain to be read in the current buffer. Each access to the data buffer decrements this value. A value of zero in this field indicates the buffer has been completely read.

ABRT A copy of the ABRT bit in the TD currently being read.

IOC A copy of the IOC bit in the TD currently being read.

PiP The Packet Transfer in Progress bit indicates that a packet is

currently being transmitted on this channel at this priority level.

NA Indicates that a ‘null abort’ is to be sent to the downstream block

when it next requests data on this channel. The NA bit is set if a mal-formed TD is encountered while searching down a host chain.

U Indicates that a underflow has occurred on this channel. This bit is

set in response to an underflow indication for the downstream THDL block and is cleared when a TDR is written to the TDR Free Queue (or to the free queue cache).

Host TD Pointer [13:0] A copy of the Host Next TD Pointer field of the TD currently being

read, i.e. a pointer to the next TD in the chain currently being read. (See Figure 14)

DMA Current Address[31:0]

The DMA Current Address [31:0] bits hold the address of the next dword in the current buffer. This field is incremented on each access to the buffer.

V Indicates if the linked list of packets for this channel contains more

than one host-linked chain (See Figure 14). If the V bit is set to logic 1, the list contains more than one chain and the next and last TD pointer fields are valid. If the V bit is set to logic 0, the list is either empty or contains only one host-linked chain and the next and last TD pointer fields are invalid.

Next TD Pointer [13:0] Offset to the head of the next host-linked chain of TDs to be read.

(See Figure 14)

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Transmit Descriptor Linking

As described above, the TCDR table contains pointers which the TMAC uses to construct linked lists of data packets to be transmitted. After the host places a new TDR in the TDR Ready queue, the TMAC retrieves the TDR and links it to the TD pointed at by the Last TD Pointer field. The TMAC may create up to 256 linked lists, viz. a high-priority list and a low-priority list for each DMA channel. Whenever a new data packet is requested by the downstream block, the TMAC picks a packet from the high-priority linked list unless it is empty, in which case, a packet from the lowpriority linked list is used.

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Figure 14 – TD Linking

TD TD

V=1

M=1

CE=0

TMAC Link

Data

Host Link

M=0

CE=1

Data

V=0

M=0

CE=1

Curr.

TDR

Last

TCDR Table

Host TDR

Host Link

V=1

M=1

CE=0

M=1

CE=0

TMAC Link

Data

Host Link

M=0

CE=0

Data

Host Link

M=0

CE=1

Data

The host links the TDs vertically while the TMAC links TDs horizontally. Figure 14 shows the TDs for packets P1 and P2 linked by the host before the TDR is placed on the TDRR queue, as are the TDs for packet P3. Packet P3 is linked to packet P1 by the TMAC, as is packet P4 linked to packet P3. The TMAC indicates valid horizontal links by setting the V bit to logic 1.

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9.6.2 Task Priorities

The TMAC must perform a number of tasks concurrently in order to maintain a steady flow of data through the system. The main tasks of the TMAC are managing the Ready Queue (i.e. removing chains of data packets from the queue and attaching them to the appropriate per-channel linked list) and servicing requests for data from the Transmit Packet Interface. The priority of service for each of the tasks is fixed by the TMAC as follows:-

· Top priority is given to servicing ‘expedited’ read requests from the Transmit HDLC Processor

/ Partial Packet Buffer block (THDL).

· Second priority is given to removing chains of data packets from the TDRR queue and

attaching them to the appropriate per-channel linked list.

· Third priority is given to servicing non-expedited read requests from the THDL.

9.6.3 DMA Transaction Controller

The DMA Transaction Controller coordinates the processing of requests from the THDL with the reading of data stored in host memory. The reading of a data packet may require a number of separate host memory transactions, interleaved with transactions of other DMA channels. As well as reading data from the Host Master Interface, the DMA Transaction Controller initiates read and write transactions to the PCI Controller block (GPIC) for the purposes of maintaining the data structures (queues, descriptors, etc.) in host memory.

9.6.4 Read Data Pipeline

The Read Data Pipeline inserts delay in the data stream between the GPIC interface and the THDL interface to enable the DMA Transaction Controller to generate appropriate control signals at the Transmit Packet Interface.

9.6.5 Descriptor Information Cache

The Descriptor Information Cache provides the storage for the Transmit Channel Descriptor Reference (TCDR) Table.

9.6.6 Free Queue Cache

The Free Queue Cache block implements the 6 element TDR Free Queue cache. Caching TDRs reduces the number of host bus accesses that the TMAC makes.

TDRs are written to the cache one at a time as they are released by the TMAC. The cache is then flushed to host memory when it becomes full, when a TD with the IOC bit set high is released or when a TD is released as the result of unprovisioning a channel. The cache controller may also flush the cache when it contains fewer than six elements or if the pointer index is within six

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elements of the end of the free queue. If the write pointer is near the end of the free queue, the cache controller writes only to the end of the queue and does not start writing from the top of the queue until the next time a flush is required. To do so would require two host memory transactions and would be of no benefit.

9.7 Transmit HDLC Controller / Partial Packet Buffer

The Transmit HDLC Controller / Partial Packet Buffer block (THDL) contains a partial packet buffer for PCI latency control and a transmit HDLC controller. Packet data retrieved from the PCI host memory by the Transmit DMA Controller block (TMAC) is stored in channel specific FIFOs residing in the partial packet buffer. When the amount of data in a FIFO reaches a programmable threshold, the HDLC controller is enabled to initiate transmission. The HDLC controller performs flag generation, bit stuffing and, optionally, frame check sequence (FCS) insertion. The FCS is software selectable to be CRC-CCITT or CRC-32. The minimum packet size, excluding FCS, is two bytes. A single byte payload is illegal. The HDLC controller delivers data to the Transmit Channel Assigner block (TCAS) on demand. A packet in progress is aborted if an under-run occurs. The THDL is programmable to operate in transparent mode where packet data retrieved from the PCI host is transmitted verbatim.

9.7.1 Transmit HDLC Processor

The HDLC processor is a time-slice state machine which can process up to 128 independent channels. The state vector and provisioning information for each channel is stored in a RAM. Whenever the TCAS requests data, the appropriate state vector is read from the RAM, processed and finally written back to the RAM. The HDLC state-machine can be configured to perform flag insertion, bit stuffing and CRC generation. The HDLC processor requests data from the partial packet processor whenever a request for channel data arrives. However, the HDLC processor does not start transmitting a packet until the entire packet is stored in the channel FIFO or until the FIFO free space is less than the software programmable limit. If a channel FIFO under-runs, the HDLC processor aborts the packet.

The configuration of the HDLC processor is accessed using indirect channel read and write operations. When an indirect operation is performed, the information is accessed from RAM during a null clock cycle inserted by the TCAS block. Writing new provisioning data to a channel resets the channel's entire state vector.

9.7.2 Transmit Partial Packet Buffer Processor

The partial packet buffer processor controls the 8 Kbyte partial packet RAM which is divided into 16 byte blocks. A block pointer RAM is used to chain the partial packet blocks into circular channel FIFO buffers. Thus, non-contiguous sections of RAM can be allocated in the partial packet buffer RAM to create a channel FIFOFigure 15 shows an example of three blocks (blocks 1, 3, and 200) linked together to form a 48 byte channel FIFO. The three pointer values would be written sequentially using indirect block write accesses. When a channel is provisioned with this FIFO, the state machine can be initialised to point to any one of the three blocks.

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The partial packet buffer processor is divided into three sections: reader, writer and roamer. The roamer is a time-sliced state machine which tracks each channel's FIFO buffer free space and signals the writer to service a particular channel. The writer requests data from the TMAC block and transfers packet data from the TMAC to the associated channel FIFO. The reader is a timesliced state machine which transfers the HDLC information from a channel FIFO to the HDLC processor when the HDLC processor requests it. If a buffer under-run occurs for a channel, the reader informs the HDLC processor and purges the rest of the packet.

Figure 15 – Partial Packet Buffer Structure

Block 0

Block 1

Partial Packet

Buffer RAM

16 bytes

Block 0

Block 1

Block

Pointer RAM

0x03

Block 2

Block 3

Block 511

16 bytes

Block 2

Block 3

Block 200Block 200

Block 511

0xC8

0x01

The FIFO algorithm of the partial packet buffer processor is based on per-channel software programmable transfer size and free space trigger level. Instead of tracking the number of full blocks in a channel FIFO, the processor tracks the number of empty blocks, called free space, as well as the number of end of packets stored in the FIFO. Recording the number of empty blocks

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instead of the number of full blocks reduces the amount of information the roamer must store in its state RAM.

The partial packet roamer records the FIFO free space and end-of-packet count for all channel FIFOs. When the reader signals that a block has been read, the roamer increments the FIFO free space and sets a per-channel request flag if the free space is greater than the limit set by XFER[2:0]. The roamer also decrements the end-of-packet count when the reader signals that it has passed an end of a packet to the HDLC processor. If the HDLC is transmitting a packet and the FIFO free space is greater than the free space trigger level and there are no complete packets within the FIFO (end-of-packet count equal to zero), a per-channel expedite flag is set. The roamer searches the expedite flags in a round-robin fashion to decide which channel FIFO should make expedited data requests to the TMAC block. If no expedite flags are set, the roamer searches the request flags in a round-robin fashion to decide which channel FIFO should make regular data requests to the TMAC block. The roamer informs the partial packet writer of the channel FIFO to process, the FIFO free space and the type of request it should make. The writer sends a request for data to the TMAC block and writes the response data to the channel FIFO setting block full flags. The writer reports back to the roamer the number of blocks and end-ofpackets transferred. The maximum amount of data transferred during one request is limited by a software programmable limit.

The configuration of the HDLC processor is accessed using indirect channel read and write operations as well as indirect block read and write operations. When an indirect operation is performed, the information is accessed from RAM during a null clock cycle identified by the TCAS block. Writing new provisioning data to a channel resets the entire state vector.

9.8 Transmit Channel Assigner

The Transmit Channel Assigner block (TCAS) processes up to 128 channels. Data for all channels is sourced from a single byte-serial stream from the Transmit HDLC Controller / Partial Packet Buffer block (THDL). The TCAS demultiplexes the data and assigns each byte to any one of 8 links. Each link is independent and has its own associated clock. For each high-speed link (TD[2:0]), the TCAS provides a six byte FIFO. For the remaining links (TD[7:3]), the TCAS provides a holding register. The TCAS also performs parallel to serial conversion to form a bitserial stream. In the event where multiple links are in need of data, TCAS requests data from upstream blocks on a fixed priority basis with link TD[0] having the highest priority and link TD[7] the lowest.

Links containing a T1 or an E1 stream may be channelised. Data at each time-slot may be independently assigned to be sourced from a different channel. The link clock is only active during time-slots 1 to 24 of a T1 stream and is inactive during the frame bit. Similarly, the clock is only active during time-slots 1 to 31 of an E1 stream and is inactive during the FAS and NFAS framing bytes. The most significant bit of time-slot 1 of a channelised link is identified by noting the absence of the clock and its re-activation. With knowledge of the transmit link and time-slot identity, the TCAS performs a table look-up to identify the channel from which a data byte is to be sourced.

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Links may also be unchannelised. Then, all data bytes on that link belong to one channel. The TCAS performs a table look-up to identify the channel to which a data byte belongs using only the outgoing link identity, as no time-slots are associated with unchannelised links. Link clocks are no longer limited to T1 or E1 rates and may range up to 52 MHz for TCLK[2:0]. For TCLK[7:3] the maximum clock rate is 10 MHz. The link clock is only active during bit times containing data to be transmitted and inactive during bits that are to be ignored by the downstream devices, such as framing and overhead bits. For the case of two unchannelised links, the maximum link rate 52 MHz for SYSCLK at 33 MHz. For the case of more numerous unchannelised links or a mixture of channelised and unchannelised links, the total instantaneous link rate over all the links is limited to 64 MHz.

9.8.1 Line Interface

There are two types of line interfaces in the TCAS; high-speed and low-speed interfaces. Three identical high-speed interfaces are attached to the first three links, while five identical low-speed interfaces are attached to the remaining links. Each line interface contains a bit counter, an 8-bit shift register and a byte FIFO, that, together, perform parallel to serial conversion. For the highspeed interfaces the FIFO is six bytes deep. For the low-speed interfaces, the FIFO is a single byte holding register. Whenever the shift register is updated, a request for service is sent to the priority encoder block. The request will eventually be serviced by the THDL block and the data is written into the FIFO.

To support channelised links, each line interface block contains a time-slot counter and a clock activity monitor. The time-slot counter is incremented each time the shift register is updated. The clock activity monitor is a counter that increments at the system clock (SYSCLK) rate and is cleared by a rising edge of the transmit clock (TCLK[n]). A framing bit (T1) or framing byte (E1) is detected when the counter reaches a programmable threshold. At which point, the bit and timeslot counters are initialised to indicate the next bit sampled is the most significant bit of the first time-slot. For unchannelised links, the time-slot counter and the clock activity monitor are held reset.

9.8.2 Priority Encoder

The priority encoder monitors the line interfaces for requests and synchronises them to the SYSCLK timing domain. Requests are serviced on a fixed priority scheme where highest to lowest priority is assigned from line interface TD[0] to line interface TD[7]. Thus, simultaneous requests from line interface TD[m] will be serviced ahead of line interface TD[n], if m < n. The priority encoder selects the request from the link with the highest priority for service. When there are no pending requests, the priority encoder generates an idle cycle. In addition, once every fourth SYSCLK cycle, the priority encoder inserts a null cycle where no requests are serviced. This cycle is used by the channel assigner downstream for CBI accesses to the channel provision RAM.

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9.8.3 Channel Assigner

The channel assigner block determines the channel number of the request currently being processed. The block contains a 256 word channel provision RAM. The address of the RAM is constructed from concatenating the link number and the time-slot number of the highest priority requester. The fields of each RAM word include the channel number and a time-slot enable flag. The time-slot enable flag labels the current time-slot as belonging to the channel indicted by the channel number field. For time-slots that are enabled, the channel assigner issues a request to the THDL block which responds with packet data within one byte period of the transmit stream.

9.9 Performance Monitor

The Performance Monitor block (PMON) contains four counters. The first two accumulate receive partial packet buffer FIFO overrun events and transmit partial packet buffer FIFO underflow events, respectively. The remaining two counters are software programmable to accumulate a variety of events, such as receive packet count, FCS error counts, etc. All counters saturate upon reaching maximum value. The accumulation logic consists of a counter and holding register pair. The counter is incremented when the associated event is detected. Writing to the FREEDM-8 Master Clock / BERT Activity Monitor and Accumulation Trigger register transfer the count to the corresponding holding register and clear the counter. The contents of the holding register is accessible via the PCI interface.

9.10 JTAG Test Access Port Interface

The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG

EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The FREEDM8 identification code is 173660CD hexadecimal.

9.11 PCI Host Interface

The FREEDM-8 supports two different normal mode register types as defined below:

1. PCI Host Accessible registers (PA) - these registers can be accessed through the PCI Host interface.

2. PCI Configuration registers (PC) - these register can only be accessed through the PCI Host interface during a PCI configuration cycle.

The PCI registers are addressable on dword boundaries only. The PCI offset shown in the table below must be combined with a base address to form the PCI Interface address. The base address can be found in the FREEDM-8 Memory Base Address register in the PCI Configuration memory space.

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Table 14 – Normal Mode PCI Host Accessible Register Memory Map

PCI Offset Register

0x000 FREEDM-8 Master Reset

0x004 FREEDM-8 Master Interrupt Enable

0x008 FREEDM-8 Master Interrupt Status

0x00C FREEDM-8 Master Clock / BERT Activity Monitor and Accumulation Trigger

0x010 FREEDM-8 Master Link Activity Monitor

0x014 FREEDM-8 Master Line Loopback

0x018 - 0x01C Reserved

0x020 FREEDM-8 Master BERT Control

0x024 FREEDM-8 Master Performance Monitor Control

0x028 - 0x03C Reserved

0x040 GPIC Control

0x044 - 0x07C GPIC Reserved

0x080 - 0x0FC Reserved

0x100 RCAS Indirect Channel and Time-slot Select

0x104 RCAS Indirect Channel Data

0x108 RCAS Framing Bit Threshold

0x10C RCAS Channel Disable

0x110 - 0x17C RCAS Reserved

0x180 RCAS Link #0 Configuration

0x184 - 0x19C RCAS Link #1 to Link #7 Configuration

0x1A0 - 0x1FC RCAS Reserved

0x200 RHDL Indirect Channel Select

0x204 RHDL Indirect Channel Data Register #1

0x208 RHDL Indirect Channel Data Register #2

0x20C RHDL Reserved

0x210 RHDL Indirect Block Select

0x214 RHDL Indirect Block Data Register

0x218 RHDL Reserved

0x21C RHDL Reserved

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PCI Offset Register

0x220 RHDL Configuration

0x224 RHDL Maximum Packet Length

0x228 - 0x23C RHDL Reserved

0x240 - 0x27C Reserved

0x280 RMAC Control

0x284 RMAC Indirect Channel Provisioning

0x288 RMAC Packet Descriptor Table Base LSW

0x28C RMAC Packet Descriptor Table Base MSW

0x290 RMAC Queue Base LSW

0x294 RMAC Queue Base MSW

0x298 RMAC Packet Descriptor Reference Large Buffer Free Queue Start

0x29C RMAC Packet Descriptor Reference Large Buffer Free Queue Write

0x2A0 RMAC Packet Descriptor Reference Large Buffer Free Queue Read

0x2A4 RMAC Packet Descriptor Reference Large Buffer Free Queue End

0x2A8 RMAC Packet Descriptor Reference Small Buffer Free Queue Start

0x2AC RMAC Packet Descriptor Reference Small Buffer Free Queue Write

0x2B0 RMAC Packet Descriptor Reference Small Buffer Free Queue Read

0x2B4 RMAC Packet Descriptor Reference Small Buffer Free Queue End

0x2B8 RMAC Packet Descriptor Reference Ready Queue Start

0x2BC RMAC Packet Descriptor Reference Ready Queue Write

0x2C0 RMAC Packet Descriptor Reference Ready Queue Read

0x2C4 RMAC Packet Descriptor Reference Ready Queue End

0x2C8 - 0x2FC RMAC Reserved

0x300 TMAC Control

0x304 TMAC Indirect Channel Provisioning

0x308 TMAC Descriptor Table Base LSW

0x30C TMAC Descriptor Table Base MSW

0x310 TMAC Queue Base LSW

0x314 TMAC Queue Base MSW

0x318 TMAC Descriptor Reference Free Queue Start

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0x31C TMAC Descriptor Reference Free Queue Write

0x320 TMAC Descriptor Reference Free Queue Read

0x324 TMAC Descriptor Reference Free Queue End

0x328 TMAC Descriptor Reference Ready Queue Start

0x32C TMAC Descriptor Reference Ready Queue Write

0x330 TMAC Descriptor Reference Ready Queue Read

0x334 TMAC Descriptor Reference Ready Queue End

0x338 - 0x37C TMAC Reserved

0x380 THDL Indirect Channel Select

0x384 THDL Indirect Channel Data #1

0x388 THDL Indirect Channel Data #2

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0x38C THDL Indirect Channel Data #3

0x390 THDL Reserved

0x394 THDL Reserved

0x398 THDL Reserved

0x39C THDL Reserved

0x3A0 THDL Indirect Block Select

0x3A4 THDL Indirect Block Data

0x3A8 THDL Reserved

0x3AC THDL Reserved

0x3B0 THDL Configuration

0x3B4 - 0x3BC THDL Reserved

0x3C0 - 0x3FF Reserved

0x400 TCAS Indirect Channel and Time-slot Select

0x404 TCAS Indirect Channel Data

0x408 TCAS Framing Bit Threshold

0x40C TCAS Idle Time-slot Fill Data and Config.

0x410 TCAS Channel Disable

0x414 - 0x47C TCAS Reserved

0x480 TCAS Link #0 Configuration

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PCI Offset Register

0x484 - 0x49C TCAS Link #1 to Link #7 Configuration

0x4A0 - 0x4FC TCAS Reserved

0x500 PMON Status

0x504 PMON Receive FIFO Overflow Count

0x508 PMON Transmit FIFO Underflow Count

0x50C PMON Configurable Count #1

0x510 PMON Configurable Count #2

0x514 - 0x51C PMON Reserved

0x520 - 0x7FC Reserved

The following PCI configuration registers are implemented by the PCI Interface. These registers can only be accessed when the PCI Interface is a target and a configuration cycle is in progress as indicated using the IDSEL input.

PM7366 FREEDM-8

Table 15 – PCI Configuration Register Memory Map

PCI Offset Register

0x00 Vendor Identification/Device Identification

0x04 Command/Status

0x08 Revision Identifier/Class Code

0x0C Cache Line Size/Latency Timer/Header Type/BIST

0x10 CBI Memory Base Address Register

0x14 - 0x24 Unused Base Address Register

0x28 Reserved

0x2C Reserved

0x30 Reserved

0x34 Reserved

0x38 Reserved

0x3C Interrupt Line/Interrupt Pin/MIN_GNT/MAX_LAT

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10 NORMAL MODE REGISTER DESCRIPTION

Normal mode registers are used to configure and monitor the operation of the FREEDM.

Notes on Normal Mode Register Bits:

1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read.

2. Except where noted, all configuration bits that can be written into can also be read back. This allows the processor controlling the FREEDM-8 to determine the programming state of the block.

3. Writable normal mode register bits are cleared to logic zero upon reset unless otherwise noted.

4. Writing into read-only normal mode register bit locations does not affect FREEDM-8 operation unless otherwise noted.

5. Certain register bits are reserved. These bits are associated with megacell functions that are unused in this application. To ensure that the FREEDM-8 operates as intended, reserved register bits must only be written with their default values. Similarly, writing to reserved registers should be avoided.

10.1 PCI Host Accessible Registers

PCI host accessible registers can be accessed by the PCI host. For each register description below, the hexadecimal register number indicates the PCI offset from the base address in the FREEDM-8 CBI Register Base Address Register when accesses are made using the PCI Host Port.

Note

These registers are not byte addressable. Writing to any one of these registers modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to the register.

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Bit Type Function Default

Bit 31

Unused XXXXH

Bit 16

Bit 15 R/W Reset 0

Bit 14 Unused X

Bit 13 Unused X

Bit 12 Unused X

Bit 11 Unused X

Bit 10 Unused X

Bit 9 Unused X

Bit 8 Unused X

Bit 7 Unused X

Bit 6 Unused X

Bit 5 Unused X

Bit 4 Unused X

Bit 3 Unused X

Bit 2 Unused X

Bit 1 Unused X

Bit 0 Unused X

This register provides software reset capability.

Note

This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.

RESET:

The RESET bit allows the FREEDM-8 to be reset under software control. If the RESET bit is a logic one, the entire FREEDM-8 except the PCI Interface is held in reset. This bit is not self-clearing. Therefore, a logic zero must be written to bring the FREEDM-8 out of reset.

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Holding the FREEDM-8 in a reset state places it into a low power, stand-by mode. A hardware reset clears the RESET bit, thus negating the software reset.

Note

Unlike the hardware reset input (RSTB), RESET does not force the FREEDM-8's PCI pins tri-state. Transmit link data pins (TD[7:0]) are forced high. In addition, all registers except the GPIC PCI Configuration registers, are reset to their default values.

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Bit Type Function Default

Bit 31 to

Unused XXXXH

Bit 16

Bit 15 R/W TFUDRE 0

Bit 14 R/W IOCE 0

Bit 13 R/W TDFQEE 0

Bit 12 R/W TDQRDYE 0

Bit 11 R/W TDQFE 0

Bit 10 R/W RPDRQEE 0

Bit 9 R/W RPDFQEE 0

Bit 8 R/W RPQRDYE 0

Bit 7 R/W RPQLFE 0

Bit 6 R/W RPQSFE 0

Bit 5 R/W RFOVRE 0

Bit 4 R/W RPFEE 0

Bit 3 R/W RABRTE 0

Bit 2 R/W RFCSEE 0

Bit 1 R/W PERRE 0

Bit 0 R/W SERRE 0

This register provides interrupt enables for various events detected or initiated by the FREEDM.

Note

SERRE:

The system error interrupt enable bit (SERRE) enables PCI system error interrupts to the PCI host. When SERRE is set high, any address parity error, data parity error on Special Cycle commands, reception of a master abort or detection of a target abort will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when SERRE is set low.

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However, the SERRI bit remains valid when interrupts are disabled and may be polled to detect PCI system error events.

PERRE:

The parity error interrupt enable bit (PERRE) enables PCI parity error interrupts to the PCI host. When PERRE is set high, data parity errors detected by the FREEDM-8 or parity errors reported by a target will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when PERRE is set low. However, the PERRI bit remains valid when interrupts are disabled and may be polled to detect PCI parity error events.

RFCSEE:

The receive frame check sequence error interrupt enable bit (RFCSEE) enables receive FCS error interrupts to the PCI host. When RFCSEE is set high, a mismatch between the received FCS code and the computed CRC residue will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RFCSEE is set low. However, the RFCSEI bit remains valid when interrupts are disabled and may be polled to detect receive FCS error events.

RABRTE:

The receive abort interrupt enable bit (RABRTE) enables receive HDLC abort interrupts to the PCI host. When RABRTE is set high, receipt of an abort code (at least 7 contiguous 1's) will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RABRTE is set low. However, the RABRTI bit remains valid when interrupts are disabled and may be polled to detect receive abort events.

RPFEE:

The receive packet format error interrupt enable bit (RPFEE) enables receive packet format error interrupts to the PCI host. When RPFEE is set high, receipt of a packet that is longer than the maximum specified in the RHDL Maximum Packet Length register, of a packet that is shorter than 32 bits (CRC-CCITT) or 48 bits (CRC-32), or of a packet that is not octet aligned will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RPFEE is set low. However, the RPFEI bit remains valid when interrupts are disabled and may be polled to detect receive packet format error events.

RFOVRE:

The receive FIFO overrun error interrupt enable bit (RFOVRE) enables receive FIFO overrun error interrupts to the PCI host. When RFOVRE is set high, attempts to write data into the logical FIFO of a channel when it is already full will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RFOVRE is set low. However, the RFOVRI bit remains valid when interrupts are disabled and may be polled to detect receive FIFO overrun events.

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RPQSFE:

The receive packet descriptor small buffer free queue cache read interrupt enable bit (RPQSFE) enables receive packet descriptor small free queue cache read interrupts to the PCI host. When RPQSFE is set high, reading a programmable number of RPDR blocks from the RPDR Small Buffer Free Queue will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RPQSFE is set low. However, the RPQSFI bit remains valid when interrupts are disabled and may be polled to detect RPDR small buffer free queue cache read events.

RPQLFE:

The receive packet descriptor large buffer free queue cache read interrupt enable bit (RPQLFE) enables receive packet descriptor large free queue cache read interrupts to the PCI host. When RPQLFE is set high, reading a programmable number of RPDR blocks from the RPDR Large Buffer Free Queue will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RPQLFE is set low. However, the RPQLFI bit remains valid when interrupts are disabled and may be polled to detect RPDR large buffer free queue cache read events.

RPQRDYE:

The receive packet descriptor ready queue write interrupt enable bit (RPQRDYE) enables receive packet descriptor ready queue write interrupts to the PCI host. When RPQRDYE is set high, writing a programmable number of RPDRs to the RPDR Ready Queue will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RPQRDYE is set low. However, the RPQRDYI bit remains valid when interrupts are disabled and may be polled to detect RPDR ready queue write events.

RPDFQEE:

The receive packet descriptor free queue error interrupt enable bit (RPDFQEE) enables receive packet descriptor free queue error interrupts to the PCI host. When RPDFQEE is set high, attempts to retrieve an RPDR when both the large buffer and small buffer free queues are empty will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RPDFQEE is set low. However, the RPDFQEI bit remains valid when interrupts are disabled and may be polled to detect RPDR free queue empty error events.

RPDRQEE:

The receive packet descriptor ready queue error interrupt enable bit (RPDRQEE) enables receive packet descriptor ready queue error interrupts to the PCI host. When RPDRQEE is set high, attempts to write an RPDR when ready queue is ready full will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RPDRQEE is set low. However, the RPDRQEI bit remains valid when interrupts are disabled and may be polled to detect RPDR ready queue full error events.

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TDQFE:

The transmit packet descriptor free queue write interrupt enable bit (TDQFE) enables transmit packet descriptor free queue write interrupts to the PCI host. When TDQFE is set high, writing a programmable number of TDRs to the TDR Free Queue will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when TDQFE is set low. However, the TDQFI bit remains valid when interrupts are disabled and may be polled to detect TDR free queue write events.

TDQRDYE:

The transmit descriptor ready queue cache read interrupt enable bit (TDQRDYE) enables transmit descriptor ready queue cache read interrupts to the PCI host. When TDQRDYE is set high, reading a programmable number of TDRs from the TDR Ready Queue will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when TDQRDYE is set low. However, the TDQRDYI bit remains valid when interrupts are disabled and may be polled to detect TDR ready queue cache read events.

TDFQEE:

The transmit descriptor free queue error interrupt enable bit (TDFQEE) enables transmit descriptor free queue error interrupts to the PCI host. When TDFQEE is set high, attempting to write to the transmit free queue while the queue is full will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when TDFQEE is set low. However, the TDFQEI bit remains valid when interrupts are disabled and may be polled to detect TD free queue error events.

IOCE:

The transmit interrupt on complete enable bit (IOCE) enables transmission complete interrupts to the PCI host. When IOCE is set high, complete transmission of a packet with the IOC bit in the TD set high will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when IOCE is set low. However, the IOCI bit remains valid when interrupts are disabled and may be polled to detect transmission of IOC tagged packets.

TFUDRE:

The transmit FIFO underflow error interrupt enable bit (TFUDRE) enables transmit FIFO underflow error interrupts to the PCI host. When TFUDRE is set high, attempts to read data from the logical FIFO when it is already empty will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when TFUDRE is set low. However, the TFUDRI bit remains valid when interrupts are disabled and may be polled to detect transmit FIFO underflow events.

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Bit Type Function Default

Bit 31 to

Unused XXXXH

Bit 16

Bit 15 R TFUDRI X

Bit 14 R IOCI X

Bit 13 R TDFQEI X

Bit 12 R TDQRDYI X

Bit 11 R TDQFI X

Bit 10 R RPDRQEI X

Bit 9 R RPDFQEI X

Bit 8 R RPQRDYI X

Bit 7 R RPQLFI X

Bit 6 R RPQSFI X

Bit 5 R RFOVRI X

Bit 4 R RPFEI X

Bit 3 R RABRTI X

Bit 2 R RFCSEI X

Bit 1 R PERRI X

Bit 0 R SERRI X

This register reports the interrupt status for various events detected or initiated by the FREEDM. Reading this registers acknowledges and clears the interrupts.

Note

This register is not byte addressable. Reading this register clears all the interrupt bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.

SERRI:

The system error interrupt status bit (SERRI) reports PCI system error interrupts to the PCI host. SERRI is set high upon detection of any address parity error, data parity error on Special Cycle commands, reception of a master abort or detection of a target abort event.

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The SERRI bit remains valid when interrupts are disabled and may be polled to detect PCI system error events.

PERRI:

The parity error interrupt status bit (PERRI) reports PCI parity error interrupts to the PCI host. PERRI is set high when data parity errors are detected by the FREEDM-8 while acting as a master, and when parity errors are reported to the FREEDM-8 by a target via the PERRB input. The PERRI bit remains valid when interrupts are disabled and may be polled to detect PCI parity error events.

RFCSEI:

The receive frame check sequence error interrupt status bit (RFCSEI) reports receive FCS error interrupts to the PCI host. RFCSEI is set high, when a mismatch between the received FCS code and the computed CRC residue is detected. RFCSEI remains valid when interrupts are disabled and may be polled to detect receive FCS error events.

RABRTI:

The receive abort interrupt status bit (RABRTI) reports receive HDLC abort interrupts to the PCI host. RABRTI is set high upon receipt of an abort code (at least 7 contiguous 1's). RABRTI remains valid when interrupts are disabled and may be polled to detect receive abort events.

RPFEI:

The receive packet format error interrupt status bit (RPFEI) reports receive packet format error interrupts to the PCI host. RPFEI is set high upon receipt of a packet that is longer than the maximum programmed length, of a packet that is shorter than 32 bits (CRC-CCITT) or 48 bits (CRC-32), or of a packet that is not octet aligned. RPFEI remains valid when interrupts are disabled and may be polled to detect receive packet format error events.

RFOVRI:

The receive FIFO overrun error interrupt status bit (RFOVRI) reports receive FIFO overrun error interrupts to the PCI host. RFOVRI is set high on attempts to write data into the logical FIFO of a channel when it is already full. RFOVRI remains valid when interrupts are disabled and may be polled to detect receive FIFO overrun events.

RPQSFI:

The receive packet descriptor small buffer free queue cache read interrupt status bit (RPQSFI) reports receive packet descriptor small free queue cache read interrupts to the PCI host. RPQSFI is set high when the programmable number of RPDR blocks is read from the RPDR Small Buffer Free Queue. RPQSFI remains valid when interrupts are disabled and may be polled to detect RPDR small buffer free queue cache read events.

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RPQLFI:

The receive packet descriptor large buffer free queue cache read interrupt status bit (RPQLFI) reports receive packet descriptor large free queue cache read interrupts to the PCI host. RPQLFI is set high when the programmable number of RPDR blocks is read from the RPDR Large Buffer Free Queue. RPQLFI remains valid when interrupts are disabled and may be polled to detect RPDR large buffer free queue cache read events.

RPQRDYI:

The receive packet descriptor ready queue write interrupt status bit (RPQRDYI) reports receive packet descriptor ready queue write interrupts to the PCI host. RPQRDYI is set high when the programmable number of RPDRs is written to the RPDR Ready Queue. RPQRDYI remains valid when interrupts are disabled and may be polled to detect RPDR ready queue write events.

RPDFQEI:

The receive packet descriptor free queue error interrupt status bit (RPDFQEI) reports receive packet descriptor free queue error interrupts to the PCI host. RPDFQEI is set high upon attempts to retrieve an RPDR when both the large buffer and small buffer free queues are empty. RPDFQEI remains valid when interrupts are disabled and may be polled to detect RPDR free queue empty error events.

RPDRQEI:

The receive packet descriptor ready queue error interrupt status bit (RPDRQEI) reports receive packet descriptor ready queue error interrupts to the PCI host. RPDRQEI is set high upon attempts to write an RPDR when ready queue is ready full. RPDRQEI remains valid when interrupts are disabled and may be polled to detect RPDR ready queue full error events.

TDQFI:

The transmit packet descriptor free queue write interrupt status bit (TDQFI) reports transmit packet descriptor free queue write interrupts to the PCI host. TDQFI is set high when the programmable number of TDRs is written to the TDR Free Queue. TDQFI remains valid when interrupts are disabled and may be polled to detect TDR free queue write events.

TDQRDYI:

The transmit descriptor ready queue cache read interrupt status bit (TDQRDYI) reports transmit descriptor ready queue cache read interrupts to the PCI host. TDQRDYI is set high when the programmable number of TDRs is read from the TDR Ready Queue. TDQRDYI remains valid when interrupts are disabled and may be polled to detect TDR ready queue cache read events.

TDFQEI:

The transmit descriptor free queue error interrupt status bit (TDFQEI) reports transmit descriptor free queue error interrupts to the PCI host. TDFQEI is set high when an attempt to

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write to the transmit free queue fail due to the queue being already full. TDFQEI bit remains valid when interrupts are disabled and may be polled to detect TD free queue error events.

IOCI:

The transmit interrupt on complete status bit (IOCI) reports transmission complete interrupts to the PCI host. IOCI is set high, when a packet with the IOC bit in the TD set high is completely transmitted. IOCI remains valid when interrupts are disabled and may be polled to detect transmission of IOC tagged packets.

TFUDRI:

The transmit FIFO underflow error interrupt status bit (TFUDRI) reports transmit FIFO underflow error interrupts to the PCI host. TFUDRI is set high upon attempts to read data from the logical FIFO when it is already empty. TFUDRI remains valid when interrupts are disabled and may be polled to detect transmit FIFO underflow events.

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Bit Type Function Default

Bit 31 to

Unused XXXXH

Bit 16

Bit 15 Unused X

Bit 14 Unused X

Bit 13 Unused X

Bit 12 Unused X

Bit 11 Unused X

Bit 10 Unused X

Bit 9 Unused X

Bit 8 Unused X

Bit 7 Unused X

Bit 6 Unused X

Bit 5 Unused X

Bit 4 Unused X

Bit 3 Unused X

Bit 2 Unused X

Bit 1 R TBDA X

Bit 0 R SYSCLKA X

This register provides activity monitoring on FREEDM-8 clock inputs and BERT port input. When a monitored input makes a low to high transition, the corresponding register bit is set high. The bit will remain high until this register is read, at which point, all the bits in this register are cleared. A lack of transitions is indicated by the corresponding register bit reading low. This register should be read periodically to detect for stuck at conditions.

Writing to this register delimits the accumulation intervals in the PMON accumulation registers. Counts accumulated in those registers are transferred to holding registers where they can be read. The counters themselves are then cleared to begin accumulating events for a new accumulation interval. The bits in this register are not affected by write accesses.

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PMC PM7366-BI, PM7366-PI Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

REVISION HISTORY

CONTENTS

LIST OF REGISTERS

LIST OF FIGURES

LIST OF TABLES

9.1 High-Level Data Link Control Protocol

9.3 Receive HDLC Processor / Partial Packet Buffer

9.4 Receive DMA Controller

9.6 Transmit DMA Controller

9.7 Transmit HDLC Controller / Partial Packet Buffer

10 NORMAL MODE REGISTER DESCRIPTION