PMC PM4351-NI, PM4351-RI, PM7366 Datasheet

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

PM4351

COMET

COMBINED E1/T1

TRANSCEIVER/FRAMER

DATA SHEET

ISSUE10: NOVEMBER 2000

PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

LIST OF REGISTERS

Register 000H: Global Configuration................................................................ 76

Register 001H: Clock Monitor........................................................................... 78

Register 002H: Receive Options....................................................................... 80

Register 003H: Receive Line Interface Configuration....................................... 82

Register 004H: Transmit Line Interface Configuration...................................... 85

Register 005H: Transmit Framing and Bypass Options.................................... 87

Register 006H: Transmit Timing Options.......................................................... 90

Register 007H: Interrupt Source #1.................................................................. 95

Register 008H: Interrupt Source #2.................................................................. 96

Register 009H: Interrupt Source #3.................................................................. 97

Register 00AH: Master Diagnostics.................................................................. 98

Register 00BH: Master Test............................................................................ 100

Register 00CH: Analog Diagnostics................................................................ 102

Register 00DH: Revision/Chip ID/Global PMON Update................................ 103

Register 00EH: Reset..................................................................................... 104

Register 00FH: PRGD Positioning/Control and HDLC Control....................... 105

Register 010H: CDRC Configuration.............................................................. 108

Register 011H: CDRC Interrupt Control...........................................................110

Register 012H: CDRC Interrupt Status............................................................111

Register 013H: Alternate Loss of Signal Status...............................................113

Register 014H: RJAT Interrupt Status..............................................................114

Register 015H: RJAT Divider N1 Control.........................................................115

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STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Register 016H: RJAT Divider N2 Control.........................................................116

Register 017H: RJAT Configuration.................................................................117

Register 018H: TJAT Interrupt Status..............................................................119

Register 019H: TJAT Jitter Attenuator Divider N1 Control.............................. 120

Register 01AH: TJAT Divider N2 Control........................................................ 121

Register 01BH: TJAT Configuration................................................................ 123

Register 01CH: RX-ELST Configuration ......................................................... 125

Register 01DH: RX-ELST Interrupt Enable/Status.......................................... 126

Register 01EH: RX-ELST Idle Code............................................................... 127

Register 020H: TX-ELST Configuration.......................................................... 128

Register 021H: TX-ELST Interrupt Enable/Status........................................... 129

Register 028H: RXCE Receive Data Link 1 Control....................................... 130

Register 029H: RXCE Receive Data Link 1 Bit Select.................................... 132

Register 02AH: RXCE Receive Data Link 2 Control....................................... 133

Register 02BH: RXCE Receive Data Link 2 Bit Select................................... 134

Register 02CH: RXCE Receive Data Link 3 Control....................................... 135

Register 02DH: RXCE Receive Data Link 3 Bit Select................................... 136

Register 030H: BRIF Configuration................................................................ 137

Register 031H: BRIF Frame Pulse Configuration........................................... 140

Register 032H: BRIF Parity/F-bit Configuration.............................................. 144

Register 033H: BRIF Time Slot Offset............................................................ 146

Register 034H: BRIF Bit Offset....................................................................... 147

Register 038H: TXCI Transmit Data Link 1 Control ........................................ 149

Register 039H: TXCI Transmit Data Link 1 Bit Select..................................... 151

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DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Register 03AH: TXCI Transmit Data Link 2 Control........................................ 152

Register 03BH: TXCI Transmit Data Link 2 Bit Select.................................... 153

Register 03CH: TXCI Transmit Data Link 3 Control........................................ 154

Register 03DH: TXCI Transmit Data Link 3 Bit Select.................................... 155

Register 040H: BTIF Configuration................................................................. 156

Register 041H: BTIF Frame Pulse Configuration........................................... 159

Register 042H: BTIF Parity Configuration and Status..................................... 161

Register 043H: BTIF Time Slot Offset ............................................................ 163

Register 044H: BTIF Bit Offset....................................................................... 164

Register 048H: T1 FRMR Configuration......................................................... 166

Register 049H: T1 FRMR Interrupt Enable..................................................... 168

Register 04AH: T1 FRMR Interrupt Status...................................................... 170

Register 04CH: IBCD Configuration ............................................................... 172

Register 04DH: IBCD Interrupt Enable/Status................................................ 173

Register 04EH: IBCD Activate Code............................................................... 175

Register 04FH: IBCD Deactivate Code........................................................... 176

Register 050H: SIGX Configuration Register (COSS = 0)............................. 177

Register 050H: SIGX Change of Signaling State Register (COSS = 1).......... 179

Register 051H: SIGX Timeslot Indirect Status (COSS = 0)............................ 180

Register 051H: SIGX Change Of Signaling State Change (COSS=1)............ 181

Register 052H: SIGX Timeslot Indirect Address/Control (COSS = 0)............. 182

Register 052H: SIGX Change of Signaling State Register (COSS = 1).......... 183

Register 053H: SIGX Timeslot Indirect Data Buffer (COSS = 0) .................... 184

Register 053H: SIGX Change of Signaling State (COSS = 1)........................ 185

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STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Register 054H: T1 XBAS Configuration.......................................................... 191

Register 055H: T1 XBAS Alarm Transmit....................................................... 193

Register 056H: T1 XIBC Control..................................................................... 194

Register 057H: T1 XIBC Loopback Code....................................................... 196

Register 058H: PMON Interrupt Enable/Status............................................... 197

Register 059H: PMON Framing Bit Error Count............................................. 199

Register 05AH: PMON OOF/COFA/Far End Block Error Count LSB ............. 200

Register 05BH: PMON OOF/COFA/Far End Block Error Count MSB ............ 201

Register 05CH: PMON Bit Error/CRC Error Count LSB ................................. 202

Register 05DH: PMON Bit Error/CRC Error Count MSB ................................ 203

Register 05EH: PMON LCV Count (LSB)....................................................... 204

Register 05FH: PMON LCV Count (MSB) ...................................................... 205

Register 060H: T1 ALMI Configuration ........................................................... 206

Register 061H: T1 ALMI Interrupt Enable....................................................... 208

Register 062H: T1 ALMI Interrupt Status........................................................ 209

Register 063H: T1 ALMI Alarm Detection Status............................................ 210

Register 065H: T1 PDVD Interrupt Enable/Status.......................................... 212

Register 067H: T1 XBOC Code...................................................................... 214

Register 069H: T1 XPDE Interrupt Enable/Status .......................................... 215

Register 06AH: T1 RBOC Enable................................................................... 217

Register 06BH: T1 RBOC Code Status .......................................................... 218

Register 06CH: TPSC Configuration .............................................................. 219

Register 06DH: TPSC µP Access Status........................................................ 220

Register 06EH: TPSC Channel Indirect Address/Control ............................... 221

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DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

Register 06FH: TPSC Channel Indirect Data Buffer....................................... 222

Register 070H: RPSC Configuration............................................................... 231

Register 071H: RPSC µP Access Status........................................................ 232

Register 072H: RPSC Channel Indirect Address/Control ............................... 233

Register 073H: RPSC Channel Indirect Data Buffer....................................... 234

Register 078H: T1 APRM Configuration/Control............................................. 239

Register 079H: T1 APRM Manual Load.......................................................... 241

Register 07AH: T1 APRM Interrupt Status...................................................... 242

Register 07BH: T1 APRM One Second Content Octet 2................................ 243

Register 07CH: T1 APRM One Second Content Octet 3................................ 244

Register 07DH: T1 APRM One Second Content Octet 4................................ 245

Register 07EH: T1 APRM One Second Content MSB (Octet 5)..................... 246

Register 07FH: T1 APRM One Second Content LSB (Octet 6)..................... 248

Register 080H: E1 TRAN Configuration ......................................................... 250

Register 081H: E1 TRAN Transmit Alarm/Diagnostic Control......................... 253

Register 082H: E1 TRAN International/National Control................................ 255

Register 083H: E1 TRAN Extra Bits Control................................................... 256

Register 084H: E1 TRAN Interrupt Enable..................................................... 257

Register 085H: E1 TRAN Interrupt Status...................................................... 259

Register 086H: E1 TRAN National Bits Codeword Select.............................. 261

Register 087H: E1 TRAN National Bits Codeword......................................... 263

Register 090H: E1 FRMR Frame Alignment Options...................................... 265

Register 091H: E1 FRMR Maintenance Mode Options .................................. 267

Register 092H: E1 FRMR Framing Status Interrupt Enable............................ 269

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PM4351 COMET

Register 093H: E1 FRMR Maintenance/Alarm Status Interrupt Enable.......... 270

Register 094H: E1 FRMR Framing Status Interrupt Indication ....................... 271

Register 095H: E1 FRMR Maintenance/Alarm Status Interrupt Indication...... 272

Register 096H: E1 FRMR Framing Status...................................................... 273

Register 097H: E1 FRMR Maintenance/Alarm Status.................................... 275

Register 098H: E1 FRMR Timeslot 0 International/National Bits.................... 277

Register 099H: E1 FRMR CRC Error Counter - LSB...................................... 279

Register 09AH: E1 FRMR CRC Error Counter – MSB/Timeslot 16 Extra Bits 280

Register 09BH: E1 FRMR National Bit Codeword Interrupt Enables.............. 283

Register 09CH: E1 FRMR National Bit Codeword Interrupts.......................... 285

Register 09DH: E1 FRMR National Bit Codeword.......................................... 286

Register 09EH: E1 FRMR Frame Pulse/Alarm/V5.2 Link ID Interrupt Enables287

Register 09FH: E1 FRMR Frame Pulse/Alarm Interrupts............................... 289

Register 0A8H (#1), 0B0H (#2), 0B8H (#3): TDPR Configuration .................. 291

Register 0A9H (#1), 0B1H (#2), 0B9H (#3): TDPR Upper Transmit Threshold293 Register 0AAH (#1), 0B2H (#2), 0BAH (#3): TDPR Lower Interrupt Threshold294

Register 0ABH (#1), 0B3H (#2), 0BBH (#3): TDPR Interrupt Enable............. 295

Register 0ACH (#1), 0B4H (#2), 0BCH (#3): TDPR Interrupt Status.............. 296

Register 0ADH (#1), 0B5H (#2), 0BDH (#3): TDPR Transmit Data ................ 298

Registers 0C0H (#1), 0C8H (#2), 0D0H (#3): RDLC Configuration................ 299

Registers 0C1H (#1), 0C9H (#2), 0D1H (#3): RDLC Interrupt Control ........... 301

Registers 0C2H (#1), 0CAH (#2), 0D2H (#3): RDLC Status........................... 302

Registers 0C3H (#1), 0CBH (#2), 0D3H (#3): RDLC Data ............................. 305

Registers 0C4H (#1), 0CCH (#2), 0D4H (#3): RDLC Primary Address Match 306

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PM4351 COMET

Registers 0C5H (#1), 0CDH (#2), 0D5H (#3): RDLC Secondary Address Match

............................................................................................................. 307

Register 0D6H: CSU Configuration ................................................................ 308

Register 0D8H: RLPS Equalization Indirect Data........................................... 310

Register 0D9H: RLPS Equalization Indirect Data............................................311

Register 0DAH: RLPS Equalization Indirect Data........................................... 312

Register 0DBH: RLPS Equalization Indirect Data........................................... 313

Register 0DCH: RLPS Equalizer Voltage Reference...................................... 314

Register 0E0H: PRGD Control........................................................................ 315

Register 0E1H: PRGD Interrupt Enable/Status............................................... 317

Register 0E2H: PRGD Shift Register Length.................................................. 319

Register 0E3H: PRGD Tap ............................................................................. 320

Register 0E4H: PRGD Error Insertion ............................................................ 321

Register 0E8H: PRGD Pattern Insertion #1.................................................... 322

Register 0E9H: PRGD Pattern Insertion #2.................................................... 323

Register 0EAH: PRGD Pattern Insertion #3 ................................................... 324

Register 0EBH: PRGD Pattern Insertion #4 ................................................... 325

Register 0ECH: PRGD Pattern Detector #1 ................................................... 326

Register 0EDH: PRGD Pattern Detector #2 ................................................... 327

Register 0EEH: PRGD Pattern Detector #3.................................................... 328

Register 0EFH: PRGD Pattern Detector #4.................................................... 329

Register 0F0H: XLPG Line Driver Configuration.............................................330

Register 0F1H: XLPG Control/Status.............................................................. 332

Register 0F2H: XLPG Pulse Waveform Storage Write Address..................... 333

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PM4351 COMET

Register 0F3H: XLPG Pulse Waveform Storage Data.................................... 334

Register 0F4H: XLPG Analog Test Negative Control...................................... 335

Register 0F5H: XLPG Analog Test Positive Control........................................ 336

Register 0F6H: XLPG Fuse Data Select......................................................... 337

Register 0F8H: RLPS Configuration and Status............................................. 338

Register 0F9H: RLPS ALOS Detection/Clearance Threshold......................... 340

Register 0FAH: RLPS ALOS Detection Period............................................... 342

Register 0FBH: RLPS ALOS Clearance Period.............................................. 343

Register 0FCH: RLPS Equalization Indirect Address...................................... 344

Register 0FDH: RLPS Equalization Read/WriteB Select................................ 345

Register 0FEH: RLPS Equalizer Loop Status and Control.............................. 346

Register 0FFH: RLPS Equalizer Configuration............................................... 347

Register 00BH: COMET Master Test .............................................................. 350

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PM4351 COMET

LIST OF FIGURES

Figure 1 - Wireless Base Station Application ................................................11

Figure 2 - V5.1 Interface Application............................................................ 12

Figure 3 PM4351-RI COMET Pin Diagram.................................................. 17

Figure 4 PM4351-NI COMET Pin Diagram.................................................. 18

Figure 5 - External Analog Interface Circuits................................................ 33

Figure 6 - T1 Jitter Tolerance ....................................................................... 37

Figure 7 - Compliance with ITU-T Specification G.823 for E1 Input Jitter .... 38

Figure 8 - CRC Multiframe Alignment Algorithm........................................... 43

Figure 9 - TJAT Jitter Tolerance ................................................................... 59

Figure 10 - TJAT Minimum Jitter Tolerance vs. XCLK Accuracy .................... 60

Figure 11 - TJAT Jitter Transfer...................................................................... 61

Figure 12 - Transmit Timing Options.............................................................. 94

Figure 13 - Transmit Backplane: CMS=0, FE=1, DE=1, BTFP is Input........... 356

Figure 14 - Transmit Backplane: CMS=0, FE=1, DE=0, BTFP is Input........... 356

Figure 15 - Transmit Backplane: CMS=1, FE=1, DE=1, BTFP is Input........... 356

Figure 16 - Transmit Backplane: CMS=1, FE=0, DE=1, BTFP is Input.......... 356

Figure 17 - Transmit Backplane: CMS=0, FE=1, DE=1, BTFP is Output........ 357

Figure 18 - Transmit Backplane: CMS=0, FE=1, DE=0, BTFP is Output........ 357

Figure 19 - Transmit Backplane at 1.544 Mbit/s (T1 mode)......................... 357

Figure 20 - Transmit Backplane at 2.048 Mbit/s (T1 mode)......................... 358

Figure 21 - Transmit Backplane at 2.048 Mbit/s (E1 mode)......................... 359

Figure 22 - Transmit Backplane at 4.096 Mbit/s (T1 mode)......................... 359

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PM4351 COMET

Figure 23 - Transmit Backplane at 4.096 Mbit/s (E1 mode)......................... 360

Figure 24 - Transmit Backplane at 8.192 Mbit/s (T1 mode)......................... 360

Figure 25 - Transmit Backplane at 8.192 Mbit/s (E1 mode)......................... 361

Figure 26 - Concentration Highway Interface Timing, Example 1 ................ 361

Figure 27 - Concentration Highway Interface Timing, Example 2 ................ 361

Figure 28 - Receive Backplane at 1.544 Mbit/s (T1 Mode).......................... 362

Figure 29 - Receive Backplane at 2.048 Mbit/s (T1 Mode).......................... 363

Figure 30 - Receive Backplane at 2.048 Mbit/s (E1 Mode).......................... 363

Figure 31 - Receive Backplane at 4.096 Mbit/s (T1 Mode)......................... 364

Figure 32 - Receive Backplane at 4.096 Mbit/s (E1 Mode)......................... 364

Figure 33 - Receive Backplane at 8.192 Mbit/s (T1 Mode)......................... 365

Figure 34 - Receive Backplane at 8.192 Mbit/s (E1 Mode)......................... 365

Figure 35 - Concentration Highway Interface Timing, Example 1 ............... 366

Figure 36 - Concentration Highway Interface Timing, Example 2 ............... 366

Figure 37 - Typical Data Frame.................................................................... 377

Figure 38 - Pattern Generator Structure....................................................... 414

Figure 39 - Line Loopback........................................................................... 418

Figure 40 - Payload Loopback..................................................................... 419

Figure 41 - Diagnostic Digital Loopback....................................................... 420

Figure 42 - LCV Count vs. BER (E1 mode).................................................. 424

Figure 43 - FER Count vs. BER (E1 mode) ................................................. 424

Figure 44 - CRCE Count vs. BER (E1 mode).............................................. 425

Figure 45 - LCV Count vs. BER (T1 mode).................................................. 426

Figure 46 - FER Count vs. BER (T1 ESF mode).......................................... 426

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PM4351 COMET

Figure 47 - CRCE Count vs. BER (T1 ESF mode)....................................... 427

Figure 48 - CRCE Count vs. BER (T1 SF mode)......................................... 427

Figure 49 - Boundary Scan Architecture ...................................................... 428

Figure 50 - TAP Controller Finite State Machine.......................................... 430

Figure 51 - Input Observation Cell (IN_CELL) ............................................. 435

Figure 52 - Output Cell (OUT_CELL)........................................................... 436

Figure 53 - Bidirectional Cell (IO_CELL)...................................................... 436

Figure 54 - Layout of Output Enable and Bidirectional Cells........................ 437

Figure 55 - Microprocessor Read Access Timing......................................... 443

Figure 56 - Microprocessor Write Access Timing......................................... 445

Figure 57 - Backplane Transmit Input Timing Diagram................................ 447

Figure 58 - Backplane Transmit Output Timing Diagram ............................. 448

Figure 59 - Backplane Receive Input Timing Diagram................................. 450

Figure 60 - Backplane Receive Output Timing Diagram.............................. 451

Figure 61 - Digital Receive Interface Timing Diagram.................................. 453

Figure 62 - Digital Transmit Interface Timing Diagram................................. 454

Figure 63 - JTAG Port Interface Timing........................................................ 456

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PM4351 COMET

LIST OF TABLES

Table 1 - Backplane Transmit Interface (4 pins)......................................... 19

Table 2 - Backplane Receive Interface (4 pins).......................................... 21

Table 3 - Transmit Line Interface (6 pins) ................................................... 23

Table 4 - Receive Line Interface (4 pins).................................................... 24

Table 5 - Timing Options Control (5 pins) ................................................... 24

Table 6 - Analog Support Circuitry (4 pins)................................................. 25

Table 7 - JTAG (IEEE 1149.1) Boundary Scan Test Interface (5 pins)........ 26

Table 8 - Microprocessor Interface (23 pins).............................................. 26

Table 9 - Power and Ground (25 pins)........................................................ 28

Table 10 - PM4351-RI Pin Summary............................................................ 30

Table 11 PM4351-NI Pin Summary.............................................................. 30

Table 12 - External Component Descriptions............................................... 34

Table 13 - Typical Input Return Loss at Receiver ......................................... 35

Table 14 - Termination Resistors, Transformer Ratios and TRL................... 35

Table 15 - E1-FRMR Framing States............................................................ 44

Table 16 - Normal Mode Register Memory Map........................................... 66

Table 17 - TJAT FIFO Output Clock Source................................................ 90

Table 18 - TJAT PLL Source......................................................................... 91

Table 19 - Transmit Timing Options Summary.............................................. 91

Table 20 - Loss of Signal Thresholds.......................................................... 109

Table 21 - Receive Backplane NXDS0 Mode Selection ............................. 137

Table 22 - Receive Backplane Rate............................................................ 139

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Table 23 - E1 Receive Backplane Frame Pulse Configurations................. 142

Table 24 - Receive Backplane Tri-state Control.......................................... 145

Table 25 - Receive Backplane Bit Offset for CMS = 0................................ 148

Table 26 - Receive Backplane Bit Offset for CMS = 1................................ 148

Table 27 - Transmit Backplane NXDS0 Mode Selection............................. 156

Table 28 - Transmit Backplane Rate........................................................... 158

Table 29 - Transmit Backplane Bit Offset for CMS = 0............................... 165

Table 30 - Transmit Backplane Bit Offset for CMS = 1............................... 165

Table 31 - T1 Framing Modes..................................................................... 167

Table 32 - Loopback Code Configurations ................................................. 172

Table 33 - SIGX Indirect Register Map....................................................... 185

Table 34 - SIGX Indirect Registers 10H - 1FH: Current Timeslot/Channel

Signaling Data ................................................................................................ 187

Table 35 - SIGX Indirect Registers 20H - 3FH: Delayed Timeslot/Channel

Signaling Data ................................................................................................ 188

Table 36 - Indirect Registers 40H - 5FH: Per-Timeslot Configuration......... 188

Table 37 - SIGX Per-Channel T1 Data Conditioning................................... 189

Table 38 - SIGX Per-Channel E1 Data Conditioning.................................. 189

Table 39 - T1 Framing Formats.................................................................. 192

Table 40 - T1 Zero Code Suppression Formats.......................................... 192

Table 41 - Transmit In-band Code Length.................................................. 194

Table 42 - T1 Framing Modes..................................................................... 207

Table 43 - TPSC Indirect Register Map...................................................... 222

Table 44 - TPSC Indirect Registers 20H-3FH: PCM Data Control byte...... 224

Table 45 - TPSC Transmit Data Conditioning............................................. 225

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Table 46 - Transmit Test Pattern Modes..................................................... 225

Table 47 - Transmit Zero Code Suppression Formats................................ 226

Table 48 - TPSC Indirect Registers 40H-5FH: IDLE Code byte.................. 227

Table 49 - TPSC Indirect Registers 60H-7FH: Signaling/E1 Control byte... 227

Table 50 - Transmit Per-timeslot Data Manipulation................................... 228

Table 51 - A-Law Digital Milliwatt Pattern.................................................... 228

Table 52 - µ-Law Digital Milliwatt Pattern.................................................... 229

Table 53 - RPSC Indirect Register Map ...................................................... 234

Table 54 - RPSC Indirect Registers 20H-3FH: PCM Data Control byte...... 236

Table 55 - Receive Test Pattern Modes...................................................... 236

Table 56 - RPSC Indirect Registers 40H-5FH: Data Trunk Conditioning Code byte 238

Table 57 - RPSC Indirect Registers 61H-7FH: Signaling Trunk Conditioning byte 238

Table 58 - NmNi Settings............................................................................ 249

Table 59 - E1 Signaling Insertion Mode...................................................... 250

Table 60 - E1 Timeslot 0 Bit 1 Insertion Control Summary......................... 252

Table 61 - National Bits Codeword Select .................................................. 262

Table 62 - Timeslot 0 Bit Position Allocation............................................... 278

Table 63 - Signaling Multiframe Timeslot 16, Frame 0 Bit Positions........... 282

Table 64 - E1 FRMR Codeword Select....................................................... 284

Table 65 - Receive Packet Byte Status....................................................... 302

Table 66 - Clock Synthesis Mode ............................................................... 308

Table 67 - Pattern Detector Register Configurations.................................. 315

Table 68 - Error Insertion Rates.................................................................. 321

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Table 69 - Transmit Output Amplitude........................................................ 331

Table 70 - ALOS Detection/Clearance Thresholds..................................... 340

Table 71 - Equalization Feedback Frequencies.......................................... 347

Table 72 - Valid Period................................................................................ 348

Table 73 - Observing Inputs in Test Mode 0 ............................................... 351

Table 74 - Controlling Outputs in Test Mode 0............................................ 352

Table 75 - Boundary Scan Register............................................................ 354

Table 76 - Default Settings ......................................................................... 367

Table 77 - ESF Frame Format.................................................................... 368

Table 78 - SLC®96 Frame Format ............................................................. 369

Table 79 - SF Frame Format ...................................................................... 370

Table 80 - T1DM Frame Format................................................................. 370

Table 81 - E1 Frame Format....................................................................... 371

Table 82 - PMON Polling Sequence........................................................... 372

Table 83 - ESF FDL Processing ................................................................. 373

Table 84 - Performance Report Message Structure and Contents............. 380

Table 85 - Performance Report Message Structure Notes......................... 380

Table 86 - Performance Report Message Contents.................................... 381

Table 87 - Transmit Waveform Values for T1 Long Haul (LBO 0 dB):........ 382

Table 88 - Transmit Waveform Values for T1 Long Haul (LBO 7.5 dB):..... 383

Table 89 - Transmit Waveform Values for T1 Long Haul (LBO 15 dB):...... 384

Table 90 - Transmit Waveform Values for T1 Long Haul (LBO 22.5 dB): ... 385

Table 91 - Transmit Waveform Values for T1 Short Haul (0 - 110 ft.):........ 386

Table 92 - Transmit Waveform Values for T1 Short Haul (110 – 220 ft.):.... 387

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Table 93 - Transmit Waveform Values for T1 Short Haul (220 – 330 ft.): ... 388 Table 94 - Transmit Waveform Values for T1 Short Haul (330 – 440 ft.): ... 389 Table 95 - Transmit Waveform Values for T1 Short Haul (440 – 550 ft.): ... 390 Table 96 - Transmit Waveform Values for T1 Short Haul (550 – 660 ft.): ... 391 Table 97 - TR62411 Transmit Waveform Values for T1 Long Haul (LBO 0 dB):

392

Table 98 - TR62411 Transmit Waveform Values for T1 Short Haul (0 - 110 ft.):

393

Table 99 - TR62411 Transmit Waveform Values for T1 Short Haul (110 – 220 ft.): 394

Table 100 - TR62411 Transmit Waveform Values for T1 Short Haul (220 – 330 ft.): 395

Table 101 - TR62411 Transmit Waveform Values for T1 Short Haul (330 – 440 ft.): 396

Table 102 - TR62411 Transmit Waveform Values for T1 Short Haul (440 – 550 ft.): 397

Table 103 - TR62411 Transmit Waveform Values for T1 Short Haul (550 – 660 ft.): 398

Table 104 - Transmit Waveform Values for E1 120 Ohm:............................. 399

Table 105 - Transmit Waveform Values for E1 75 Ohm:............................... 400

Table 106 - RLPS Register Programming....................................................... 401

Table 107 - RLPS Equalizer RAM Table (T1 mode) ..................................... 402

Table 108 - RLPS Equalizer RAM Table (E1 mode) ..................................... 407

Table 109 - RLPS Equalizer Lookup Table for T1 Performance Monitor Mode412

Table 110 - Pseudo-Random Pattern Generation (PS bit = 0) ..................... 415

Table 111 - Repetitive Pattern Generation (PS bit = 1).................................416

Table 112 - PMON Counter Saturation Limits (E1 mode)............................. 423

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Table 113 - PMON Counter Saturation Limits (T1 mode)............................. 423

Table 114 - Boundary Scan Register............................................................ 433

Table 115 - D.C. Characteristics................................................................... 439

Table 116 - Microprocessor Read Access (Figure 55).................................. 442

Table 117 - Microprocessor Write Access (Figure 56).................................. 444

Table 118 - Transmit Backplane Interface.................................................... 446

Table 119 - Receive Backplane Interface..................................................... 448

Table 120 - Receive Digital Interface............................................................ 452

Table 121 - Transmit Digital Interface........................................................... 453

Table 122 - JTAG Port Interface................................................................... 455

Table 123 - Ordering Information.................................................................. 458

Table 124 - Thermal Information................................................................... 458

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DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

1 FEATURES

• Monolithic device which integrates software selectable full-featured T1 and

E1 framers and T1 and E1 short haul and long haul line interfaces.

• Meets or exceeds T1 and E1 shorthaul and longhaul network access

specifications including AN SI T1.102, T1.403, T1.408, AT&T TR 62411, ITU-T G.703, G.704 as well as ETSI 300-011, CTR-4, CTR-12 and CTR-13.

• Provides encoding and decoding of B8ZS, HDB3 and AMI line codes.

• Provides receive equalization, clock recovery and line performance

monitoring.

• Provides transmit jitter attenuation and digitally programmable long haul and

short haul line build out.

• Provides on-board programmable binary sequence generators and detectors

for error testing including support for patterns recommended in ITU-T O.151.

• Provides three full-featured HDLC controllers, each with 128-byte transmit

and receive FIFO buffers.

• Automatically generates and transmits DS-1 performance report messages to

ANSI T1.231 and ANSI T1.408 specifications.

• Compatible with Mitel ST®-bus, A T&T CHI® and MVIP PCM backplanes,

supporting rates of 1.544 Mbit/s, 2.048 Mbit/s, 4.096 Mbit/s, and 8.192 Mbit/s. Up to four COMET devices may be byte-interleaved on a single backplane with no external circuitry.

• Supports NxDS0 fractional bandwidth backplane.

• Provides an 8-bit microprocessor bus interface for configuration, control, and

status monitoring.

• Uses line rate system clock.

• Provides a IEEE P1149.1 (JTAG) compliant test access port (TAP) and

controller for boundary scan test.

• Implemented in a low power 5 V tolerant +3.3 V CMOS technology.

PROPRIETARY AND CONFIDENTIAL

1

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

• Available in a high density 80-pin MQFP (14 mm by 14 mm) package or an

81-ball CABGA (9 mm by 9 mm) package.

• Provides a -40°C to +85°C Industrial temperature operating range.

1.1 Receiver section:

• Guaranteed T1 signal reception for distances with up to 36 dB of cable

attenuation under production test conditions (772 kHz, VDD = 3.069V and 25°C) using PIC 22 gauge cable emulation.

• Guaranteed E1 signal reception for distances with up to 36 dB of cable

attenuation under production test conditions (1.024 MHz, VDD = 3.069V and 25°C) using PIC 22 gauge cable emulation.

• Recovers clock and data using a digital phase locked loop for high jitter

tolerance.

• Provides an alternative digital interface for applications without line interface

units.

• Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals.

The framing procedures are consistent ITU-T G.706 specifications.

• Frames to DSX/DS-1 signals in D4, SF, ESF and SLC®96 formats.

• Frames to TTC JT-G704 multiframe formatted J1 signals. Supports the

alternate CRC-6 calculation for Japanese applications.

• Frames in the presence of and detects the “Japanese Yellow” alarm.

• Tolerates more than 0.3 UI peak-to-peak, high frequency jitter as required by

AT&T TR 62411 and Bellcore TR-TSY-000170.

• Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving

192-bit window.

• Provides loss of signal detection as per ITU-T G.775 and ANSI T1.231. Red,

Yellow, and AIS alarm detection and integration are according to ANSI T1.231 specifications.

• Provides programmable in-band loopback activate and deactivate code

detection.

PROPRIETARY AND CONFIDENTIAL

2

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

• Supports line and path performance monitoring according to AT&T and ANSI

specifications. Accumulators are provided for counting ESF CRC-6 errors, framing bit errors, line code violations and loss of frame or change of frame alignment events.

• Provides ESF bit-oriented code detection and an HDLC/LAPD interface for

terminating the ESF facility data link.

• Supports polled or interrupt-driven servicing of the HDLC interface.

• Extracts the data link in ESF and T1DM (DDS) modes. Optionally extracts a

datalink in the E1 national use bits.

• Extracts 4-bit codewords from the E1 national use bits as specified in

ETS 300 233

• Extracts up to three HDLC links from arbitrary time slots to support the D-

channel for ISDN Primary Rate Interfaces and the C-channels for V5.1/V5.2 interfaces.

• Detects the V5.2 link identification signal.

• Provides a two-frame elastic store buffer for backplane rate adaptation that

performs controlled slips and indicates slip occurrence and direction.

• Provides DS-1 robbed bit signaling extraction, with optional data inversion,

programmable idle code substitution, digital milliwatt code substitution, bit fixing, and two superframes of signaling debounce on a per-channel basis.

• Frames to the E1 signaling multiframe alignment when enabled and extracts

channel associated signaling. Alternatively, a common channel signaling data link may be extracted from timeslot 16.

• Can be programmed to generate an interrupt on change of signaling state.

• Provides trunk conditioning which forces programmable trouble code

substitution and signaling conditioning on all channels or on selected channels.

• Provides diagnostic, line loopbacks and per-DS0 line loopback.

• Provides an integral pattern detector that may be programmed to detect

common pseudo-random sequences. The programmed sequence may be detected in the entire frame, or on an NxDS0 basis.

PROPRIETARY AND CONFIDENTIAL

3

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

• Provides an integral pattern generator that may be programmed to generate

common pseudo-random or repetitive sequences towards the backplane.

• Provides tristateable single-rail PCM and signaling data outputs for

1.544 Mbit/s, 2.048 Mbit/s, 4.096 Mbit/s or 8.192 Mbit/s backplane buses.

1.2 Transmitter section:

• Supports transfer of transmitted single rail PCM and signaling data from

1.544 Mbit/s, 2.048 Mbit/s, 4.096 Mbit/s or 8.192 Mbit/s backplane buses.

• Generates DSX-1 shorthaul and DS-1 longhaul pulses with programmable

pulse shape compatible with AT&T, ANSI and ITU requirements.

• Generates E1 pulses compliant to G.703 recommendations.

• Provides a digitally programmable pulse shape extending up to 5 transmitted

bit periods for custom long haul pulse shaping applications.

• Provides line outputs which are current limited and may be tristated for

protection or in redundant applications.

• Provides an alternative digital interface for external line interface units.

• Provides a digital phase locked loop for generation of a low jitter transmit

clock complying with all jitter attenuation, jitter transfer and residual jitter specifications of AT&T TR 62411 and ETSI TBR 12 and TBR 13.

• Provides a FIFO buffer for jitter attenuation and rate conversion in the

transmit path.

• Provides a two-frame payload slip buffer to allow independent backplane and

line timing.

• Provides an integral pattern generator that may be programmed to generate

common pseudo-random or repetitive sequences. The programmed sequence may be inserted in the entire frame, or on an NxDS0 basis.

• Provides an integral pattern detector that may be programmed to detect

common pseudo-random or repetitive sequences from the backplane.

• Transmits G.704 basic and CRC-4 multiframe formatted E1 signals or D4, SF

or ESF formatted DSX/DS-1 signals.

PROPRIETARY AND CONFIDENTIAL

4

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

• Transmits TTC JT-G704 multiframe formatted J1 signals. Supports the

alternate ESF CRC-6 calculation for Japanese applications.

• Transmits the “Japanese Yellow” alarm.

• Supports unframed mode and framing bit, CRC, or data link by-pass.

• Provides signaling insertion, programmable idle code substitution, digital

milliwatt code substitution, and data inversion on a per channel basis.

• Provides trunk conditioning which forces programmable trouble code

substitution and signaling conditioning on all channels or on selected channels.

• Provides minimum ones density through Bell (bit 7), GTE or DDS zero code

suppression on a per channel basis.

• Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving

192-bit window and optionally stuffs ones to maintain minimum ones density.

• Allows insertion of framed or unframed in-band loopback code sequences.

• Allows insertion of a data link in ESF or T1DM (DDS) DS-1 modes.

Optionally inserts a datalink in the E1 national use bits.

• Supports 4-bit codeword insertion in the E1 national use bits as specified in

ETS 300 233

• Inserts up to three HDLC links into arbitrary time slots to support the D-

channel for ISDN Primary Rate Interfaces and the C-channels for V5.1/V5.2 interfaces.

• Supports transmission of the alarm indication signal (AIS) and the Yellow

alarm signal. Supports “Japanese Yellow” alarm generation.

• Provides ESF bit-oriented code generation.

PROPRIETARY AND CONFIDENTIAL

5

STANDARD PRODUCT

DATA SHEET PMC-1970624 ISSUE 10 COMBINED E1/T1 TRANSCEIVER

PM4351 COMET

2 APPLICATIONS

• T1/E1 Wireless Digital Loop Carriers (DLC's) and Cellular Base Stations

• T1/E1 Internet Access Equipment

• T1/E1 Channel Service Units (CSU)

• T1/E1 Frame Relay Interfaces

• T1/E1 ATM Interfaces

• T1/E1 Multiplexers (CPE MUX)

• Digital Private Branch Exchanges (PBX)

• Digital Access Cross-Connect Systems (DACS) and Electronic DSX Cross-

Connect Systems (EDSX)

• ISDN Primary Rate Interfaces (PRI)

• Test Equipment

PROPRIETARY AND CONFIDENTIAL

6

PMC PM4351-NI, PM4351-RI, PM7366 Datasheet

CONTENTS

LIST OF REGISTERS

LIST OF FIGURES

LIST OF TABLES