PMC PM7364-BI Datasheet
RELEASED
DATA SHEET
PMC-1960758 ISSUE 6 FRAME ENGINE AND DATA LINK MANAGER
PM7364 FREEDM-32
PM7364
FREEDM™-32
FRAME ENGINE AND DATALINK
MANAGER
DATA SHEET
ISSUE 6: AUGUST 2001
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PMC-1960758 ISSUE 6 FRAME ENGINE AND DATA LINK MANAGER
PM7364 FREEDM-32
PUBLIC REVISION HISTORY
Issue No. Issue Date Details of Change
6 August
Patent information added to legal footer.
2001
5 May 1998 Document re-issue.
4 April 1998 Document re-issue.
3 October
Document re-formatted.
1997
2 April 23,
1997
Pin Diagram page replaced.
Two entries added to Pin table diagram.
Added AC, DC Timing section and 256 BGA
mechanical package information.
1 July 24,
Creation of Data Sheet
1996
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PMC-1960758 ISSUE 6 FRAME ENGINE AND DATA LINK MANAGER
PM7364 FREEDM-32
CONTENTS
1 FEATURES...............................................................................................1
2 APPLICATIONS........................................................................................3
3 REFERENCES .........................................................................................4
4 APPLICATION EXAMPLES......................................................................5
5 BLOCK DIAGRAM....................................................................................6
6 DESCRIPTION .........................................................................................7
7 PIN DIAGRAM ..........................................................................................9
8 PIN DESCRIPTION ................................................................................10
9 FUNCTIONAL DESCRIPTION ...............................................................31
9.1 HIGH-LEVEL DATA LINK CONTROL PROTOCOL......................31
9.2 RECEIVE CHANNEL ASSIGNER ................................................32
9.2.1 LINE INTERFACE..........................................................33
9.2.2 PRIORITY ENCODER...................................................33
9.2.3 CHANNEL ASSIGNER ..................................................33
9.2.4 LOOPBACK CONTROLLER .........................................34
9.3 RECEIVE HDLC PROCESSOR / PARTIAL PACKET BUFFER...34
9.3.1 HDLC PROCESSOR .....................................................34
9.3.2 PARTIAL PACKET BUFFER PROCESSOR ..................35
9.4 RECEIVE DMA CONTROLLER ...................................................37
9.4.1 DATA STRUCTURES ....................................................37
9.4.2 DMA TRANSACTION CONTROLLER...........................47
9.4.3 WRITE DATA PIPELINE/MUX .......................................47
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9.4.4 DESCRIPTOR INFORMATION CACHE ........................47
9.4.5 FREE QUEUE CACHE..................................................47
9.5 PCI CONTROLLER......................................................................48
9.5.1 MASTER MACHINE ......................................................49
9.5.2 MASTER LOCAL BUS INTERFACE..............................51
9.5.3 TARGET MACHINE.......................................................52
9.5.4 CBI BUS INTERFACE ...................................................54
9.5.5 ERROR / BUS CONTROL .............................................54
9.6 TRANSMIT DMA CONTROLLER.................................................54
9.6.1 DATA STRUCTURES ....................................................55
9.6.2 TASK PRIORITIES ........................................................67
9.6.3 DMA TRANSACTION CONTROLLER...........................67
9.6.4 READ DATA PIPELINE..................................................67
9.6.5 DESCRIPTOR INFORMATION CACHE ........................67
9.6.6 FREE QUEUE CACHE..................................................67
9.7 TRANSMIT HDLC CONTROLLER / PARTIAL PACKET BUFFER68
9.7.1 TRANSMIT HDLC PROCESSOR..................................68
9.7.2 TRANSMIT PARTIAL PACKET BUFFER PROCESSOR69
9.8 TRANSMIT CHANNEL ASSIGNER .............................................71
9.8.1 LINE INTERFACE..........................................................72
9.8.2 PRIORITY ENCODER...................................................72
9.8.3 CHANNEL ASSIGNER ..................................................73
9.9 PERFORMANCE MONITOR .......................................................73
9.10 JTAG TEST ACCESS PORT INTERFACE...................................73
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9.11 PCI HOST INTERFACE ...............................................................73
10 NORMAL MODE REGISTER DESCRIPTION ........................................79
10.1 PCI HOST ACCESSIBLE REGISTERS .......................................79
11 PCI CONFIGURATION REGISTER DESCRIPTION ............................251
11.1 PCI CONFIGURATION REGISTERS.........................................251
12 TEST FEATURES DESCRIPTION .......................................................262
12.1 TEST MODE REGISTERS ........................................................262
12.2 JTAG TEST PORT .....................................................................263
12.2.1 IDENTIFICATION REGISTER .....................................264
12.2.2 BOUNDARY SCAN REGISTER ..................................264
13 OPERATIONS ......................................................................................278
13.1 EQUAD CONNECTIONS...........................................................278
13.2 TOCTL CONNECTIONS............................................................278
13.3 JTAG SUPPORT........................................................................279
14 FUNCTIONAL TIMING .........................................................................285
14.1 RECEIVE LINK INPUT TIMING .................................................285
14.2 TRANSMIT LINK OUTPUT TIMING...........................................286
14.3 PCI INTERFACE........................................................................288
14.4 BERT INTERFACE ....................................................................297
15 ABSOLUTE MAXIMUM RATINGS........................................................299
16 D.C. CHARACTERISTICS....................................................................300
17 FREEDM-32 TIMING CHARACTERISTICS .........................................302
18 ORDERING AND THERMAL INFORMATION ......................................308
19 MECHANICAL INFORMATION.............................................................309
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PM7364 FREEDM-32
LIST OF REGISTERS
REGISTER 0X000 : FREEDM-32 MASTER RESET.........................................80
REGISTER 0X004 : FREEDM-32 MASTER INTERRUPT ENABLE .................82
REGISTER 0X008 : FREEDM-32 MASTER INTERRUPT STATUS .................87
REGISTER 0X00C : FREEDM-32 MASTER CLOCK / BERT ACTIVITY
MONITOR AND ACCUMULATION TRIGGER ........................................91
REGISTER 0X010 : FREEDM-32 MASTER LINK ACTIVITY MONITOR..........93
REGISTER 0X014 : FREEDM-32 MASTER LINE LOOPBACK #1...................97
REGISTER 0X018 : FREEDM-32 MASTER LINE LOOPBACK #2...................99
REGISTER 0X020 : FREEDM-32 MASTER BERT CONTROL.......................101
REGISTER 0X024 : FREEDM-32 MASTER PERFORMANCE MONITOR
CONTROL ............................................................................................103
REGISTER 0X040 : GPIC CONTROL ............................................................107
REGISTER 0X100 : RCAS INDIRECT LINK AND TIME-SLOT SELECT........ 110
REGISTER 0X104 : RCAS INDIRECT CHANNEL DATA................................ 112
REGISTER 0X108 : RCAS FRAMING BIT THRESHOLD...............................114
REGISTER 0X10C : RCAS CHANNEL DISABLE ........................................... 116
REGISTER 0X180 : RCAS LINK #0 CONFIGURATION ................................. 118
REGISTER 0X184 - 0X188 : RCAS LINK #1 TO #2 CONFIGURATION.........120
REGISTER 0X18C : RCAS LINK #3 CONFIGURATION ................................122
REGISTER 0X190-0X1FC : RCAS LINK #4 TO LINK #31 CONFIGURATION124
REGISTER 0X200 : RHDL INDIRECT CHANNEL SELECT ...........................126
REGISTER 0X204 : RHDL INDIRECT CHANNEL DATA REGISTER #1 ........128
REGISTER 0X208 : RHDL INDIRECT CHANNEL DATA REGISTER #2 ........131
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REGISTER 0X210 : RHDL INDIRECT BLOCK SELECT ................................134
REGISTER 0X214 : RHDL INDIRECT BLOCK DATA .....................................136
REGISTER 0X220 : RHDL CONFIGURATION ...............................................138
REGISTER 0X224 : RHDL MAXIMUM PACKET LENGTH .............................140
REGISTER 0X280 : RMAC CONTROL...........................................................142
REGISTER 0X284 : RMAC INDIRECT CHANNEL PROVISIONING ..............145
REGISTER 0X288 : RMAC PACKET DESCRIPTOR TABLE BASE LSW ......147
REGISTER 0X28C : RMAC PACKET DESCRIPTOR TABLE BASE MSW .....148
REGISTER 0X290 : RMAC QUEUE BASE LSW ............................................150
REGISTER 0X294 : RMAC QUEUE BASE MSW ...........................................151
REGISTER 0X298 : RMAC PACKET DESCRIPTOR REFERENCE LARGE
BUFFER FREE QUEUE START...........................................................153
REGISTER 0X29C : RMAC PACKET DESCRIPTOR REFERENCE LARGE
BUFFER FREE QUEUE WRITE ..........................................................155
REGISTER 0X2A0 : RMAC PACKET DESCRIPTOR REFERENCE LARGE
BUFFER FREE QUEUE READ ............................................................157
REGISTER 0X2A4 : RMAC PACKET DESCRIPTOR REFERENCE LARGE
BUFFER FREE QUEUE END...............................................................159
REGISTER 0X2A8 : RMAC PACKET DESCRIPTOR REFERENCE SMALL
BUFFER FREE QUEUE START...........................................................161
REGISTER 0X2AC : RMAC PACKET DESCRIPTOR REFERENCE SMALL
BUFFER FREE QUEUE WRITE ..........................................................163
REGISTER 0X2B0 : RMAC PACKET DESCRIPTOR REFERENCE SMALL
BUFFER FREE QUEUE READ ............................................................165
REGISTER 0X2B4 : RMAC PACKET DESCRIPTOR REFERENCE SMALL
BUFFER FREE QUEUE END...............................................................167
REGISTER 0X2B8 : RMAC PACKET DESCRIPTOR REFERENCE READY
QUEUE START ....................................................................................169
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REGISTER 0X2BC : RMAC PACKET DESCRIPTOR REFERENCE READY
QUEUE WRITE ....................................................................................171
REGISTER 0X2C0 : RMAC PACKET DESCRIPTOR REFERENCE READY
QUEUE READ ......................................................................................173
REGISTER 0X2C4 : RMAC PACKET DESCRIPTOR REFERENCE READY
QUEUE END ........................................................................................175
REGISTER 0X300 : TMAC CONTROL ...........................................................177
REGISTER 0X304 : TMAC INDIRECT CHANNEL PROVISIONING...............180
REGISTER 0X308 : TMAC DESCRIPTOR TABLE BASE LSW......................182
REGISTER 0X30C : TMAC DESCRIPTOR TABLE BASE MSW ....................183
REGISTER 0X310 : TMAC QUEUE BASE LSW ............................................185
REGISTER 0X314 : TMAC QUEUE BASE MSW ...........................................186
REGISTER 0X318 : TMAC DESCRIPTOR REFERENCE FREE QUEUE START
..............................................................................................................188
REGISTER 0X31C TMAC DESCRIPTOR REFERENCE FREE QUEUE WRITE
..............................................................................................................190
REGISTER 0X320 : TMAC DESCRIPTOR REFERENCE FREE QUEUE READ
..............................................................................................................192
REGISTER 0X324 : TMAC DESCRIPTOR REFERENCE FREE QUEUE END
..............................................................................................................194
REGISTER 0X328 :TMAC DESCRIPTOR REFERENCE READY QUEUE
START ..................................................................................................196
REGISTER 0X32C : TMAC DESCRIPTOR REFERENCE READY QUEUE
WRITE ..................................................................................................198
REGISTER 0X330 : TMAC DESCRIPTOR REFERENCE READY QUEUE READ200
REGISTER 0X334 : TMAC DESCRIPTOR REFERENCE READY QUEUE END
..............................................................................................................202
REGISTER 0X380 : THDL INDIRECT CHANNEL SELECT............................204
REGISTER 0X384 : THDL INDIRECT CHANNEL DATA #1 ............................206
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REGISTER 0X388 : THDL INDIRECT CHANNEL DATA #2 ............................209
REGISTER 0X38C : THDL INDIRECT CHANNEL DATA #3 ...........................212
REGISTER 0X3A0 : THDL INDIRECT BLOCK SELECT ................................217
REGISTER 0X3A4 : THDL INDIRECT BLOCK DATA.....................................219
REGISTER 0X3B0 : THDL CONFIGURATION ...............................................221
REGISTER 0X400 : TCAS INDIRECT LINK AND TIME-SLOT SELECT ........223
REGISTER 0X404 : TCAS INDIRECT CHANNEL DATA ................................225
REGISTER 0X408 : TCAS FRAMING BIT THRESHOLD ...............................227
REGISTER 0X40C : TCAS IDLE TIME-SLOT FILL DATA...............................229
REGISTER 0X410 : TCAS CHANNEL DISABLE ............................................231
REGISTER 0X480 : TCAS LINK #0 CONFIGURATION .................................233
REGISTER 0X484-0X488 : TCAS LINK #1 TO LINK #2 CONFIGURATION ..235
REGISTER 0X48C : TCAS LINK #3 CONFIGURATION.................................237
REGISTER 0X490-0X4FC : TCAS LINK #4 TO LINK #31 CONFIGURATION239
REGISTER 0X500 : PMON STATUS ..............................................................241
REGISTER 0X504 : PMON RECEIVE FIFO OVERFLOW COUNT................243
REGISTER 0X508 : PMON RECEIVE FIFO UNDERFLOW COUNT .............245
REGISTER 0X50C : PMON CONFIGURABLE COUNT #1.............................247
REGISTER 0X510 : PMON CONFIGURABLE COUNT #2 .............................249
REGISTER 0X00 : VENDOR IDENTIFICATION/DEVICE IDENTIFICATION..252
REGISTER 0X04 : COMMAND/STATUS ........................................................253
REGISTER 0X08 : REVISION IDENTIFIER/CLASS CODE............................257
REGISTER 0X0C : CACHE LINE SIZE/LATENCY TIMER/HEADER TYPE ...258
REGISTER 0X10 : CBI MEMORY BASE ADDRESS REGISTER ...................259
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PM7364 FREEDM-32
REGISTER 0X3C : INTERRUPT LINE / INTERRUPT PIN / MIN_GNT /
MAX_LAT..............................................................................................261
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PMC-1960758 ISSUE 6 FRAME ENGINE AND DATA LINK MANAGER
PM7364 FREEDM-32
LIST OF FIGURES
FIGURE 1 – HDLC FRAME...............................................................................31
FIGURE 2 – CRC GENERATOR.......................................................................32
FIGURE 3 – PARTIAL PACKET BUFFER STRUCTURE ..................................36
FIGURE 4 – RECEIVE PACKET DESCRIPTOR...............................................38
FIGURE 5 – RECEIVE PACKET DESCRIPTOR TABLE...................................41
FIGURE 6 – RPDRF AND RPDRR QUEUES ...................................................43
FIGURE 7 – RPDRR QUEUE OPERATION......................................................45
FIGURE 8 – RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE.........46
FIGURE 9 – GPIC ADDRESS MAP ..................................................................53
FIGURE 10 – TRANSMIT DESCRIPTOR .........................................................55
FIGURE 11 – TRANSMIT DESCRIPTOR TABLE .............................................59
FIGURE 12 – TDRR AND TDRF QUEUES .......................................................61
FIGURE 13 – TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE ....63
FIGURE 14 – TD LINKING................................................................................66
FIGURE 15 – PARTIAL PACKET BUFFER STRUCTURE ................................70
FIGURE 16 – INPUT OBSERVATION CELL (IN_CELL) .................................275
FIGURE 17 – OUTPUT CELL (OUT_CELL) ...................................................276
FIGURE 18 – BI-DIRECTIONAL CELL (IO_CELL) .........................................276
FIGURE 19 – LAYOUT OF OUTPUT ENABLE AND BI-DIRECTIONAL CELLS
..............................................................................................................277
FIGURE 20 – BOUNDARY SCAN ARCHITECTURE ......................................279
FIGURE 21 – TAP CONTROLLER FINITE STATE MACHINE........................281
FIGURE 22 – UNCHANNELISED RECEIVE LINK TIMING ............................285
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FIGURE 23 – CHANNELISED T1 RECEIVE LINK TIMING ............................286
FIGURE 24 – CHANNELISED E1 RECEIVE LINK TIMING............................286
FIGURE 25 – UNCHANNELISED TRANSMIT LINK TIMING..........................287
FIGURE 26 – CHANNELISED T1 TRANSMIT LINK TIMING..........................287
FIGURE 27 – CHANNELISED E1 TRANSMIT LINK TIMING .........................288
FIGURE 28 – PCI READ CYCLE ....................................................................289
FIGURE 29 – PCI WRITE CYCLE ..................................................................291
FIGURE 30 – PCI TARGET DISCONNECT ....................................................292
FIGURE 31 – PCI TARGET ABORT................................................................292
FIGURE 32 – PCI BUS REQUEST CYCLE ....................................................293
FIGURE 33 – PCI INITIATOR ABORT TERMINATION ...................................294
FIGURE 34 – PCI EXCLUSIVE LOCK CYCLE ...............................................295
FIGURE 35 – PCI FAST BACK TO BACK.......................................................297
FIGURE 36 – RECEIVE BERT PORT TIMING ...............................................297
FIGURE 37 – TRANSMIT BERT PORT TIMING .............................................298
FIGURE 38 – RECEIVE LINK INPUT TIMING ................................................303
FIGURE 39 – BERT INPUT TIMING ...............................................................303
FIGURE 40 – TRANSMIT LINK OUTPUT TIMING..........................................305
FIGURE 41 – BERT OUTPUT TIMING ...........................................................305
FIGURE 42 – PCI INTERFACE TIMING .........................................................306
FIGURE 43 – JTAG PORT INTERFACE TIMING............................................307
FIGURE 44 – 256 PIN ENHANCED BALL GRID ARRAY (SBGA) ..................309
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PM7364 FREEDM-32
LIST OF TABLES
TABLE 1 – LINE SIDE INTERFACE SIGNALS (132)........................................10
TABLE 2 – PCI HOST INTERFACE SIGNALS (51) ..........................................15
TABLE 3 – MISCELLANEOUS INTERFACE SIGNALS (13).............................24
TABLE 4 – PRODUCTION TEST INTERFACE SIGNALS (0 - MULTIPLEXED)26
TABLE 5 – POWER AND GROUND SIGNALS (60) .........................................28
TABLE 6 – RECEIVE PACKET DESCRIPTOR FIELDS....................................38
TABLE 7 – RPDRR QUEUE ELEMENT ............................................................44
TABLE 8 – RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE FIELDS
................................................................................................................46
TABLE 9 – TRANSMIT DESCRIPTOR FIELDS ................................................56
TABLE 10 – TRANSMIT DESCRIPTOR REFERENCE.....................................62
TABLE 11 – TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE
FIELDS ...................................................................................................64
TABLE 12 – NORMAL MODE PCI HOST ACCESSIBLE REGISTER MEMORY
MAP ........................................................................................................74
TABLE 13 – PCI CONFIGURATION REGISTER MEMORY MAP.....................78
TABLE 14 – BIG ENDIAN FORMAT................................................................108
TABLE 15 – LITTLE ENDIAN FORMAT..........................................................108
TABLE 16 – CRC[1:0] SETTINGS...................................................................130
TABLE 17 – RPQ_RDYN[2:0] SETTINGS ......................................................143
TABLE 18 – RPQ_LFN[1:0] SETTINGS..........................................................144
TABLE 19 – RPQ_SFN[1:0] SETTINGS .........................................................144
TABLE 20 – TDQ_RDYN[2:0] SETTINGS.......................................................178
TABLE 21 – TDQ_FRN[1:0] SETTINGS .........................................................178
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TABLE 22 – CRC[1:0] SETTINGS...................................................................207
TABLE 23 – FLAG[2:0] SETTINGS .................................................................213
TABLE 24 – LEVEL[3:0]/TRANS SETTINGS ..................................................215
TABLE 25 – TEST MODE REGISTER MEMORY MAP ..................................263
TABLE 26 – INSTRUCTION REGISTER ........................................................264
TABLE 27 – BOUNDARY SCAN CHAIN .........................................................265
TABLE 28 – FREEDM–EQUAD CONNECTIONS ...........................................278
TABLE 29 – FREEDM–TOCTAL CONNECTIONS..........................................278
TABLE 30 – FREEDM-32 ABSOLUTE MAXIMUM RATINGS .........................299
TABLE 31 – FREEDM-32 D.C. CHARACTERISTICS .....................................300
TABLE 32 – FREEDM-32 LINK INPUT (FIGURE 38, FIGURE 39).................302
TABLE 33 – FREEDM-32 LINK OUTPUT (FIGURE 40, FIGURE 41).............304
TABLE 34 – PCI INTERFACE (FIGURE 42) ...................................................305
TABLE 35 – JTAG PORT INTERFACE (FIGURE 43)......................................306
TABLE 36 – FREEDM-32 ORDERING INFORMATION..................................308
TABLE 37 – FREEDM-32 THERMAL INFORMATION ....................................308
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1 FEATURES
· Single-chip Peripheral Component Interconnect (PCI) Bus multi-channel
HDLC controller.
· Supports up to 128 bi-directional HDLC channels assigned to a maximum of
32 channelised T1 or E1 links. The number of time-slots assigned to an
HDLC channel is programmable from 1 to 24 (for T1) and from 1 to 31 (for
E1).
· Supports up to 32 bi-directional HDLC channels each assigned to an
unchannelised arbitrary rate link; subject to a maximum aggregate link clock
rate of 64 MHz in each direction. Channels assigned to links 0 to 2 can have
a clock rate of up to 45 MHz when SYSCLK is at or above 25 MHz and up to
52 MHz when SYSCLK is at 33 MHz. Channels assigned to links 3 to 31 can
have a clock rate of up to 10 MHz.
· Supports up to two bi-directional HDLC channels each assigned to an
unchannelised arbitrary rate link of up to 45 MHz when SYSCLK is at or
above 25 MHz and up to 52 MHz when SYSCLK is at 33 MHz.
· Supports a mix of up to 32 channelised and unchannelised links; subject to
the constraint of a maximum of 128 channels and a maximum aggregate link
clock rate of 64 MHz in each direction.
· For each channel, the HDLC receiver performs flag sequence detection, bit
de-stuffing, and frame check sequence validation. The receiver supports the
validation of both CRC-CCITT and CRC-32 frame check sequences. The
receiver also checks for packet abort sequences, octet aligned packet length
and for minimum and maximum packet length.
· Alternatively, for each channel, the receiver supports a transparent mode
where each octet is transferred transparently to host memory. For
channelised links, the octets are aligned with the receive time-slots.
· For each channel, time-slots are selectable to be in 56 kbits/s format or 64
kbits/s clear channel format.
· For each channel, the HDLC transmitter performs flag sequence generation,
bit stuffing, and, optionally, frame check sequence generation. The
transmitter supports the generation of both CRC-CCITT and CRC-32 frame
check sequences. The transmitter also aborts packets under the direction of
the host or automatically when the channel underflows.
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· Supports two levels of non-preemptive packet priority on each transmit
channel. Low priority packets will not begin transmission until all high priority
packets are transmitted.
· Alternatively, for each channel, the transmitter supports a transparent mode
where each octet is inserted transparently from host memory. For
channelised links, the octets are aligned with the transmit time-slots.
· Directly supports a 32-bit, 33 MHz PCI 2.1 interface for configuration,
monitoring and transfer of packet data, with an on-chip DMA controller with
scatter/gather capabilities.
· Provides 8 kbytes of on-chip memory for partial packet buffering in each
direction. This memory can be configured to support a variety of different
channel configurations from a single channel with 8 kbytes of buffering to 128
channels, each with a minimum of 48 bytes of buffering.
· Supports PCI burst sizes of up to 128 bytes for transfers of packet data.
· Pin compatible with PM7366 (FREEDM-8) device.
· Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board
test purposes.
· Supports 3.3 and 5 Volt PCI signaling environments.
· Low power CMOS technology.
· 256 pin enhanced ball grid array (SBGA) package (27 mm X 27 mm).
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2 APPLICATIONS
· IETF PPP interfaces for routers
· Frame Relay interfaces for ATM or Frame Relay switches and multiplexors
· FUNI or Frame Relay service inter-working interfaces for ATM switches and
multiplexors.
· D-channel processing in ISDN terminals and switches.
· Internet/Intranet access equipment.
· Packet-based DSLAM equipment.
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3 REFERENCES
1. International Organization for Standardization, ISO Standard 3309-1993,
"Information Technology - Telecommunications and information exchange
between systems - High-level data link control (HDLC) procedures - Frame
structure", December 1993.
2. RFC-1662 - "PPP in HDLC-like Framing" Internet Engineering Task Force,
July 1994.
3. PCI Special Interest Group, PCI Local Bus Specification, June 1, 1995,
Version 2.1.
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4 APPLICATION EXAMPLES
ACCESS SIDE
PM8313
DS3
T1
E1
D3MX
M13 Access Module
PM4314
QDSX
T1 Access Modu le
PM4314
QDSX
PM4388
TOCTL
PM4388
TOCTL
PM6344
EQU
PM7364
FREEDM
FREEDM-32
PCI Bus
Packet
Memory
D
Processor Module
Micro-
processor
HDLC BASED UPLINK SIDE
HSSI
Module
DS3/E3
Framer
LIU
HDLC Based
Uplink Module
HSSI
DS3/E3/J2
ACCESS SIDE
DSL
E1 Access Module
XDSL
PHY
xDSL Access Module
PM7364
FREEDM-32
PCI Bus
Packet
Memory
PM7322
RCMP
processor
SAR
Micro-
ATM CELL BASED UPLINK SIDE
PM7345
S/UNI-PDH
DS-3/E3 ATM
PM5346
S/UNI-LITE
PM5348
S/UNI-DU
L
STS-3c ATM UNI
PM5347
S/UNI-PLUS
STS-3c ATM NNI
PM5355
S/UNI-622
T3/E3
OC-3
OC-3
OC-12
Processor Module
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STS-12c ATM UNI/NNI
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5 BLOCK DIAGRAM
.
AD[31:0]
C/BEB[3:0]
PAR
TRDYB
IRDYB
STOPB
DEVSELB
IDSEL
LOCKB
GNTB
PERRB
SERRB
PCIINTB
PCICLK
PCICLKO
SYSCLK
PMCTEST
TDO
TDI
TCK
TMS
JTAG Port
TRSTB
RSTB
FRAMEB
PCI
Controller
REQB
(GPIC)
RBCLK
RBD
DM
Receive
Controller
(RHDL)
Partial Packet Buffer
(RMAC)
(PMON)
Performance Monitor
Receive HDLC Processor
Transmit
Transmit HDLC Processor
DM
Partial Packet Buffer
(TMAC)
Controller
(THDL)
TBCLK
ssigner
Channel
(RCAS)
Receive
Transmit
Channel
ssigner
(TCAS)
TBD
RD[31:0]
RCLK[31:0]
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 6
TD[31:0]
TCLK[31:0]
RELEASED
DATA SHEET
PMC-1960758 ISSUE 6 FRAME ENGINE AND DATA LINK MANAGER
PM7364 FREEDM-32
6 DESCRIPTION
The PM7364 FREEDM-32 Frame Engine and Datalink Manager device is a
monolithic integrated circuit that implements HDLC processing, and PCI Bus
memory management functions for a maximum of 128 bi-directional channels.
For channelised links, the FREEDM-32 allows up to 128 bi-directional HDLC
channels to be assigned to individual time-slots within a maximum of 32
independently timed T1 or E1 links. The channel assignment supports the
concatenation of time-slots (N x DS0) up to a maximum of 24 concatenated timeslots for a T1 link and 31 concatenated time-slots for an E1 link. Time-slots
assigned to any particular channel need not be contiguous within the T1 or E1
link.
For unchannelised links, the FREEDM-32 processes up to 32 bi-directional
HDLC channels within 32 independently timed links. The links can be of
arbitrary frame format. When limited to two unchannelised links, each link can
be rated at up to 45 MHz when SYSCLK is at 25 MHz and at up to 52 MHz when
SYSCLK is at 33 MHz. For lower rate unchannelised links, the FREEDM-32
processes up to 32 links, where the aggregate clock rate of all the links is limited
to 64 MHz, links 0 to 2 can have a clock rate of up to 45 MHz when SYSCLK is
at or above 25 MHz and up to 52 MHz when SYSCLK is at 33 MHz and links 3 to
31 can have a clock rate of up to 10 MHz.
The FREEDM-32 supports mixing of up to 32 channelised and unchannelised
links. The total number of channels in each direction is limited to 128. The
aggregate clock rate over all 32 possible links is limited to 64 MHz.
In the receive direction, the FREEDM-32 performs channel assignment and
packet extraction and validation. For each provisioned HDLC channel, the
FREEDM-32 delineates the packet boundaries using flag sequence detection,
and performs bit de-stuffing. Sharing of opening and closing flags, as well as,
sharing of zeros between flags are supported. The resulting packet data is
placed into the internal 8 kbyte partial packet buffer RAM. The partial packet
buffer acts as a logical FIFO for each of the assigned channels. Partial packets
are DMA'd out of the RAM, across the PCI bus and into host packet memory.
The FREEDM-32 validates the frame check sequence for each packet, and
verifies that the packet is an integral number of octets in length and is within a
programmable minimum and maximum length. The receive packet status is
updated before linking the packet into a receive ready queue. The FREEDM-32
alerts the PCI Host that there are packets in a receive ready queue by, optionally,
asserting an interrupt on the PCI bus.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 7
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PMC-1960758 ISSUE 6 FRAME ENGINE AND DATA LINK MANAGER
PM7364 FREEDM-32
Alternatively, in the receive direction, the FREEDM-32 supports a transparent
operating mode. For each provisioned transparent channel, the FREEDM-32
directly transfers the received octets into host memory verbatim. If the
transparent channel is assigned to a channelised link, then the octets are aligned
to the received time-slots.
In the transmit direction, the PCI Host provides packets to transmit using a
transmit ready queue. For each provisioned HDLC channel, the FREEDM-32
DMA's partial packets across the PCI bus and into the transmit partial packet
buffer. The partial packets are read out of the packet buffer by the FREEDM-32
and frame check sequence is optionally calculated and inserted at the end of
each packet. Bit stuffing is performed before being assigned to a particular link.
The flag sequence is automatically inserted when there is no packet data for a
particular channel. Sequential packets are optionally separated by two flags (an
opening flag and a closing flag) or a single flag (combined opening and closing
flag). Zeros between flags are not shared. PCI bus latency may cause one or
more channels to underflow, in which case, the packets are aborted, and the
host is notified. For normal traffic, an abort sequence is generated, followed by
inter-frame time fill characters (flags or all-ones bytes) until a new packet is
sourced from the PCI host. No attempt is made to automatically re-transmit an
aborted packet.
Alternatively, in the transmit direction, the FREEDM-32 supports a transparent
operating mode. For each provisioned transparent channel, the FREEDM-32
directly inserts the transmitted octets from host memory. If the transparent
channel is assigned to a channelised link, then the octets are aligned to the
transmitted time-slots. If a channel underflows due to excessive PCI bus latency,
an abort sequence is generated, followed by inter-frame time fill characters (flags
or all-ones bytes) to indicate idle channel. Data resumes immediately when the
FREEDM-32 receives new data from the host.
The FREEDM-32 is configured, controlled and monitored using the PCI bus
interface. The FREEDM-32 is implemented in low power CMOS technology. It
has TTL compatible inputs and outputs and is packaged in a 256 pin enhanced
ball grid array (SBGA) package.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 8
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DATA SHEET
PMC-1960758 ISSUE 6 FRAME ENGINE AND DATA LINK MANAGER
PM7364 FREEDM-32
7 PIN DIAGRAM
The FREEDM-32 is manufactured in a 256 pin enhanced ball grid array package.
2019181716151413121110987654321
VSS VSS VSS RCLK[8] RCLK[10] RD[12] RD[14] VSS RD[17] RD[19] VSS VSS RCLK[21] RCLK[23] RCLK[25] RD[27] RD[29] VSS VSS VSS
A
VSS VDD VDD RD[8] RD[10] RCLK[11] RCLK[13] RCLK[15] RCLK[16] RCLK[18] RD[20] RCLK[20] RCLK[22] RD[24] RD[26] RCLK[27] RCLK[29] VDD VDD VSS
B
VSS VDD VDD RD[7] RD[9] RD[11] RCLK[12] RCLK[14] RD[16] RD[18] RCLK[19] RD[21] RD[23] RD[25] RCLK[26] RCLK[28] PCICLK VDD VDD VSS
C
RD[5] RCLK[5] RCLK[6] EN5V RCLK[7] RCLK[9] VDD RD[13] RD[15] RCLK[17] VDD RD[22] RCLK[24] VDD RD[28] PCICLKO VBIAS[2] GNTB AD[31] AD[30]
D
RD[3] RCLK[3] RCLK[4] RD[6] REQB AD[29] AD[27] AD[26]
E
RCLK[1] RD[2] RCLK[2] RD[4] AD[28] AD[25] AD[24] CBEB[3]
F
RBCLK RD[0] RD[1] VDD VDD IDSEL AD[22] AD[21]
G
A
B
C
D
E
F
G
VBIAS[1] SYSCLK RBD RCLK[0] AD[23] AD[20] AD[18] VSS
H
VSS TCK TMS TRSTB AD[19] AD[17] AD[16] CBEB[2]
J
VSS TDI TDO VDD
K
TD[0] TCLK[0] TD[1] TCLK[1] VDD STOPB LOCKB VSS
L
TD[2] TCLK[2] TD[3] TD[4] CBEB[1] SERRB PERRB VSS
M
VSS TCLK[3] TCLK[4] TD[6] AD[11] AD[14] AD[15] PAR
N
TD[5] TCLK[5] TCLK[6] VDD VDD AD[10] AD[12] AD[13]
P
TD[7] TCLK[7] TD[8] TCLK[9] AD[5] CBEB[0] AD[8] AD[9]
R
TCLK[8] TD[9] TD[10] TCLK[11] AD[1] AD[4] AD[6] AD[7]
T
TCLK[10] TD[11] TD[12] NC TD[13] TD[15] VDD TCLK[18] TD[21] VDD TCLK[25] TD[28] TD[30] VDD PMCTEST RCLK[30] VBIAS[3] AD[0] AD[2] AD[3]
U
VSS VDD VDD TCLK[12] TCLK[14] TCLK[16] TD[18] TD[20] TD[22] TCLK[23] TD[25] TD[27] TCLK[28] TCLK[30] TBD PCIINTB RD[30] VDD VDD VSS
V
VSS VDD VDD TCLK[13] TCLK[15] TD[17] TD[19] TCLK[20] TCLK[22] TD[23] TCLK[24] TCLK[26] TCLK[27] TCLK[29] TCLK[31] RSTB RD[31] VDD VDD VSS
W
VSS VSS VSS TD[14] TD[16] TCLK[17] TCLK[19] TCLK[21] VSS VSS TD[24] TD[26] VSS TD[29] TD[31] TBCLK RCLK[31] VSS VSS VSS
Y
2019181716151413121110987654321
BOTTOM VIEW
FRAMEB IRDYB TRDYB DEVSELB
H
J
K
L
M
N
P
R
T
U
V
W
Y
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 9
RELEASED
DATA SHEET
PMC-1960758 ISSUE 6 FRAME ENGINE AND DATA LINK MANAGER
PM7364 FREEDM-32
8 PIN DESCRIPTION
Table 1 – Line Side Interface Signals (132)
Pin Name Type Pin
Function
No.
RCLK[0]
RCLK[1]
RCLK[2]
RCLK[3]
RCLK[4]
RCLK[5]
RCLK[6]
RCLK[7]
RCLK[8]
RCLK[9]
RCLK[10]
RCLK[11]
RCLK[12]
RCLK[13]
RCLK[14]
RCLK[15]
RCLK[16]
RCLK[17]
RCLK[18]
RCLK[19]
RCLK[20]
RCLK[21]
RCLK[22]
RCLK[23]
RCLK[24]
RCLK[25]
RCLK[26]
RCLK[27]
RCLK[28]
RCLK[29]
RCLK[30]
RCLK[31]
Input H17
F20
F18
E19
E18
D19
D18
D16
A17
D15
A16
B15
C14
B14
C13
B13
B12
D11
B11
C10
B9
A8
B8
A7
D8
A6
C6
B5
C5
B4
U5
Y4
The receive line clock signals (RCLK[31:0])
contain the recovered line clock for the 32
independently timed links. Processing of
the receive links is on a priority basis, in
descending order from RCLK[0] to
RCLK[31]. Therefore, the highest rate link
should be connected to RCLK[0] and the
lowest to RCLK[31]. RD[31:0] is sampled
on the rising edge of the corresponding
RCLK[31:0] clock.
For channelised T1 or E1 links, RCLK[n]
must be gapped during the framing bit (for
T1 interfaces) or during time-slot 0 (for E1
interfaces) of the RD[n] stream. The
FREEDM-32 uses the gapping information
to determine the time-slot alignment in the
receive stream. RCLK[31:0] is nominally a
50% duty cycle clock of 1.544 MHz for T1
links and 2.048 MHz for E1 links.
For unchannelised links, RCLK[n] must be
externally gapped during the bits or timeslots that are not part of the transmission
format payload (i.e. not part of the HDLC
packet). RCLK[2:0] is nominally a 50% duty
cycle clock between 0 and 52 MHz.
RCLK[31:3] is nominally a 50% duty cycle
clock between 0 and 10 MHz.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 10
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PMC-1960758 ISSUE 6 FRAME ENGINE AND DATA LINK MANAGER
Pin Name Type Pin
Function
PM7364 FREEDM-32
No.
RD[0]
RD[1]
RD[2]
RD[3]
RD[4]
RD[5]
RD[6]
RD[7]
RD[8]
RD[9]
RD[10]
RD[11]
RD[12]
RD[13]
RD[14]
RD[15]
RD[16]
RD[17]
RD[18]
RD[19]
RD[20]
RD[21]
RD[22]
RD[23]
RD[24]
RD[25]
RD[26]
RD[27]
RD[28]
RD[29]
RD[30]
RD[31]
Input G19
G18
F19
E20
F17
D20
E17
C17
B17
C16
B16
C15
A15
D13
A14
D12
C12
A12
C11
A11
B10
C9
D9
C8
B7
C7
B6
A5
D6
A4
V4
W4
The receive data signals (RD[31:0]) contain
the recovered line data for the 32
independently timed links in normal mode
(PMCTEST set low). Processing of the
receive links is on a priority basis, in
descending order form RD[0] to RD[31].
Therefore, the highest rate link should be
connected to RD[0] and the lowest to
RD[31].
For channelised links, RD[n] contains the 24
(T1) or 31 (E1) time-slots that comprise the
channelised link. RCLK[n] must be gapped
during the T1 framing bit position or the E1
frame alignment signal (time-slot 0). The
FREEDM-32 uses the location of the gap to
determine the channel alignment on RD[n].
For unchannelised links, RD[n] contains the
HDLC packet data. For certain transmission
formats, RD[n] may contain place holder bits
or time-slots. RCLK[n] must be externally
gapped during the place holder positions in
the RD[n] stream. The FREEDM-32
supports a maximum data rate of 10 Mbit/s
on an individual RD[31:3] link and a
maximum data rate of 52 Mbit/s on RD[2:0].
RD[31:0] is sampled on the rising edge of
the corresponding RCLK[31:0] clock.
RBD Tristate
Output
H18 The receive BERT data signal (RBD)
contains the receive bit error rate test data.
RBD reports the data on the selected one of
the receive data signals (RD[31:0]) and is
updated on the falling edge of RBCLK.
RBD may be tri-stated by setting the RBEN
bit in the FREEDM-32 Master BERT Control
register low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 11
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PMC-1960758 ISSUE 6 FRAME ENGINE AND DATA LINK MANAGER
Pin Name Type Pin
Function
PM7364 FREEDM-32
No.
RBCLK Tristate
Output
G20 The receive BERT clock signal (RBCLK)
contains the receive bit error rate test clock.
RBCLK is a buffered version of the selected
one of the receive clock signals
(RCLK[31:0]). RBCLK may be tri-stated by
setting the RBEN bit in the FREEDM-32
Master BERT Control register low.
TCLK[0]
TCLK[1]
TCLK[2]
TCLK[3]
TCLK[4]
TCLK[5]
TCLK[6]
TCLK[7]
TCLK[8]
TCLK[9]
TCLK[10]
TCLK[11]
TCLK[12]
TCLK[13]
TCLK[14]
TCLK[15]
TCLK[16]
TCLK[17]
TCLK[18]
TCLK[19]
TCLK[20]
TCLK[21]
TCLK[22]
TCLK[23]
TCLK[24]
TCLK[25]
TCLK[26]
TCLK[27]
TCLK[28]
TCLK[29]
TCLK[30]
TCLK[31]
Input L19
L17
M19
N19
N18
P19
P18
R19
T20
R17
U20
T17
V17
W17
V16
W16
V15
Y15
U13
Y14
W13
Y13
W12
V11
W10
U10
W9
W8
V8
W7
V7
W6
The transmit line clock signals (TCLK[31:0])
contain the transmit clocks for the 32
independently timed links. Processing of
the transmit links is on a priority basis, in
descending order from TCLK[0] to
TCLK[31]. Therefore, the highest rate link
should be connected to TCLK[0] and the
lowest to TCLK[31]. TD[31:0] is updated on
the falling edge of the corresponding
TCLK[31:0] clock.
For channelised T1 or E1 links, TCLK[n]
must be gapped during the framing bit (for
T1 interfaces) or during time-slot 0 (for E1
interfaces) of the TD[n] stream. The
FREEDM-32 uses the gapping information
to determine the time-slot alignment in the
transmit stream.
For unchannelised links, TCLK[n] must be
externally gapped during the bits or timeslots that are not part of the transmission
format payload (i.e. not part of the HDLC
packet).
TCLK[31:3] is nominally a 50% duty cycle
clock between 0 and 10 MHz. TCLK[2:0] is
nominally a 50% duty cycle clock between 0
and 52 MHz. Typical values for TCLK[31:0]
include 1.544 MHz (for T1 links) and 2.048
MHz (for E1 links).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 12
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PMC-1960758 ISSUE 6 FRAME ENGINE AND DATA LINK MANAGER
Pin Name Type Pin
Function
PM7364 FREEDM-32
No.
TD[0]
TD[1]
TD[2]
TD[3]
TD[4]
TD[5]
TD[6]
TD[7]
TD[8]
TD[9]
TD[10]
TD[11]
TD[12]
TD[13]
TD[14]
TD[15]
TD[16]
TD[17]
TD[18]
TD[19]
TD[20]
TD[21]
TD[22]
TD[23]
TD[24]
TD[25]
TD[26]
TD[27]
TD[28]
TD[29]
TD[30]
TD[31]
Output L20
L18
M20
M18
M17
P20
N17
R20
R18
T19
T18
U19
U18
U16
Y17
U15
Y16
W15
V14
W14
V13
U12
V12
W11
Y10
V10
Y9
V9
U9
Y7
U8
Y6
The transmit data signals (TD[31:0])
contains the transmit data for the 32
independently timed links in normal mode
(PMCTEST set low). Processing of the
transmit links is on a priority basis, in
descending order from TD[0] to TD[31].
Therefore, the highest rate link should be
connected to TD[0] and the lowest to
TD[31].
For channelised links, TD[n] contains the 24
(T1) or 31 (E1) time-slots that comprise the
channelised link. TCLK[n] must be gapped
during the T1 framing bit position or the E1
frame alignment signal (time-slot 0). The
FREEDM-32 uses the location of the gap to
determine the channel alignment on TD[n].
For unchannelised links, TD[n] contains the
HDLC packet data. For certain transmission
formats, TD[n] may contain place holder bits
or time-slots. TCLK[n] must be externally
gapped during the place holder positions in
the TD[n] stream. The FREEDM-32
supports a maximum data rate of 10 Mbit/s
on an individual TD[31:3] link and a
maximum data rate of 52 Mbit/s on TD[2:0]
TD[31:0] is updated on the falling edge of
the corresponding TCLK[31:0] clock.
TBD Input V6 The transmit BERT data signal (TBD)
contains the transmit bit error rate test data.
When the TBERTEN bit in the BERT
Control register is set high, the data on TBD
is transmitted on the selected one of the
transmit data signals (TD[31:0]). TBD is
sampled on the rising edge of TBCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 13
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DATA SHEET
PMC-1960758 ISSUE 6 FRAME ENGINE AND DATA LINK MANAGER
Pin Name Type Pin
Function
PM7364 FREEDM-32
No.
TBCLK Tristate
Output
Y5 The transmit BERT clock signal (TBCLK)
contains the transmit bit error rate test
clock. TBCLK is a buffered version of the
selected one of the transmit clock signals
(TCLK[31:0]). TBCLK may be tri-stated by
setting the TBEN bit in the FREEDM-32
Master BERT Control register low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 14
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PMC-1960758 ISSUE 6 FRAME ENGINE AND DATA LINK MANAGER
PM7364 FREEDM-32
Table 2 – PCI Host Interface Signals (51)
Pin Name Type Pin
Function
No.
PCICLK Input C4 The PCI clock signal (PCICLK) provides timing
for PCI bus accesses. PCICLK is a nominally
50% duty cycle, 0 to 33 MHz clock.
PCICLKO Output D5 The PCI clock output signal (PCICLKO) is a
buffered version of the PCICLK. PCICLKO may
be used to drive the SYSCLK input.
AD[0]
AD[1]
AD[2]
AD[3]
AD[4]
AD[5]
AD[6]
AD[7]
AD[8]
AD[9]
AD[10]
AD[11]
AD[12]
AD[13]
AD[14]
AD[15]
AD[16]
AD[17]
AD[18]
AD[19]
AD[20]
AD[21]
AD[22]
AD[23]
AD[24]
AD[25]
AD[26]
AD[27]
AD[28]
AD[29]
AD[30]
I/O U3
T4
U2
U1
T3
R4
T2
T1
R2
R1
P3
N4
P2
P1
N3
N2
J2
J3
H2
J4
H3
G1
G2
H4
F2
F3
E1
E2
F4
E3
The PCI address and data bus (AD[31:0])
carries the PCI bus multiplexed address and
data. During the first clock cycle of a
transaction, AD[31:0] contains a physical byte
address. During subsequent clock cycles of a
transaction, AD[31:0] contains data.
A transaction is defined as an address phase
followed by one or more data phases. When
Little-Endian byte formatting is selected,
AD[31:24] contain the most significant byte of a
DWORD while AD[7:0] contain the least
significant byte. When Big-Endian byte
formatting is selected. AD[7:0] contain the most
significant byte of a DWORD while AD[31:24]
contain the least significant byte. When the
FREEDM-32 is the initiator, AD[31:0] is an
output bus during the first (address) phase of a
transaction. For write transactions, AD[31:0]
remains an output bus for the data phases of
the transaction. For read transactions, AD[31:0]
is an input bus during the data phases.
When the FREEDM-32 is the target, AD[31:0] is
an input bus during the first (address) phase of
a transaction. For write transactions, AD[31:0]
remains an input bus during the data phases of
the transaction. For read transactions, AD[31:0]
is an output bus during the data phases.
When the FREEDM-32 is not involved in the
current transaction, AD[31:0] is tri-stated.
D1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 15
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PMC-1960758 ISSUE 6 FRAME ENGINE AND DATA LINK MANAGER
Pin Name Type Pin
Function
PM7364 FREEDM-32
No.
AD[31] I/O D2 As an output bus, AD[31:0] is updated on the
rising edge of PCICLK. As an input bus,
AD[31:0] is sampled on the rising edge of
PCICLK.
C/BEB[0]
C/BEB[1]
C/BEB[2]
C/BEB[3]
I/O R3
M4
J1
F1
The PCI bus command and byte enable bus
(C/BEB[3:0]) contains the bus command or the
byte valid indications. During the first clock
cycle of a transaction, C/BEB[3:0] contains the
bus command code. For subsequent clock
cycles, C/BEB[3:0] identifies which bytes on the
AD[31:0] bus carry valid data. C/BEB[3] is
associated with byte 3 (AD[31:24]) while
C/BEB[0] is associated with byte 0 (AD[7:0]).
When C/BEB[n] is set high, the associated byte
is invalid. When C/BEB[n] is set low, the
associated byte is valid.
When the FREEDM-32 is the initiator,
C/BEB[3:0] is an output bus.
When the FREEDM-32 is the target, C/BEB[3:0]
is an input bus.
When the FREEDM-32 is not involved in the
current transaction, C/BEB[3:0] is tri-stated.
As an output bus, C/BEB[3:0] is updated on the
rising edge of PCICLK. As an input bus,
C/BEB[3:0] is sampled on the rising edge of
PCICLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 16
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